1/*
  2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 21 * SOFTWARE.
 22 *
 23 * Authors:
 24 *    Ke Yu
 25 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
 26 *
 27 * Contributors:
 28 *    Terrence Xu <terrence.xu@intel.com>
 29 *    Changbin Du <changbin.du@intel.com>
 30 *    Bing Niu <bing.niu@intel.com>
 31 *    Zhi Wang <zhi.a.wang@intel.com>
 32 *
 33 */
 34
 35#ifndef _GVT_DISPLAY_H_
 36#define _GVT_DISPLAY_H_
 37
 38#include <linux/types.h>
 39#include <linux/hrtimer.h>
 40
 41struct intel_gvt;
 42struct intel_vgpu;
 43
 44#define SBI_REG_MAX	20
 45#define DPCD_SIZE	0x700
 46
 47#define intel_vgpu_port(vgpu, port) \
 48	(&(vgpu->display.ports[port]))
 49
 50#define intel_vgpu_has_monitor_on_port(vgpu, port) \
 51	(intel_vgpu_port(vgpu, port)->edid && \
 52		intel_vgpu_port(vgpu, port)->edid->data_valid)
 53
 54#define intel_vgpu_port_is_dp(vgpu, port) \
 55	((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
 56	(intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
 57	(intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
 58	(intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
 59
 60#define INTEL_GVT_MAX_UEVENT_VARS	3
 61
 62#define AUX_NATIVE_REPLY_NAK    (0x1 << 4)
 63
 64#define AUX_BURST_SIZE          20
 65
 66#define SBI_RESPONSE_MASK               0x3
 67#define SBI_RESPONSE_SHIFT              0x1
 68#define SBI_STAT_MASK                   0x1
 69#define SBI_STAT_SHIFT                  0x0
 70#define SBI_OPCODE_SHIFT                8
 71#define SBI_OPCODE_MASK			(0xff << SBI_OPCODE_SHIFT)
 72#define SBI_CMD_IORD                    2
 73#define SBI_CMD_IOWR                    3
 74#define SBI_CMD_CRRD                    6
 75#define SBI_CMD_CRWR                    7
 76#define SBI_ADDR_OFFSET_SHIFT           16
 77#define SBI_ADDR_OFFSET_MASK            (0xffff << SBI_ADDR_OFFSET_SHIFT)
 78
 79struct intel_vgpu_sbi_register {
 80	unsigned int offset;
 81	u32 value;
 82};
 83
 84struct intel_vgpu_sbi {
 85	int number;
 86	struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
 87};
 88
 89enum intel_gvt_plane_type {
 90	PRIMARY_PLANE = 0,
 91	CURSOR_PLANE,
 92	SPRITE_PLANE,
 93	MAX_PLANE
 94};
 95
 96struct intel_vgpu_dpcd_data {
 97	bool data_valid;
 98	u8 data[DPCD_SIZE];
 99};
100
101enum intel_vgpu_port_type {
102	GVT_CRT = 0,
103	GVT_DP_A,
104	GVT_DP_B,
105	GVT_DP_C,
106	GVT_DP_D,
107	GVT_HDMI_B,
108	GVT_HDMI_C,
109	GVT_HDMI_D,
110	GVT_PORT_MAX
111};
112
113enum intel_vgpu_edid {
114	GVT_EDID_1024_768,
115	GVT_EDID_1920_1200,
116	GVT_EDID_NUM,
117};
118
119#define GVT_DEFAULT_REFRESH_RATE 60
120struct intel_vgpu_port {
121	/* per display EDID information */
122	struct intel_vgpu_edid_data *edid;
123	/* per display DPCD information */
124	struct intel_vgpu_dpcd_data *dpcd;
125	int type;
126	enum intel_vgpu_edid id;
127	/* x1000 to get accurate 59.94, 24.976, 29.94, etc. in timing std. */
128	u32 vrefresh_k;
129};
130
131struct intel_vgpu_vblank_timer {
132	struct hrtimer timer;
133	u32 vrefresh_k;
134	u64 period;
135};
136
137static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
138{
139	switch (id) {
140	case GVT_EDID_1024_768:
141		return "1024x768";
142	case GVT_EDID_1920_1200:
143		return "1920x1200";
144	default:
145		return "";
146	}
147}
148
149static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
150{
151	switch (id) {
152	case GVT_EDID_1024_768:
153		return 1024;
154	case GVT_EDID_1920_1200:
155		return 1920;
156	default:
157		return 0;
158	}
159}
160
161static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
162{
163	switch (id) {
164	case GVT_EDID_1024_768:
165		return 768;
166	case GVT_EDID_1920_1200:
167		return 1200;
168	default:
169		return 0;
170	}
171}
172
173void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu);
174void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
175
176int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
177void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
178void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
179
180int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
181
182#endif