Loading...
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#ifndef _GVT_DISPLAY_H_
36#define _GVT_DISPLAY_H_
37
38#include <linux/types.h>
39#include <linux/hrtimer.h>
40
41struct intel_gvt;
42struct intel_vgpu;
43
44#define SBI_REG_MAX 20
45#define DPCD_SIZE 0x700
46
47#define intel_vgpu_port(vgpu, port) \
48 (&(vgpu->display.ports[port]))
49
50#define intel_vgpu_has_monitor_on_port(vgpu, port) \
51 (intel_vgpu_port(vgpu, port)->edid && \
52 intel_vgpu_port(vgpu, port)->edid->data_valid)
53
54#define intel_vgpu_port_is_dp(vgpu, port) \
55 ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
56 (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
57 (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
58 (intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
59
60#define INTEL_GVT_MAX_UEVENT_VARS 3
61
62/* DPCD start */
63#define DPCD_SIZE 0x700
64
65/* DPCD */
66#define DP_SET_POWER 0x600
67#define DP_SET_POWER_D0 0x1
68#define AUX_NATIVE_WRITE 0x8
69#define AUX_NATIVE_READ 0x9
70
71#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
72#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
73#define AUX_NATIVE_REPLY_NAK (0x1 << 4)
74#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
75
76#define AUX_BURST_SIZE 20
77
78/* DPCD addresses */
79#define DPCD_REV 0x000
80#define DPCD_MAX_LINK_RATE 0x001
81#define DPCD_MAX_LANE_COUNT 0x002
82
83#define DPCD_TRAINING_PATTERN_SET 0x102
84#define DPCD_SINK_COUNT 0x200
85#define DPCD_LANE0_1_STATUS 0x202
86#define DPCD_LANE2_3_STATUS 0x203
87#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
88#define DPCD_SINK_STATUS 0x205
89
90/* link training */
91#define DPCD_TRAINING_PATTERN_SET_MASK 0x03
92#define DPCD_LINK_TRAINING_DISABLED 0x00
93#define DPCD_TRAINING_PATTERN_1 0x01
94#define DPCD_TRAINING_PATTERN_2 0x02
95
96#define DPCD_CP_READY_MASK (1 << 6)
97
98/* lane status */
99#define DPCD_LANES_CR_DONE 0x11
100#define DPCD_LANES_EQ_DONE 0x22
101#define DPCD_SYMBOL_LOCKED 0x44
102
103#define DPCD_INTERLANE_ALIGN_DONE 0x01
104
105#define DPCD_SINK_IN_SYNC 0x03
106/* DPCD end */
107
108#define SBI_RESPONSE_MASK 0x3
109#define SBI_RESPONSE_SHIFT 0x1
110#define SBI_STAT_MASK 0x1
111#define SBI_STAT_SHIFT 0x0
112#define SBI_OPCODE_SHIFT 8
113#define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT)
114#define SBI_CMD_IORD 2
115#define SBI_CMD_IOWR 3
116#define SBI_CMD_CRRD 6
117#define SBI_CMD_CRWR 7
118#define SBI_ADDR_OFFSET_SHIFT 16
119#define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT)
120
121struct intel_vgpu_sbi_register {
122 unsigned int offset;
123 u32 value;
124};
125
126struct intel_vgpu_sbi {
127 int number;
128 struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
129};
130
131enum intel_gvt_plane_type {
132 PRIMARY_PLANE = 0,
133 CURSOR_PLANE,
134 SPRITE_PLANE,
135 MAX_PLANE
136};
137
138struct intel_vgpu_dpcd_data {
139 bool data_valid;
140 u8 data[DPCD_SIZE];
141};
142
143enum intel_vgpu_port_type {
144 GVT_CRT = 0,
145 GVT_DP_A,
146 GVT_DP_B,
147 GVT_DP_C,
148 GVT_DP_D,
149 GVT_HDMI_B,
150 GVT_HDMI_C,
151 GVT_HDMI_D,
152 GVT_PORT_MAX
153};
154
155enum intel_vgpu_edid {
156 GVT_EDID_1024_768,
157 GVT_EDID_1920_1200,
158 GVT_EDID_NUM,
159};
160
161#define GVT_DEFAULT_REFRESH_RATE 60
162struct intel_vgpu_port {
163 /* per display EDID information */
164 struct intel_vgpu_edid_data *edid;
165 /* per display DPCD information */
166 struct intel_vgpu_dpcd_data *dpcd;
167 int type;
168 enum intel_vgpu_edid id;
169 /* x1000 to get accurate 59.94, 24.976, 29.94, etc. in timing std. */
170 u32 vrefresh_k;
171};
172
173struct intel_vgpu_vblank_timer {
174 struct hrtimer timer;
175 u32 vrefresh_k;
176 u64 period;
177};
178
179static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
180{
181 switch (id) {
182 case GVT_EDID_1024_768:
183 return "1024x768";
184 case GVT_EDID_1920_1200:
185 return "1920x1200";
186 default:
187 return "";
188 }
189}
190
191static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
192{
193 switch (id) {
194 case GVT_EDID_1024_768:
195 return 1024;
196 case GVT_EDID_1920_1200:
197 return 1920;
198 default:
199 return 0;
200 }
201}
202
203static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
204{
205 switch (id) {
206 case GVT_EDID_1024_768:
207 return 768;
208 case GVT_EDID_1920_1200:
209 return 1200;
210 default:
211 return 0;
212 }
213}
214
215void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu);
216void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
217
218int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
219void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
220void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
221
222int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
223
224#endif