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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2014-2019 Intel Corporation
4 *
5 * Authors:
6 * Vinit Azad <vinit.azad@intel.com>
7 * Ben Widawsky <ben@bwidawsk.net>
8 * Dave Gordon <david.s.gordon@intel.com>
9 * Alex Dai <yu.dai@intel.com>
10 */
11
12#include "gt/intel_gt.h"
13#include "gt/intel_gt_mcr.h"
14#include "gt/intel_gt_regs.h"
15#include "gt/intel_rps.h"
16#include "intel_guc_fw.h"
17#include "intel_guc_print.h"
18#include "i915_drv.h"
19
20static void guc_prepare_xfer(struct intel_gt *gt)
21{
22 struct intel_uncore *uncore = gt->uncore;
23
24 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
25 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
26 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
27 GUC_ENABLE_MIA_CLOCK_GATING;
28
29 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 55))
30 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
31 GUC_ENABLE_MIA_CACHING;
32
33 /* Must program this register before loading the ucode with DMA */
34 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
35
36 if (IS_GEN9_LP(uncore->i915))
37 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
38 else
39 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
40
41 if (GRAPHICS_VER(uncore->i915) == 9) {
42 /* DOP Clock Gating Enable for GuC clocks */
43 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0,
44 GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
45
46 /* allows for 5us (in 10ns units) before GT can go to RC6 */
47 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
48 }
49}
50
51static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw,
52 struct intel_uncore *uncore)
53{
54 u32 rsa[UOS_RSA_SCRATCH_COUNT];
55 size_t copied;
56 int i;
57
58 copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
59 if (copied < sizeof(rsa))
60 return -ENOMEM;
61
62 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
63 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
64
65 return 0;
66}
67
68static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw,
69 struct intel_uncore *uncore)
70{
71 struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
72
73 intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
74 intel_guc_ggtt_offset(guc, guc_fw->rsa_data));
75
76 return 0;
77}
78
79/* Copy RSA signature from the fw image to HW for verification */
80static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
81 struct intel_uncore *uncore)
82{
83 if (guc_fw->rsa_data)
84 return guc_xfer_rsa_vma(guc_fw, uncore);
85 else
86 return guc_xfer_rsa_mmio(guc_fw, uncore);
87}
88
89/*
90 * Read the GuC status register (GUC_STATUS) and store it in the
91 * specified location; then return a boolean indicating whether
92 * the value matches either completion or a known failure code.
93 *
94 * This is used for polling the GuC status in a wait_for()
95 * loop below.
96 */
97static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool *success)
98{
99 u32 val = intel_uncore_read(uncore, GUC_STATUS);
100 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
101 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val);
102
103 *status = val;
104 switch (uk_val) {
105 case INTEL_GUC_LOAD_STATUS_READY:
106 *success = true;
107 return true;
108
109 case INTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH:
110 case INTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH:
111 case INTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE:
112 case INTEL_GUC_LOAD_STATUS_HWCONFIG_ERROR:
113 case INTEL_GUC_LOAD_STATUS_DPC_ERROR:
114 case INTEL_GUC_LOAD_STATUS_EXCEPTION:
115 case INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID:
116 case INTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID:
117 case INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
118 case INTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR:
119 *success = false;
120 return true;
121 }
122
123 switch (br_val) {
124 case INTEL_BOOTROM_STATUS_NO_KEY_FOUND:
125 case INTEL_BOOTROM_STATUS_RSA_FAILED:
126 case INTEL_BOOTROM_STATUS_PAVPC_FAILED:
127 case INTEL_BOOTROM_STATUS_WOPCM_FAILED:
128 case INTEL_BOOTROM_STATUS_LOADLOC_FAILED:
129 case INTEL_BOOTROM_STATUS_JUMP_FAILED:
130 case INTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED:
131 case INTEL_BOOTROM_STATUS_MPUMAP_INCORRECT:
132 case INTEL_BOOTROM_STATUS_EXCEPTION:
133 case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
134 *success = false;
135 return true;
136 }
137
138 return false;
139}
140
141/*
142 * Use a longer timeout for debug builds so that problems can be detected
143 * and analysed. But a shorter timeout for releases so that user's don't
144 * wait forever to find out there is a problem. Note that the only reason
145 * an end user should hit the timeout is in case of extreme thermal throttling.
146 * And a system that is that hot during boot is probably dead anyway!
147 */
148#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
149#define GUC_LOAD_RETRY_LIMIT 20
150#else
151#define GUC_LOAD_RETRY_LIMIT 3
152#endif
153
154static int guc_wait_ucode(struct intel_guc *guc)
155{
156 struct intel_gt *gt = guc_to_gt(guc);
157 struct intel_uncore *uncore = gt->uncore;
158 ktime_t before, after, delta;
159 bool success;
160 u32 status;
161 int ret, count;
162 u64 delta_ms;
163 u32 before_freq;
164
165 /*
166 * Wait for the GuC to start up.
167 *
168 * Measurements indicate this should take no more than 20ms
169 * (assuming the GT clock is at maximum frequency). So, a
170 * timeout here indicates that the GuC has failed and is unusable.
171 * (Higher levels of the driver may decide to reset the GuC and
172 * attempt the ucode load again if this happens.)
173 *
174 * FIXME: There is a known (but exceedingly unlikely) race condition
175 * where the asynchronous frequency management code could reduce
176 * the GT clock while a GuC reload is in progress (during a full
177 * GT reset). A fix is in progress but there are complex locking
178 * issues to be resolved. In the meantime bump the timeout to
179 * 200ms. Even at slowest clock, this should be sufficient. And
180 * in the working case, a larger timeout makes no difference.
181 *
182 * IFWI updates have also been seen to cause sporadic failures due to
183 * the requested frequency not being granted and thus the firmware
184 * load is attempted at minimum frequency. That can lead to load times
185 * in the seconds range. However, there is a limit on how long an
186 * individual wait_for() can wait. So wrap it in a loop.
187 */
188 before_freq = intel_rps_read_actual_frequency(>->rps);
189 before = ktime_get();
190 for (count = 0; count < GUC_LOAD_RETRY_LIMIT; count++) {
191 ret = wait_for(guc_load_done(uncore, &status, &success), 1000);
192 if (!ret || !success)
193 break;
194
195 guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz, status = 0x%08X [0x%02X/%02X]\n",
196 count, intel_rps_read_actual_frequency(>->rps), status,
197 REG_FIELD_GET(GS_BOOTROM_MASK, status),
198 REG_FIELD_GET(GS_UKERNEL_MASK, status));
199 }
200 after = ktime_get();
201 delta = ktime_sub(after, before);
202 delta_ms = ktime_to_ms(delta);
203 if (ret || !success) {
204 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);
205 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);
206
207 guc_info(guc, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz, ret = %d\n",
208 status, delta_ms, intel_rps_read_actual_frequency(>->rps), ret);
209 guc_info(guc, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
210 REG_FIELD_GET(GS_MIA_IN_RESET, status),
211 bootrom, ukernel,
212 REG_FIELD_GET(GS_MIA_MASK, status),
213 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
214
215 switch (bootrom) {
216 case INTEL_BOOTROM_STATUS_NO_KEY_FOUND:
217 guc_info(guc, "invalid key requested, header = 0x%08X\n",
218 intel_uncore_read(uncore, GUC_HEADER_INFO));
219 ret = -ENOEXEC;
220 break;
221
222 case INTEL_BOOTROM_STATUS_RSA_FAILED:
223 guc_info(guc, "firmware signature verification failed\n");
224 ret = -ENOEXEC;
225 break;
226
227 case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
228 guc_info(guc, "firmware production part check failure\n");
229 ret = -ENOEXEC;
230 break;
231 }
232
233 switch (ukernel) {
234 case INTEL_GUC_LOAD_STATUS_EXCEPTION:
235 guc_info(guc, "firmware exception. EIP: %#x\n",
236 intel_uncore_read(uncore, SOFT_SCRATCH(13)));
237 ret = -ENXIO;
238 break;
239
240 case INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
241 guc_info(guc, "illegal register in save/restore workaround list\n");
242 ret = -EPERM;
243 break;
244
245 case INTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR:
246 guc_info(guc, "invalid w/a KLV entry\n");
247 ret = -EINVAL;
248 break;
249
250 case INTEL_GUC_LOAD_STATUS_HWCONFIG_START:
251 guc_info(guc, "still extracting hwconfig table.\n");
252 ret = -ETIMEDOUT;
253 break;
254 }
255
256 /* Uncommon/unexpected error, see earlier status code print for details */
257 if (ret == 0)
258 ret = -ENXIO;
259 } else if (delta_ms > 200) {
260 guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
261 delta_ms, status, count, ret);
262 guc_warn(guc, "excessive init time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n",
263 intel_rps_read_actual_frequency(>->rps), before_freq,
264 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
265 } else {
266 guc_dbg(guc, "init took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n",
267 delta_ms, intel_rps_read_actual_frequency(>->rps),
268 before_freq, status, count, ret);
269 }
270
271 return ret;
272}
273
274/**
275 * intel_guc_fw_upload() - load GuC uCode to device
276 * @guc: intel_guc structure
277 *
278 * Called from intel_uc_init_hw() during driver load, resume from sleep and
279 * after a GPU reset.
280 *
281 * The firmware image should have already been fetched into memory, so only
282 * check that fetch succeeded, and then transfer the image to the h/w.
283 *
284 * Return: non-zero code on error
285 */
286int intel_guc_fw_upload(struct intel_guc *guc)
287{
288 struct intel_gt *gt = guc_to_gt(guc);
289 struct intel_uncore *uncore = gt->uncore;
290 int ret;
291
292 guc_prepare_xfer(gt);
293
294 /*
295 * Note that GuC needs the CSS header plus uKernel code to be copied
296 * by the DMA engine in one operation, whereas the RSA signature is
297 * loaded separately, either by copying it to the UOS_RSA_SCRATCH
298 * register (if key size <= 256) or through a ggtt-pinned vma (if key
299 * size > 256). The RSA size and therefore the way we provide it to the
300 * HW is fixed for each platform and hard-coded in the bootrom.
301 */
302 ret = guc_xfer_rsa(&guc->fw, uncore);
303 if (ret)
304 goto out;
305
306 /*
307 * Current uCode expects the code to be loaded at 8k; locations below
308 * this are used for the stack.
309 */
310 ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
311 if (ret)
312 goto out;
313
314 ret = guc_wait_ucode(guc);
315 if (ret)
316 goto out;
317
318 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
319 return 0;
320
321out:
322 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
323 return ret;
324}