1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2014-2019 Intel Corporation
  4 *
  5 * Authors:
  6 *    Vinit Azad <vinit.azad@intel.com>
  7 *    Ben Widawsky <ben@bwidawsk.net>
  8 *    Dave Gordon <david.s.gordon@intel.com>
  9 *    Alex Dai <yu.dai@intel.com>
 10 */
 11
 12#include "gt/intel_gt.h"
 13#include "gt/intel_gt_mcr.h"
 14#include "gt/intel_gt_regs.h"
 15#include "intel_guc_fw.h"
 16#include "i915_drv.h"
 17
 18static void guc_prepare_xfer(struct intel_gt *gt)
 19{
 20	struct intel_uncore *uncore = gt->uncore;
 21
 22	u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
 23			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
 24			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
 25			 GUC_ENABLE_MIA_CLOCK_GATING;
 26
 27	if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
 28		shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
 29			      GUC_ENABLE_MIA_CACHING;
 30
 31	/* Must program this register before loading the ucode with DMA */
 32	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
 33
 34	if (IS_GEN9_LP(uncore->i915))
 35		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 36	else
 37		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 38
 39	if (GRAPHICS_VER(uncore->i915) == 9) {
 40		/* DOP Clock Gating Enable for GuC clocks */
 41		intel_gt_mcr_multicast_write(gt, GEN8_MISCCPCTL,
 42					     GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 43					     intel_gt_mcr_read_any(gt, GEN8_MISCCPCTL));
 44
 45		/* allows for 5us (in 10ns units) before GT can go to RC6 */
 46		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
 47	}
 48}
 49
 50static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw,
 51			     struct intel_uncore *uncore)
 52{
 53	u32 rsa[UOS_RSA_SCRATCH_COUNT];
 54	size_t copied;
 55	int i;
 56
 57	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
 58	if (copied < sizeof(rsa))
 59		return -ENOMEM;
 60
 61	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
 62		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
 63
 64	return 0;
 65}
 66
 67static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw,
 68			    struct intel_uncore *uncore)
 69{
 70	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
 71
 72	intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
 73			   intel_guc_ggtt_offset(guc, guc_fw->rsa_data));
 74
 75	return 0;
 76}
 77
 78/* Copy RSA signature from the fw image to HW for verification */
 79static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
 80			struct intel_uncore *uncore)
 81{
 82	if (guc_fw->rsa_data)
 83		return guc_xfer_rsa_vma(guc_fw, uncore);
 84	else
 85		return guc_xfer_rsa_mmio(guc_fw, uncore);
 86}
 87
 88/*
 89 * Read the GuC status register (GUC_STATUS) and store it in the
 90 * specified location; then return a boolean indicating whether
 91 * the value matches either of two values representing completion
 92 * of the GuC boot process.
 93 *
 94 * This is used for polling the GuC status in a wait_for()
 95 * loop below.
 96 */
 97static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
 98{
 99	u32 val = intel_uncore_read(uncore, GUC_STATUS);
100	u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
101
102	*status = val;
103	return uk_val == INTEL_GUC_LOAD_STATUS_READY;
104}
105
106static int guc_wait_ucode(struct intel_uncore *uncore)
107{
108	u32 status;
109	int ret;
110
111	/*
112	 * Wait for the GuC to start up.
113	 * NB: Docs recommend not using the interrupt for completion.
114	 * Measurements indicate this should take no more than 20ms
115	 * (assuming the GT clock is at maximum frequency). So, a
116	 * timeout here indicates that the GuC has failed and is unusable.
117	 * (Higher levels of the driver may decide to reset the GuC and
118	 * attempt the ucode load again if this happens.)
119	 *
120	 * FIXME: There is a known (but exceedingly unlikely) race condition
121	 * where the asynchronous frequency management code could reduce
122	 * the GT clock while a GuC reload is in progress (during a full
123	 * GT reset). A fix is in progress but there are complex locking
124	 * issues to be resolved. In the meantime bump the timeout to
125	 * 200ms. Even at slowest clock, this should be sufficient. And
126	 * in the working case, a larger timeout makes no difference.
127	 */
128	ret = wait_for(guc_ready(uncore, &status), 200);
129	if (ret) {
130		struct drm_device *drm = &uncore->i915->drm;
131
132		drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
133		drm_info(drm, "GuC load failed: status: Reset = %d, "
134			"BootROM = 0x%02X, UKernel = 0x%02X, "
135			"MIA = 0x%02X, Auth = 0x%02X\n",
136			REG_FIELD_GET(GS_MIA_IN_RESET, status),
137			REG_FIELD_GET(GS_BOOTROM_MASK, status),
138			REG_FIELD_GET(GS_UKERNEL_MASK, status),
139			REG_FIELD_GET(GS_MIA_MASK, status),
140			REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
141
142		if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
143			drm_info(drm, "GuC firmware signature verification failed\n");
144			ret = -ENOEXEC;
145		}
146
147		if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
148			drm_info(drm, "GuC firmware exception. EIP: %#x\n",
149				 intel_uncore_read(uncore, SOFT_SCRATCH(13)));
150			ret = -ENXIO;
151		}
152	}
153
154	return ret;
155}
156
157/**
158 * intel_guc_fw_upload() - load GuC uCode to device
159 * @guc: intel_guc structure
160 *
161 * Called from intel_uc_init_hw() during driver load, resume from sleep and
162 * after a GPU reset.
163 *
164 * The firmware image should have already been fetched into memory, so only
165 * check that fetch succeeded, and then transfer the image to the h/w.
166 *
167 * Return:	non-zero code on error
168 */
169int intel_guc_fw_upload(struct intel_guc *guc)
170{
171	struct intel_gt *gt = guc_to_gt(guc);
172	struct intel_uncore *uncore = gt->uncore;
173	int ret;
174
175	guc_prepare_xfer(gt);
176
177	/*
178	 * Note that GuC needs the CSS header plus uKernel code to be copied
179	 * by the DMA engine in one operation, whereas the RSA signature is
180	 * loaded separately, either by copying it to the UOS_RSA_SCRATCH
181	 * register (if key size <= 256) or through a ggtt-pinned vma (if key
182	 * size > 256). The RSA size and therefore the way we provide it to the
183	 * HW is fixed for each platform and hard-coded in the bootrom.
184	 */
185	ret = guc_xfer_rsa(&guc->fw, uncore);
186	if (ret)
187		goto out;
188
189	/*
190	 * Current uCode expects the code to be loaded at 8k; locations below
191	 * this are used for the stack.
192	 */
193	ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
194	if (ret)
195		goto out;
196
197	ret = guc_wait_ucode(uncore);
198	if (ret)
199		goto out;
200
201	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
202	return 0;
203
204out:
205	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
206	return ret;
207}