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1// SPDX-License-Identifier: GPL-2.0
2//
3// Register cache access API
4//
5// Copyright 2011 Wolfson Microelectronics plc
6//
7// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8
9#include <linux/bsearch.h>
10#include <linux/device.h>
11#include <linux/export.h>
12#include <linux/slab.h>
13#include <linux/sort.h>
14
15#include "trace.h"
16#include "internal.h"
17
18static const struct regcache_ops *cache_types[] = {
19 ®cache_rbtree_ops,
20 ®cache_maple_ops,
21 ®cache_flat_ops,
22};
23
24static int regcache_hw_init(struct regmap *map)
25{
26 int i, j;
27 int ret;
28 int count;
29 unsigned int reg, val;
30 void *tmp_buf;
31
32 if (!map->num_reg_defaults_raw)
33 return -EINVAL;
34
35 /* calculate the size of reg_defaults */
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
37 if (regmap_readable(map, i * map->reg_stride) &&
38 !regmap_volatile(map, i * map->reg_stride))
39 count++;
40
41 /* all registers are unreadable or volatile, so just bypass */
42 if (!count) {
43 map->cache_bypass = true;
44 return 0;
45 }
46
47 map->num_reg_defaults = count;
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
49 GFP_KERNEL);
50 if (!map->reg_defaults)
51 return -ENOMEM;
52
53 if (!map->reg_defaults_raw) {
54 bool cache_bypass = map->cache_bypass;
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
56
57 /* Bypass the cache access till data read from HW */
58 map->cache_bypass = true;
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
60 if (!tmp_buf) {
61 ret = -ENOMEM;
62 goto err_free;
63 }
64 ret = regmap_raw_read(map, 0, tmp_buf,
65 map->cache_size_raw);
66 map->cache_bypass = cache_bypass;
67 if (ret == 0) {
68 map->reg_defaults_raw = tmp_buf;
69 map->cache_free = true;
70 } else {
71 kfree(tmp_buf);
72 }
73 }
74
75 /* fill the reg_defaults */
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 reg = i * map->reg_stride;
78
79 if (!regmap_readable(map, reg))
80 continue;
81
82 if (regmap_volatile(map, reg))
83 continue;
84
85 if (map->reg_defaults_raw) {
86 val = regcache_get_val(map, map->reg_defaults_raw, i);
87 } else {
88 bool cache_bypass = map->cache_bypass;
89
90 map->cache_bypass = true;
91 ret = regmap_read(map, reg, &val);
92 map->cache_bypass = cache_bypass;
93 if (ret != 0) {
94 dev_err(map->dev, "Failed to read %d: %d\n",
95 reg, ret);
96 goto err_free;
97 }
98 }
99
100 map->reg_defaults[j].reg = reg;
101 map->reg_defaults[j].def = val;
102 j++;
103 }
104
105 return 0;
106
107err_free:
108 kfree(map->reg_defaults);
109
110 return ret;
111}
112
113int regcache_init(struct regmap *map, const struct regmap_config *config)
114{
115 int ret;
116 int i;
117 void *tmp_buf;
118
119 if (map->cache_type == REGCACHE_NONE) {
120 if (config->reg_defaults || config->num_reg_defaults_raw)
121 dev_warn(map->dev,
122 "No cache used with register defaults set!\n");
123
124 map->cache_bypass = true;
125 return 0;
126 }
127
128 if (config->reg_defaults && !config->num_reg_defaults) {
129 dev_err(map->dev,
130 "Register defaults are set without the number!\n");
131 return -EINVAL;
132 }
133
134 if (config->num_reg_defaults && !config->reg_defaults) {
135 dev_err(map->dev,
136 "Register defaults number are set without the reg!\n");
137 return -EINVAL;
138 }
139
140 for (i = 0; i < config->num_reg_defaults; i++)
141 if (config->reg_defaults[i].reg % map->reg_stride)
142 return -EINVAL;
143
144 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
145 if (cache_types[i]->type == map->cache_type)
146 break;
147
148 if (i == ARRAY_SIZE(cache_types)) {
149 dev_err(map->dev, "Could not match cache type: %d\n",
150 map->cache_type);
151 return -EINVAL;
152 }
153
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
159
160 map->cache = NULL;
161 map->cache_ops = cache_types[i];
162
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
166 return -EINVAL;
167
168 /* We still need to ensure that the reg_defaults
169 * won't vanish from under us. We'll need to make
170 * a copy of it.
171 */
172 if (config->reg_defaults) {
173 tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,
174 sizeof(*map->reg_defaults), GFP_KERNEL);
175 if (!tmp_buf)
176 return -ENOMEM;
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
179 /* Some devices such as PMICs don't have cache defaults,
180 * we cope with this by reading back the HW registers and
181 * crafting the cache defaults by hand.
182 */
183 ret = regcache_hw_init(map);
184 if (ret < 0)
185 return ret;
186 if (map->cache_bypass)
187 return 0;
188 }
189
190 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
192 map->max_register_is_set = true;
193 }
194
195 if (map->cache_ops->init) {
196 dev_dbg(map->dev, "Initializing %s cache\n",
197 map->cache_ops->name);
198 map->lock(map->lock_arg);
199 ret = map->cache_ops->init(map);
200 map->unlock(map->lock_arg);
201 if (ret)
202 goto err_free;
203 }
204 return 0;
205
206err_free:
207 kfree(map->reg_defaults);
208 if (map->cache_free)
209 kfree(map->reg_defaults_raw);
210
211 return ret;
212}
213
214void regcache_exit(struct regmap *map)
215{
216 if (map->cache_type == REGCACHE_NONE)
217 return;
218
219 BUG_ON(!map->cache_ops);
220
221 kfree(map->reg_defaults);
222 if (map->cache_free)
223 kfree(map->reg_defaults_raw);
224
225 if (map->cache_ops->exit) {
226 dev_dbg(map->dev, "Destroying %s cache\n",
227 map->cache_ops->name);
228 map->lock(map->lock_arg);
229 map->cache_ops->exit(map);
230 map->unlock(map->lock_arg);
231 }
232}
233
234/**
235 * regcache_read - Fetch the value of a given register from the cache.
236 *
237 * @map: map to configure.
238 * @reg: The register index.
239 * @value: The value to be returned.
240 *
241 * Return a negative value on failure, 0 on success.
242 */
243int regcache_read(struct regmap *map,
244 unsigned int reg, unsigned int *value)
245{
246 int ret;
247
248 if (map->cache_type == REGCACHE_NONE)
249 return -EINVAL;
250
251 BUG_ON(!map->cache_ops);
252
253 if (!regmap_volatile(map, reg)) {
254 ret = map->cache_ops->read(map, reg, value);
255
256 if (ret == 0)
257 trace_regmap_reg_read_cache(map, reg, *value);
258
259 return ret;
260 }
261
262 return -EINVAL;
263}
264
265/**
266 * regcache_write - Set the value of a given register in the cache.
267 *
268 * @map: map to configure.
269 * @reg: The register index.
270 * @value: The new register value.
271 *
272 * Return a negative value on failure, 0 on success.
273 */
274int regcache_write(struct regmap *map,
275 unsigned int reg, unsigned int value)
276{
277 if (map->cache_type == REGCACHE_NONE)
278 return 0;
279
280 BUG_ON(!map->cache_ops);
281
282 if (!regmap_volatile(map, reg))
283 return map->cache_ops->write(map, reg, value);
284
285 return 0;
286}
287
288bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
289 unsigned int val)
290{
291 int ret;
292
293 if (!regmap_writeable(map, reg))
294 return false;
295
296 /* If we don't know the chip just got reset, then sync everything. */
297 if (!map->no_sync_defaults)
298 return true;
299
300 /* Is this the hardware default? If so skip. */
301 ret = regcache_lookup_reg(map, reg);
302 if (ret >= 0 && val == map->reg_defaults[ret].def)
303 return false;
304 return true;
305}
306
307static int regcache_default_sync(struct regmap *map, unsigned int min,
308 unsigned int max)
309{
310 unsigned int reg;
311
312 for (reg = min; reg <= max; reg += map->reg_stride) {
313 unsigned int val;
314 int ret;
315
316 if (regmap_volatile(map, reg) ||
317 !regmap_writeable(map, reg))
318 continue;
319
320 ret = regcache_read(map, reg, &val);
321 if (ret == -ENOENT)
322 continue;
323 if (ret)
324 return ret;
325
326 if (!regcache_reg_needs_sync(map, reg, val))
327 continue;
328
329 map->cache_bypass = true;
330 ret = _regmap_write(map, reg, val);
331 map->cache_bypass = false;
332 if (ret) {
333 dev_err(map->dev, "Unable to sync register %#x. %d\n",
334 reg, ret);
335 return ret;
336 }
337 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
338 }
339
340 return 0;
341}
342
343static int rbtree_all(const void *key, const struct rb_node *node)
344{
345 return 0;
346}
347
348/**
349 * regcache_sync - Sync the register cache with the hardware.
350 *
351 * @map: map to configure.
352 *
353 * Any registers that should not be synced should be marked as
354 * volatile. In general drivers can choose not to use the provided
355 * syncing functionality if they so require.
356 *
357 * Return a negative value on failure, 0 on success.
358 */
359int regcache_sync(struct regmap *map)
360{
361 int ret = 0;
362 unsigned int i;
363 const char *name;
364 bool bypass;
365 struct rb_node *node;
366
367 if (WARN_ON(map->cache_type == REGCACHE_NONE))
368 return -EINVAL;
369
370 BUG_ON(!map->cache_ops);
371
372 map->lock(map->lock_arg);
373 /* Remember the initial bypass state */
374 bypass = map->cache_bypass;
375 dev_dbg(map->dev, "Syncing %s cache\n",
376 map->cache_ops->name);
377 name = map->cache_ops->name;
378 trace_regcache_sync(map, name, "start");
379
380 if (!map->cache_dirty)
381 goto out;
382
383 /* Apply any patch first */
384 map->cache_bypass = true;
385 for (i = 0; i < map->patch_regs; i++) {
386 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
387 if (ret != 0) {
388 dev_err(map->dev, "Failed to write %x = %x: %d\n",
389 map->patch[i].reg, map->patch[i].def, ret);
390 goto out;
391 }
392 }
393 map->cache_bypass = false;
394
395 if (map->cache_ops->sync)
396 ret = map->cache_ops->sync(map, 0, map->max_register);
397 else
398 ret = regcache_default_sync(map, 0, map->max_register);
399
400 if (ret == 0)
401 map->cache_dirty = false;
402
403out:
404 /* Restore the bypass state */
405 map->cache_bypass = bypass;
406 map->no_sync_defaults = false;
407
408 /*
409 * If we did any paging with cache bypassed and a cached
410 * paging register then the register and cache state might
411 * have gone out of sync, force writes of all the paging
412 * registers.
413 */
414 rb_for_each(node, NULL, &map->range_tree, rbtree_all) {
415 struct regmap_range_node *this =
416 rb_entry(node, struct regmap_range_node, node);
417
418 /* If there's nothing in the cache there's nothing to sync */
419 if (regcache_read(map, this->selector_reg, &i) != 0)
420 continue;
421
422 ret = _regmap_write(map, this->selector_reg, i);
423 if (ret != 0) {
424 dev_err(map->dev, "Failed to write %x = %x: %d\n",
425 this->selector_reg, i, ret);
426 break;
427 }
428 }
429
430 map->unlock(map->lock_arg);
431
432 regmap_async_complete(map);
433
434 trace_regcache_sync(map, name, "stop");
435
436 return ret;
437}
438EXPORT_SYMBOL_GPL(regcache_sync);
439
440/**
441 * regcache_sync_region - Sync part of the register cache with the hardware.
442 *
443 * @map: map to sync.
444 * @min: first register to sync
445 * @max: last register to sync
446 *
447 * Write all non-default register values in the specified region to
448 * the hardware.
449 *
450 * Return a negative value on failure, 0 on success.
451 */
452int regcache_sync_region(struct regmap *map, unsigned int min,
453 unsigned int max)
454{
455 int ret = 0;
456 const char *name;
457 bool bypass;
458
459 if (WARN_ON(map->cache_type == REGCACHE_NONE))
460 return -EINVAL;
461
462 BUG_ON(!map->cache_ops);
463
464 map->lock(map->lock_arg);
465
466 /* Remember the initial bypass state */
467 bypass = map->cache_bypass;
468
469 name = map->cache_ops->name;
470 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
471
472 trace_regcache_sync(map, name, "start region");
473
474 if (!map->cache_dirty)
475 goto out;
476
477 map->async = true;
478
479 if (map->cache_ops->sync)
480 ret = map->cache_ops->sync(map, min, max);
481 else
482 ret = regcache_default_sync(map, min, max);
483
484out:
485 /* Restore the bypass state */
486 map->cache_bypass = bypass;
487 map->async = false;
488 map->no_sync_defaults = false;
489 map->unlock(map->lock_arg);
490
491 regmap_async_complete(map);
492
493 trace_regcache_sync(map, name, "stop region");
494
495 return ret;
496}
497EXPORT_SYMBOL_GPL(regcache_sync_region);
498
499/**
500 * regcache_drop_region - Discard part of the register cache
501 *
502 * @map: map to operate on
503 * @min: first register to discard
504 * @max: last register to discard
505 *
506 * Discard part of the register cache.
507 *
508 * Return a negative value on failure, 0 on success.
509 */
510int regcache_drop_region(struct regmap *map, unsigned int min,
511 unsigned int max)
512{
513 int ret = 0;
514
515 if (!map->cache_ops || !map->cache_ops->drop)
516 return -EINVAL;
517
518 map->lock(map->lock_arg);
519
520 trace_regcache_drop_region(map, min, max);
521
522 ret = map->cache_ops->drop(map, min, max);
523
524 map->unlock(map->lock_arg);
525
526 return ret;
527}
528EXPORT_SYMBOL_GPL(regcache_drop_region);
529
530/**
531 * regcache_cache_only - Put a register map into cache only mode
532 *
533 * @map: map to configure
534 * @enable: flag if changes should be written to the hardware
535 *
536 * When a register map is marked as cache only writes to the register
537 * map API will only update the register cache, they will not cause
538 * any hardware changes. This is useful for allowing portions of
539 * drivers to act as though the device were functioning as normal when
540 * it is disabled for power saving reasons.
541 */
542void regcache_cache_only(struct regmap *map, bool enable)
543{
544 map->lock(map->lock_arg);
545 WARN_ON(map->cache_type != REGCACHE_NONE &&
546 map->cache_bypass && enable);
547 map->cache_only = enable;
548 trace_regmap_cache_only(map, enable);
549 map->unlock(map->lock_arg);
550}
551EXPORT_SYMBOL_GPL(regcache_cache_only);
552
553/**
554 * regcache_mark_dirty - Indicate that HW registers were reset to default values
555 *
556 * @map: map to mark
557 *
558 * Inform regcache that the device has been powered down or reset, so that
559 * on resume, regcache_sync() knows to write out all non-default values
560 * stored in the cache.
561 *
562 * If this function is not called, regcache_sync() will assume that
563 * the hardware state still matches the cache state, modulo any writes that
564 * happened when cache_only was true.
565 */
566void regcache_mark_dirty(struct regmap *map)
567{
568 map->lock(map->lock_arg);
569 map->cache_dirty = true;
570 map->no_sync_defaults = true;
571 map->unlock(map->lock_arg);
572}
573EXPORT_SYMBOL_GPL(regcache_mark_dirty);
574
575/**
576 * regcache_cache_bypass - Put a register map into cache bypass mode
577 *
578 * @map: map to configure
579 * @enable: flag if changes should not be written to the cache
580 *
581 * When a register map is marked with the cache bypass option, writes
582 * to the register map API will only update the hardware and not
583 * the cache directly. This is useful when syncing the cache back to
584 * the hardware.
585 */
586void regcache_cache_bypass(struct regmap *map, bool enable)
587{
588 map->lock(map->lock_arg);
589 WARN_ON(map->cache_only && enable);
590 map->cache_bypass = enable;
591 trace_regmap_cache_bypass(map, enable);
592 map->unlock(map->lock_arg);
593}
594EXPORT_SYMBOL_GPL(regcache_cache_bypass);
595
596/**
597 * regcache_reg_cached - Check if a register is cached
598 *
599 * @map: map to check
600 * @reg: register to check
601 *
602 * Reports if a register is cached.
603 */
604bool regcache_reg_cached(struct regmap *map, unsigned int reg)
605{
606 unsigned int val;
607 int ret;
608
609 map->lock(map->lock_arg);
610
611 ret = regcache_read(map, reg, &val);
612
613 map->unlock(map->lock_arg);
614
615 return ret == 0;
616}
617EXPORT_SYMBOL_GPL(regcache_reg_cached);
618
619void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
620 unsigned int val)
621{
622 /* Use device native format if possible */
623 if (map->format.format_val) {
624 map->format.format_val(base + (map->cache_word_size * idx),
625 val, 0);
626 return;
627 }
628
629 switch (map->cache_word_size) {
630 case 1: {
631 u8 *cache = base;
632
633 cache[idx] = val;
634 break;
635 }
636 case 2: {
637 u16 *cache = base;
638
639 cache[idx] = val;
640 break;
641 }
642 case 4: {
643 u32 *cache = base;
644
645 cache[idx] = val;
646 break;
647 }
648 default:
649 BUG();
650 }
651}
652
653unsigned int regcache_get_val(struct regmap *map, const void *base,
654 unsigned int idx)
655{
656 if (!base)
657 return -EINVAL;
658
659 /* Use device native format if possible */
660 if (map->format.parse_val)
661 return map->format.parse_val(regcache_get_val_addr(map, base,
662 idx));
663
664 switch (map->cache_word_size) {
665 case 1: {
666 const u8 *cache = base;
667
668 return cache[idx];
669 }
670 case 2: {
671 const u16 *cache = base;
672
673 return cache[idx];
674 }
675 case 4: {
676 const u32 *cache = base;
677
678 return cache[idx];
679 }
680 default:
681 BUG();
682 }
683 /* unreachable */
684 return -1;
685}
686
687static int regcache_default_cmp(const void *a, const void *b)
688{
689 const struct reg_default *_a = a;
690 const struct reg_default *_b = b;
691
692 return _a->reg - _b->reg;
693}
694
695int regcache_lookup_reg(struct regmap *map, unsigned int reg)
696{
697 struct reg_default key;
698 struct reg_default *r;
699
700 key.reg = reg;
701 key.def = 0;
702
703 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
704 sizeof(struct reg_default), regcache_default_cmp);
705
706 if (r)
707 return r - map->reg_defaults;
708 else
709 return -ENOENT;
710}
711
712static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
713{
714 if (!cache_present)
715 return true;
716
717 return test_bit(idx, cache_present);
718}
719
720int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
721{
722 int ret;
723
724 if (!regcache_reg_needs_sync(map, reg, val))
725 return 0;
726
727 map->cache_bypass = true;
728
729 ret = _regmap_write(map, reg, val);
730
731 map->cache_bypass = false;
732
733 if (ret != 0) {
734 dev_err(map->dev, "Unable to sync register %#x. %d\n",
735 reg, ret);
736 return ret;
737 }
738 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
739 reg, val);
740
741 return 0;
742}
743
744static int regcache_sync_block_single(struct regmap *map, void *block,
745 unsigned long *cache_present,
746 unsigned int block_base,
747 unsigned int start, unsigned int end)
748{
749 unsigned int i, regtmp, val;
750 int ret;
751
752 for (i = start; i < end; i++) {
753 regtmp = block_base + (i * map->reg_stride);
754
755 if (!regcache_reg_present(cache_present, i) ||
756 !regmap_writeable(map, regtmp))
757 continue;
758
759 val = regcache_get_val(map, block, i);
760 ret = regcache_sync_val(map, regtmp, val);
761 if (ret != 0)
762 return ret;
763 }
764
765 return 0;
766}
767
768static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
769 unsigned int base, unsigned int cur)
770{
771 size_t val_bytes = map->format.val_bytes;
772 int ret, count;
773
774 if (*data == NULL)
775 return 0;
776
777 count = (cur - base) / map->reg_stride;
778
779 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
780 count * val_bytes, count, base, cur - map->reg_stride);
781
782 map->cache_bypass = true;
783
784 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
785 if (ret)
786 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
787 base, cur - map->reg_stride, ret);
788
789 map->cache_bypass = false;
790
791 *data = NULL;
792
793 return ret;
794}
795
796static int regcache_sync_block_raw(struct regmap *map, void *block,
797 unsigned long *cache_present,
798 unsigned int block_base, unsigned int start,
799 unsigned int end)
800{
801 unsigned int i, val;
802 unsigned int regtmp = 0;
803 unsigned int base = 0;
804 const void *data = NULL;
805 int ret;
806
807 for (i = start; i < end; i++) {
808 regtmp = block_base + (i * map->reg_stride);
809
810 if (!regcache_reg_present(cache_present, i) ||
811 !regmap_writeable(map, regtmp)) {
812 ret = regcache_sync_block_raw_flush(map, &data,
813 base, regtmp);
814 if (ret != 0)
815 return ret;
816 continue;
817 }
818
819 val = regcache_get_val(map, block, i);
820 if (!regcache_reg_needs_sync(map, regtmp, val)) {
821 ret = regcache_sync_block_raw_flush(map, &data,
822 base, regtmp);
823 if (ret != 0)
824 return ret;
825 continue;
826 }
827
828 if (!data) {
829 data = regcache_get_val_addr(map, block, i);
830 base = regtmp;
831 }
832 }
833
834 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
835 map->reg_stride);
836}
837
838int regcache_sync_block(struct regmap *map, void *block,
839 unsigned long *cache_present,
840 unsigned int block_base, unsigned int start,
841 unsigned int end)
842{
843 if (regmap_can_raw_write(map) && !map->use_single_write)
844 return regcache_sync_block_raw(map, block, cache_present,
845 block_base, start, end);
846 else
847 return regcache_sync_block_single(map, block, cache_present,
848 block_base, start, end);
849}