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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/hardirq.h>
11#include <linux/init.h>
12#include <linux/highmem.h>
13#include <linux/kernel.h>
14#include <linux/linkage.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/mm.h>
18#include <linux/module.h>
19#include <linux/bitops.h>
20
21#include <asm/bcache.h>
22#include <asm/bootinfo.h>
23#include <asm/cache.h>
24#include <asm/cacheops.h>
25#include <asm/cpu.h>
26#include <asm/cpu-features.h>
27#include <asm/io.h>
28#include <asm/page.h>
29#include <asm/pgtable.h>
30#include <asm/r4kcache.h>
31#include <asm/sections.h>
32#include <asm/system.h>
33#include <asm/mmu_context.h>
34#include <asm/war.h>
35#include <asm/cacheflush.h> /* for run_uncached() */
36
37
38/*
39 * Special Variant of smp_call_function for use by cache functions:
40 *
41 * o No return value
42 * o collapses to normal function call on UP kernels
43 * o collapses to normal function call on systems with a single shared
44 * primary cache.
45 * o doesn't disable interrupts on the local CPU
46 */
47static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
48{
49 preempt_disable();
50
51#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
52 smp_call_function(func, info, 1);
53#endif
54 func(info);
55 preempt_enable();
56}
57
58#if defined(CONFIG_MIPS_CMP)
59#define cpu_has_safe_index_cacheops 0
60#else
61#define cpu_has_safe_index_cacheops 1
62#endif
63
64/*
65 * Must die.
66 */
67static unsigned long icache_size __read_mostly;
68static unsigned long dcache_size __read_mostly;
69static unsigned long scache_size __read_mostly;
70
71/*
72 * Dummy cache handling routines for machines without boardcaches
73 */
74static void cache_noop(void) {}
75
76static struct bcache_ops no_sc_ops = {
77 .bc_enable = (void *)cache_noop,
78 .bc_disable = (void *)cache_noop,
79 .bc_wback_inv = (void *)cache_noop,
80 .bc_inv = (void *)cache_noop
81};
82
83struct bcache_ops *bcops = &no_sc_ops;
84
85#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
86#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
87
88#define R4600_HIT_CACHEOP_WAR_IMPL \
89do { \
90 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
91 *(volatile unsigned long *)CKSEG1; \
92 if (R4600_V1_HIT_CACHEOP_WAR) \
93 __asm__ __volatile__("nop;nop;nop;nop"); \
94} while (0)
95
96static void (*r4k_blast_dcache_page)(unsigned long addr);
97
98static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
99{
100 R4600_HIT_CACHEOP_WAR_IMPL;
101 blast_dcache32_page(addr);
102}
103
104static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
105{
106 R4600_HIT_CACHEOP_WAR_IMPL;
107 blast_dcache64_page(addr);
108}
109
110static void __cpuinit r4k_blast_dcache_page_setup(void)
111{
112 unsigned long dc_lsize = cpu_dcache_line_size();
113
114 if (dc_lsize == 0)
115 r4k_blast_dcache_page = (void *)cache_noop;
116 else if (dc_lsize == 16)
117 r4k_blast_dcache_page = blast_dcache16_page;
118 else if (dc_lsize == 32)
119 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
120 else if (dc_lsize == 64)
121 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
122}
123
124static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
125
126static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
127{
128 unsigned long dc_lsize = cpu_dcache_line_size();
129
130 if (dc_lsize == 0)
131 r4k_blast_dcache_page_indexed = (void *)cache_noop;
132 else if (dc_lsize == 16)
133 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
134 else if (dc_lsize == 32)
135 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
136 else if (dc_lsize == 64)
137 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
138}
139
140static void (* r4k_blast_dcache)(void);
141
142static void __cpuinit r4k_blast_dcache_setup(void)
143{
144 unsigned long dc_lsize = cpu_dcache_line_size();
145
146 if (dc_lsize == 0)
147 r4k_blast_dcache = (void *)cache_noop;
148 else if (dc_lsize == 16)
149 r4k_blast_dcache = blast_dcache16;
150 else if (dc_lsize == 32)
151 r4k_blast_dcache = blast_dcache32;
152 else if (dc_lsize == 64)
153 r4k_blast_dcache = blast_dcache64;
154}
155
156/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
157#define JUMP_TO_ALIGN(order) \
158 __asm__ __volatile__( \
159 "b\t1f\n\t" \
160 ".align\t" #order "\n\t" \
161 "1:\n\t" \
162 )
163#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
164#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
165
166static inline void blast_r4600_v1_icache32(void)
167{
168 unsigned long flags;
169
170 local_irq_save(flags);
171 blast_icache32();
172 local_irq_restore(flags);
173}
174
175static inline void tx49_blast_icache32(void)
176{
177 unsigned long start = INDEX_BASE;
178 unsigned long end = start + current_cpu_data.icache.waysize;
179 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
180 unsigned long ws_end = current_cpu_data.icache.ways <<
181 current_cpu_data.icache.waybit;
182 unsigned long ws, addr;
183
184 CACHE32_UNROLL32_ALIGN2;
185 /* I'm in even chunk. blast odd chunks */
186 for (ws = 0; ws < ws_end; ws += ws_inc)
187 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
188 cache32_unroll32(addr|ws, Index_Invalidate_I);
189 CACHE32_UNROLL32_ALIGN;
190 /* I'm in odd chunk. blast even chunks */
191 for (ws = 0; ws < ws_end; ws += ws_inc)
192 for (addr = start; addr < end; addr += 0x400 * 2)
193 cache32_unroll32(addr|ws, Index_Invalidate_I);
194}
195
196static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
197{
198 unsigned long flags;
199
200 local_irq_save(flags);
201 blast_icache32_page_indexed(page);
202 local_irq_restore(flags);
203}
204
205static inline void tx49_blast_icache32_page_indexed(unsigned long page)
206{
207 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
208 unsigned long start = INDEX_BASE + (page & indexmask);
209 unsigned long end = start + PAGE_SIZE;
210 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
211 unsigned long ws_end = current_cpu_data.icache.ways <<
212 current_cpu_data.icache.waybit;
213 unsigned long ws, addr;
214
215 CACHE32_UNROLL32_ALIGN2;
216 /* I'm in even chunk. blast odd chunks */
217 for (ws = 0; ws < ws_end; ws += ws_inc)
218 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
219 cache32_unroll32(addr|ws, Index_Invalidate_I);
220 CACHE32_UNROLL32_ALIGN;
221 /* I'm in odd chunk. blast even chunks */
222 for (ws = 0; ws < ws_end; ws += ws_inc)
223 for (addr = start; addr < end; addr += 0x400 * 2)
224 cache32_unroll32(addr|ws, Index_Invalidate_I);
225}
226
227static void (* r4k_blast_icache_page)(unsigned long addr);
228
229static void __cpuinit r4k_blast_icache_page_setup(void)
230{
231 unsigned long ic_lsize = cpu_icache_line_size();
232
233 if (ic_lsize == 0)
234 r4k_blast_icache_page = (void *)cache_noop;
235 else if (ic_lsize == 16)
236 r4k_blast_icache_page = blast_icache16_page;
237 else if (ic_lsize == 32)
238 r4k_blast_icache_page = blast_icache32_page;
239 else if (ic_lsize == 64)
240 r4k_blast_icache_page = blast_icache64_page;
241}
242
243
244static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
245
246static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
247{
248 unsigned long ic_lsize = cpu_icache_line_size();
249
250 if (ic_lsize == 0)
251 r4k_blast_icache_page_indexed = (void *)cache_noop;
252 else if (ic_lsize == 16)
253 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
254 else if (ic_lsize == 32) {
255 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
256 r4k_blast_icache_page_indexed =
257 blast_icache32_r4600_v1_page_indexed;
258 else if (TX49XX_ICACHE_INDEX_INV_WAR)
259 r4k_blast_icache_page_indexed =
260 tx49_blast_icache32_page_indexed;
261 else
262 r4k_blast_icache_page_indexed =
263 blast_icache32_page_indexed;
264 } else if (ic_lsize == 64)
265 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
266}
267
268static void (* r4k_blast_icache)(void);
269
270static void __cpuinit r4k_blast_icache_setup(void)
271{
272 unsigned long ic_lsize = cpu_icache_line_size();
273
274 if (ic_lsize == 0)
275 r4k_blast_icache = (void *)cache_noop;
276 else if (ic_lsize == 16)
277 r4k_blast_icache = blast_icache16;
278 else if (ic_lsize == 32) {
279 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
280 r4k_blast_icache = blast_r4600_v1_icache32;
281 else if (TX49XX_ICACHE_INDEX_INV_WAR)
282 r4k_blast_icache = tx49_blast_icache32;
283 else
284 r4k_blast_icache = blast_icache32;
285 } else if (ic_lsize == 64)
286 r4k_blast_icache = blast_icache64;
287}
288
289static void (* r4k_blast_scache_page)(unsigned long addr);
290
291static void __cpuinit r4k_blast_scache_page_setup(void)
292{
293 unsigned long sc_lsize = cpu_scache_line_size();
294
295 if (scache_size == 0)
296 r4k_blast_scache_page = (void *)cache_noop;
297 else if (sc_lsize == 16)
298 r4k_blast_scache_page = blast_scache16_page;
299 else if (sc_lsize == 32)
300 r4k_blast_scache_page = blast_scache32_page;
301 else if (sc_lsize == 64)
302 r4k_blast_scache_page = blast_scache64_page;
303 else if (sc_lsize == 128)
304 r4k_blast_scache_page = blast_scache128_page;
305}
306
307static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
308
309static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
310{
311 unsigned long sc_lsize = cpu_scache_line_size();
312
313 if (scache_size == 0)
314 r4k_blast_scache_page_indexed = (void *)cache_noop;
315 else if (sc_lsize == 16)
316 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
317 else if (sc_lsize == 32)
318 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
319 else if (sc_lsize == 64)
320 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
321 else if (sc_lsize == 128)
322 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
323}
324
325static void (* r4k_blast_scache)(void);
326
327static void __cpuinit r4k_blast_scache_setup(void)
328{
329 unsigned long sc_lsize = cpu_scache_line_size();
330
331 if (scache_size == 0)
332 r4k_blast_scache = (void *)cache_noop;
333 else if (sc_lsize == 16)
334 r4k_blast_scache = blast_scache16;
335 else if (sc_lsize == 32)
336 r4k_blast_scache = blast_scache32;
337 else if (sc_lsize == 64)
338 r4k_blast_scache = blast_scache64;
339 else if (sc_lsize == 128)
340 r4k_blast_scache = blast_scache128;
341}
342
343static inline void local_r4k___flush_cache_all(void * args)
344{
345#if defined(CONFIG_CPU_LOONGSON2)
346 r4k_blast_scache();
347 return;
348#endif
349 r4k_blast_dcache();
350 r4k_blast_icache();
351
352 switch (current_cpu_type()) {
353 case CPU_R4000SC:
354 case CPU_R4000MC:
355 case CPU_R4400SC:
356 case CPU_R4400MC:
357 case CPU_R10000:
358 case CPU_R12000:
359 case CPU_R14000:
360 r4k_blast_scache();
361 }
362}
363
364static void r4k___flush_cache_all(void)
365{
366 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
367}
368
369static inline int has_valid_asid(const struct mm_struct *mm)
370{
371#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
372 int i;
373
374 for_each_online_cpu(i)
375 if (cpu_context(i, mm))
376 return 1;
377
378 return 0;
379#else
380 return cpu_context(smp_processor_id(), mm);
381#endif
382}
383
384static void r4k__flush_cache_vmap(void)
385{
386 r4k_blast_dcache();
387}
388
389static void r4k__flush_cache_vunmap(void)
390{
391 r4k_blast_dcache();
392}
393
394static inline void local_r4k_flush_cache_range(void * args)
395{
396 struct vm_area_struct *vma = args;
397 int exec = vma->vm_flags & VM_EXEC;
398
399 if (!(has_valid_asid(vma->vm_mm)))
400 return;
401
402 r4k_blast_dcache();
403 if (exec)
404 r4k_blast_icache();
405}
406
407static void r4k_flush_cache_range(struct vm_area_struct *vma,
408 unsigned long start, unsigned long end)
409{
410 int exec = vma->vm_flags & VM_EXEC;
411
412 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
413 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
414}
415
416static inline void local_r4k_flush_cache_mm(void * args)
417{
418 struct mm_struct *mm = args;
419
420 if (!has_valid_asid(mm))
421 return;
422
423 /*
424 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
425 * only flush the primary caches but R10000 and R12000 behave sane ...
426 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
427 * caches, so we can bail out early.
428 */
429 if (current_cpu_type() == CPU_R4000SC ||
430 current_cpu_type() == CPU_R4000MC ||
431 current_cpu_type() == CPU_R4400SC ||
432 current_cpu_type() == CPU_R4400MC) {
433 r4k_blast_scache();
434 return;
435 }
436
437 r4k_blast_dcache();
438}
439
440static void r4k_flush_cache_mm(struct mm_struct *mm)
441{
442 if (!cpu_has_dc_aliases)
443 return;
444
445 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
446}
447
448struct flush_cache_page_args {
449 struct vm_area_struct *vma;
450 unsigned long addr;
451 unsigned long pfn;
452};
453
454static inline void local_r4k_flush_cache_page(void *args)
455{
456 struct flush_cache_page_args *fcp_args = args;
457 struct vm_area_struct *vma = fcp_args->vma;
458 unsigned long addr = fcp_args->addr;
459 struct page *page = pfn_to_page(fcp_args->pfn);
460 int exec = vma->vm_flags & VM_EXEC;
461 struct mm_struct *mm = vma->vm_mm;
462 int map_coherent = 0;
463 pgd_t *pgdp;
464 pud_t *pudp;
465 pmd_t *pmdp;
466 pte_t *ptep;
467 void *vaddr;
468
469 /*
470 * If ownes no valid ASID yet, cannot possibly have gotten
471 * this page into the cache.
472 */
473 if (!has_valid_asid(mm))
474 return;
475
476 addr &= PAGE_MASK;
477 pgdp = pgd_offset(mm, addr);
478 pudp = pud_offset(pgdp, addr);
479 pmdp = pmd_offset(pudp, addr);
480 ptep = pte_offset(pmdp, addr);
481
482 /*
483 * If the page isn't marked valid, the page cannot possibly be
484 * in the cache.
485 */
486 if (!(pte_present(*ptep)))
487 return;
488
489 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
490 vaddr = NULL;
491 else {
492 /*
493 * Use kmap_coherent or kmap_atomic to do flushes for
494 * another ASID than the current one.
495 */
496 map_coherent = (cpu_has_dc_aliases &&
497 page_mapped(page) && !Page_dcache_dirty(page));
498 if (map_coherent)
499 vaddr = kmap_coherent(page, addr);
500 else
501 vaddr = kmap_atomic(page, KM_USER0);
502 addr = (unsigned long)vaddr;
503 }
504
505 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
506 r4k_blast_dcache_page(addr);
507 if (exec && !cpu_icache_snoops_remote_store)
508 r4k_blast_scache_page(addr);
509 }
510 if (exec) {
511 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
512 int cpu = smp_processor_id();
513
514 if (cpu_context(cpu, mm) != 0)
515 drop_mmu_context(mm, cpu);
516 } else
517 r4k_blast_icache_page(addr);
518 }
519
520 if (vaddr) {
521 if (map_coherent)
522 kunmap_coherent();
523 else
524 kunmap_atomic(vaddr, KM_USER0);
525 }
526}
527
528static void r4k_flush_cache_page(struct vm_area_struct *vma,
529 unsigned long addr, unsigned long pfn)
530{
531 struct flush_cache_page_args args;
532
533 args.vma = vma;
534 args.addr = addr;
535 args.pfn = pfn;
536
537 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
538}
539
540static inline void local_r4k_flush_data_cache_page(void * addr)
541{
542 r4k_blast_dcache_page((unsigned long) addr);
543}
544
545static void r4k_flush_data_cache_page(unsigned long addr)
546{
547 if (in_atomic())
548 local_r4k_flush_data_cache_page((void *)addr);
549 else
550 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
551}
552
553struct flush_icache_range_args {
554 unsigned long start;
555 unsigned long end;
556};
557
558static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
559{
560 if (!cpu_has_ic_fills_f_dc) {
561 if (end - start >= dcache_size) {
562 r4k_blast_dcache();
563 } else {
564 R4600_HIT_CACHEOP_WAR_IMPL;
565 protected_blast_dcache_range(start, end);
566 }
567 }
568
569 if (end - start > icache_size)
570 r4k_blast_icache();
571 else
572 protected_blast_icache_range(start, end);
573}
574
575static inline void local_r4k_flush_icache_range_ipi(void *args)
576{
577 struct flush_icache_range_args *fir_args = args;
578 unsigned long start = fir_args->start;
579 unsigned long end = fir_args->end;
580
581 local_r4k_flush_icache_range(start, end);
582}
583
584static void r4k_flush_icache_range(unsigned long start, unsigned long end)
585{
586 struct flush_icache_range_args args;
587
588 args.start = start;
589 args.end = end;
590
591 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
592 instruction_hazard();
593}
594
595#ifdef CONFIG_DMA_NONCOHERENT
596
597static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
598{
599 /* Catch bad driver code */
600 BUG_ON(size == 0);
601
602 if (cpu_has_inclusive_pcaches) {
603 if (size >= scache_size)
604 r4k_blast_scache();
605 else
606 blast_scache_range(addr, addr + size);
607 __sync();
608 return;
609 }
610
611 /*
612 * Either no secondary cache or the available caches don't have the
613 * subset property so we have to flush the primary caches
614 * explicitly
615 */
616 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
617 r4k_blast_dcache();
618 } else {
619 R4600_HIT_CACHEOP_WAR_IMPL;
620 blast_dcache_range(addr, addr + size);
621 }
622
623 bc_wback_inv(addr, size);
624 __sync();
625}
626
627static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
628{
629 /* Catch bad driver code */
630 BUG_ON(size == 0);
631
632 if (cpu_has_inclusive_pcaches) {
633 if (size >= scache_size)
634 r4k_blast_scache();
635 else {
636 unsigned long lsize = cpu_scache_line_size();
637 unsigned long almask = ~(lsize - 1);
638
639 /*
640 * There is no clearly documented alignment requirement
641 * for the cache instruction on MIPS processors and
642 * some processors, among them the RM5200 and RM7000
643 * QED processors will throw an address error for cache
644 * hit ops with insufficient alignment. Solved by
645 * aligning the address to cache line size.
646 */
647 cache_op(Hit_Writeback_Inv_SD, addr & almask);
648 cache_op(Hit_Writeback_Inv_SD,
649 (addr + size - 1) & almask);
650 blast_inv_scache_range(addr, addr + size);
651 }
652 __sync();
653 return;
654 }
655
656 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
657 r4k_blast_dcache();
658 } else {
659 unsigned long lsize = cpu_dcache_line_size();
660 unsigned long almask = ~(lsize - 1);
661
662 R4600_HIT_CACHEOP_WAR_IMPL;
663 cache_op(Hit_Writeback_Inv_D, addr & almask);
664 cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask);
665 blast_inv_dcache_range(addr, addr + size);
666 }
667
668 bc_inv(addr, size);
669 __sync();
670}
671#endif /* CONFIG_DMA_NONCOHERENT */
672
673/*
674 * While we're protected against bad userland addresses we don't care
675 * very much about what happens in that case. Usually a segmentation
676 * fault will dump the process later on anyway ...
677 */
678static void local_r4k_flush_cache_sigtramp(void * arg)
679{
680 unsigned long ic_lsize = cpu_icache_line_size();
681 unsigned long dc_lsize = cpu_dcache_line_size();
682 unsigned long sc_lsize = cpu_scache_line_size();
683 unsigned long addr = (unsigned long) arg;
684
685 R4600_HIT_CACHEOP_WAR_IMPL;
686 if (dc_lsize)
687 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
688 if (!cpu_icache_snoops_remote_store && scache_size)
689 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
690 if (ic_lsize)
691 protected_flush_icache_line(addr & ~(ic_lsize - 1));
692 if (MIPS4K_ICACHE_REFILL_WAR) {
693 __asm__ __volatile__ (
694 ".set push\n\t"
695 ".set noat\n\t"
696 ".set mips3\n\t"
697#ifdef CONFIG_32BIT
698 "la $at,1f\n\t"
699#endif
700#ifdef CONFIG_64BIT
701 "dla $at,1f\n\t"
702#endif
703 "cache %0,($at)\n\t"
704 "nop; nop; nop\n"
705 "1:\n\t"
706 ".set pop"
707 :
708 : "i" (Hit_Invalidate_I));
709 }
710 if (MIPS_CACHE_SYNC_WAR)
711 __asm__ __volatile__ ("sync");
712}
713
714static void r4k_flush_cache_sigtramp(unsigned long addr)
715{
716 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
717}
718
719static void r4k_flush_icache_all(void)
720{
721 if (cpu_has_vtag_icache)
722 r4k_blast_icache();
723}
724
725static inline void rm7k_erratum31(void)
726{
727 const unsigned long ic_lsize = 32;
728 unsigned long addr;
729
730 /* RM7000 erratum #31. The icache is screwed at startup. */
731 write_c0_taglo(0);
732 write_c0_taghi(0);
733
734 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
735 __asm__ __volatile__ (
736 ".set push\n\t"
737 ".set noreorder\n\t"
738 ".set mips3\n\t"
739 "cache\t%1, 0(%0)\n\t"
740 "cache\t%1, 0x1000(%0)\n\t"
741 "cache\t%1, 0x2000(%0)\n\t"
742 "cache\t%1, 0x3000(%0)\n\t"
743 "cache\t%2, 0(%0)\n\t"
744 "cache\t%2, 0x1000(%0)\n\t"
745 "cache\t%2, 0x2000(%0)\n\t"
746 "cache\t%2, 0x3000(%0)\n\t"
747 "cache\t%1, 0(%0)\n\t"
748 "cache\t%1, 0x1000(%0)\n\t"
749 "cache\t%1, 0x2000(%0)\n\t"
750 "cache\t%1, 0x3000(%0)\n\t"
751 ".set pop\n"
752 :
753 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
754 }
755}
756
757static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
758 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
759};
760
761static void __cpuinit probe_pcache(void)
762{
763 struct cpuinfo_mips *c = ¤t_cpu_data;
764 unsigned int config = read_c0_config();
765 unsigned int prid = read_c0_prid();
766 unsigned long config1;
767 unsigned int lsize;
768
769 switch (c->cputype) {
770 case CPU_R4600: /* QED style two way caches? */
771 case CPU_R4700:
772 case CPU_R5000:
773 case CPU_NEVADA:
774 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
775 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
776 c->icache.ways = 2;
777 c->icache.waybit = __ffs(icache_size/2);
778
779 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
780 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
781 c->dcache.ways = 2;
782 c->dcache.waybit= __ffs(dcache_size/2);
783
784 c->options |= MIPS_CPU_CACHE_CDEX_P;
785 break;
786
787 case CPU_R5432:
788 case CPU_R5500:
789 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
790 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
791 c->icache.ways = 2;
792 c->icache.waybit= 0;
793
794 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
795 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
796 c->dcache.ways = 2;
797 c->dcache.waybit = 0;
798
799 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
800 break;
801
802 case CPU_TX49XX:
803 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
804 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
805 c->icache.ways = 4;
806 c->icache.waybit= 0;
807
808 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
809 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
810 c->dcache.ways = 4;
811 c->dcache.waybit = 0;
812
813 c->options |= MIPS_CPU_CACHE_CDEX_P;
814 c->options |= MIPS_CPU_PREFETCH;
815 break;
816
817 case CPU_R4000PC:
818 case CPU_R4000SC:
819 case CPU_R4000MC:
820 case CPU_R4400PC:
821 case CPU_R4400SC:
822 case CPU_R4400MC:
823 case CPU_R4300:
824 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
825 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
826 c->icache.ways = 1;
827 c->icache.waybit = 0; /* doesn't matter */
828
829 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
830 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
831 c->dcache.ways = 1;
832 c->dcache.waybit = 0; /* does not matter */
833
834 c->options |= MIPS_CPU_CACHE_CDEX_P;
835 break;
836
837 case CPU_R10000:
838 case CPU_R12000:
839 case CPU_R14000:
840 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
841 c->icache.linesz = 64;
842 c->icache.ways = 2;
843 c->icache.waybit = 0;
844
845 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
846 c->dcache.linesz = 32;
847 c->dcache.ways = 2;
848 c->dcache.waybit = 0;
849
850 c->options |= MIPS_CPU_PREFETCH;
851 break;
852
853 case CPU_VR4133:
854 write_c0_config(config & ~VR41_CONF_P4K);
855 case CPU_VR4131:
856 /* Workaround for cache instruction bug of VR4131 */
857 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
858 c->processor_id == 0x0c82U) {
859 config |= 0x00400000U;
860 if (c->processor_id == 0x0c80U)
861 config |= VR41_CONF_BP;
862 write_c0_config(config);
863 } else
864 c->options |= MIPS_CPU_CACHE_CDEX_P;
865
866 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
867 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
868 c->icache.ways = 2;
869 c->icache.waybit = __ffs(icache_size/2);
870
871 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
872 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
873 c->dcache.ways = 2;
874 c->dcache.waybit = __ffs(dcache_size/2);
875 break;
876
877 case CPU_VR41XX:
878 case CPU_VR4111:
879 case CPU_VR4121:
880 case CPU_VR4122:
881 case CPU_VR4181:
882 case CPU_VR4181A:
883 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
884 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
885 c->icache.ways = 1;
886 c->icache.waybit = 0; /* doesn't matter */
887
888 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
889 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
890 c->dcache.ways = 1;
891 c->dcache.waybit = 0; /* does not matter */
892
893 c->options |= MIPS_CPU_CACHE_CDEX_P;
894 break;
895
896 case CPU_RM7000:
897 rm7k_erratum31();
898
899 case CPU_RM9000:
900 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
901 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
902 c->icache.ways = 4;
903 c->icache.waybit = __ffs(icache_size / c->icache.ways);
904
905 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
906 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
907 c->dcache.ways = 4;
908 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
909
910#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
911 c->options |= MIPS_CPU_CACHE_CDEX_P;
912#endif
913 c->options |= MIPS_CPU_PREFETCH;
914 break;
915
916 case CPU_LOONGSON2:
917 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
918 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
919 if (prid & 0x3)
920 c->icache.ways = 4;
921 else
922 c->icache.ways = 2;
923 c->icache.waybit = 0;
924
925 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
926 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
927 if (prid & 0x3)
928 c->dcache.ways = 4;
929 else
930 c->dcache.ways = 2;
931 c->dcache.waybit = 0;
932 break;
933
934 default:
935 if (!(config & MIPS_CONF_M))
936 panic("Don't know how to probe P-caches on this cpu.");
937
938 /*
939 * So we seem to be a MIPS32 or MIPS64 CPU
940 * So let's probe the I-cache ...
941 */
942 config1 = read_c0_config1();
943
944 if ((lsize = ((config1 >> 19) & 7)))
945 c->icache.linesz = 2 << lsize;
946 else
947 c->icache.linesz = lsize;
948 c->icache.sets = 64 << ((config1 >> 22) & 7);
949 c->icache.ways = 1 + ((config1 >> 16) & 7);
950
951 icache_size = c->icache.sets *
952 c->icache.ways *
953 c->icache.linesz;
954 c->icache.waybit = __ffs(icache_size/c->icache.ways);
955
956 if (config & 0x8) /* VI bit */
957 c->icache.flags |= MIPS_CACHE_VTAG;
958
959 /*
960 * Now probe the MIPS32 / MIPS64 data cache.
961 */
962 c->dcache.flags = 0;
963
964 if ((lsize = ((config1 >> 10) & 7)))
965 c->dcache.linesz = 2 << lsize;
966 else
967 c->dcache.linesz= lsize;
968 c->dcache.sets = 64 << ((config1 >> 13) & 7);
969 c->dcache.ways = 1 + ((config1 >> 7) & 7);
970
971 dcache_size = c->dcache.sets *
972 c->dcache.ways *
973 c->dcache.linesz;
974 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
975
976 c->options |= MIPS_CPU_PREFETCH;
977 break;
978 }
979
980 /*
981 * Processor configuration sanity check for the R4000SC erratum
982 * #5. With page sizes larger than 32kB there is no possibility
983 * to get a VCE exception anymore so we don't care about this
984 * misconfiguration. The case is rather theoretical anyway;
985 * presumably no vendor is shipping his hardware in the "bad"
986 * configuration.
987 */
988 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
989 !(config & CONF_SC) && c->icache.linesz != 16 &&
990 PAGE_SIZE <= 0x8000)
991 panic("Improper R4000SC processor configuration detected");
992
993 /* compute a couple of other cache variables */
994 c->icache.waysize = icache_size / c->icache.ways;
995 c->dcache.waysize = dcache_size / c->dcache.ways;
996
997 c->icache.sets = c->icache.linesz ?
998 icache_size / (c->icache.linesz * c->icache.ways) : 0;
999 c->dcache.sets = c->dcache.linesz ?
1000 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1001
1002 /*
1003 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1004 * 2-way virtually indexed so normally would suffer from aliases. So
1005 * normally they'd suffer from aliases but magic in the hardware deals
1006 * with that for us so we don't need to take care ourselves.
1007 */
1008 switch (c->cputype) {
1009 case CPU_20KC:
1010 case CPU_25KF:
1011 case CPU_SB1:
1012 case CPU_SB1A:
1013 case CPU_XLR:
1014 c->dcache.flags |= MIPS_CACHE_PINDEX;
1015 break;
1016
1017 case CPU_R10000:
1018 case CPU_R12000:
1019 case CPU_R14000:
1020 break;
1021
1022 case CPU_24K:
1023 case CPU_34K:
1024 case CPU_74K:
1025 case CPU_1004K:
1026 if ((read_c0_config7() & (1 << 16))) {
1027 /* effectively physically indexed dcache,
1028 thus no virtual aliases. */
1029 c->dcache.flags |= MIPS_CACHE_PINDEX;
1030 break;
1031 }
1032 default:
1033 if (c->dcache.waysize > PAGE_SIZE)
1034 c->dcache.flags |= MIPS_CACHE_ALIASES;
1035 }
1036
1037 switch (c->cputype) {
1038 case CPU_20KC:
1039 /*
1040 * Some older 20Kc chips doesn't have the 'VI' bit in
1041 * the config register.
1042 */
1043 c->icache.flags |= MIPS_CACHE_VTAG;
1044 break;
1045
1046 case CPU_ALCHEMY:
1047 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1048 break;
1049 }
1050
1051#ifdef CONFIG_CPU_LOONGSON2
1052 /*
1053 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1054 * one op will act on all 4 ways
1055 */
1056 c->icache.ways = 1;
1057#endif
1058
1059 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1060 icache_size >> 10,
1061 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1062 way_string[c->icache.ways], c->icache.linesz);
1063
1064 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1065 dcache_size >> 10, way_string[c->dcache.ways],
1066 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1067 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1068 "cache aliases" : "no aliases",
1069 c->dcache.linesz);
1070}
1071
1072/*
1073 * If you even _breathe_ on this function, look at the gcc output and make sure
1074 * it does not pop things on and off the stack for the cache sizing loop that
1075 * executes in KSEG1 space or else you will crash and burn badly. You have
1076 * been warned.
1077 */
1078static int __cpuinit probe_scache(void)
1079{
1080 unsigned long flags, addr, begin, end, pow2;
1081 unsigned int config = read_c0_config();
1082 struct cpuinfo_mips *c = ¤t_cpu_data;
1083
1084 if (config & CONF_SC)
1085 return 0;
1086
1087 begin = (unsigned long) &_stext;
1088 begin &= ~((4 * 1024 * 1024) - 1);
1089 end = begin + (4 * 1024 * 1024);
1090
1091 /*
1092 * This is such a bitch, you'd think they would make it easy to do
1093 * this. Away you daemons of stupidity!
1094 */
1095 local_irq_save(flags);
1096
1097 /* Fill each size-multiple cache line with a valid tag. */
1098 pow2 = (64 * 1024);
1099 for (addr = begin; addr < end; addr = (begin + pow2)) {
1100 unsigned long *p = (unsigned long *) addr;
1101 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1102 pow2 <<= 1;
1103 }
1104
1105 /* Load first line with zero (therefore invalid) tag. */
1106 write_c0_taglo(0);
1107 write_c0_taghi(0);
1108 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1109 cache_op(Index_Store_Tag_I, begin);
1110 cache_op(Index_Store_Tag_D, begin);
1111 cache_op(Index_Store_Tag_SD, begin);
1112
1113 /* Now search for the wrap around point. */
1114 pow2 = (128 * 1024);
1115 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1116 cache_op(Index_Load_Tag_SD, addr);
1117 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1118 if (!read_c0_taglo())
1119 break;
1120 pow2 <<= 1;
1121 }
1122 local_irq_restore(flags);
1123 addr -= begin;
1124
1125 scache_size = addr;
1126 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1127 c->scache.ways = 1;
1128 c->dcache.waybit = 0; /* does not matter */
1129
1130 return 1;
1131}
1132
1133#if defined(CONFIG_CPU_LOONGSON2)
1134static void __init loongson2_sc_init(void)
1135{
1136 struct cpuinfo_mips *c = ¤t_cpu_data;
1137
1138 scache_size = 512*1024;
1139 c->scache.linesz = 32;
1140 c->scache.ways = 4;
1141 c->scache.waybit = 0;
1142 c->scache.waysize = scache_size / (c->scache.ways);
1143 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1144 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1145 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1146
1147 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1148}
1149#endif
1150
1151extern int r5k_sc_init(void);
1152extern int rm7k_sc_init(void);
1153extern int mips_sc_init(void);
1154
1155static void __cpuinit setup_scache(void)
1156{
1157 struct cpuinfo_mips *c = ¤t_cpu_data;
1158 unsigned int config = read_c0_config();
1159 int sc_present = 0;
1160
1161 /*
1162 * Do the probing thing on R4000SC and R4400SC processors. Other
1163 * processors don't have a S-cache that would be relevant to the
1164 * Linux memory management.
1165 */
1166 switch (c->cputype) {
1167 case CPU_R4000SC:
1168 case CPU_R4000MC:
1169 case CPU_R4400SC:
1170 case CPU_R4400MC:
1171 sc_present = run_uncached(probe_scache);
1172 if (sc_present)
1173 c->options |= MIPS_CPU_CACHE_CDEX_S;
1174 break;
1175
1176 case CPU_R10000:
1177 case CPU_R12000:
1178 case CPU_R14000:
1179 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1180 c->scache.linesz = 64 << ((config >> 13) & 1);
1181 c->scache.ways = 2;
1182 c->scache.waybit= 0;
1183 sc_present = 1;
1184 break;
1185
1186 case CPU_R5000:
1187 case CPU_NEVADA:
1188#ifdef CONFIG_R5000_CPU_SCACHE
1189 r5k_sc_init();
1190#endif
1191 return;
1192
1193 case CPU_RM7000:
1194 case CPU_RM9000:
1195#ifdef CONFIG_RM7000_CPU_SCACHE
1196 rm7k_sc_init();
1197#endif
1198 return;
1199
1200#if defined(CONFIG_CPU_LOONGSON2)
1201 case CPU_LOONGSON2:
1202 loongson2_sc_init();
1203 return;
1204#endif
1205
1206 default:
1207 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1208 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1209 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1210 c->isa_level == MIPS_CPU_ISA_M64R2) {
1211#ifdef CONFIG_MIPS_CPU_SCACHE
1212 if (mips_sc_init ()) {
1213 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1214 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1215 scache_size >> 10,
1216 way_string[c->scache.ways], c->scache.linesz);
1217 }
1218#else
1219 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1220 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1221#endif
1222 return;
1223 }
1224 sc_present = 0;
1225 }
1226
1227 if (!sc_present)
1228 return;
1229
1230 /* compute a couple of other cache variables */
1231 c->scache.waysize = scache_size / c->scache.ways;
1232
1233 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1234
1235 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1236 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1237
1238 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1239}
1240
1241void au1x00_fixup_config_od(void)
1242{
1243 /*
1244 * c0_config.od (bit 19) was write only (and read as 0)
1245 * on the early revisions of Alchemy SOCs. It disables the bus
1246 * transaction overlapping and needs to be set to fix various errata.
1247 */
1248 switch (read_c0_prid()) {
1249 case 0x00030100: /* Au1000 DA */
1250 case 0x00030201: /* Au1000 HA */
1251 case 0x00030202: /* Au1000 HB */
1252 case 0x01030200: /* Au1500 AB */
1253 /*
1254 * Au1100 errata actually keeps silence about this bit, so we set it
1255 * just in case for those revisions that require it to be set according
1256 * to the (now gone) cpu table.
1257 */
1258 case 0x02030200: /* Au1100 AB */
1259 case 0x02030201: /* Au1100 BA */
1260 case 0x02030202: /* Au1100 BC */
1261 set_c0_config(1 << 19);
1262 break;
1263 }
1264}
1265
1266/* CP0 hazard avoidance. */
1267#define NXP_BARRIER() \
1268 __asm__ __volatile__( \
1269 ".set noreorder\n\t" \
1270 "nop; nop; nop; nop; nop; nop;\n\t" \
1271 ".set reorder\n\t")
1272
1273static void nxp_pr4450_fixup_config(void)
1274{
1275 unsigned long config0;
1276
1277 config0 = read_c0_config();
1278
1279 /* clear all three cache coherency fields */
1280 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1281 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1282 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1283 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1284 write_c0_config(config0);
1285 NXP_BARRIER();
1286}
1287
1288static int __cpuinitdata cca = -1;
1289
1290static int __init cca_setup(char *str)
1291{
1292 get_option(&str, &cca);
1293
1294 return 1;
1295}
1296
1297__setup("cca=", cca_setup);
1298
1299static void __cpuinit coherency_setup(void)
1300{
1301 if (cca < 0 || cca > 7)
1302 cca = read_c0_config() & CONF_CM_CMASK;
1303 _page_cachable_default = cca << _CACHE_SHIFT;
1304
1305 pr_debug("Using cache attribute %d\n", cca);
1306 change_c0_config(CONF_CM_CMASK, cca);
1307
1308 /*
1309 * c0_status.cu=0 specifies that updates by the sc instruction use
1310 * the coherency mode specified by the TLB; 1 means cachable
1311 * coherent update on write will be used. Not all processors have
1312 * this bit and; some wire it to zero, others like Toshiba had the
1313 * silly idea of putting something else there ...
1314 */
1315 switch (current_cpu_type()) {
1316 case CPU_R4000PC:
1317 case CPU_R4000SC:
1318 case CPU_R4000MC:
1319 case CPU_R4400PC:
1320 case CPU_R4400SC:
1321 case CPU_R4400MC:
1322 clear_c0_config(CONF_CU);
1323 break;
1324 /*
1325 * We need to catch the early Alchemy SOCs with
1326 * the write-only co_config.od bit and set it back to one on:
1327 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1328 */
1329 case CPU_ALCHEMY:
1330 au1x00_fixup_config_od();
1331 break;
1332
1333 case PRID_IMP_PR4450:
1334 nxp_pr4450_fixup_config();
1335 break;
1336 }
1337}
1338
1339#if defined(CONFIG_DMA_NONCOHERENT)
1340
1341static int __cpuinitdata coherentio;
1342
1343static int __init setcoherentio(char *str)
1344{
1345 coherentio = 1;
1346
1347 return 1;
1348}
1349
1350__setup("coherentio", setcoherentio);
1351#endif
1352
1353void __cpuinit r4k_cache_init(void)
1354{
1355 extern void build_clear_page(void);
1356 extern void build_copy_page(void);
1357 extern char __weak except_vec2_generic;
1358 extern char __weak except_vec2_sb1;
1359 struct cpuinfo_mips *c = ¤t_cpu_data;
1360
1361 switch (c->cputype) {
1362 case CPU_SB1:
1363 case CPU_SB1A:
1364 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1365 break;
1366
1367 default:
1368 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1369 break;
1370 }
1371
1372 probe_pcache();
1373 setup_scache();
1374
1375 r4k_blast_dcache_page_setup();
1376 r4k_blast_dcache_page_indexed_setup();
1377 r4k_blast_dcache_setup();
1378 r4k_blast_icache_page_setup();
1379 r4k_blast_icache_page_indexed_setup();
1380 r4k_blast_icache_setup();
1381 r4k_blast_scache_page_setup();
1382 r4k_blast_scache_page_indexed_setup();
1383 r4k_blast_scache_setup();
1384
1385 /*
1386 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1387 * This code supports virtually indexed processors and will be
1388 * unnecessarily inefficient on physically indexed processors.
1389 */
1390 if (c->dcache.linesz)
1391 shm_align_mask = max_t( unsigned long,
1392 c->dcache.sets * c->dcache.linesz - 1,
1393 PAGE_SIZE - 1);
1394 else
1395 shm_align_mask = PAGE_SIZE-1;
1396
1397 __flush_cache_vmap = r4k__flush_cache_vmap;
1398 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1399
1400 flush_cache_all = cache_noop;
1401 __flush_cache_all = r4k___flush_cache_all;
1402 flush_cache_mm = r4k_flush_cache_mm;
1403 flush_cache_page = r4k_flush_cache_page;
1404 flush_cache_range = r4k_flush_cache_range;
1405
1406 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1407 flush_icache_all = r4k_flush_icache_all;
1408 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1409 flush_data_cache_page = r4k_flush_data_cache_page;
1410 flush_icache_range = r4k_flush_icache_range;
1411 local_flush_icache_range = local_r4k_flush_icache_range;
1412
1413#if defined(CONFIG_DMA_NONCOHERENT)
1414 if (coherentio) {
1415 _dma_cache_wback_inv = (void *)cache_noop;
1416 _dma_cache_wback = (void *)cache_noop;
1417 _dma_cache_inv = (void *)cache_noop;
1418 } else {
1419 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1420 _dma_cache_wback = r4k_dma_cache_wback_inv;
1421 _dma_cache_inv = r4k_dma_cache_inv;
1422 }
1423#endif
1424
1425 build_clear_page();
1426 build_copy_page();
1427#if !defined(CONFIG_MIPS_CMP)
1428 local_r4k___flush_cache_all(NULL);
1429#endif
1430 coherency_setup();
1431}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/cpu_pm.h>
11#include <linux/hardirq.h>
12#include <linux/init.h>
13#include <linux/highmem.h>
14#include <linux/kernel.h>
15#include <linux/linkage.h>
16#include <linux/preempt.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19#include <linux/mm.h>
20#include <linux/export.h>
21#include <linux/bitops.h>
22#include <linux/dma-map-ops.h> /* for dma_default_coherent */
23
24#include <asm/bcache.h>
25#include <asm/bootinfo.h>
26#include <asm/cache.h>
27#include <asm/cacheops.h>
28#include <asm/cpu.h>
29#include <asm/cpu-features.h>
30#include <asm/cpu-type.h>
31#include <asm/io.h>
32#include <asm/page.h>
33#include <asm/r4kcache.h>
34#include <asm/sections.h>
35#include <asm/mmu_context.h>
36#include <asm/cacheflush.h> /* for run_uncached() */
37#include <asm/traps.h>
38#include <asm/mips-cps.h>
39
40/*
41 * Bits describing what cache ops an SMP callback function may perform.
42 *
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
44 * active_mm must be checked before using user addresses, falling
45 * back to kmap.
46 * R4K_INDEX - Index based cache operations.
47 */
48
49#define R4K_HIT BIT(0)
50#define R4K_INDEX BIT(1)
51
52/**
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
54 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
55 *
56 * Decides whether a cache op needs to be performed on every core in the system.
57 * This may change depending on the @type of cache operation, as well as the set
58 * of online CPUs, so preemption should be disabled by the caller to prevent CPU
59 * hotplug from changing the result.
60 *
61 * Returns: 1 if the cache operation @type should be done on every core in
62 * the system.
63 * 0 if the cache operation @type is globalized and only needs to
64 * be performed on a simple CPU.
65 */
66static inline bool r4k_op_needs_ipi(unsigned int type)
67{
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
69 if (type == R4K_HIT && mips_cm_present())
70 return false;
71
72 /*
73 * Hardware doesn't globalize the required cache ops, so SMP calls may
74 * be needed, but only if there are foreign CPUs (non-siblings with
75 * separate caches).
76 */
77 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
78#ifdef CONFIG_SMP
79 return !cpumask_empty(&cpu_foreign_map[0]);
80#else
81 return false;
82#endif
83}
84
85/*
86 * Special Variant of smp_call_function for use by cache functions:
87 *
88 * o No return value
89 * o collapses to normal function call on UP kernels
90 * o collapses to normal function call on systems with a single shared
91 * primary cache.
92 * o doesn't disable interrupts on the local CPU
93 */
94static inline void r4k_on_each_cpu(unsigned int type,
95 void (*func)(void *info), void *info)
96{
97 preempt_disable();
98 if (r4k_op_needs_ipi(type))
99 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
100 func, info, 1);
101 func(info);
102 preempt_enable();
103}
104
105/*
106 * Must die.
107 */
108static unsigned long icache_size __read_mostly;
109static unsigned long dcache_size __read_mostly;
110static unsigned long vcache_size __read_mostly;
111static unsigned long scache_size __read_mostly;
112
113#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
114#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
115
116#define R4600_HIT_CACHEOP_WAR_IMPL \
117do { \
118 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \
119 cpu_is_r4600_v2_x()) \
120 *(volatile unsigned long *)CKSEG1; \
121 if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
122 __asm__ __volatile__("nop;nop;nop;nop"); \
123} while (0)
124
125static void (*r4k_blast_dcache_page)(unsigned long addr);
126
127static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
128{
129 R4600_HIT_CACHEOP_WAR_IMPL;
130 blast_dcache32_page(addr);
131}
132
133static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
134{
135 blast_dcache64_page(addr);
136}
137
138static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
139{
140 blast_dcache128_page(addr);
141}
142
143static void r4k_blast_dcache_page_setup(void)
144{
145 unsigned long dc_lsize = cpu_dcache_line_size();
146
147 switch (dc_lsize) {
148 case 0:
149 r4k_blast_dcache_page = (void *)cache_noop;
150 break;
151 case 16:
152 r4k_blast_dcache_page = blast_dcache16_page;
153 break;
154 case 32:
155 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
156 break;
157 case 64:
158 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
159 break;
160 case 128:
161 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
162 break;
163 default:
164 break;
165 }
166}
167
168#ifndef CONFIG_EVA
169#define r4k_blast_dcache_user_page r4k_blast_dcache_page
170#else
171
172static void (*r4k_blast_dcache_user_page)(unsigned long addr);
173
174static void r4k_blast_dcache_user_page_setup(void)
175{
176 unsigned long dc_lsize = cpu_dcache_line_size();
177
178 if (dc_lsize == 0)
179 r4k_blast_dcache_user_page = (void *)cache_noop;
180 else if (dc_lsize == 16)
181 r4k_blast_dcache_user_page = blast_dcache16_user_page;
182 else if (dc_lsize == 32)
183 r4k_blast_dcache_user_page = blast_dcache32_user_page;
184 else if (dc_lsize == 64)
185 r4k_blast_dcache_user_page = blast_dcache64_user_page;
186}
187
188#endif
189
190void (* r4k_blast_dcache)(void);
191EXPORT_SYMBOL(r4k_blast_dcache);
192
193static void r4k_blast_dcache_setup(void)
194{
195 unsigned long dc_lsize = cpu_dcache_line_size();
196
197 if (dc_lsize == 0)
198 r4k_blast_dcache = (void *)cache_noop;
199 else if (dc_lsize == 16)
200 r4k_blast_dcache = blast_dcache16;
201 else if (dc_lsize == 32)
202 r4k_blast_dcache = blast_dcache32;
203 else if (dc_lsize == 64)
204 r4k_blast_dcache = blast_dcache64;
205 else if (dc_lsize == 128)
206 r4k_blast_dcache = blast_dcache128;
207}
208
209/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
210#define JUMP_TO_ALIGN(order) \
211 __asm__ __volatile__( \
212 "b\t1f\n\t" \
213 ".align\t" #order "\n\t" \
214 "1:\n\t" \
215 )
216#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
217#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
218
219static inline void blast_r4600_v1_icache32(void)
220{
221 unsigned long flags;
222
223 local_irq_save(flags);
224 blast_icache32();
225 local_irq_restore(flags);
226}
227
228static inline void tx49_blast_icache32(void)
229{
230 unsigned long start = INDEX_BASE;
231 unsigned long end = start + current_cpu_data.icache.waysize;
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
233 unsigned long ws_end = current_cpu_data.icache.ways <<
234 current_cpu_data.icache.waybit;
235 unsigned long ws, addr;
236
237 CACHE32_UNROLL32_ALIGN2;
238 /* I'm in even chunk. blast odd chunks */
239 for (ws = 0; ws < ws_end; ws += ws_inc)
240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
241 cache_unroll(32, kernel_cache, Index_Invalidate_I,
242 addr | ws, 32);
243 CACHE32_UNROLL32_ALIGN;
244 /* I'm in odd chunk. blast even chunks */
245 for (ws = 0; ws < ws_end; ws += ws_inc)
246 for (addr = start; addr < end; addr += 0x400 * 2)
247 cache_unroll(32, kernel_cache, Index_Invalidate_I,
248 addr | ws, 32);
249}
250
251static void (* r4k_blast_icache_page)(unsigned long addr);
252
253static void r4k_blast_icache_page_setup(void)
254{
255 unsigned long ic_lsize = cpu_icache_line_size();
256
257 if (ic_lsize == 0)
258 r4k_blast_icache_page = (void *)cache_noop;
259 else if (ic_lsize == 16)
260 r4k_blast_icache_page = blast_icache16_page;
261 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
262 r4k_blast_icache_page = loongson2_blast_icache32_page;
263 else if (ic_lsize == 32)
264 r4k_blast_icache_page = blast_icache32_page;
265 else if (ic_lsize == 64)
266 r4k_blast_icache_page = blast_icache64_page;
267 else if (ic_lsize == 128)
268 r4k_blast_icache_page = blast_icache128_page;
269}
270
271#ifndef CONFIG_EVA
272#define r4k_blast_icache_user_page r4k_blast_icache_page
273#else
274
275static void (*r4k_blast_icache_user_page)(unsigned long addr);
276
277static void r4k_blast_icache_user_page_setup(void)
278{
279 unsigned long ic_lsize = cpu_icache_line_size();
280
281 if (ic_lsize == 0)
282 r4k_blast_icache_user_page = (void *)cache_noop;
283 else if (ic_lsize == 16)
284 r4k_blast_icache_user_page = blast_icache16_user_page;
285 else if (ic_lsize == 32)
286 r4k_blast_icache_user_page = blast_icache32_user_page;
287 else if (ic_lsize == 64)
288 r4k_blast_icache_user_page = blast_icache64_user_page;
289}
290
291#endif
292
293void (* r4k_blast_icache)(void);
294EXPORT_SYMBOL(r4k_blast_icache);
295
296static void r4k_blast_icache_setup(void)
297{
298 unsigned long ic_lsize = cpu_icache_line_size();
299
300 if (ic_lsize == 0)
301 r4k_blast_icache = (void *)cache_noop;
302 else if (ic_lsize == 16)
303 r4k_blast_icache = blast_icache16;
304 else if (ic_lsize == 32) {
305 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
306 cpu_is_r4600_v1_x())
307 r4k_blast_icache = blast_r4600_v1_icache32;
308 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
309 r4k_blast_icache = tx49_blast_icache32;
310 else if (current_cpu_type() == CPU_LOONGSON2EF)
311 r4k_blast_icache = loongson2_blast_icache32;
312 else
313 r4k_blast_icache = blast_icache32;
314 } else if (ic_lsize == 64)
315 r4k_blast_icache = blast_icache64;
316 else if (ic_lsize == 128)
317 r4k_blast_icache = blast_icache128;
318}
319
320static void (* r4k_blast_scache_page)(unsigned long addr);
321
322static void r4k_blast_scache_page_setup(void)
323{
324 unsigned long sc_lsize = cpu_scache_line_size();
325
326 if (scache_size == 0)
327 r4k_blast_scache_page = (void *)cache_noop;
328 else if (sc_lsize == 16)
329 r4k_blast_scache_page = blast_scache16_page;
330 else if (sc_lsize == 32)
331 r4k_blast_scache_page = blast_scache32_page;
332 else if (sc_lsize == 64)
333 r4k_blast_scache_page = blast_scache64_page;
334 else if (sc_lsize == 128)
335 r4k_blast_scache_page = blast_scache128_page;
336}
337
338static void (* r4k_blast_scache)(void);
339
340static void r4k_blast_scache_setup(void)
341{
342 unsigned long sc_lsize = cpu_scache_line_size();
343
344 if (scache_size == 0)
345 r4k_blast_scache = (void *)cache_noop;
346 else if (sc_lsize == 16)
347 r4k_blast_scache = blast_scache16;
348 else if (sc_lsize == 32)
349 r4k_blast_scache = blast_scache32;
350 else if (sc_lsize == 64)
351 r4k_blast_scache = blast_scache64;
352 else if (sc_lsize == 128)
353 r4k_blast_scache = blast_scache128;
354}
355
356static void (*r4k_blast_scache_node)(long node);
357
358static void r4k_blast_scache_node_setup(void)
359{
360 unsigned long sc_lsize = cpu_scache_line_size();
361
362 if (current_cpu_type() != CPU_LOONGSON64)
363 r4k_blast_scache_node = (void *)cache_noop;
364 else if (sc_lsize == 16)
365 r4k_blast_scache_node = blast_scache16_node;
366 else if (sc_lsize == 32)
367 r4k_blast_scache_node = blast_scache32_node;
368 else if (sc_lsize == 64)
369 r4k_blast_scache_node = blast_scache64_node;
370 else if (sc_lsize == 128)
371 r4k_blast_scache_node = blast_scache128_node;
372}
373
374static inline void local_r4k___flush_cache_all(void * args)
375{
376 switch (current_cpu_type()) {
377 case CPU_LOONGSON2EF:
378 case CPU_R4000SC:
379 case CPU_R4000MC:
380 case CPU_R4400SC:
381 case CPU_R4400MC:
382 case CPU_R10000:
383 case CPU_R12000:
384 case CPU_R14000:
385 case CPU_R16000:
386 /*
387 * These caches are inclusive caches, that is, if something
388 * is not cached in the S-cache, we know it also won't be
389 * in one of the primary caches.
390 */
391 r4k_blast_scache();
392 break;
393
394 case CPU_LOONGSON64:
395 /* Use get_ebase_cpunum() for both NUMA=y/n */
396 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
397 break;
398
399 case CPU_BMIPS5000:
400 r4k_blast_scache();
401 __sync();
402 break;
403
404 default:
405 r4k_blast_dcache();
406 r4k_blast_icache();
407 break;
408 }
409}
410
411static void r4k___flush_cache_all(void)
412{
413 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
414}
415
416/**
417 * has_valid_asid() - Determine if an mm already has an ASID.
418 * @mm: Memory map.
419 * @type: R4K_HIT or R4K_INDEX, type of cache op.
420 *
421 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
422 * of type @type within an r4k_on_each_cpu() call will affect. If
423 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
424 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
425 * will need to be checked.
426 *
427 * Must be called in non-preemptive context.
428 *
429 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
430 * 0 otherwise.
431 */
432static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
433{
434 unsigned int i;
435 const cpumask_t *mask = cpu_present_mask;
436
437 if (cpu_has_mmid)
438 return cpu_context(0, mm) != 0;
439
440 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
441#ifdef CONFIG_SMP
442 /*
443 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
444 * each foreign core, so we only need to worry about siblings.
445 * Otherwise we need to worry about all present CPUs.
446 */
447 if (r4k_op_needs_ipi(type))
448 mask = &cpu_sibling_map[smp_processor_id()];
449#endif
450 for_each_cpu(i, mask)
451 if (cpu_context(i, mm))
452 return 1;
453 return 0;
454}
455
456static void r4k__flush_cache_vmap(void)
457{
458 r4k_blast_dcache();
459}
460
461static void r4k__flush_cache_vunmap(void)
462{
463 r4k_blast_dcache();
464}
465
466/*
467 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
468 * whole caches when vma is executable.
469 */
470static inline void local_r4k_flush_cache_range(void * args)
471{
472 struct vm_area_struct *vma = args;
473 int exec = vma->vm_flags & VM_EXEC;
474
475 if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
476 return;
477
478 /*
479 * If dcache can alias, we must blast it since mapping is changing.
480 * If executable, we must ensure any dirty lines are written back far
481 * enough to be visible to icache.
482 */
483 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
484 r4k_blast_dcache();
485 /* If executable, blast stale lines from icache */
486 if (exec)
487 r4k_blast_icache();
488}
489
490static void r4k_flush_cache_range(struct vm_area_struct *vma,
491 unsigned long start, unsigned long end)
492{
493 int exec = vma->vm_flags & VM_EXEC;
494
495 if (cpu_has_dc_aliases || exec)
496 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
497}
498
499static inline void local_r4k_flush_cache_mm(void * args)
500{
501 struct mm_struct *mm = args;
502
503 if (!has_valid_asid(mm, R4K_INDEX))
504 return;
505
506 /*
507 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
508 * only flush the primary caches but R1x000 behave sane ...
509 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
510 * caches, so we can bail out early.
511 */
512 if (current_cpu_type() == CPU_R4000SC ||
513 current_cpu_type() == CPU_R4000MC ||
514 current_cpu_type() == CPU_R4400SC ||
515 current_cpu_type() == CPU_R4400MC) {
516 r4k_blast_scache();
517 return;
518 }
519
520 r4k_blast_dcache();
521}
522
523static void r4k_flush_cache_mm(struct mm_struct *mm)
524{
525 if (!cpu_has_dc_aliases)
526 return;
527
528 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
529}
530
531struct flush_cache_page_args {
532 struct vm_area_struct *vma;
533 unsigned long addr;
534 unsigned long pfn;
535};
536
537static inline void local_r4k_flush_cache_page(void *args)
538{
539 struct flush_cache_page_args *fcp_args = args;
540 struct vm_area_struct *vma = fcp_args->vma;
541 unsigned long addr = fcp_args->addr;
542 struct page *page = pfn_to_page(fcp_args->pfn);
543 int exec = vma->vm_flags & VM_EXEC;
544 struct mm_struct *mm = vma->vm_mm;
545 int map_coherent = 0;
546 pmd_t *pmdp;
547 pte_t *ptep;
548 void *vaddr;
549
550 /*
551 * If owns no valid ASID yet, cannot possibly have gotten
552 * this page into the cache.
553 */
554 if (!has_valid_asid(mm, R4K_HIT))
555 return;
556
557 addr &= PAGE_MASK;
558 pmdp = pmd_off(mm, addr);
559 ptep = pte_offset_kernel(pmdp, addr);
560
561 /*
562 * If the page isn't marked valid, the page cannot possibly be
563 * in the cache.
564 */
565 if (!(pte_present(*ptep)))
566 return;
567
568 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
569 vaddr = NULL;
570 else {
571 struct folio *folio = page_folio(page);
572 /*
573 * Use kmap_coherent or kmap_atomic to do flushes for
574 * another ASID than the current one.
575 */
576 map_coherent = (cpu_has_dc_aliases &&
577 folio_mapped(folio) &&
578 !folio_test_dcache_dirty(folio));
579 if (map_coherent)
580 vaddr = kmap_coherent(page, addr);
581 else
582 vaddr = kmap_atomic(page);
583 addr = (unsigned long)vaddr;
584 }
585
586 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
587 vaddr ? r4k_blast_dcache_page(addr) :
588 r4k_blast_dcache_user_page(addr);
589 if (exec && !cpu_icache_snoops_remote_store)
590 r4k_blast_scache_page(addr);
591 }
592 if (exec) {
593 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
594 drop_mmu_context(mm);
595 } else
596 vaddr ? r4k_blast_icache_page(addr) :
597 r4k_blast_icache_user_page(addr);
598 }
599
600 if (vaddr) {
601 if (map_coherent)
602 kunmap_coherent();
603 else
604 kunmap_atomic(vaddr);
605 }
606}
607
608static void r4k_flush_cache_page(struct vm_area_struct *vma,
609 unsigned long addr, unsigned long pfn)
610{
611 struct flush_cache_page_args args;
612
613 args.vma = vma;
614 args.addr = addr;
615 args.pfn = pfn;
616
617 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
618}
619
620static inline void local_r4k_flush_data_cache_page(void * addr)
621{
622 r4k_blast_dcache_page((unsigned long) addr);
623}
624
625static void r4k_flush_data_cache_page(unsigned long addr)
626{
627 if (in_atomic())
628 local_r4k_flush_data_cache_page((void *)addr);
629 else
630 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
631 (void *) addr);
632}
633
634struct flush_icache_range_args {
635 unsigned long start;
636 unsigned long end;
637 unsigned int type;
638 bool user;
639};
640
641static inline void __local_r4k_flush_icache_range(unsigned long start,
642 unsigned long end,
643 unsigned int type,
644 bool user)
645{
646 if (!cpu_has_ic_fills_f_dc) {
647 if (type == R4K_INDEX ||
648 (type & R4K_INDEX && end - start >= dcache_size)) {
649 r4k_blast_dcache();
650 } else {
651 R4600_HIT_CACHEOP_WAR_IMPL;
652 if (user)
653 protected_blast_dcache_range(start, end);
654 else
655 blast_dcache_range(start, end);
656 }
657 }
658
659 if (type == R4K_INDEX ||
660 (type & R4K_INDEX && end - start > icache_size))
661 r4k_blast_icache();
662 else {
663 switch (boot_cpu_type()) {
664 case CPU_LOONGSON2EF:
665 protected_loongson2_blast_icache_range(start, end);
666 break;
667
668 default:
669 if (user)
670 protected_blast_icache_range(start, end);
671 else
672 blast_icache_range(start, end);
673 break;
674 }
675 }
676}
677
678static inline void local_r4k_flush_icache_range(unsigned long start,
679 unsigned long end)
680{
681 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
682}
683
684static inline void local_r4k_flush_icache_user_range(unsigned long start,
685 unsigned long end)
686{
687 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
688}
689
690static inline void local_r4k_flush_icache_range_ipi(void *args)
691{
692 struct flush_icache_range_args *fir_args = args;
693 unsigned long start = fir_args->start;
694 unsigned long end = fir_args->end;
695 unsigned int type = fir_args->type;
696 bool user = fir_args->user;
697
698 __local_r4k_flush_icache_range(start, end, type, user);
699}
700
701static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
702 bool user)
703{
704 struct flush_icache_range_args args;
705 unsigned long size, cache_size;
706
707 args.start = start;
708 args.end = end;
709 args.type = R4K_HIT | R4K_INDEX;
710 args.user = user;
711
712 /*
713 * Indexed cache ops require an SMP call.
714 * Consider if that can or should be avoided.
715 */
716 preempt_disable();
717 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
718 /*
719 * If address-based cache ops don't require an SMP call, then
720 * use them exclusively for small flushes.
721 */
722 size = end - start;
723 cache_size = icache_size;
724 if (!cpu_has_ic_fills_f_dc) {
725 size *= 2;
726 cache_size += dcache_size;
727 }
728 if (size <= cache_size)
729 args.type &= ~R4K_INDEX;
730 }
731 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
732 preempt_enable();
733 instruction_hazard();
734}
735
736static void r4k_flush_icache_range(unsigned long start, unsigned long end)
737{
738 return __r4k_flush_icache_range(start, end, false);
739}
740
741static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
742{
743 return __r4k_flush_icache_range(start, end, true);
744}
745
746#ifdef CONFIG_DMA_NONCOHERENT
747
748static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
749{
750 /* Catch bad driver code */
751 if (WARN_ON(size == 0))
752 return;
753
754 preempt_disable();
755 if (cpu_has_inclusive_pcaches) {
756 if (size >= scache_size) {
757 if (current_cpu_type() != CPU_LOONGSON64)
758 r4k_blast_scache();
759 else
760 r4k_blast_scache_node(pa_to_nid(addr));
761 } else {
762 blast_scache_range(addr, addr + size);
763 }
764 preempt_enable();
765 __sync();
766 return;
767 }
768
769 /*
770 * Either no secondary cache or the available caches don't have the
771 * subset property so we have to flush the primary caches
772 * explicitly.
773 * If we would need IPI to perform an INDEX-type operation, then
774 * we have to use the HIT-type alternative as IPI cannot be used
775 * here due to interrupts possibly being disabled.
776 */
777 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
778 r4k_blast_dcache();
779 } else {
780 R4600_HIT_CACHEOP_WAR_IMPL;
781 blast_dcache_range(addr, addr + size);
782 }
783 preempt_enable();
784
785 bc_wback_inv(addr, size);
786 __sync();
787}
788
789static void prefetch_cache_inv(unsigned long addr, unsigned long size)
790{
791 unsigned int linesz = cpu_scache_line_size();
792 unsigned long addr0 = addr, addr1;
793
794 addr0 &= ~(linesz - 1);
795 addr1 = (addr0 + size - 1) & ~(linesz - 1);
796
797 protected_writeback_scache_line(addr0);
798 if (likely(addr1 != addr0))
799 protected_writeback_scache_line(addr1);
800 else
801 return;
802
803 addr0 += linesz;
804 if (likely(addr1 != addr0))
805 protected_writeback_scache_line(addr0);
806 else
807 return;
808
809 addr1 -= linesz;
810 if (likely(addr1 > addr0))
811 protected_writeback_scache_line(addr0);
812}
813
814static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
815{
816 /* Catch bad driver code */
817 if (WARN_ON(size == 0))
818 return;
819
820 preempt_disable();
821
822 if (current_cpu_type() == CPU_BMIPS5000)
823 prefetch_cache_inv(addr, size);
824
825 if (cpu_has_inclusive_pcaches) {
826 if (size >= scache_size) {
827 if (current_cpu_type() != CPU_LOONGSON64)
828 r4k_blast_scache();
829 else
830 r4k_blast_scache_node(pa_to_nid(addr));
831 } else {
832 /*
833 * There is no clearly documented alignment requirement
834 * for the cache instruction on MIPS processors and
835 * some processors, among them the RM5200 and RM7000
836 * QED processors will throw an address error for cache
837 * hit ops with insufficient alignment. Solved by
838 * aligning the address to cache line size.
839 */
840 blast_inv_scache_range(addr, addr + size);
841 }
842 preempt_enable();
843 __sync();
844 return;
845 }
846
847 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
848 r4k_blast_dcache();
849 } else {
850 R4600_HIT_CACHEOP_WAR_IMPL;
851 blast_inv_dcache_range(addr, addr + size);
852 }
853 preempt_enable();
854
855 bc_inv(addr, size);
856 __sync();
857}
858#endif /* CONFIG_DMA_NONCOHERENT */
859
860static void r4k_flush_icache_all(void)
861{
862 if (cpu_has_vtag_icache)
863 r4k_blast_icache();
864}
865
866struct flush_kernel_vmap_range_args {
867 unsigned long vaddr;
868 int size;
869};
870
871static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
872{
873 /*
874 * Aliases only affect the primary caches so don't bother with
875 * S-caches or T-caches.
876 */
877 r4k_blast_dcache();
878}
879
880static inline void local_r4k_flush_kernel_vmap_range(void *args)
881{
882 struct flush_kernel_vmap_range_args *vmra = args;
883 unsigned long vaddr = vmra->vaddr;
884 int size = vmra->size;
885
886 /*
887 * Aliases only affect the primary caches so don't bother with
888 * S-caches or T-caches.
889 */
890 R4600_HIT_CACHEOP_WAR_IMPL;
891 blast_dcache_range(vaddr, vaddr + size);
892}
893
894static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
895{
896 struct flush_kernel_vmap_range_args args;
897
898 args.vaddr = (unsigned long) vaddr;
899 args.size = size;
900
901 if (size >= dcache_size)
902 r4k_on_each_cpu(R4K_INDEX,
903 local_r4k_flush_kernel_vmap_range_index, NULL);
904 else
905 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
906 &args);
907}
908
909static inline void rm7k_erratum31(void)
910{
911 const unsigned long ic_lsize = 32;
912 unsigned long addr;
913
914 /* RM7000 erratum #31. The icache is screwed at startup. */
915 write_c0_taglo(0);
916 write_c0_taghi(0);
917
918 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
919 __asm__ __volatile__ (
920 ".set push\n\t"
921 ".set noreorder\n\t"
922 ".set mips3\n\t"
923 "cache\t%1, 0(%0)\n\t"
924 "cache\t%1, 0x1000(%0)\n\t"
925 "cache\t%1, 0x2000(%0)\n\t"
926 "cache\t%1, 0x3000(%0)\n\t"
927 "cache\t%2, 0(%0)\n\t"
928 "cache\t%2, 0x1000(%0)\n\t"
929 "cache\t%2, 0x2000(%0)\n\t"
930 "cache\t%2, 0x3000(%0)\n\t"
931 "cache\t%1, 0(%0)\n\t"
932 "cache\t%1, 0x1000(%0)\n\t"
933 "cache\t%1, 0x2000(%0)\n\t"
934 "cache\t%1, 0x3000(%0)\n\t"
935 ".set pop\n"
936 :
937 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
938 }
939}
940
941static inline int alias_74k_erratum(struct cpuinfo_mips *c)
942{
943 unsigned int imp = c->processor_id & PRID_IMP_MASK;
944 unsigned int rev = c->processor_id & PRID_REV_MASK;
945 int present = 0;
946
947 /*
948 * Early versions of the 74K do not update the cache tags on a
949 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
950 * aliases. In this case it is better to treat the cache as always
951 * having aliases. Also disable the synonym tag update feature
952 * where available. In this case no opportunistic tag update will
953 * happen where a load causes a virtual address miss but a physical
954 * address hit during a D-cache look-up.
955 */
956 switch (imp) {
957 case PRID_IMP_74K:
958 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
959 present = 1;
960 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
961 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
962 break;
963 case PRID_IMP_1074K:
964 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
965 present = 1;
966 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
967 }
968 break;
969 default:
970 BUG();
971 }
972
973 return present;
974}
975
976static void b5k_instruction_hazard(void)
977{
978 __sync();
979 __sync();
980 __asm__ __volatile__(
981 " nop; nop; nop; nop; nop; nop; nop; nop\n"
982 " nop; nop; nop; nop; nop; nop; nop; nop\n"
983 " nop; nop; nop; nop; nop; nop; nop; nop\n"
984 " nop; nop; nop; nop; nop; nop; nop; nop\n"
985 : : : "memory");
986}
987
988static char *way_string[] = { NULL, "direct mapped", "2-way",
989 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
990 "9-way", "10-way", "11-way", "12-way",
991 "13-way", "14-way", "15-way", "16-way",
992};
993
994static void probe_pcache(void)
995{
996 struct cpuinfo_mips *c = ¤t_cpu_data;
997 unsigned int config = read_c0_config();
998 unsigned int prid = read_c0_prid();
999 int has_74k_erratum = 0;
1000 unsigned long config1;
1001 unsigned int lsize;
1002
1003 switch (current_cpu_type()) {
1004 case CPU_R4600: /* QED style two way caches? */
1005 case CPU_R4700:
1006 case CPU_R5000:
1007 case CPU_NEVADA:
1008 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1009 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1010 c->icache.ways = 2;
1011 c->icache.waybit = __ffs(icache_size/2);
1012
1013 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1014 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1015 c->dcache.ways = 2;
1016 c->dcache.waybit= __ffs(dcache_size/2);
1017
1018 c->options |= MIPS_CPU_CACHE_CDEX_P;
1019 break;
1020
1021 case CPU_R5500:
1022 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1023 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1024 c->icache.ways = 2;
1025 c->icache.waybit= 0;
1026
1027 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1028 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1029 c->dcache.ways = 2;
1030 c->dcache.waybit = 0;
1031
1032 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1033 break;
1034
1035 case CPU_TX49XX:
1036 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1037 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1038 c->icache.ways = 4;
1039 c->icache.waybit= 0;
1040
1041 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1042 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1043 c->dcache.ways = 4;
1044 c->dcache.waybit = 0;
1045
1046 c->options |= MIPS_CPU_CACHE_CDEX_P;
1047 c->options |= MIPS_CPU_PREFETCH;
1048 break;
1049
1050 case CPU_R4000PC:
1051 case CPU_R4000SC:
1052 case CPU_R4000MC:
1053 case CPU_R4400PC:
1054 case CPU_R4400SC:
1055 case CPU_R4400MC:
1056 case CPU_R4300:
1057 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1058 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1059 c->icache.ways = 1;
1060 c->icache.waybit = 0; /* doesn't matter */
1061
1062 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1063 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1064 c->dcache.ways = 1;
1065 c->dcache.waybit = 0; /* does not matter */
1066
1067 c->options |= MIPS_CPU_CACHE_CDEX_P;
1068 break;
1069
1070 case CPU_R10000:
1071 case CPU_R12000:
1072 case CPU_R14000:
1073 case CPU_R16000:
1074 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1075 c->icache.linesz = 64;
1076 c->icache.ways = 2;
1077 c->icache.waybit = 0;
1078
1079 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1080 c->dcache.linesz = 32;
1081 c->dcache.ways = 2;
1082 c->dcache.waybit = 0;
1083
1084 c->options |= MIPS_CPU_PREFETCH;
1085 break;
1086
1087 case CPU_RM7000:
1088 rm7k_erratum31();
1089
1090 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1091 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1092 c->icache.ways = 4;
1093 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1094
1095 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1096 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1097 c->dcache.ways = 4;
1098 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1099
1100 c->options |= MIPS_CPU_CACHE_CDEX_P;
1101 c->options |= MIPS_CPU_PREFETCH;
1102 break;
1103
1104 case CPU_LOONGSON2EF:
1105 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1106 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1107 if (prid & 0x3)
1108 c->icache.ways = 4;
1109 else
1110 c->icache.ways = 2;
1111 c->icache.waybit = 0;
1112
1113 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1114 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1115 if (prid & 0x3)
1116 c->dcache.ways = 4;
1117 else
1118 c->dcache.ways = 2;
1119 c->dcache.waybit = 0;
1120 break;
1121
1122 case CPU_LOONGSON64:
1123 config1 = read_c0_config1();
1124 lsize = (config1 >> 19) & 7;
1125 if (lsize)
1126 c->icache.linesz = 2 << lsize;
1127 else
1128 c->icache.linesz = 0;
1129 c->icache.sets = 64 << ((config1 >> 22) & 7);
1130 c->icache.ways = 1 + ((config1 >> 16) & 7);
1131 icache_size = c->icache.sets *
1132 c->icache.ways *
1133 c->icache.linesz;
1134 c->icache.waybit = 0;
1135
1136 lsize = (config1 >> 10) & 7;
1137 if (lsize)
1138 c->dcache.linesz = 2 << lsize;
1139 else
1140 c->dcache.linesz = 0;
1141 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1142 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1143 dcache_size = c->dcache.sets *
1144 c->dcache.ways *
1145 c->dcache.linesz;
1146 c->dcache.waybit = 0;
1147 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
1148 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1149 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1150 c->options |= MIPS_CPU_PREFETCH;
1151 break;
1152
1153 case CPU_CAVIUM_OCTEON3:
1154 /* For now lie about the number of ways. */
1155 c->icache.linesz = 128;
1156 c->icache.sets = 16;
1157 c->icache.ways = 8;
1158 c->icache.flags |= MIPS_CACHE_VTAG;
1159 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1160
1161 c->dcache.linesz = 128;
1162 c->dcache.ways = 8;
1163 c->dcache.sets = 8;
1164 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1165 c->options |= MIPS_CPU_PREFETCH;
1166 break;
1167
1168 default:
1169 if (!(config & MIPS_CONF_M))
1170 panic("Don't know how to probe P-caches on this cpu.");
1171
1172 /*
1173 * So we seem to be a MIPS32 or MIPS64 CPU
1174 * So let's probe the I-cache ...
1175 */
1176 config1 = read_c0_config1();
1177
1178 lsize = (config1 >> 19) & 7;
1179
1180 /* IL == 7 is reserved */
1181 if (lsize == 7)
1182 panic("Invalid icache line size");
1183
1184 c->icache.linesz = lsize ? 2 << lsize : 0;
1185
1186 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1187 c->icache.ways = 1 + ((config1 >> 16) & 7);
1188
1189 icache_size = c->icache.sets *
1190 c->icache.ways *
1191 c->icache.linesz;
1192 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1193
1194 if (config & MIPS_CONF_VI)
1195 c->icache.flags |= MIPS_CACHE_VTAG;
1196
1197 /*
1198 * Now probe the MIPS32 / MIPS64 data cache.
1199 */
1200 c->dcache.flags = 0;
1201
1202 lsize = (config1 >> 10) & 7;
1203
1204 /* DL == 7 is reserved */
1205 if (lsize == 7)
1206 panic("Invalid dcache line size");
1207
1208 c->dcache.linesz = lsize ? 2 << lsize : 0;
1209
1210 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1211 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1212
1213 dcache_size = c->dcache.sets *
1214 c->dcache.ways *
1215 c->dcache.linesz;
1216 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1217
1218 c->options |= MIPS_CPU_PREFETCH;
1219 break;
1220 }
1221
1222 /*
1223 * Processor configuration sanity check for the R4000SC erratum
1224 * #5. With page sizes larger than 32kB there is no possibility
1225 * to get a VCE exception anymore so we don't care about this
1226 * misconfiguration. The case is rather theoretical anyway;
1227 * presumably no vendor is shipping his hardware in the "bad"
1228 * configuration.
1229 */
1230 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1231 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1232 !(config & CONF_SC) && c->icache.linesz != 16 &&
1233 PAGE_SIZE <= 0x8000)
1234 panic("Improper R4000SC processor configuration detected");
1235
1236 /* compute a couple of other cache variables */
1237 c->icache.waysize = icache_size / c->icache.ways;
1238 c->dcache.waysize = dcache_size / c->dcache.ways;
1239
1240 c->icache.sets = c->icache.linesz ?
1241 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1242 c->dcache.sets = c->dcache.linesz ?
1243 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1244
1245 /*
1246 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1247 * virtually indexed so normally would suffer from aliases. So
1248 * normally they'd suffer from aliases but magic in the hardware deals
1249 * with that for us so we don't need to take care ourselves.
1250 */
1251 switch (current_cpu_type()) {
1252 case CPU_20KC:
1253 case CPU_25KF:
1254 case CPU_I6400:
1255 case CPU_I6500:
1256 case CPU_SB1:
1257 case CPU_SB1A:
1258 c->dcache.flags |= MIPS_CACHE_PINDEX;
1259 break;
1260
1261 case CPU_R10000:
1262 case CPU_R12000:
1263 case CPU_R14000:
1264 case CPU_R16000:
1265 break;
1266
1267 case CPU_74K:
1268 case CPU_1074K:
1269 has_74k_erratum = alias_74k_erratum(c);
1270 fallthrough;
1271 case CPU_M14KC:
1272 case CPU_M14KEC:
1273 case CPU_24K:
1274 case CPU_34K:
1275 case CPU_1004K:
1276 case CPU_INTERAPTIV:
1277 case CPU_P5600:
1278 case CPU_PROAPTIV:
1279 case CPU_M5150:
1280 case CPU_QEMU_GENERIC:
1281 case CPU_P6600:
1282 case CPU_M6250:
1283 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1284 (c->icache.waysize > PAGE_SIZE))
1285 c->icache.flags |= MIPS_CACHE_ALIASES;
1286 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1287 /*
1288 * Effectively physically indexed dcache,
1289 * thus no virtual aliases.
1290 */
1291 c->dcache.flags |= MIPS_CACHE_PINDEX;
1292 break;
1293 }
1294 fallthrough;
1295 default:
1296 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1297 c->dcache.flags |= MIPS_CACHE_ALIASES;
1298 }
1299
1300 /* Physically indexed caches don't suffer from virtual aliasing */
1301 if (c->dcache.flags & MIPS_CACHE_PINDEX)
1302 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1303
1304 /*
1305 * In systems with CM the icache fills from L2 or closer caches, and
1306 * thus sees remote stores without needing to write them back any
1307 * further than that.
1308 */
1309 if (mips_cm_present())
1310 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1311
1312 switch (current_cpu_type()) {
1313 case CPU_20KC:
1314 /*
1315 * Some older 20Kc chips doesn't have the 'VI' bit in
1316 * the config register.
1317 */
1318 c->icache.flags |= MIPS_CACHE_VTAG;
1319 break;
1320
1321 case CPU_ALCHEMY:
1322 case CPU_I6400:
1323 case CPU_I6500:
1324 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1325 break;
1326
1327 case CPU_BMIPS5000:
1328 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1329 /* Cache aliases are handled in hardware; allow HIGHMEM */
1330 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1331 break;
1332
1333 case CPU_LOONGSON2EF:
1334 /*
1335 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1336 * one op will act on all 4 ways
1337 */
1338 c->icache.ways = 1;
1339 }
1340
1341 pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1342 icache_size >> 10,
1343 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1344 way_string[c->icache.ways], c->icache.linesz);
1345
1346 pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1347 dcache_size >> 10, way_string[c->dcache.ways],
1348 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1349 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1350 "cache aliases" : "no aliases",
1351 c->dcache.linesz);
1352}
1353
1354static void probe_vcache(void)
1355{
1356 struct cpuinfo_mips *c = ¤t_cpu_data;
1357 unsigned int config2, lsize;
1358
1359 if (current_cpu_type() != CPU_LOONGSON64)
1360 return;
1361
1362 config2 = read_c0_config2();
1363 if ((lsize = ((config2 >> 20) & 15)))
1364 c->vcache.linesz = 2 << lsize;
1365 else
1366 c->vcache.linesz = lsize;
1367
1368 c->vcache.sets = 64 << ((config2 >> 24) & 15);
1369 c->vcache.ways = 1 + ((config2 >> 16) & 15);
1370
1371 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1372
1373 c->vcache.waybit = 0;
1374 c->vcache.waysize = vcache_size / c->vcache.ways;
1375
1376 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1377 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1378}
1379
1380/*
1381 * If you even _breathe_ on this function, look at the gcc output and make sure
1382 * it does not pop things on and off the stack for the cache sizing loop that
1383 * executes in KSEG1 space or else you will crash and burn badly. You have
1384 * been warned.
1385 */
1386static int probe_scache(void)
1387{
1388 unsigned long flags, addr, begin, end, pow2;
1389 unsigned int config = read_c0_config();
1390 struct cpuinfo_mips *c = ¤t_cpu_data;
1391
1392 if (config & CONF_SC)
1393 return 0;
1394
1395 begin = (unsigned long) &_stext;
1396 begin &= ~((4 * 1024 * 1024) - 1);
1397 end = begin + (4 * 1024 * 1024);
1398
1399 /*
1400 * This is such a bitch, you'd think they would make it easy to do
1401 * this. Away you daemons of stupidity!
1402 */
1403 local_irq_save(flags);
1404
1405 /* Fill each size-multiple cache line with a valid tag. */
1406 pow2 = (64 * 1024);
1407 for (addr = begin; addr < end; addr = (begin + pow2)) {
1408 unsigned long *p = (unsigned long *) addr;
1409 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1410 pow2 <<= 1;
1411 }
1412
1413 /* Load first line with zero (therefore invalid) tag. */
1414 write_c0_taglo(0);
1415 write_c0_taghi(0);
1416 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1417 cache_op(Index_Store_Tag_I, begin);
1418 cache_op(Index_Store_Tag_D, begin);
1419 cache_op(Index_Store_Tag_SD, begin);
1420
1421 /* Now search for the wrap around point. */
1422 pow2 = (128 * 1024);
1423 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1424 cache_op(Index_Load_Tag_SD, addr);
1425 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1426 if (!read_c0_taglo())
1427 break;
1428 pow2 <<= 1;
1429 }
1430 local_irq_restore(flags);
1431 addr -= begin;
1432
1433 scache_size = addr;
1434 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1435 c->scache.ways = 1;
1436 c->scache.waybit = 0; /* does not matter */
1437
1438 return 1;
1439}
1440
1441static void loongson2_sc_init(void)
1442{
1443 struct cpuinfo_mips *c = ¤t_cpu_data;
1444
1445 scache_size = 512*1024;
1446 c->scache.linesz = 32;
1447 c->scache.ways = 4;
1448 c->scache.waybit = 0;
1449 c->scache.waysize = scache_size / (c->scache.ways);
1450 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1451 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1452 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1453
1454 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1455}
1456
1457static void loongson3_sc_init(void)
1458{
1459 struct cpuinfo_mips *c = ¤t_cpu_data;
1460 unsigned int config2, lsize;
1461
1462 config2 = read_c0_config2();
1463 lsize = (config2 >> 4) & 15;
1464 if (lsize)
1465 c->scache.linesz = 2 << lsize;
1466 else
1467 c->scache.linesz = 0;
1468 c->scache.sets = 64 << ((config2 >> 8) & 15);
1469 c->scache.ways = 1 + (config2 & 15);
1470
1471 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1472 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1473 c->scache.sets *= 2;
1474 else
1475 c->scache.sets *= 4;
1476
1477 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
1478
1479 c->scache.waybit = 0;
1480 c->scache.waysize = scache_size / c->scache.ways;
1481 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1482 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1483 if (scache_size)
1484 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1485 return;
1486}
1487
1488static void setup_scache(void)
1489{
1490 struct cpuinfo_mips *c = ¤t_cpu_data;
1491 unsigned int config = read_c0_config();
1492 int sc_present = 0;
1493
1494 /*
1495 * Do the probing thing on R4000SC and R4400SC processors. Other
1496 * processors don't have a S-cache that would be relevant to the
1497 * Linux memory management.
1498 */
1499 switch (current_cpu_type()) {
1500 case CPU_R4000SC:
1501 case CPU_R4000MC:
1502 case CPU_R4400SC:
1503 case CPU_R4400MC:
1504 sc_present = run_uncached(probe_scache);
1505 if (sc_present)
1506 c->options |= MIPS_CPU_CACHE_CDEX_S;
1507 break;
1508
1509 case CPU_R10000:
1510 case CPU_R12000:
1511 case CPU_R14000:
1512 case CPU_R16000:
1513 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1514 c->scache.linesz = 64 << ((config >> 13) & 1);
1515 c->scache.ways = 2;
1516 c->scache.waybit= 0;
1517 sc_present = 1;
1518 break;
1519
1520 case CPU_R5000:
1521 case CPU_NEVADA:
1522#ifdef CONFIG_R5000_CPU_SCACHE
1523 r5k_sc_init();
1524#endif
1525 return;
1526
1527 case CPU_RM7000:
1528#ifdef CONFIG_RM7000_CPU_SCACHE
1529 rm7k_sc_init();
1530#endif
1531 return;
1532
1533 case CPU_LOONGSON2EF:
1534 loongson2_sc_init();
1535 return;
1536
1537 case CPU_LOONGSON64:
1538 loongson3_sc_init();
1539 return;
1540
1541 case CPU_CAVIUM_OCTEON3:
1542 /* don't need to worry about L2, fully coherent */
1543 return;
1544
1545 default:
1546 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1547 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1548 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1549 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1550#ifdef CONFIG_MIPS_CPU_SCACHE
1551 if (mips_sc_init ()) {
1552 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1553 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1554 scache_size >> 10,
1555 way_string[c->scache.ways], c->scache.linesz);
1556
1557 if (current_cpu_type() == CPU_BMIPS5000)
1558 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1559 }
1560
1561#else
1562 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1563 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1564#endif
1565 return;
1566 }
1567 sc_present = 0;
1568 }
1569
1570 if (!sc_present)
1571 return;
1572
1573 /* compute a couple of other cache variables */
1574 c->scache.waysize = scache_size / c->scache.ways;
1575
1576 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1577
1578 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1579 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1580
1581 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1582}
1583
1584void au1x00_fixup_config_od(void)
1585{
1586 /*
1587 * c0_config.od (bit 19) was write only (and read as 0)
1588 * on the early revisions of Alchemy SOCs. It disables the bus
1589 * transaction overlapping and needs to be set to fix various errata.
1590 */
1591 switch (read_c0_prid()) {
1592 case 0x00030100: /* Au1000 DA */
1593 case 0x00030201: /* Au1000 HA */
1594 case 0x00030202: /* Au1000 HB */
1595 case 0x01030200: /* Au1500 AB */
1596 /*
1597 * Au1100 errata actually keeps silence about this bit, so we set it
1598 * just in case for those revisions that require it to be set according
1599 * to the (now gone) cpu table.
1600 */
1601 case 0x02030200: /* Au1100 AB */
1602 case 0x02030201: /* Au1100 BA */
1603 case 0x02030202: /* Au1100 BC */
1604 set_c0_config(1 << 19);
1605 break;
1606 }
1607}
1608
1609/* CP0 hazard avoidance. */
1610#define NXP_BARRIER() \
1611 __asm__ __volatile__( \
1612 ".set noreorder\n\t" \
1613 "nop; nop; nop; nop; nop; nop;\n\t" \
1614 ".set reorder\n\t")
1615
1616static void nxp_pr4450_fixup_config(void)
1617{
1618 unsigned long config0;
1619
1620 config0 = read_c0_config();
1621
1622 /* clear all three cache coherency fields */
1623 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1624 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1625 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1626 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1627 write_c0_config(config0);
1628 NXP_BARRIER();
1629}
1630
1631static int cca = -1;
1632
1633static int __init cca_setup(char *str)
1634{
1635 get_option(&str, &cca);
1636
1637 return 0;
1638}
1639
1640early_param("cca", cca_setup);
1641
1642static void coherency_setup(void)
1643{
1644 if (cca < 0 || cca > 7)
1645 cca = read_c0_config() & CONF_CM_CMASK;
1646 _page_cachable_default = cca << _CACHE_SHIFT;
1647
1648 pr_debug("Using cache attribute %d\n", cca);
1649 change_c0_config(CONF_CM_CMASK, cca);
1650
1651 /*
1652 * c0_status.cu=0 specifies that updates by the sc instruction use
1653 * the coherency mode specified by the TLB; 1 means cacheable
1654 * coherent update on write will be used. Not all processors have
1655 * this bit and; some wire it to zero, others like Toshiba had the
1656 * silly idea of putting something else there ...
1657 */
1658 switch (current_cpu_type()) {
1659 case CPU_R4000PC:
1660 case CPU_R4000SC:
1661 case CPU_R4000MC:
1662 case CPU_R4400PC:
1663 case CPU_R4400SC:
1664 case CPU_R4400MC:
1665 clear_c0_config(CONF_CU);
1666 break;
1667 /*
1668 * We need to catch the early Alchemy SOCs with
1669 * the write-only co_config.od bit and set it back to one on:
1670 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1671 */
1672 case CPU_ALCHEMY:
1673 au1x00_fixup_config_od();
1674 break;
1675
1676 case PRID_IMP_PR4450:
1677 nxp_pr4450_fixup_config();
1678 break;
1679 }
1680}
1681
1682static void r4k_cache_error_setup(void)
1683{
1684 extern char __weak except_vec2_generic;
1685 extern char __weak except_vec2_sb1;
1686
1687 switch (current_cpu_type()) {
1688 case CPU_SB1:
1689 case CPU_SB1A:
1690 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1691 break;
1692
1693 default:
1694 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1695 break;
1696 }
1697}
1698
1699void r4k_cache_init(void)
1700{
1701 extern void build_clear_page(void);
1702 extern void build_copy_page(void);
1703 struct cpuinfo_mips *c = ¤t_cpu_data;
1704
1705 probe_pcache();
1706 probe_vcache();
1707 setup_scache();
1708
1709 r4k_blast_dcache_page_setup();
1710 r4k_blast_dcache_setup();
1711 r4k_blast_icache_page_setup();
1712 r4k_blast_icache_setup();
1713 r4k_blast_scache_page_setup();
1714 r4k_blast_scache_setup();
1715 r4k_blast_scache_node_setup();
1716#ifdef CONFIG_EVA
1717 r4k_blast_dcache_user_page_setup();
1718 r4k_blast_icache_user_page_setup();
1719#endif
1720
1721 /*
1722 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1723 * This code supports virtually indexed processors and will be
1724 * unnecessarily inefficient on physically indexed processors.
1725 */
1726 if (c->dcache.linesz && cpu_has_dc_aliases)
1727 shm_align_mask = max_t( unsigned long,
1728 c->dcache.sets * c->dcache.linesz - 1,
1729 PAGE_SIZE - 1);
1730 else
1731 shm_align_mask = PAGE_SIZE-1;
1732
1733 __flush_cache_vmap = r4k__flush_cache_vmap;
1734 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1735
1736 flush_cache_all = cache_noop;
1737 __flush_cache_all = r4k___flush_cache_all;
1738 flush_cache_mm = r4k_flush_cache_mm;
1739 flush_cache_page = r4k_flush_cache_page;
1740 flush_cache_range = r4k_flush_cache_range;
1741
1742 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1743
1744 flush_icache_all = r4k_flush_icache_all;
1745 flush_data_cache_page = r4k_flush_data_cache_page;
1746 flush_icache_range = r4k_flush_icache_range;
1747 local_flush_icache_range = local_r4k_flush_icache_range;
1748 __flush_icache_user_range = r4k_flush_icache_user_range;
1749 __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1750
1751#ifdef CONFIG_DMA_NONCOHERENT
1752 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1753 _dma_cache_wback = r4k_dma_cache_wback_inv;
1754 _dma_cache_inv = r4k_dma_cache_inv;
1755#endif /* CONFIG_DMA_NONCOHERENT */
1756
1757 build_clear_page();
1758 build_copy_page();
1759
1760 /*
1761 * We want to run CMP kernels on core with and without coherent
1762 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1763 * or not to flush caches.
1764 */
1765 local_r4k___flush_cache_all(NULL);
1766
1767 coherency_setup();
1768 board_cache_error_setup = r4k_cache_error_setup;
1769
1770 /*
1771 * Per-CPU overrides
1772 */
1773 switch (current_cpu_type()) {
1774 case CPU_BMIPS4350:
1775 case CPU_BMIPS4380:
1776 /* No IPI is needed because all CPUs share the same D$ */
1777 flush_data_cache_page = r4k_blast_dcache_page;
1778 break;
1779 case CPU_BMIPS5000:
1780 /* We lose our superpowers if L2 is disabled */
1781 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1782 break;
1783
1784 /* I$ fills from D$ just by emptying the write buffers */
1785 flush_cache_page = (void *)b5k_instruction_hazard;
1786 flush_cache_range = (void *)b5k_instruction_hazard;
1787 flush_data_cache_page = (void *)b5k_instruction_hazard;
1788 flush_icache_range = (void *)b5k_instruction_hazard;
1789 local_flush_icache_range = (void *)b5k_instruction_hazard;
1790
1791
1792 /* Optimization: an L2 flush implicitly flushes the L1 */
1793 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1794 break;
1795 case CPU_LOONGSON64:
1796 /* Loongson-3 maintains cache coherency by hardware */
1797 __flush_cache_all = cache_noop;
1798 __flush_cache_vmap = cache_noop;
1799 __flush_cache_vunmap = cache_noop;
1800 __flush_kernel_vmap_range = (void *)cache_noop;
1801 flush_cache_mm = (void *)cache_noop;
1802 flush_cache_page = (void *)cache_noop;
1803 flush_cache_range = (void *)cache_noop;
1804 flush_icache_all = (void *)cache_noop;
1805 flush_data_cache_page = (void *)cache_noop;
1806 break;
1807 }
1808}
1809
1810static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1811 void *v)
1812{
1813 switch (cmd) {
1814 case CPU_PM_ENTER_FAILED:
1815 case CPU_PM_EXIT:
1816 coherency_setup();
1817 break;
1818 }
1819
1820 return NOTIFY_OK;
1821}
1822
1823static struct notifier_block r4k_cache_pm_notifier_block = {
1824 .notifier_call = r4k_cache_pm_notifier,
1825};
1826
1827static int __init r4k_cache_init_pm(void)
1828{
1829 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1830}
1831arch_initcall(r4k_cache_init_pm);