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1/*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * To do:
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
15 */
16
17#include <linux/kernel.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <asm/mach-types.h> /* for machine_is_* */
22
23#include <plat/clock.h>
24#include <plat/cpu.h>
25#include <plat/clkdev_omap.h>
26#include <plat/usb.h> /* for OTG_BASE */
27
28#include "clock.h"
29
30/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
31#define IDL_CLKOUT_ARM_SHIFT 12
32#define IDLTIM_ARM_SHIFT 9
33#define IDLAPI_ARM_SHIFT 8
34#define IDLIF_ARM_SHIFT 6
35#define IDLLB_ARM_SHIFT 4 /* undocumented? */
36#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
37#define IDLPER_ARM_SHIFT 2
38#define IDLXORP_ARM_SHIFT 1
39#define IDLWDT_ARM_SHIFT 0
40
41/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
42#define CONF_MOD_UART3_CLK_MODE_R 31
43#define CONF_MOD_UART2_CLK_MODE_R 30
44#define CONF_MOD_UART1_CLK_MODE_R 29
45#define CONF_MOD_MMC_SD_CLK_REQ_R 23
46#define CONF_MOD_MCBSP3_AUXON 20
47
48/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
49#define CONF_MOD_SOSSI_CLK_EN_R 16
50
51/* Some OTG_SYSCON_2-specific bit fields */
52#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
53
54/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
55#define SOFT_MMC2_DPLL_REQ_SHIFT 13
56#define SOFT_MMC_DPLL_REQ_SHIFT 12
57#define SOFT_UART3_DPLL_REQ_SHIFT 11
58#define SOFT_UART2_DPLL_REQ_SHIFT 10
59#define SOFT_UART1_DPLL_REQ_SHIFT 9
60#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
61#define SOFT_CAM_DPLL_REQ_SHIFT 7
62#define SOFT_COM_MCKO_REQ_SHIFT 6
63#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
64#define USB_REQ_EN_SHIFT 4
65#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
66#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
67#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
68#define SOFT_DPLL_REQ_SHIFT 0
69
70/*
71 * Omap1 clocks
72 */
73
74static struct clk ck_ref = {
75 .name = "ck_ref",
76 .ops = &clkops_null,
77 .rate = 12000000,
78};
79
80static struct clk ck_dpll1 = {
81 .name = "ck_dpll1",
82 .ops = &clkops_null,
83 .parent = &ck_ref,
84};
85
86/*
87 * FIXME: This clock seems to be necessary but no-one has asked for its
88 * activation. [ FIX: SoSSI, SSR ]
89 */
90static struct arm_idlect1_clk ck_dpll1out = {
91 .clk = {
92 .name = "ck_dpll1out",
93 .ops = &clkops_generic,
94 .parent = &ck_dpll1,
95 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
96 ENABLE_ON_INIT,
97 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
98 .enable_bit = EN_CKOUT_ARM,
99 .recalc = &followparent_recalc,
100 },
101 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
102};
103
104static struct clk sossi_ck = {
105 .name = "ck_sossi",
106 .ops = &clkops_generic,
107 .parent = &ck_dpll1out.clk,
108 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
109 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
111 .recalc = &omap1_sossi_recalc,
112 .set_rate = &omap1_set_sossi_rate,
113};
114
115static struct clk arm_ck = {
116 .name = "arm_ck",
117 .ops = &clkops_null,
118 .parent = &ck_dpll1,
119 .rate_offset = CKCTL_ARMDIV_OFFSET,
120 .recalc = &omap1_ckctl_recalc,
121 .round_rate = omap1_clk_round_rate_ckctl_arm,
122 .set_rate = omap1_clk_set_rate_ckctl_arm,
123};
124
125static struct arm_idlect1_clk armper_ck = {
126 .clk = {
127 .name = "armper_ck",
128 .ops = &clkops_generic,
129 .parent = &ck_dpll1,
130 .flags = CLOCK_IDLE_CONTROL,
131 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
132 .enable_bit = EN_PERCK,
133 .rate_offset = CKCTL_PERDIV_OFFSET,
134 .recalc = &omap1_ckctl_recalc,
135 .round_rate = omap1_clk_round_rate_ckctl_arm,
136 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 },
138 .idlect_shift = IDLPER_ARM_SHIFT,
139};
140
141/*
142 * FIXME: This clock seems to be necessary but no-one has asked for its
143 * activation. [ GPIO code for 1510 ]
144 */
145static struct clk arm_gpio_ck = {
146 .name = "ick",
147 .ops = &clkops_generic,
148 .parent = &ck_dpll1,
149 .flags = ENABLE_ON_INIT,
150 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
151 .enable_bit = EN_GPIOCK,
152 .recalc = &followparent_recalc,
153};
154
155static struct arm_idlect1_clk armxor_ck = {
156 .clk = {
157 .name = "armxor_ck",
158 .ops = &clkops_generic,
159 .parent = &ck_ref,
160 .flags = CLOCK_IDLE_CONTROL,
161 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
162 .enable_bit = EN_XORPCK,
163 .recalc = &followparent_recalc,
164 },
165 .idlect_shift = IDLXORP_ARM_SHIFT,
166};
167
168static struct arm_idlect1_clk armtim_ck = {
169 .clk = {
170 .name = "armtim_ck",
171 .ops = &clkops_generic,
172 .parent = &ck_ref,
173 .flags = CLOCK_IDLE_CONTROL,
174 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
175 .enable_bit = EN_TIMCK,
176 .recalc = &followparent_recalc,
177 },
178 .idlect_shift = IDLTIM_ARM_SHIFT,
179};
180
181static struct arm_idlect1_clk armwdt_ck = {
182 .clk = {
183 .name = "armwdt_ck",
184 .ops = &clkops_generic,
185 .parent = &ck_ref,
186 .flags = CLOCK_IDLE_CONTROL,
187 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
188 .enable_bit = EN_WDTCK,
189 .fixed_div = 14,
190 .recalc = &omap_fixed_divisor_recalc,
191 },
192 .idlect_shift = IDLWDT_ARM_SHIFT,
193};
194
195static struct clk arminth_ck16xx = {
196 .name = "arminth_ck",
197 .ops = &clkops_null,
198 .parent = &arm_ck,
199 .recalc = &followparent_recalc,
200 /* Note: On 16xx the frequency can be divided by 2 by programming
201 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
202 *
203 * 1510 version is in TC clocks.
204 */
205};
206
207static struct clk dsp_ck = {
208 .name = "dsp_ck",
209 .ops = &clkops_generic,
210 .parent = &ck_dpll1,
211 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
212 .enable_bit = EN_DSPCK,
213 .rate_offset = CKCTL_DSPDIV_OFFSET,
214 .recalc = &omap1_ckctl_recalc,
215 .round_rate = omap1_clk_round_rate_ckctl_arm,
216 .set_rate = omap1_clk_set_rate_ckctl_arm,
217};
218
219static struct clk dspmmu_ck = {
220 .name = "dspmmu_ck",
221 .ops = &clkops_null,
222 .parent = &ck_dpll1,
223 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
224 .recalc = &omap1_ckctl_recalc,
225 .round_rate = omap1_clk_round_rate_ckctl_arm,
226 .set_rate = omap1_clk_set_rate_ckctl_arm,
227};
228
229static struct clk dspper_ck = {
230 .name = "dspper_ck",
231 .ops = &clkops_dspck,
232 .parent = &ck_dpll1,
233 .enable_reg = DSP_IDLECT2,
234 .enable_bit = EN_PERCK,
235 .rate_offset = CKCTL_PERDIV_OFFSET,
236 .recalc = &omap1_ckctl_recalc_dsp_domain,
237 .round_rate = omap1_clk_round_rate_ckctl_arm,
238 .set_rate = &omap1_clk_set_rate_dsp_domain,
239};
240
241static struct clk dspxor_ck = {
242 .name = "dspxor_ck",
243 .ops = &clkops_dspck,
244 .parent = &ck_ref,
245 .enable_reg = DSP_IDLECT2,
246 .enable_bit = EN_XORPCK,
247 .recalc = &followparent_recalc,
248};
249
250static struct clk dsptim_ck = {
251 .name = "dsptim_ck",
252 .ops = &clkops_dspck,
253 .parent = &ck_ref,
254 .enable_reg = DSP_IDLECT2,
255 .enable_bit = EN_DSPTIMCK,
256 .recalc = &followparent_recalc,
257};
258
259static struct arm_idlect1_clk tc_ck = {
260 .clk = {
261 .name = "tc_ck",
262 .ops = &clkops_null,
263 .parent = &ck_dpll1,
264 .flags = CLOCK_IDLE_CONTROL,
265 .rate_offset = CKCTL_TCDIV_OFFSET,
266 .recalc = &omap1_ckctl_recalc,
267 .round_rate = omap1_clk_round_rate_ckctl_arm,
268 .set_rate = omap1_clk_set_rate_ckctl_arm,
269 },
270 .idlect_shift = IDLIF_ARM_SHIFT,
271};
272
273static struct clk arminth_ck1510 = {
274 .name = "arminth_ck",
275 .ops = &clkops_null,
276 .parent = &tc_ck.clk,
277 .recalc = &followparent_recalc,
278 /* Note: On 1510 the frequency follows TC_CK
279 *
280 * 16xx version is in MPU clocks.
281 */
282};
283
284static struct clk tipb_ck = {
285 /* No-idle controlled by "tc_ck" */
286 .name = "tipb_ck",
287 .ops = &clkops_null,
288 .parent = &tc_ck.clk,
289 .recalc = &followparent_recalc,
290};
291
292static struct clk l3_ocpi_ck = {
293 /* No-idle controlled by "tc_ck" */
294 .name = "l3_ocpi_ck",
295 .ops = &clkops_generic,
296 .parent = &tc_ck.clk,
297 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
298 .enable_bit = EN_OCPI_CK,
299 .recalc = &followparent_recalc,
300};
301
302static struct clk tc1_ck = {
303 .name = "tc1_ck",
304 .ops = &clkops_generic,
305 .parent = &tc_ck.clk,
306 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
307 .enable_bit = EN_TC1_CK,
308 .recalc = &followparent_recalc,
309};
310
311/*
312 * FIXME: This clock seems to be necessary but no-one has asked for its
313 * activation. [ pm.c (SRAM), CCP, Camera ]
314 */
315static struct clk tc2_ck = {
316 .name = "tc2_ck",
317 .ops = &clkops_generic,
318 .parent = &tc_ck.clk,
319 .flags = ENABLE_ON_INIT,
320 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
321 .enable_bit = EN_TC2_CK,
322 .recalc = &followparent_recalc,
323};
324
325static struct clk dma_ck = {
326 /* No-idle controlled by "tc_ck" */
327 .name = "dma_ck",
328 .ops = &clkops_null,
329 .parent = &tc_ck.clk,
330 .recalc = &followparent_recalc,
331};
332
333static struct clk dma_lcdfree_ck = {
334 .name = "dma_lcdfree_ck",
335 .ops = &clkops_null,
336 .parent = &tc_ck.clk,
337 .recalc = &followparent_recalc,
338};
339
340static struct arm_idlect1_clk api_ck = {
341 .clk = {
342 .name = "api_ck",
343 .ops = &clkops_generic,
344 .parent = &tc_ck.clk,
345 .flags = CLOCK_IDLE_CONTROL,
346 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
347 .enable_bit = EN_APICK,
348 .recalc = &followparent_recalc,
349 },
350 .idlect_shift = IDLAPI_ARM_SHIFT,
351};
352
353static struct arm_idlect1_clk lb_ck = {
354 .clk = {
355 .name = "lb_ck",
356 .ops = &clkops_generic,
357 .parent = &tc_ck.clk,
358 .flags = CLOCK_IDLE_CONTROL,
359 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
360 .enable_bit = EN_LBCK,
361 .recalc = &followparent_recalc,
362 },
363 .idlect_shift = IDLLB_ARM_SHIFT,
364};
365
366static struct clk rhea1_ck = {
367 .name = "rhea1_ck",
368 .ops = &clkops_null,
369 .parent = &tc_ck.clk,
370 .recalc = &followparent_recalc,
371};
372
373static struct clk rhea2_ck = {
374 .name = "rhea2_ck",
375 .ops = &clkops_null,
376 .parent = &tc_ck.clk,
377 .recalc = &followparent_recalc,
378};
379
380static struct clk lcd_ck_16xx = {
381 .name = "lcd_ck",
382 .ops = &clkops_generic,
383 .parent = &ck_dpll1,
384 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
385 .enable_bit = EN_LCDCK,
386 .rate_offset = CKCTL_LCDDIV_OFFSET,
387 .recalc = &omap1_ckctl_recalc,
388 .round_rate = omap1_clk_round_rate_ckctl_arm,
389 .set_rate = omap1_clk_set_rate_ckctl_arm,
390};
391
392static struct arm_idlect1_clk lcd_ck_1510 = {
393 .clk = {
394 .name = "lcd_ck",
395 .ops = &clkops_generic,
396 .parent = &ck_dpll1,
397 .flags = CLOCK_IDLE_CONTROL,
398 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
399 .enable_bit = EN_LCDCK,
400 .rate_offset = CKCTL_LCDDIV_OFFSET,
401 .recalc = &omap1_ckctl_recalc,
402 .round_rate = omap1_clk_round_rate_ckctl_arm,
403 .set_rate = omap1_clk_set_rate_ckctl_arm,
404 },
405 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
406};
407
408/*
409 * XXX The enable_bit here is misused - it simply switches between 12MHz
410 * and 48MHz. Reimplement with clksel.
411 *
412 * XXX does this need SYSC register handling?
413 */
414static struct clk uart1_1510 = {
415 .name = "uart1_ck",
416 .ops = &clkops_null,
417 /* Direct from ULPD, no real parent */
418 .parent = &armper_ck.clk,
419 .rate = 12000000,
420 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
421 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
422 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
423 .set_rate = &omap1_set_uart_rate,
424 .recalc = &omap1_uart_recalc,
425};
426
427/*
428 * XXX The enable_bit here is misused - it simply switches between 12MHz
429 * and 48MHz. Reimplement with clksel.
430 *
431 * XXX SYSC register handling does not belong in the clock framework
432 */
433static struct uart_clk uart1_16xx = {
434 .clk = {
435 .name = "uart1_ck",
436 .ops = &clkops_uart_16xx,
437 /* Direct from ULPD, no real parent */
438 .parent = &armper_ck.clk,
439 .rate = 48000000,
440 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
441 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
442 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
443 },
444 .sysc_addr = 0xfffb0054,
445};
446
447/*
448 * XXX The enable_bit here is misused - it simply switches between 12MHz
449 * and 48MHz. Reimplement with clksel.
450 *
451 * XXX does this need SYSC register handling?
452 */
453static struct clk uart2_ck = {
454 .name = "uart2_ck",
455 .ops = &clkops_null,
456 /* Direct from ULPD, no real parent */
457 .parent = &armper_ck.clk,
458 .rate = 12000000,
459 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
460 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
461 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
462 .set_rate = &omap1_set_uart_rate,
463 .recalc = &omap1_uart_recalc,
464};
465
466/*
467 * XXX The enable_bit here is misused - it simply switches between 12MHz
468 * and 48MHz. Reimplement with clksel.
469 *
470 * XXX does this need SYSC register handling?
471 */
472static struct clk uart3_1510 = {
473 .name = "uart3_ck",
474 .ops = &clkops_null,
475 /* Direct from ULPD, no real parent */
476 .parent = &armper_ck.clk,
477 .rate = 12000000,
478 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
479 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
480 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
481 .set_rate = &omap1_set_uart_rate,
482 .recalc = &omap1_uart_recalc,
483};
484
485/*
486 * XXX The enable_bit here is misused - it simply switches between 12MHz
487 * and 48MHz. Reimplement with clksel.
488 *
489 * XXX SYSC register handling does not belong in the clock framework
490 */
491static struct uart_clk uart3_16xx = {
492 .clk = {
493 .name = "uart3_ck",
494 .ops = &clkops_uart_16xx,
495 /* Direct from ULPD, no real parent */
496 .parent = &armper_ck.clk,
497 .rate = 48000000,
498 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
499 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
500 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
501 },
502 .sysc_addr = 0xfffb9854,
503};
504
505static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
506 .name = "usb_clko",
507 .ops = &clkops_generic,
508 /* Direct from ULPD, no parent */
509 .rate = 6000000,
510 .flags = ENABLE_REG_32BIT,
511 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
512 .enable_bit = USB_MCLK_EN_BIT,
513};
514
515static struct clk usb_hhc_ck1510 = {
516 .name = "usb_hhc_ck",
517 .ops = &clkops_generic,
518 /* Direct from ULPD, no parent */
519 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
520 .flags = ENABLE_REG_32BIT,
521 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
522 .enable_bit = USB_HOST_HHC_UHOST_EN,
523};
524
525static struct clk usb_hhc_ck16xx = {
526 .name = "usb_hhc_ck",
527 .ops = &clkops_generic,
528 /* Direct from ULPD, no parent */
529 .rate = 48000000,
530 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
531 .flags = ENABLE_REG_32BIT,
532 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
533 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
534};
535
536static struct clk usb_dc_ck = {
537 .name = "usb_dc_ck",
538 .ops = &clkops_generic,
539 /* Direct from ULPD, no parent */
540 .rate = 48000000,
541 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
542 .enable_bit = USB_REQ_EN_SHIFT,
543};
544
545static struct clk usb_dc_ck7xx = {
546 .name = "usb_dc_ck",
547 .ops = &clkops_generic,
548 /* Direct from ULPD, no parent */
549 .rate = 48000000,
550 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
551 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
552};
553
554static struct clk uart1_7xx = {
555 .name = "uart1_ck",
556 .ops = &clkops_generic,
557 /* Direct from ULPD, no parent */
558 .rate = 12000000,
559 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
560 .enable_bit = 9,
561};
562
563static struct clk uart2_7xx = {
564 .name = "uart2_ck",
565 .ops = &clkops_generic,
566 /* Direct from ULPD, no parent */
567 .rate = 12000000,
568 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
569 .enable_bit = 11,
570};
571
572static struct clk mclk_1510 = {
573 .name = "mclk",
574 .ops = &clkops_generic,
575 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
576 .rate = 12000000,
577 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
578 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
579};
580
581static struct clk mclk_16xx = {
582 .name = "mclk",
583 .ops = &clkops_generic,
584 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
585 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
586 .enable_bit = COM_ULPD_PLL_CLK_REQ,
587 .set_rate = &omap1_set_ext_clk_rate,
588 .round_rate = &omap1_round_ext_clk_rate,
589 .init = &omap1_init_ext_clk,
590};
591
592static struct clk bclk_1510 = {
593 .name = "bclk",
594 .ops = &clkops_generic,
595 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
596 .rate = 12000000,
597};
598
599static struct clk bclk_16xx = {
600 .name = "bclk",
601 .ops = &clkops_generic,
602 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
603 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
604 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
605 .set_rate = &omap1_set_ext_clk_rate,
606 .round_rate = &omap1_round_ext_clk_rate,
607 .init = &omap1_init_ext_clk,
608};
609
610static struct clk mmc1_ck = {
611 .name = "mmc1_ck",
612 .ops = &clkops_generic,
613 /* Functional clock is direct from ULPD, interface clock is ARMPER */
614 .parent = &armper_ck.clk,
615 .rate = 48000000,
616 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
617 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
618 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
619};
620
621/*
622 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
623 * CONF_MOD_MCBSP3_AUXON ??
624 */
625static struct clk mmc2_ck = {
626 .name = "mmc2_ck",
627 .ops = &clkops_generic,
628 /* Functional clock is direct from ULPD, interface clock is ARMPER */
629 .parent = &armper_ck.clk,
630 .rate = 48000000,
631 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
632 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
633 .enable_bit = 20,
634};
635
636static struct clk mmc3_ck = {
637 .name = "mmc3_ck",
638 .ops = &clkops_generic,
639 /* Functional clock is direct from ULPD, interface clock is ARMPER */
640 .parent = &armper_ck.clk,
641 .rate = 48000000,
642 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
643 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
644 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
645};
646
647static struct clk virtual_ck_mpu = {
648 .name = "mpu",
649 .ops = &clkops_null,
650 .parent = &arm_ck, /* Is smarter alias for */
651 .recalc = &followparent_recalc,
652 .set_rate = &omap1_select_table_rate,
653 .round_rate = &omap1_round_to_table_rate,
654};
655
656/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
657remains active during MPU idle whenever this is enabled */
658static struct clk i2c_fck = {
659 .name = "i2c_fck",
660 .ops = &clkops_null,
661 .flags = CLOCK_NO_IDLE_PARENT,
662 .parent = &armxor_ck.clk,
663 .recalc = &followparent_recalc,
664};
665
666static struct clk i2c_ick = {
667 .name = "i2c_ick",
668 .ops = &clkops_null,
669 .flags = CLOCK_NO_IDLE_PARENT,
670 .parent = &armper_ck.clk,
671 .recalc = &followparent_recalc,
672};
673
674/*
675 * clkdev integration
676 */
677
678static struct omap_clk omap_clks[] = {
679 /* non-ULPD clocks */
680 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
681 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
682 /* CK_GEN1 clocks */
683 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
684 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
685 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
686 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
687 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
688 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
689 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
690 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
691 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
692 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
693 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
694 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
695 /* CK_GEN2 clocks */
696 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
697 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
698 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
699 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
700 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
701 /* CK_GEN3 clocks */
702 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
703 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
704 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
705 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
706 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
707 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
708 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
709 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
710 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
711 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
712 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
713 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
714 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
715 /* ULPD clocks */
716 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
717 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
718 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
719 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
720 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
721 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
722 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
723 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
724 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
725 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
726 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
727 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
728 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
729 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
730 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
731 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
732 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
733 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
734 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
735 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
736 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
737 /* Virtual clocks */
738 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
739 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
740 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
741 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
742 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
743 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
744 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
745 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
746 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
747 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
748 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
749 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
750 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
751 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
752 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
753 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
754 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
755 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
756};
757
758/*
759 * init
760 */
761
762static struct clk_functions omap1_clk_functions = {
763 .clk_enable = omap1_clk_enable,
764 .clk_disable = omap1_clk_disable,
765 .clk_round_rate = omap1_clk_round_rate,
766 .clk_set_rate = omap1_clk_set_rate,
767 .clk_disable_unused = omap1_clk_disable_unused,
768};
769
770int __init omap1_clk_init(void)
771{
772 struct omap_clk *c;
773 const struct omap_clock_config *info;
774 int crystal_type = 0; /* Default 12 MHz */
775 u32 reg, cpu_mask;
776
777#ifdef CONFIG_DEBUG_LL
778 /*
779 * Resets some clocks that may be left on from bootloader,
780 * but leaves serial clocks on.
781 */
782 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
783#endif
784
785 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
786 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
787 omap_writew(reg, SOFT_REQ_REG);
788 if (!cpu_is_omap15xx())
789 omap_writew(0, SOFT_REQ_REG2);
790
791 clk_init(&omap1_clk_functions);
792
793 /* By default all idlect1 clocks are allowed to idle */
794 arm_idlect1_mask = ~0;
795
796 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
797 clk_preinit(c->lk.clk);
798
799 cpu_mask = 0;
800 if (cpu_is_omap16xx())
801 cpu_mask |= CK_16XX;
802 if (cpu_is_omap1510())
803 cpu_mask |= CK_1510;
804 if (cpu_is_omap7xx())
805 cpu_mask |= CK_7XX;
806 if (cpu_is_omap310())
807 cpu_mask |= CK_310;
808
809 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
810 if (c->cpu & cpu_mask) {
811 clkdev_add(&c->lk);
812 clk_register(c->lk.clk);
813 }
814
815 /* Pointers to these clocks are needed by code in clock.c */
816 api_ck_p = clk_get(NULL, "api_ck");
817 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
818 ck_ref_p = clk_get(NULL, "ck_ref");
819
820 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
821 if (info != NULL) {
822 if (!cpu_is_omap15xx())
823 crystal_type = info->system_clock_type;
824 }
825
826 if (cpu_is_omap7xx())
827 ck_ref.rate = 13000000;
828 if (cpu_is_omap16xx() && crystal_type == 2)
829 ck_ref.rate = 19200000;
830
831 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
832 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
833 omap_readw(ARM_CKCTL));
834
835 /* We want to be in syncronous scalable mode */
836 omap_writew(0x1000, ARM_SYSST);
837
838#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
839 /* Use values set by bootloader. Determine PLL rate and recalculate
840 * dependent clocks as if kernel had changed PLL or divisors.
841 */
842 {
843 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
844
845 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
846 if (pll_ctl_val & 0x10) {
847 /* PLL enabled, apply multiplier and divisor */
848 if (pll_ctl_val & 0xf80)
849 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
850 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
851 } else {
852 /* PLL disabled, apply bypass divisor */
853 switch (pll_ctl_val & 0xc) {
854 case 0:
855 break;
856 case 0x4:
857 ck_dpll1.rate /= 2;
858 break;
859 default:
860 ck_dpll1.rate /= 4;
861 break;
862 }
863 }
864 }
865#else
866 /* Find the highest supported frequency and enable it */
867 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
868 printk(KERN_ERR "System frequencies not set. Check your config.\n");
869 /* Guess sane values (60MHz) */
870 omap_writew(0x2290, DPLL_CTL);
871 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
872 ck_dpll1.rate = 60000000;
873 }
874#endif
875 propagate_rate(&ck_dpll1);
876 /* Cache rates for clocks connected to ck_ref (not dpll1) */
877 propagate_rate(&ck_ref);
878 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
879 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
880 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
881 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
882 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
883
884 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
885 /* Select slicer output as OMAP input clock */
886 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
887 OMAP7XX_PCC_UPLD_CTRL);
888 }
889
890 /* Amstrad Delta wants BCLK high when inactive */
891 if (machine_is_ams_delta())
892 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
893 (1 << SDW_MCLK_INV_BIT),
894 ULPD_CLOCK_CTRL);
895
896 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
897 /* (on 730, bit 13 must not be cleared) */
898 if (cpu_is_omap7xx())
899 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
900 else
901 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
902
903 /* Put DSP/MPUI into reset until needed */
904 omap_writew(0, ARM_RSTCT1);
905 omap_writew(1, ARM_RSTCT2);
906 omap_writew(0x400, ARM_IDLECT1);
907
908 /*
909 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
910 * of the ARM_IDLECT2 register must be set to zero. The power-on
911 * default value of this bit is one.
912 */
913 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
914
915 /*
916 * Only enable those clocks we will need, let the drivers
917 * enable other clocks as necessary
918 */
919 clk_enable(&armper_ck.clk);
920 clk_enable(&armxor_ck.clk);
921 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
922
923 if (cpu_is_omap15xx())
924 clk_enable(&arm_gpio_ck);
925
926 return 0;
927}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap1/clock_data.c
4 *
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 *
9 * To do:
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/clk-provider.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/soc/ti/omap1-io.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include "soc.h"
26#include "hardware.h"
27#include "usb.h" /* for OTG_BASE */
28#include "iomap.h"
29#include "clock.h"
30#include "sram.h"
31
32/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
33#define IDL_CLKOUT_ARM_SHIFT 12
34#define IDLTIM_ARM_SHIFT 9
35#define IDLAPI_ARM_SHIFT 8
36#define IDLIF_ARM_SHIFT 6
37#define IDLLB_ARM_SHIFT 4 /* undocumented? */
38#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
39#define IDLPER_ARM_SHIFT 2
40#define IDLXORP_ARM_SHIFT 1
41#define IDLWDT_ARM_SHIFT 0
42
43/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
44#define CONF_MOD_UART3_CLK_MODE_R 31
45#define CONF_MOD_UART2_CLK_MODE_R 30
46#define CONF_MOD_UART1_CLK_MODE_R 29
47#define CONF_MOD_MMC_SD_CLK_REQ_R 23
48#define CONF_MOD_MCBSP3_AUXON 20
49
50/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
51#define CONF_MOD_SOSSI_CLK_EN_R 16
52
53/* Some OTG_SYSCON_2-specific bit fields */
54#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
55
56/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
57#define SOFT_MMC2_DPLL_REQ_SHIFT 13
58#define SOFT_MMC_DPLL_REQ_SHIFT 12
59#define SOFT_UART3_DPLL_REQ_SHIFT 11
60#define SOFT_UART2_DPLL_REQ_SHIFT 10
61#define SOFT_UART1_DPLL_REQ_SHIFT 9
62#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
63#define SOFT_CAM_DPLL_REQ_SHIFT 7
64#define SOFT_COM_MCKO_REQ_SHIFT 6
65#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
66#define USB_REQ_EN_SHIFT 4
67#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
68#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
69#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
70#define SOFT_DPLL_REQ_SHIFT 0
71
72/*
73 * Omap1 clocks
74 */
75
76static struct omap1_clk ck_ref = {
77 .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
78 .rate = 12000000,
79};
80
81static struct omap1_clk ck_dpll1 = {
82 .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
83 /*
84 * force recursive refresh of rates of the clock
85 * and its children when clk_get_rate() is called
86 */
87 CLK_GET_RATE_NOCACHE),
88};
89
90/*
91 * FIXME: This clock seems to be necessary but no-one has asked for its
92 * activation. [ FIX: SoSSI, SSR ]
93 */
94static struct arm_idlect1_clk ck_dpll1out = {
95 .clk = {
96 .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
97 .ops = &clkops_generic,
98 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
99 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
100 .enable_bit = EN_CKOUT_ARM,
101 },
102 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
103};
104
105static struct omap1_clk sossi_ck = {
106 .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
107 .ops = &clkops_generic,
108 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
109 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
111 .recalc = &omap1_sossi_recalc,
112 .round_rate = &omap1_round_sossi_rate,
113 .set_rate = &omap1_set_sossi_rate,
114};
115
116static struct omap1_clk arm_ck = {
117 .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
118 .rate_offset = CKCTL_ARMDIV_OFFSET,
119 .recalc = &omap1_ckctl_recalc,
120 .round_rate = omap1_clk_round_rate_ckctl_arm,
121 .set_rate = omap1_clk_set_rate_ckctl_arm,
122};
123
124static struct arm_idlect1_clk armper_ck = {
125 .clk = {
126 .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
127 CLK_IS_CRITICAL),
128 .ops = &clkops_generic,
129 .flags = CLOCK_IDLE_CONTROL,
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
131 .enable_bit = EN_PERCK,
132 .rate_offset = CKCTL_PERDIV_OFFSET,
133 .recalc = &omap1_ckctl_recalc,
134 .round_rate = omap1_clk_round_rate_ckctl_arm,
135 .set_rate = omap1_clk_set_rate_ckctl_arm,
136 },
137 .idlect_shift = IDLPER_ARM_SHIFT,
138};
139
140/*
141 * FIXME: This clock seems to be necessary but no-one has asked for its
142 * activation. [ GPIO code for 1510 ]
143 */
144static struct omap1_clk arm_gpio_ck = {
145 .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
146 .ops = &clkops_generic,
147 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
148 .enable_bit = EN_GPIOCK,
149};
150
151static struct arm_idlect1_clk armxor_ck = {
152 .clk = {
153 .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
154 CLK_IS_CRITICAL),
155 .ops = &clkops_generic,
156 .flags = CLOCK_IDLE_CONTROL,
157 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
158 .enable_bit = EN_XORPCK,
159 },
160 .idlect_shift = IDLXORP_ARM_SHIFT,
161};
162
163static struct arm_idlect1_clk armtim_ck = {
164 .clk = {
165 .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
166 CLK_IS_CRITICAL),
167 .ops = &clkops_generic,
168 .flags = CLOCK_IDLE_CONTROL,
169 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
170 .enable_bit = EN_TIMCK,
171 },
172 .idlect_shift = IDLTIM_ARM_SHIFT,
173};
174
175static struct arm_idlect1_clk armwdt_ck = {
176 .clk = {
177 .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
178 .ops = &clkops_generic,
179 .flags = CLOCK_IDLE_CONTROL,
180 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
181 .enable_bit = EN_WDTCK,
182 .fixed_div = 14,
183 .recalc = &omap_fixed_divisor_recalc,
184 },
185 .idlect_shift = IDLWDT_ARM_SHIFT,
186};
187
188static struct omap1_clk arminth_ck16xx = {
189 .hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0),
190 /* Note: On 16xx the frequency can be divided by 2 by programming
191 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
192 *
193 * 1510 version is in TC clocks.
194 */
195};
196
197static struct omap1_clk dsp_ck = {
198 .hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
199 .ops = &clkops_generic,
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
201 .enable_bit = EN_DSPCK,
202 .rate_offset = CKCTL_DSPDIV_OFFSET,
203 .recalc = &omap1_ckctl_recalc,
204 .round_rate = omap1_clk_round_rate_ckctl_arm,
205 .set_rate = omap1_clk_set_rate_ckctl_arm,
206};
207
208static struct omap1_clk dspmmu_ck = {
209 .hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
210 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
211 .recalc = &omap1_ckctl_recalc,
212 .round_rate = omap1_clk_round_rate_ckctl_arm,
213 .set_rate = omap1_clk_set_rate_ckctl_arm,
214};
215
216static struct omap1_clk dspper_ck = {
217 .hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
218 .ops = &clkops_dspck,
219 .enable_reg = DSP_IDLECT2,
220 .enable_bit = EN_PERCK,
221 .rate_offset = CKCTL_PERDIV_OFFSET,
222 .recalc = &omap1_ckctl_recalc_dsp_domain,
223 .round_rate = omap1_clk_round_rate_ckctl_arm,
224 .set_rate = &omap1_clk_set_rate_dsp_domain,
225};
226
227static struct omap1_clk dspxor_ck = {
228 .hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0),
229 .ops = &clkops_dspck,
230 .enable_reg = DSP_IDLECT2,
231 .enable_bit = EN_XORPCK,
232};
233
234static struct omap1_clk dsptim_ck = {
235 .hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0),
236 .ops = &clkops_dspck,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_DSPTIMCK,
239};
240
241static struct arm_idlect1_clk tc_ck = {
242 .clk = {
243 .hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
244 .flags = CLOCK_IDLE_CONTROL,
245 .rate_offset = CKCTL_TCDIV_OFFSET,
246 .recalc = &omap1_ckctl_recalc,
247 .round_rate = omap1_clk_round_rate_ckctl_arm,
248 .set_rate = omap1_clk_set_rate_ckctl_arm,
249 },
250 .idlect_shift = IDLIF_ARM_SHIFT,
251};
252
253static struct omap1_clk arminth_ck1510 = {
254 .hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0),
255 /* Note: On 1510 the frequency follows TC_CK
256 *
257 * 16xx version is in MPU clocks.
258 */
259};
260
261static struct omap1_clk tipb_ck = {
262 /* No-idle controlled by "tc_ck" */
263 .hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0),
264};
265
266static struct omap1_clk l3_ocpi_ck = {
267 /* No-idle controlled by "tc_ck" */
268 .hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0),
269 .ops = &clkops_generic,
270 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
271 .enable_bit = EN_OCPI_CK,
272};
273
274static struct omap1_clk tc1_ck = {
275 .hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0),
276 .ops = &clkops_generic,
277 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
278 .enable_bit = EN_TC1_CK,
279};
280
281/*
282 * FIXME: This clock seems to be necessary but no-one has asked for its
283 * activation. [ pm.c (SRAM), CCP, Camera ]
284 */
285
286static struct omap1_clk tc2_ck = {
287 .hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
288 .ops = &clkops_generic,
289 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
290 .enable_bit = EN_TC2_CK,
291};
292
293static struct omap1_clk dma_ck = {
294 /* No-idle controlled by "tc_ck" */
295 .hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0),
296};
297
298static struct omap1_clk dma_lcdfree_ck = {
299 .hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0),
300};
301
302static struct arm_idlect1_clk api_ck = {
303 .clk = {
304 .hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0),
305 .ops = &clkops_generic,
306 .flags = CLOCK_IDLE_CONTROL,
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
308 .enable_bit = EN_APICK,
309 },
310 .idlect_shift = IDLAPI_ARM_SHIFT,
311};
312
313static struct arm_idlect1_clk lb_ck = {
314 .clk = {
315 .hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0),
316 .ops = &clkops_generic,
317 .flags = CLOCK_IDLE_CONTROL,
318 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
319 .enable_bit = EN_LBCK,
320 },
321 .idlect_shift = IDLLB_ARM_SHIFT,
322};
323
324static struct omap1_clk rhea1_ck = {
325 .hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0),
326};
327
328static struct omap1_clk rhea2_ck = {
329 .hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0),
330};
331
332static struct omap1_clk lcd_ck_16xx = {
333 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
334 .ops = &clkops_generic,
335 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
336 .enable_bit = EN_LCDCK,
337 .rate_offset = CKCTL_LCDDIV_OFFSET,
338 .recalc = &omap1_ckctl_recalc,
339 .round_rate = omap1_clk_round_rate_ckctl_arm,
340 .set_rate = omap1_clk_set_rate_ckctl_arm,
341};
342
343static struct arm_idlect1_clk lcd_ck_1510 = {
344 .clk = {
345 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
346 .ops = &clkops_generic,
347 .flags = CLOCK_IDLE_CONTROL,
348 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
349 .enable_bit = EN_LCDCK,
350 .rate_offset = CKCTL_LCDDIV_OFFSET,
351 .recalc = &omap1_ckctl_recalc,
352 .round_rate = omap1_clk_round_rate_ckctl_arm,
353 .set_rate = omap1_clk_set_rate_ckctl_arm,
354 },
355 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
356};
357
358
359/*
360 * XXX The enable_bit here is misused - it simply switches between 12MHz
361 * and 48MHz. Reimplement with clk_mux.
362 *
363 * XXX does this need SYSC register handling?
364 */
365static struct omap1_clk uart1_1510 = {
366 /* Direct from ULPD, no real parent */
367 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
368 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
369 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
370 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
371 .round_rate = &omap1_round_uart_rate,
372 .set_rate = &omap1_set_uart_rate,
373 .recalc = &omap1_uart_recalc,
374};
375
376/*
377 * XXX The enable_bit here is misused - it simply switches between 12MHz
378 * and 48MHz. Reimplement with clk_mux.
379 *
380 * XXX SYSC register handling does not belong in the clock framework
381 */
382static struct uart_clk uart1_16xx = {
383 .clk = {
384 .ops = &clkops_uart_16xx,
385 /* Direct from ULPD, no real parent */
386 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
387 .rate = 48000000,
388 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
389 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
390 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
391 },
392 .sysc_addr = 0xfffb0054,
393};
394
395/*
396 * XXX The enable_bit here is misused - it simply switches between 12MHz
397 * and 48MHz. Reimplement with clk_mux.
398 *
399 * XXX does this need SYSC register handling?
400 */
401static struct omap1_clk uart2_ck = {
402 /* Direct from ULPD, no real parent */
403 .hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0),
404 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
405 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
406 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
407 .round_rate = &omap1_round_uart_rate,
408 .set_rate = &omap1_set_uart_rate,
409 .recalc = &omap1_uart_recalc,
410};
411
412/*
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clk_mux.
415 *
416 * XXX does this need SYSC register handling?
417 */
418static struct omap1_clk uart3_1510 = {
419 /* Direct from ULPD, no real parent */
420 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
422 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
423 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
424 .round_rate = &omap1_round_uart_rate,
425 .set_rate = &omap1_set_uart_rate,
426 .recalc = &omap1_uart_recalc,
427};
428
429/*
430 * XXX The enable_bit here is misused - it simply switches between 12MHz
431 * and 48MHz. Reimplement with clk_mux.
432 *
433 * XXX SYSC register handling does not belong in the clock framework
434 */
435static struct uart_clk uart3_16xx = {
436 .clk = {
437 .ops = &clkops_uart_16xx,
438 /* Direct from ULPD, no real parent */
439 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
440 .rate = 48000000,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
442 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
443 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
444 },
445 .sysc_addr = 0xfffb9854,
446};
447
448static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
449 .ops = &clkops_generic,
450 /* Direct from ULPD, no parent */
451 .hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0),
452 .rate = 6000000,
453 .flags = ENABLE_REG_32BIT,
454 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
455 .enable_bit = USB_MCLK_EN_BIT,
456};
457
458static struct omap1_clk usb_hhc_ck1510 = {
459 .ops = &clkops_generic,
460 /* Direct from ULPD, no parent */
461 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
462 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
463 .flags = ENABLE_REG_32BIT,
464 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
465 .enable_bit = USB_HOST_HHC_UHOST_EN,
466};
467
468static struct omap1_clk usb_hhc_ck16xx = {
469 .ops = &clkops_generic,
470 /* Direct from ULPD, no parent */
471 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
472 .rate = 48000000,
473 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
474 .flags = ENABLE_REG_32BIT,
475 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
476 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
477};
478
479static struct omap1_clk usb_dc_ck = {
480 .ops = &clkops_generic,
481 /* Direct from ULPD, no parent */
482 .hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0),
483 .rate = 48000000,
484 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
485 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
486};
487
488static struct omap1_clk uart1_7xx = {
489 .ops = &clkops_generic,
490 /* Direct from ULPD, no parent */
491 .hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0),
492 .rate = 12000000,
493 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
494 .enable_bit = 9,
495};
496
497static struct omap1_clk uart2_7xx = {
498 .ops = &clkops_generic,
499 /* Direct from ULPD, no parent */
500 .hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0),
501 .rate = 12000000,
502 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
503 .enable_bit = 11,
504};
505
506static struct omap1_clk mclk_1510 = {
507 .ops = &clkops_generic,
508 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
509 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
510 .rate = 12000000,
511 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
512 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
513};
514
515static struct omap1_clk mclk_16xx = {
516 .ops = &clkops_generic,
517 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
518 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
519 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
520 .enable_bit = COM_ULPD_PLL_CLK_REQ,
521 .set_rate = &omap1_set_ext_clk_rate,
522 .round_rate = &omap1_round_ext_clk_rate,
523 .init = &omap1_init_ext_clk,
524};
525
526static struct omap1_clk bclk_1510 = {
527 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
528 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0),
529 .rate = 12000000,
530};
531
532static struct omap1_clk bclk_16xx = {
533 .ops = &clkops_generic,
534 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
535 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0),
536 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
537 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
538 .set_rate = &omap1_set_ext_clk_rate,
539 .round_rate = &omap1_round_ext_clk_rate,
540 .init = &omap1_init_ext_clk,
541};
542
543static struct omap1_clk mmc1_ck = {
544 .ops = &clkops_generic,
545 /* Functional clock is direct from ULPD, interface clock is ARMPER */
546 .hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0),
547 .rate = 48000000,
548 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
549 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
550 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
551};
552
553/*
554 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
555 * CONF_MOD_MCBSP3_AUXON ??
556 */
557static struct omap1_clk mmc2_ck = {
558 .ops = &clkops_generic,
559 /* Functional clock is direct from ULPD, interface clock is ARMPER */
560 .hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0),
561 .rate = 48000000,
562 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
563 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
564 .enable_bit = 20,
565};
566
567static struct omap1_clk mmc3_ck = {
568 .ops = &clkops_generic,
569 /* Functional clock is direct from ULPD, interface clock is ARMPER */
570 .hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0),
571 .rate = 48000000,
572 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
573 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
574 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
575};
576
577static struct omap1_clk virtual_ck_mpu = {
578 /* Is smarter alias for arm_ck */
579 .hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0),
580 .recalc = &followparent_recalc,
581 .set_rate = &omap1_select_table_rate,
582 .round_rate = &omap1_round_to_table_rate,
583};
584
585/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
586remains active during MPU idle whenever this is enabled */
587static struct omap1_clk i2c_fck = {
588 .hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0),
589 .flags = CLOCK_NO_IDLE_PARENT,
590};
591
592static struct omap1_clk i2c_ick = {
593 .hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0),
594 .flags = CLOCK_NO_IDLE_PARENT,
595};
596
597/*
598 * clkdev integration
599 */
600
601static struct omap_clk omap_clks[] = {
602 /* non-ULPD clocks */
603 CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
604 CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
605 /* CK_GEN1 clocks */
606 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX),
607 CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
608 CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310),
609 CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
610 CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310),
611 CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
612 CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
613 CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
614 CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX),
615 CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310),
616 CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310),
617 CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX),
618 /* CK_GEN2 clocks */
619 CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310),
620 CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310),
621 CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310),
622 CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
623 CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310),
624 /* CK_GEN3 clocks */
625 CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
626 CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310),
627 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX),
628 CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
629 CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
630 CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310),
631 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX),
632 CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
633 CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310),
634 CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
635 CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
636 CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX),
637 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310),
638 /* ULPD clocks */
639 CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310),
640 CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX),
641 CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
642 CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310),
643 CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
644 CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310),
645 CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX),
646 CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310),
647 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310),
648 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX),
649 CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX),
650 CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310),
651 CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
652 CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310),
653 CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
654 CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
656 CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
657 CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
658 CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
659 /* Virtual clocks */
660 CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310),
661 CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
662 CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX),
663 CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX),
664 CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX),
665 CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX),
666 CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX),
667 CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX),
668 CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
669 CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
670 CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
671 CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
672 CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
673 CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
674 CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
675 CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
676 CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
677 CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
678};
679
680/*
681 * init
682 */
683
684static void __init omap1_show_rates(void)
685{
686 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
687 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
688 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
689 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
690}
691
692u32 cpu_mask;
693
694int __init omap1_clk_init(void)
695{
696 struct omap_clk *c;
697 u32 reg;
698
699#ifdef CONFIG_DEBUG_LL
700 /* Make sure UART clocks are enabled early */
701 if (cpu_is_omap16xx())
702 omap_writel(omap_readl(MOD_CONF_CTRL_0) |
703 CONF_MOD_UART1_CLK_MODE_R |
704 CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
705#endif
706
707 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
708 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
709 omap_writew(reg, SOFT_REQ_REG);
710 if (!cpu_is_omap15xx())
711 omap_writew(0, SOFT_REQ_REG2);
712
713 /* By default all idlect1 clocks are allowed to idle */
714 arm_idlect1_mask = ~0;
715
716 cpu_mask = 0;
717 if (cpu_is_omap1710())
718 cpu_mask |= CK_1710;
719 if (cpu_is_omap16xx())
720 cpu_mask |= CK_16XX;
721 if (cpu_is_omap1510())
722 cpu_mask |= CK_1510;
723 if (cpu_is_omap310())
724 cpu_mask |= CK_310;
725
726 /* Pointers to these clocks are needed by code in clock.c */
727 api_ck_p = &api_ck.clk;
728 ck_dpll1_p = &ck_dpll1;
729 ck_ref_p = &ck_ref;
730
731 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
732 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
733 omap_readw(ARM_CKCTL));
734
735 /* We want to be in synchronous scalable mode */
736 omap_writew(0x1000, ARM_SYSST);
737
738
739 /*
740 * Initially use the values set by bootloader. Determine PLL rate and
741 * recalculate dependent clocks as if kernel had changed PLL or
742 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
743 * after the SRAM is initialized.
744 */
745 {
746 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
747
748 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
749 if (pll_ctl_val & 0x10) {
750 /* PLL enabled, apply multiplier and divisor */
751 if (pll_ctl_val & 0xf80)
752 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
753 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
754 } else {
755 /* PLL disabled, apply bypass divisor */
756 switch (pll_ctl_val & 0xc) {
757 case 0:
758 break;
759 case 0x4:
760 ck_dpll1.rate /= 2;
761 break;
762 default:
763 ck_dpll1.rate /= 4;
764 break;
765 }
766 }
767 }
768
769 /* Amstrad Delta wants BCLK high when inactive */
770 if (machine_is_ams_delta())
771 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
772 (1 << SDW_MCLK_INV_BIT),
773 ULPD_CLOCK_CTRL);
774
775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
776 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
777
778 /* Put DSP/MPUI into reset until needed */
779 omap_writew(0, ARM_RSTCT1);
780 omap_writew(1, ARM_RSTCT2);
781 omap_writew(0x400, ARM_IDLECT1);
782
783 /*
784 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
785 * of the ARM_IDLECT2 register must be set to zero. The power-on
786 * default value of this bit is one.
787 */
788 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
789
790 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) {
791 if (!(c->cpu & cpu_mask))
792 continue;
793
794 if (c->lk.clk_hw->init) { /* NULL if provider already registered */
795 const struct clk_init_data *init = c->lk.clk_hw->init;
796 const char *name = c->lk.clk_hw->init->name;
797 int err;
798
799 err = clk_hw_register(NULL, c->lk.clk_hw);
800 if (err < 0) {
801 pr_err("failed to register clock \"%s\"! (%d)\n", name, err);
802 /* may be tried again, restore init data */
803 c->lk.clk_hw->init = init;
804 continue;
805 }
806 }
807
808 clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id);
809 }
810
811 omap1_show_rates();
812
813 return 0;
814}
815
816#define OMAP1_DPLL1_SANE_VALUE 60000000
817
818void __init omap1_clk_late_init(void)
819{
820 unsigned long rate = ck_dpll1.rate;
821
822 /* Find the highest supported frequency and enable it */
823 if (omap1_select_table_rate(&virtual_ck_mpu, ~0, arm_ck.rate)) {
824 pr_err("System frequencies not set, using default. Check your config.\n");
825 /*
826 * Reprogramming the DPLL is tricky, it must be done from SRAM.
827 */
828 omap_sram_reprogram_clock(0x2290, 0x0005);
829 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
830 }
831 propagate_rate(&ck_dpll1);
832 omap1_show_rates();
833 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
834}