Loading...
1/*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * To do:
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
15 */
16
17#include <linux/kernel.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <asm/mach-types.h> /* for machine_is_* */
22
23#include <plat/clock.h>
24#include <plat/cpu.h>
25#include <plat/clkdev_omap.h>
26#include <plat/usb.h> /* for OTG_BASE */
27
28#include "clock.h"
29
30/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
31#define IDL_CLKOUT_ARM_SHIFT 12
32#define IDLTIM_ARM_SHIFT 9
33#define IDLAPI_ARM_SHIFT 8
34#define IDLIF_ARM_SHIFT 6
35#define IDLLB_ARM_SHIFT 4 /* undocumented? */
36#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
37#define IDLPER_ARM_SHIFT 2
38#define IDLXORP_ARM_SHIFT 1
39#define IDLWDT_ARM_SHIFT 0
40
41/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
42#define CONF_MOD_UART3_CLK_MODE_R 31
43#define CONF_MOD_UART2_CLK_MODE_R 30
44#define CONF_MOD_UART1_CLK_MODE_R 29
45#define CONF_MOD_MMC_SD_CLK_REQ_R 23
46#define CONF_MOD_MCBSP3_AUXON 20
47
48/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
49#define CONF_MOD_SOSSI_CLK_EN_R 16
50
51/* Some OTG_SYSCON_2-specific bit fields */
52#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
53
54/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
55#define SOFT_MMC2_DPLL_REQ_SHIFT 13
56#define SOFT_MMC_DPLL_REQ_SHIFT 12
57#define SOFT_UART3_DPLL_REQ_SHIFT 11
58#define SOFT_UART2_DPLL_REQ_SHIFT 10
59#define SOFT_UART1_DPLL_REQ_SHIFT 9
60#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
61#define SOFT_CAM_DPLL_REQ_SHIFT 7
62#define SOFT_COM_MCKO_REQ_SHIFT 6
63#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
64#define USB_REQ_EN_SHIFT 4
65#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
66#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
67#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
68#define SOFT_DPLL_REQ_SHIFT 0
69
70/*
71 * Omap1 clocks
72 */
73
74static struct clk ck_ref = {
75 .name = "ck_ref",
76 .ops = &clkops_null,
77 .rate = 12000000,
78};
79
80static struct clk ck_dpll1 = {
81 .name = "ck_dpll1",
82 .ops = &clkops_null,
83 .parent = &ck_ref,
84};
85
86/*
87 * FIXME: This clock seems to be necessary but no-one has asked for its
88 * activation. [ FIX: SoSSI, SSR ]
89 */
90static struct arm_idlect1_clk ck_dpll1out = {
91 .clk = {
92 .name = "ck_dpll1out",
93 .ops = &clkops_generic,
94 .parent = &ck_dpll1,
95 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
96 ENABLE_ON_INIT,
97 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
98 .enable_bit = EN_CKOUT_ARM,
99 .recalc = &followparent_recalc,
100 },
101 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
102};
103
104static struct clk sossi_ck = {
105 .name = "ck_sossi",
106 .ops = &clkops_generic,
107 .parent = &ck_dpll1out.clk,
108 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
109 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
111 .recalc = &omap1_sossi_recalc,
112 .set_rate = &omap1_set_sossi_rate,
113};
114
115static struct clk arm_ck = {
116 .name = "arm_ck",
117 .ops = &clkops_null,
118 .parent = &ck_dpll1,
119 .rate_offset = CKCTL_ARMDIV_OFFSET,
120 .recalc = &omap1_ckctl_recalc,
121 .round_rate = omap1_clk_round_rate_ckctl_arm,
122 .set_rate = omap1_clk_set_rate_ckctl_arm,
123};
124
125static struct arm_idlect1_clk armper_ck = {
126 .clk = {
127 .name = "armper_ck",
128 .ops = &clkops_generic,
129 .parent = &ck_dpll1,
130 .flags = CLOCK_IDLE_CONTROL,
131 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
132 .enable_bit = EN_PERCK,
133 .rate_offset = CKCTL_PERDIV_OFFSET,
134 .recalc = &omap1_ckctl_recalc,
135 .round_rate = omap1_clk_round_rate_ckctl_arm,
136 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 },
138 .idlect_shift = IDLPER_ARM_SHIFT,
139};
140
141/*
142 * FIXME: This clock seems to be necessary but no-one has asked for its
143 * activation. [ GPIO code for 1510 ]
144 */
145static struct clk arm_gpio_ck = {
146 .name = "ick",
147 .ops = &clkops_generic,
148 .parent = &ck_dpll1,
149 .flags = ENABLE_ON_INIT,
150 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
151 .enable_bit = EN_GPIOCK,
152 .recalc = &followparent_recalc,
153};
154
155static struct arm_idlect1_clk armxor_ck = {
156 .clk = {
157 .name = "armxor_ck",
158 .ops = &clkops_generic,
159 .parent = &ck_ref,
160 .flags = CLOCK_IDLE_CONTROL,
161 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
162 .enable_bit = EN_XORPCK,
163 .recalc = &followparent_recalc,
164 },
165 .idlect_shift = IDLXORP_ARM_SHIFT,
166};
167
168static struct arm_idlect1_clk armtim_ck = {
169 .clk = {
170 .name = "armtim_ck",
171 .ops = &clkops_generic,
172 .parent = &ck_ref,
173 .flags = CLOCK_IDLE_CONTROL,
174 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
175 .enable_bit = EN_TIMCK,
176 .recalc = &followparent_recalc,
177 },
178 .idlect_shift = IDLTIM_ARM_SHIFT,
179};
180
181static struct arm_idlect1_clk armwdt_ck = {
182 .clk = {
183 .name = "armwdt_ck",
184 .ops = &clkops_generic,
185 .parent = &ck_ref,
186 .flags = CLOCK_IDLE_CONTROL,
187 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
188 .enable_bit = EN_WDTCK,
189 .fixed_div = 14,
190 .recalc = &omap_fixed_divisor_recalc,
191 },
192 .idlect_shift = IDLWDT_ARM_SHIFT,
193};
194
195static struct clk arminth_ck16xx = {
196 .name = "arminth_ck",
197 .ops = &clkops_null,
198 .parent = &arm_ck,
199 .recalc = &followparent_recalc,
200 /* Note: On 16xx the frequency can be divided by 2 by programming
201 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
202 *
203 * 1510 version is in TC clocks.
204 */
205};
206
207static struct clk dsp_ck = {
208 .name = "dsp_ck",
209 .ops = &clkops_generic,
210 .parent = &ck_dpll1,
211 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
212 .enable_bit = EN_DSPCK,
213 .rate_offset = CKCTL_DSPDIV_OFFSET,
214 .recalc = &omap1_ckctl_recalc,
215 .round_rate = omap1_clk_round_rate_ckctl_arm,
216 .set_rate = omap1_clk_set_rate_ckctl_arm,
217};
218
219static struct clk dspmmu_ck = {
220 .name = "dspmmu_ck",
221 .ops = &clkops_null,
222 .parent = &ck_dpll1,
223 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
224 .recalc = &omap1_ckctl_recalc,
225 .round_rate = omap1_clk_round_rate_ckctl_arm,
226 .set_rate = omap1_clk_set_rate_ckctl_arm,
227};
228
229static struct clk dspper_ck = {
230 .name = "dspper_ck",
231 .ops = &clkops_dspck,
232 .parent = &ck_dpll1,
233 .enable_reg = DSP_IDLECT2,
234 .enable_bit = EN_PERCK,
235 .rate_offset = CKCTL_PERDIV_OFFSET,
236 .recalc = &omap1_ckctl_recalc_dsp_domain,
237 .round_rate = omap1_clk_round_rate_ckctl_arm,
238 .set_rate = &omap1_clk_set_rate_dsp_domain,
239};
240
241static struct clk dspxor_ck = {
242 .name = "dspxor_ck",
243 .ops = &clkops_dspck,
244 .parent = &ck_ref,
245 .enable_reg = DSP_IDLECT2,
246 .enable_bit = EN_XORPCK,
247 .recalc = &followparent_recalc,
248};
249
250static struct clk dsptim_ck = {
251 .name = "dsptim_ck",
252 .ops = &clkops_dspck,
253 .parent = &ck_ref,
254 .enable_reg = DSP_IDLECT2,
255 .enable_bit = EN_DSPTIMCK,
256 .recalc = &followparent_recalc,
257};
258
259static struct arm_idlect1_clk tc_ck = {
260 .clk = {
261 .name = "tc_ck",
262 .ops = &clkops_null,
263 .parent = &ck_dpll1,
264 .flags = CLOCK_IDLE_CONTROL,
265 .rate_offset = CKCTL_TCDIV_OFFSET,
266 .recalc = &omap1_ckctl_recalc,
267 .round_rate = omap1_clk_round_rate_ckctl_arm,
268 .set_rate = omap1_clk_set_rate_ckctl_arm,
269 },
270 .idlect_shift = IDLIF_ARM_SHIFT,
271};
272
273static struct clk arminth_ck1510 = {
274 .name = "arminth_ck",
275 .ops = &clkops_null,
276 .parent = &tc_ck.clk,
277 .recalc = &followparent_recalc,
278 /* Note: On 1510 the frequency follows TC_CK
279 *
280 * 16xx version is in MPU clocks.
281 */
282};
283
284static struct clk tipb_ck = {
285 /* No-idle controlled by "tc_ck" */
286 .name = "tipb_ck",
287 .ops = &clkops_null,
288 .parent = &tc_ck.clk,
289 .recalc = &followparent_recalc,
290};
291
292static struct clk l3_ocpi_ck = {
293 /* No-idle controlled by "tc_ck" */
294 .name = "l3_ocpi_ck",
295 .ops = &clkops_generic,
296 .parent = &tc_ck.clk,
297 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
298 .enable_bit = EN_OCPI_CK,
299 .recalc = &followparent_recalc,
300};
301
302static struct clk tc1_ck = {
303 .name = "tc1_ck",
304 .ops = &clkops_generic,
305 .parent = &tc_ck.clk,
306 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
307 .enable_bit = EN_TC1_CK,
308 .recalc = &followparent_recalc,
309};
310
311/*
312 * FIXME: This clock seems to be necessary but no-one has asked for its
313 * activation. [ pm.c (SRAM), CCP, Camera ]
314 */
315static struct clk tc2_ck = {
316 .name = "tc2_ck",
317 .ops = &clkops_generic,
318 .parent = &tc_ck.clk,
319 .flags = ENABLE_ON_INIT,
320 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
321 .enable_bit = EN_TC2_CK,
322 .recalc = &followparent_recalc,
323};
324
325static struct clk dma_ck = {
326 /* No-idle controlled by "tc_ck" */
327 .name = "dma_ck",
328 .ops = &clkops_null,
329 .parent = &tc_ck.clk,
330 .recalc = &followparent_recalc,
331};
332
333static struct clk dma_lcdfree_ck = {
334 .name = "dma_lcdfree_ck",
335 .ops = &clkops_null,
336 .parent = &tc_ck.clk,
337 .recalc = &followparent_recalc,
338};
339
340static struct arm_idlect1_clk api_ck = {
341 .clk = {
342 .name = "api_ck",
343 .ops = &clkops_generic,
344 .parent = &tc_ck.clk,
345 .flags = CLOCK_IDLE_CONTROL,
346 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
347 .enable_bit = EN_APICK,
348 .recalc = &followparent_recalc,
349 },
350 .idlect_shift = IDLAPI_ARM_SHIFT,
351};
352
353static struct arm_idlect1_clk lb_ck = {
354 .clk = {
355 .name = "lb_ck",
356 .ops = &clkops_generic,
357 .parent = &tc_ck.clk,
358 .flags = CLOCK_IDLE_CONTROL,
359 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
360 .enable_bit = EN_LBCK,
361 .recalc = &followparent_recalc,
362 },
363 .idlect_shift = IDLLB_ARM_SHIFT,
364};
365
366static struct clk rhea1_ck = {
367 .name = "rhea1_ck",
368 .ops = &clkops_null,
369 .parent = &tc_ck.clk,
370 .recalc = &followparent_recalc,
371};
372
373static struct clk rhea2_ck = {
374 .name = "rhea2_ck",
375 .ops = &clkops_null,
376 .parent = &tc_ck.clk,
377 .recalc = &followparent_recalc,
378};
379
380static struct clk lcd_ck_16xx = {
381 .name = "lcd_ck",
382 .ops = &clkops_generic,
383 .parent = &ck_dpll1,
384 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
385 .enable_bit = EN_LCDCK,
386 .rate_offset = CKCTL_LCDDIV_OFFSET,
387 .recalc = &omap1_ckctl_recalc,
388 .round_rate = omap1_clk_round_rate_ckctl_arm,
389 .set_rate = omap1_clk_set_rate_ckctl_arm,
390};
391
392static struct arm_idlect1_clk lcd_ck_1510 = {
393 .clk = {
394 .name = "lcd_ck",
395 .ops = &clkops_generic,
396 .parent = &ck_dpll1,
397 .flags = CLOCK_IDLE_CONTROL,
398 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
399 .enable_bit = EN_LCDCK,
400 .rate_offset = CKCTL_LCDDIV_OFFSET,
401 .recalc = &omap1_ckctl_recalc,
402 .round_rate = omap1_clk_round_rate_ckctl_arm,
403 .set_rate = omap1_clk_set_rate_ckctl_arm,
404 },
405 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
406};
407
408/*
409 * XXX The enable_bit here is misused - it simply switches between 12MHz
410 * and 48MHz. Reimplement with clksel.
411 *
412 * XXX does this need SYSC register handling?
413 */
414static struct clk uart1_1510 = {
415 .name = "uart1_ck",
416 .ops = &clkops_null,
417 /* Direct from ULPD, no real parent */
418 .parent = &armper_ck.clk,
419 .rate = 12000000,
420 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
421 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
422 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
423 .set_rate = &omap1_set_uart_rate,
424 .recalc = &omap1_uart_recalc,
425};
426
427/*
428 * XXX The enable_bit here is misused - it simply switches between 12MHz
429 * and 48MHz. Reimplement with clksel.
430 *
431 * XXX SYSC register handling does not belong in the clock framework
432 */
433static struct uart_clk uart1_16xx = {
434 .clk = {
435 .name = "uart1_ck",
436 .ops = &clkops_uart_16xx,
437 /* Direct from ULPD, no real parent */
438 .parent = &armper_ck.clk,
439 .rate = 48000000,
440 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
441 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
442 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
443 },
444 .sysc_addr = 0xfffb0054,
445};
446
447/*
448 * XXX The enable_bit here is misused - it simply switches between 12MHz
449 * and 48MHz. Reimplement with clksel.
450 *
451 * XXX does this need SYSC register handling?
452 */
453static struct clk uart2_ck = {
454 .name = "uart2_ck",
455 .ops = &clkops_null,
456 /* Direct from ULPD, no real parent */
457 .parent = &armper_ck.clk,
458 .rate = 12000000,
459 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
460 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
461 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
462 .set_rate = &omap1_set_uart_rate,
463 .recalc = &omap1_uart_recalc,
464};
465
466/*
467 * XXX The enable_bit here is misused - it simply switches between 12MHz
468 * and 48MHz. Reimplement with clksel.
469 *
470 * XXX does this need SYSC register handling?
471 */
472static struct clk uart3_1510 = {
473 .name = "uart3_ck",
474 .ops = &clkops_null,
475 /* Direct from ULPD, no real parent */
476 .parent = &armper_ck.clk,
477 .rate = 12000000,
478 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
479 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
480 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
481 .set_rate = &omap1_set_uart_rate,
482 .recalc = &omap1_uart_recalc,
483};
484
485/*
486 * XXX The enable_bit here is misused - it simply switches between 12MHz
487 * and 48MHz. Reimplement with clksel.
488 *
489 * XXX SYSC register handling does not belong in the clock framework
490 */
491static struct uart_clk uart3_16xx = {
492 .clk = {
493 .name = "uart3_ck",
494 .ops = &clkops_uart_16xx,
495 /* Direct from ULPD, no real parent */
496 .parent = &armper_ck.clk,
497 .rate = 48000000,
498 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
499 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
500 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
501 },
502 .sysc_addr = 0xfffb9854,
503};
504
505static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
506 .name = "usb_clko",
507 .ops = &clkops_generic,
508 /* Direct from ULPD, no parent */
509 .rate = 6000000,
510 .flags = ENABLE_REG_32BIT,
511 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
512 .enable_bit = USB_MCLK_EN_BIT,
513};
514
515static struct clk usb_hhc_ck1510 = {
516 .name = "usb_hhc_ck",
517 .ops = &clkops_generic,
518 /* Direct from ULPD, no parent */
519 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
520 .flags = ENABLE_REG_32BIT,
521 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
522 .enable_bit = USB_HOST_HHC_UHOST_EN,
523};
524
525static struct clk usb_hhc_ck16xx = {
526 .name = "usb_hhc_ck",
527 .ops = &clkops_generic,
528 /* Direct from ULPD, no parent */
529 .rate = 48000000,
530 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
531 .flags = ENABLE_REG_32BIT,
532 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
533 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
534};
535
536static struct clk usb_dc_ck = {
537 .name = "usb_dc_ck",
538 .ops = &clkops_generic,
539 /* Direct from ULPD, no parent */
540 .rate = 48000000,
541 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
542 .enable_bit = USB_REQ_EN_SHIFT,
543};
544
545static struct clk usb_dc_ck7xx = {
546 .name = "usb_dc_ck",
547 .ops = &clkops_generic,
548 /* Direct from ULPD, no parent */
549 .rate = 48000000,
550 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
551 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
552};
553
554static struct clk uart1_7xx = {
555 .name = "uart1_ck",
556 .ops = &clkops_generic,
557 /* Direct from ULPD, no parent */
558 .rate = 12000000,
559 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
560 .enable_bit = 9,
561};
562
563static struct clk uart2_7xx = {
564 .name = "uart2_ck",
565 .ops = &clkops_generic,
566 /* Direct from ULPD, no parent */
567 .rate = 12000000,
568 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
569 .enable_bit = 11,
570};
571
572static struct clk mclk_1510 = {
573 .name = "mclk",
574 .ops = &clkops_generic,
575 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
576 .rate = 12000000,
577 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
578 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
579};
580
581static struct clk mclk_16xx = {
582 .name = "mclk",
583 .ops = &clkops_generic,
584 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
585 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
586 .enable_bit = COM_ULPD_PLL_CLK_REQ,
587 .set_rate = &omap1_set_ext_clk_rate,
588 .round_rate = &omap1_round_ext_clk_rate,
589 .init = &omap1_init_ext_clk,
590};
591
592static struct clk bclk_1510 = {
593 .name = "bclk",
594 .ops = &clkops_generic,
595 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
596 .rate = 12000000,
597};
598
599static struct clk bclk_16xx = {
600 .name = "bclk",
601 .ops = &clkops_generic,
602 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
603 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
604 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
605 .set_rate = &omap1_set_ext_clk_rate,
606 .round_rate = &omap1_round_ext_clk_rate,
607 .init = &omap1_init_ext_clk,
608};
609
610static struct clk mmc1_ck = {
611 .name = "mmc1_ck",
612 .ops = &clkops_generic,
613 /* Functional clock is direct from ULPD, interface clock is ARMPER */
614 .parent = &armper_ck.clk,
615 .rate = 48000000,
616 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
617 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
618 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
619};
620
621/*
622 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
623 * CONF_MOD_MCBSP3_AUXON ??
624 */
625static struct clk mmc2_ck = {
626 .name = "mmc2_ck",
627 .ops = &clkops_generic,
628 /* Functional clock is direct from ULPD, interface clock is ARMPER */
629 .parent = &armper_ck.clk,
630 .rate = 48000000,
631 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
632 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
633 .enable_bit = 20,
634};
635
636static struct clk mmc3_ck = {
637 .name = "mmc3_ck",
638 .ops = &clkops_generic,
639 /* Functional clock is direct from ULPD, interface clock is ARMPER */
640 .parent = &armper_ck.clk,
641 .rate = 48000000,
642 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
643 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
644 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
645};
646
647static struct clk virtual_ck_mpu = {
648 .name = "mpu",
649 .ops = &clkops_null,
650 .parent = &arm_ck, /* Is smarter alias for */
651 .recalc = &followparent_recalc,
652 .set_rate = &omap1_select_table_rate,
653 .round_rate = &omap1_round_to_table_rate,
654};
655
656/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
657remains active during MPU idle whenever this is enabled */
658static struct clk i2c_fck = {
659 .name = "i2c_fck",
660 .ops = &clkops_null,
661 .flags = CLOCK_NO_IDLE_PARENT,
662 .parent = &armxor_ck.clk,
663 .recalc = &followparent_recalc,
664};
665
666static struct clk i2c_ick = {
667 .name = "i2c_ick",
668 .ops = &clkops_null,
669 .flags = CLOCK_NO_IDLE_PARENT,
670 .parent = &armper_ck.clk,
671 .recalc = &followparent_recalc,
672};
673
674/*
675 * clkdev integration
676 */
677
678static struct omap_clk omap_clks[] = {
679 /* non-ULPD clocks */
680 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
681 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
682 /* CK_GEN1 clocks */
683 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
684 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
685 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
686 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
687 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
688 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
689 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
690 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
691 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
692 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
693 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
694 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
695 /* CK_GEN2 clocks */
696 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
697 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
698 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
699 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
700 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
701 /* CK_GEN3 clocks */
702 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
703 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
704 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
705 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
706 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
707 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
708 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
709 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
710 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
711 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
712 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
713 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
714 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
715 /* ULPD clocks */
716 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
717 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
718 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
719 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
720 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
721 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
722 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
723 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
724 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
725 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
726 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
727 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
728 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
729 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
730 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
731 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
732 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
733 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
734 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
735 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
736 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
737 /* Virtual clocks */
738 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
739 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
740 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
741 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
742 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
743 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
744 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
745 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
746 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
747 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
748 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
749 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
750 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
751 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
752 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
753 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
754 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
755 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
756};
757
758/*
759 * init
760 */
761
762static struct clk_functions omap1_clk_functions = {
763 .clk_enable = omap1_clk_enable,
764 .clk_disable = omap1_clk_disable,
765 .clk_round_rate = omap1_clk_round_rate,
766 .clk_set_rate = omap1_clk_set_rate,
767 .clk_disable_unused = omap1_clk_disable_unused,
768};
769
770int __init omap1_clk_init(void)
771{
772 struct omap_clk *c;
773 const struct omap_clock_config *info;
774 int crystal_type = 0; /* Default 12 MHz */
775 u32 reg, cpu_mask;
776
777#ifdef CONFIG_DEBUG_LL
778 /*
779 * Resets some clocks that may be left on from bootloader,
780 * but leaves serial clocks on.
781 */
782 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
783#endif
784
785 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
786 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
787 omap_writew(reg, SOFT_REQ_REG);
788 if (!cpu_is_omap15xx())
789 omap_writew(0, SOFT_REQ_REG2);
790
791 clk_init(&omap1_clk_functions);
792
793 /* By default all idlect1 clocks are allowed to idle */
794 arm_idlect1_mask = ~0;
795
796 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
797 clk_preinit(c->lk.clk);
798
799 cpu_mask = 0;
800 if (cpu_is_omap16xx())
801 cpu_mask |= CK_16XX;
802 if (cpu_is_omap1510())
803 cpu_mask |= CK_1510;
804 if (cpu_is_omap7xx())
805 cpu_mask |= CK_7XX;
806 if (cpu_is_omap310())
807 cpu_mask |= CK_310;
808
809 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
810 if (c->cpu & cpu_mask) {
811 clkdev_add(&c->lk);
812 clk_register(c->lk.clk);
813 }
814
815 /* Pointers to these clocks are needed by code in clock.c */
816 api_ck_p = clk_get(NULL, "api_ck");
817 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
818 ck_ref_p = clk_get(NULL, "ck_ref");
819
820 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
821 if (info != NULL) {
822 if (!cpu_is_omap15xx())
823 crystal_type = info->system_clock_type;
824 }
825
826 if (cpu_is_omap7xx())
827 ck_ref.rate = 13000000;
828 if (cpu_is_omap16xx() && crystal_type == 2)
829 ck_ref.rate = 19200000;
830
831 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
832 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
833 omap_readw(ARM_CKCTL));
834
835 /* We want to be in syncronous scalable mode */
836 omap_writew(0x1000, ARM_SYSST);
837
838#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
839 /* Use values set by bootloader. Determine PLL rate and recalculate
840 * dependent clocks as if kernel had changed PLL or divisors.
841 */
842 {
843 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
844
845 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
846 if (pll_ctl_val & 0x10) {
847 /* PLL enabled, apply multiplier and divisor */
848 if (pll_ctl_val & 0xf80)
849 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
850 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
851 } else {
852 /* PLL disabled, apply bypass divisor */
853 switch (pll_ctl_val & 0xc) {
854 case 0:
855 break;
856 case 0x4:
857 ck_dpll1.rate /= 2;
858 break;
859 default:
860 ck_dpll1.rate /= 4;
861 break;
862 }
863 }
864 }
865#else
866 /* Find the highest supported frequency and enable it */
867 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
868 printk(KERN_ERR "System frequencies not set. Check your config.\n");
869 /* Guess sane values (60MHz) */
870 omap_writew(0x2290, DPLL_CTL);
871 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
872 ck_dpll1.rate = 60000000;
873 }
874#endif
875 propagate_rate(&ck_dpll1);
876 /* Cache rates for clocks connected to ck_ref (not dpll1) */
877 propagate_rate(&ck_ref);
878 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
879 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
880 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
881 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
882 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
883
884 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
885 /* Select slicer output as OMAP input clock */
886 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
887 OMAP7XX_PCC_UPLD_CTRL);
888 }
889
890 /* Amstrad Delta wants BCLK high when inactive */
891 if (machine_is_ams_delta())
892 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
893 (1 << SDW_MCLK_INV_BIT),
894 ULPD_CLOCK_CTRL);
895
896 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
897 /* (on 730, bit 13 must not be cleared) */
898 if (cpu_is_omap7xx())
899 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
900 else
901 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
902
903 /* Put DSP/MPUI into reset until needed */
904 omap_writew(0, ARM_RSTCT1);
905 omap_writew(1, ARM_RSTCT2);
906 omap_writew(0x400, ARM_IDLECT1);
907
908 /*
909 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
910 * of the ARM_IDLECT2 register must be set to zero. The power-on
911 * default value of this bit is one.
912 */
913 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
914
915 /*
916 * Only enable those clocks we will need, let the drivers
917 * enable other clocks as necessary
918 */
919 clk_enable(&armper_ck.clk);
920 clk_enable(&armxor_ck.clk);
921 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
922
923 if (cpu_is_omap15xx())
924 clk_enable(&arm_gpio_ck);
925
926 return 0;
927}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap1/clock_data.c
4 *
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 *
9 * To do:
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/cpufreq.h>
18#include <linux/delay.h>
19
20#include <asm/mach-types.h> /* for machine_is_* */
21
22#include "soc.h"
23
24#include <mach/hardware.h>
25#include <mach/usb.h> /* for OTG_BASE */
26
27#include "iomap.h"
28#include "clock.h"
29#include "sram.h"
30
31/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
32#define IDL_CLKOUT_ARM_SHIFT 12
33#define IDLTIM_ARM_SHIFT 9
34#define IDLAPI_ARM_SHIFT 8
35#define IDLIF_ARM_SHIFT 6
36#define IDLLB_ARM_SHIFT 4 /* undocumented? */
37#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
38#define IDLPER_ARM_SHIFT 2
39#define IDLXORP_ARM_SHIFT 1
40#define IDLWDT_ARM_SHIFT 0
41
42/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
43#define CONF_MOD_UART3_CLK_MODE_R 31
44#define CONF_MOD_UART2_CLK_MODE_R 30
45#define CONF_MOD_UART1_CLK_MODE_R 29
46#define CONF_MOD_MMC_SD_CLK_REQ_R 23
47#define CONF_MOD_MCBSP3_AUXON 20
48
49/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
50#define CONF_MOD_SOSSI_CLK_EN_R 16
51
52/* Some OTG_SYSCON_2-specific bit fields */
53#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
54
55/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
56#define SOFT_MMC2_DPLL_REQ_SHIFT 13
57#define SOFT_MMC_DPLL_REQ_SHIFT 12
58#define SOFT_UART3_DPLL_REQ_SHIFT 11
59#define SOFT_UART2_DPLL_REQ_SHIFT 10
60#define SOFT_UART1_DPLL_REQ_SHIFT 9
61#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
62#define SOFT_CAM_DPLL_REQ_SHIFT 7
63#define SOFT_COM_MCKO_REQ_SHIFT 6
64#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
65#define USB_REQ_EN_SHIFT 4
66#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
67#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
68#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
69#define SOFT_DPLL_REQ_SHIFT 0
70
71/*
72 * Omap1 clocks
73 */
74
75static struct clk ck_ref = {
76 .name = "ck_ref",
77 .ops = &clkops_null,
78 .rate = 12000000,
79};
80
81static struct clk ck_dpll1 = {
82 .name = "ck_dpll1",
83 .ops = &clkops_null,
84 .parent = &ck_ref,
85};
86
87/*
88 * FIXME: This clock seems to be necessary but no-one has asked for its
89 * activation. [ FIX: SoSSI, SSR ]
90 */
91static struct arm_idlect1_clk ck_dpll1out = {
92 .clk = {
93 .name = "ck_dpll1out",
94 .ops = &clkops_generic,
95 .parent = &ck_dpll1,
96 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
97 ENABLE_ON_INIT,
98 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
99 .enable_bit = EN_CKOUT_ARM,
100 .recalc = &followparent_recalc,
101 },
102 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
103};
104
105static struct clk sossi_ck = {
106 .name = "ck_sossi",
107 .ops = &clkops_generic,
108 .parent = &ck_dpll1out.clk,
109 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
110 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
111 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
112 .recalc = &omap1_sossi_recalc,
113 .set_rate = &omap1_set_sossi_rate,
114};
115
116static struct clk arm_ck = {
117 .name = "arm_ck",
118 .ops = &clkops_null,
119 .parent = &ck_dpll1,
120 .rate_offset = CKCTL_ARMDIV_OFFSET,
121 .recalc = &omap1_ckctl_recalc,
122 .round_rate = omap1_clk_round_rate_ckctl_arm,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
124};
125
126static struct arm_idlect1_clk armper_ck = {
127 .clk = {
128 .name = "armper_ck",
129 .ops = &clkops_generic,
130 .parent = &ck_dpll1,
131 .flags = CLOCK_IDLE_CONTROL,
132 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
133 .enable_bit = EN_PERCK,
134 .rate_offset = CKCTL_PERDIV_OFFSET,
135 .recalc = &omap1_ckctl_recalc,
136 .round_rate = omap1_clk_round_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
138 },
139 .idlect_shift = IDLPER_ARM_SHIFT,
140};
141
142/*
143 * FIXME: This clock seems to be necessary but no-one has asked for its
144 * activation. [ GPIO code for 1510 ]
145 */
146static struct clk arm_gpio_ck = {
147 .name = "ick",
148 .ops = &clkops_generic,
149 .parent = &ck_dpll1,
150 .flags = ENABLE_ON_INIT,
151 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
152 .enable_bit = EN_GPIOCK,
153 .recalc = &followparent_recalc,
154};
155
156static struct arm_idlect1_clk armxor_ck = {
157 .clk = {
158 .name = "armxor_ck",
159 .ops = &clkops_generic,
160 .parent = &ck_ref,
161 .flags = CLOCK_IDLE_CONTROL,
162 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
163 .enable_bit = EN_XORPCK,
164 .recalc = &followparent_recalc,
165 },
166 .idlect_shift = IDLXORP_ARM_SHIFT,
167};
168
169static struct arm_idlect1_clk armtim_ck = {
170 .clk = {
171 .name = "armtim_ck",
172 .ops = &clkops_generic,
173 .parent = &ck_ref,
174 .flags = CLOCK_IDLE_CONTROL,
175 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
176 .enable_bit = EN_TIMCK,
177 .recalc = &followparent_recalc,
178 },
179 .idlect_shift = IDLTIM_ARM_SHIFT,
180};
181
182static struct arm_idlect1_clk armwdt_ck = {
183 .clk = {
184 .name = "armwdt_ck",
185 .ops = &clkops_generic,
186 .parent = &ck_ref,
187 .flags = CLOCK_IDLE_CONTROL,
188 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
189 .enable_bit = EN_WDTCK,
190 .fixed_div = 14,
191 .recalc = &omap_fixed_divisor_recalc,
192 },
193 .idlect_shift = IDLWDT_ARM_SHIFT,
194};
195
196static struct clk arminth_ck16xx = {
197 .name = "arminth_ck",
198 .ops = &clkops_null,
199 .parent = &arm_ck,
200 .recalc = &followparent_recalc,
201 /* Note: On 16xx the frequency can be divided by 2 by programming
202 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
203 *
204 * 1510 version is in TC clocks.
205 */
206};
207
208static struct clk dsp_ck = {
209 .name = "dsp_ck",
210 .ops = &clkops_generic,
211 .parent = &ck_dpll1,
212 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
213 .enable_bit = EN_DSPCK,
214 .rate_offset = CKCTL_DSPDIV_OFFSET,
215 .recalc = &omap1_ckctl_recalc,
216 .round_rate = omap1_clk_round_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
218};
219
220static struct clk dspmmu_ck = {
221 .name = "dspmmu_ck",
222 .ops = &clkops_null,
223 .parent = &ck_dpll1,
224 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
225 .recalc = &omap1_ckctl_recalc,
226 .round_rate = omap1_clk_round_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
228};
229
230static struct clk dspper_ck = {
231 .name = "dspper_ck",
232 .ops = &clkops_dspck,
233 .parent = &ck_dpll1,
234 .enable_reg = DSP_IDLECT2,
235 .enable_bit = EN_PERCK,
236 .rate_offset = CKCTL_PERDIV_OFFSET,
237 .recalc = &omap1_ckctl_recalc_dsp_domain,
238 .round_rate = omap1_clk_round_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
240};
241
242static struct clk dspxor_ck = {
243 .name = "dspxor_ck",
244 .ops = &clkops_dspck,
245 .parent = &ck_ref,
246 .enable_reg = DSP_IDLECT2,
247 .enable_bit = EN_XORPCK,
248 .recalc = &followparent_recalc,
249};
250
251static struct clk dsptim_ck = {
252 .name = "dsptim_ck",
253 .ops = &clkops_dspck,
254 .parent = &ck_ref,
255 .enable_reg = DSP_IDLECT2,
256 .enable_bit = EN_DSPTIMCK,
257 .recalc = &followparent_recalc,
258};
259
260static struct arm_idlect1_clk tc_ck = {
261 .clk = {
262 .name = "tc_ck",
263 .ops = &clkops_null,
264 .parent = &ck_dpll1,
265 .flags = CLOCK_IDLE_CONTROL,
266 .rate_offset = CKCTL_TCDIV_OFFSET,
267 .recalc = &omap1_ckctl_recalc,
268 .round_rate = omap1_clk_round_rate_ckctl_arm,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
270 },
271 .idlect_shift = IDLIF_ARM_SHIFT,
272};
273
274static struct clk arminth_ck1510 = {
275 .name = "arminth_ck",
276 .ops = &clkops_null,
277 .parent = &tc_ck.clk,
278 .recalc = &followparent_recalc,
279 /* Note: On 1510 the frequency follows TC_CK
280 *
281 * 16xx version is in MPU clocks.
282 */
283};
284
285static struct clk tipb_ck = {
286 /* No-idle controlled by "tc_ck" */
287 .name = "tipb_ck",
288 .ops = &clkops_null,
289 .parent = &tc_ck.clk,
290 .recalc = &followparent_recalc,
291};
292
293static struct clk l3_ocpi_ck = {
294 /* No-idle controlled by "tc_ck" */
295 .name = "l3_ocpi_ck",
296 .ops = &clkops_generic,
297 .parent = &tc_ck.clk,
298 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
299 .enable_bit = EN_OCPI_CK,
300 .recalc = &followparent_recalc,
301};
302
303static struct clk tc1_ck = {
304 .name = "tc1_ck",
305 .ops = &clkops_generic,
306 .parent = &tc_ck.clk,
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
308 .enable_bit = EN_TC1_CK,
309 .recalc = &followparent_recalc,
310};
311
312/*
313 * FIXME: This clock seems to be necessary but no-one has asked for its
314 * activation. [ pm.c (SRAM), CCP, Camera ]
315 */
316static struct clk tc2_ck = {
317 .name = "tc2_ck",
318 .ops = &clkops_generic,
319 .parent = &tc_ck.clk,
320 .flags = ENABLE_ON_INIT,
321 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
322 .enable_bit = EN_TC2_CK,
323 .recalc = &followparent_recalc,
324};
325
326static struct clk dma_ck = {
327 /* No-idle controlled by "tc_ck" */
328 .name = "dma_ck",
329 .ops = &clkops_null,
330 .parent = &tc_ck.clk,
331 .recalc = &followparent_recalc,
332};
333
334static struct clk dma_lcdfree_ck = {
335 .name = "dma_lcdfree_ck",
336 .ops = &clkops_null,
337 .parent = &tc_ck.clk,
338 .recalc = &followparent_recalc,
339};
340
341static struct arm_idlect1_clk api_ck = {
342 .clk = {
343 .name = "api_ck",
344 .ops = &clkops_generic,
345 .parent = &tc_ck.clk,
346 .flags = CLOCK_IDLE_CONTROL,
347 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
348 .enable_bit = EN_APICK,
349 .recalc = &followparent_recalc,
350 },
351 .idlect_shift = IDLAPI_ARM_SHIFT,
352};
353
354static struct arm_idlect1_clk lb_ck = {
355 .clk = {
356 .name = "lb_ck",
357 .ops = &clkops_generic,
358 .parent = &tc_ck.clk,
359 .flags = CLOCK_IDLE_CONTROL,
360 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
361 .enable_bit = EN_LBCK,
362 .recalc = &followparent_recalc,
363 },
364 .idlect_shift = IDLLB_ARM_SHIFT,
365};
366
367static struct clk rhea1_ck = {
368 .name = "rhea1_ck",
369 .ops = &clkops_null,
370 .parent = &tc_ck.clk,
371 .recalc = &followparent_recalc,
372};
373
374static struct clk rhea2_ck = {
375 .name = "rhea2_ck",
376 .ops = &clkops_null,
377 .parent = &tc_ck.clk,
378 .recalc = &followparent_recalc,
379};
380
381static struct clk lcd_ck_16xx = {
382 .name = "lcd_ck",
383 .ops = &clkops_generic,
384 .parent = &ck_dpll1,
385 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
386 .enable_bit = EN_LCDCK,
387 .rate_offset = CKCTL_LCDDIV_OFFSET,
388 .recalc = &omap1_ckctl_recalc,
389 .round_rate = omap1_clk_round_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
391};
392
393static struct arm_idlect1_clk lcd_ck_1510 = {
394 .clk = {
395 .name = "lcd_ck",
396 .ops = &clkops_generic,
397 .parent = &ck_dpll1,
398 .flags = CLOCK_IDLE_CONTROL,
399 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
400 .enable_bit = EN_LCDCK,
401 .rate_offset = CKCTL_LCDDIV_OFFSET,
402 .recalc = &omap1_ckctl_recalc,
403 .round_rate = omap1_clk_round_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
405 },
406 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
407};
408
409/*
410 * XXX The enable_bit here is misused - it simply switches between 12MHz
411 * and 48MHz. Reimplement with clksel.
412 *
413 * XXX does this need SYSC register handling?
414 */
415static struct clk uart1_1510 = {
416 .name = "uart1_ck",
417 .ops = &clkops_null,
418 /* Direct from ULPD, no real parent */
419 .parent = &armper_ck.clk,
420 .rate = 12000000,
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
422 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
423 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
424 .set_rate = &omap1_set_uart_rate,
425 .recalc = &omap1_uart_recalc,
426};
427
428/*
429 * XXX The enable_bit here is misused - it simply switches between 12MHz
430 * and 48MHz. Reimplement with clksel.
431 *
432 * XXX SYSC register handling does not belong in the clock framework
433 */
434static struct uart_clk uart1_16xx = {
435 .clk = {
436 .name = "uart1_ck",
437 .ops = &clkops_uart_16xx,
438 /* Direct from ULPD, no real parent */
439 .parent = &armper_ck.clk,
440 .rate = 48000000,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
442 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
443 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
444 },
445 .sysc_addr = 0xfffb0054,
446};
447
448/*
449 * XXX The enable_bit here is misused - it simply switches between 12MHz
450 * and 48MHz. Reimplement with clksel.
451 *
452 * XXX does this need SYSC register handling?
453 */
454static struct clk uart2_ck = {
455 .name = "uart2_ck",
456 .ops = &clkops_null,
457 /* Direct from ULPD, no real parent */
458 .parent = &armper_ck.clk,
459 .rate = 12000000,
460 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
461 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
462 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
463 .set_rate = &omap1_set_uart_rate,
464 .recalc = &omap1_uart_recalc,
465};
466
467/*
468 * XXX The enable_bit here is misused - it simply switches between 12MHz
469 * and 48MHz. Reimplement with clksel.
470 *
471 * XXX does this need SYSC register handling?
472 */
473static struct clk uart3_1510 = {
474 .name = "uart3_ck",
475 .ops = &clkops_null,
476 /* Direct from ULPD, no real parent */
477 .parent = &armper_ck.clk,
478 .rate = 12000000,
479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
480 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
481 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
482 .set_rate = &omap1_set_uart_rate,
483 .recalc = &omap1_uart_recalc,
484};
485
486/*
487 * XXX The enable_bit here is misused - it simply switches between 12MHz
488 * and 48MHz. Reimplement with clksel.
489 *
490 * XXX SYSC register handling does not belong in the clock framework
491 */
492static struct uart_clk uart3_16xx = {
493 .clk = {
494 .name = "uart3_ck",
495 .ops = &clkops_uart_16xx,
496 /* Direct from ULPD, no real parent */
497 .parent = &armper_ck.clk,
498 .rate = 48000000,
499 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
500 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
501 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
502 },
503 .sysc_addr = 0xfffb9854,
504};
505
506static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
507 .name = "usb_clko",
508 .ops = &clkops_generic,
509 /* Direct from ULPD, no parent */
510 .rate = 6000000,
511 .flags = ENABLE_REG_32BIT,
512 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
513 .enable_bit = USB_MCLK_EN_BIT,
514};
515
516static struct clk usb_hhc_ck1510 = {
517 .name = "usb_hhc_ck",
518 .ops = &clkops_generic,
519 /* Direct from ULPD, no parent */
520 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
521 .flags = ENABLE_REG_32BIT,
522 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
523 .enable_bit = USB_HOST_HHC_UHOST_EN,
524};
525
526static struct clk usb_hhc_ck16xx = {
527 .name = "usb_hhc_ck",
528 .ops = &clkops_generic,
529 /* Direct from ULPD, no parent */
530 .rate = 48000000,
531 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
532 .flags = ENABLE_REG_32BIT,
533 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
534 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
535};
536
537static struct clk usb_dc_ck = {
538 .name = "usb_dc_ck",
539 .ops = &clkops_generic,
540 /* Direct from ULPD, no parent */
541 .rate = 48000000,
542 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
543 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
544};
545
546static struct clk uart1_7xx = {
547 .name = "uart1_ck",
548 .ops = &clkops_generic,
549 /* Direct from ULPD, no parent */
550 .rate = 12000000,
551 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
552 .enable_bit = 9,
553};
554
555static struct clk uart2_7xx = {
556 .name = "uart2_ck",
557 .ops = &clkops_generic,
558 /* Direct from ULPD, no parent */
559 .rate = 12000000,
560 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
561 .enable_bit = 11,
562};
563
564static struct clk mclk_1510 = {
565 .name = "mclk",
566 .ops = &clkops_generic,
567 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
568 .rate = 12000000,
569 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
570 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
571};
572
573static struct clk mclk_16xx = {
574 .name = "mclk",
575 .ops = &clkops_generic,
576 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
577 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
578 .enable_bit = COM_ULPD_PLL_CLK_REQ,
579 .set_rate = &omap1_set_ext_clk_rate,
580 .round_rate = &omap1_round_ext_clk_rate,
581 .init = &omap1_init_ext_clk,
582};
583
584static struct clk bclk_1510 = {
585 .name = "bclk",
586 .ops = &clkops_generic,
587 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
588 .rate = 12000000,
589};
590
591static struct clk bclk_16xx = {
592 .name = "bclk",
593 .ops = &clkops_generic,
594 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
595 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
596 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
597 .set_rate = &omap1_set_ext_clk_rate,
598 .round_rate = &omap1_round_ext_clk_rate,
599 .init = &omap1_init_ext_clk,
600};
601
602static struct clk mmc1_ck = {
603 .name = "mmc1_ck",
604 .ops = &clkops_generic,
605 /* Functional clock is direct from ULPD, interface clock is ARMPER */
606 .parent = &armper_ck.clk,
607 .rate = 48000000,
608 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
609 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
610 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
611};
612
613/*
614 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
615 * CONF_MOD_MCBSP3_AUXON ??
616 */
617static struct clk mmc2_ck = {
618 .name = "mmc2_ck",
619 .ops = &clkops_generic,
620 /* Functional clock is direct from ULPD, interface clock is ARMPER */
621 .parent = &armper_ck.clk,
622 .rate = 48000000,
623 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
624 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
625 .enable_bit = 20,
626};
627
628static struct clk mmc3_ck = {
629 .name = "mmc3_ck",
630 .ops = &clkops_generic,
631 /* Functional clock is direct from ULPD, interface clock is ARMPER */
632 .parent = &armper_ck.clk,
633 .rate = 48000000,
634 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
635 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
636 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
637};
638
639static struct clk virtual_ck_mpu = {
640 .name = "mpu",
641 .ops = &clkops_null,
642 .parent = &arm_ck, /* Is smarter alias for */
643 .recalc = &followparent_recalc,
644 .set_rate = &omap1_select_table_rate,
645 .round_rate = &omap1_round_to_table_rate,
646};
647
648/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
649remains active during MPU idle whenever this is enabled */
650static struct clk i2c_fck = {
651 .name = "i2c_fck",
652 .ops = &clkops_null,
653 .flags = CLOCK_NO_IDLE_PARENT,
654 .parent = &armxor_ck.clk,
655 .recalc = &followparent_recalc,
656};
657
658static struct clk i2c_ick = {
659 .name = "i2c_ick",
660 .ops = &clkops_null,
661 .flags = CLOCK_NO_IDLE_PARENT,
662 .parent = &armper_ck.clk,
663 .recalc = &followparent_recalc,
664};
665
666/*
667 * clkdev integration
668 */
669
670static struct omap_clk omap_clks[] = {
671 /* non-ULPD clocks */
672 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
673 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
674 /* CK_GEN1 clocks */
675 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
676 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
677 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
678 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
679 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
680 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
681 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
683 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
684 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
685 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
686 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
687 /* CK_GEN2 clocks */
688 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
689 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
690 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
691 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
693 /* CK_GEN3 clocks */
694 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
695 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
696 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
697 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
698 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
699 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
700 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
701 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
702 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
703 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
704 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
705 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
706 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
707 /* ULPD clocks */
708 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
709 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
710 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
711 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
712 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
713 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
714 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
715 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
716 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
717 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
718 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
719 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
720 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
721 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
722 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
723 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
724 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
725 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
726 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
727 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
728 /* Virtual clocks */
729 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
730 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
731 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
732 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
733 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
734 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
735 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
736 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
737 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
738 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
739 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
740 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
741 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
742 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
743 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
744 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
745 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
746 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
747};
748
749/*
750 * init
751 */
752
753static void __init omap1_show_rates(void)
754{
755 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
756 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
757 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
758 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
759}
760
761u32 cpu_mask;
762
763int __init omap1_clk_init(void)
764{
765 struct omap_clk *c;
766 int crystal_type = 0; /* Default 12 MHz */
767 u32 reg;
768
769#ifdef CONFIG_DEBUG_LL
770 /*
771 * Resets some clocks that may be left on from bootloader,
772 * but leaves serial clocks on.
773 */
774 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
775#endif
776
777 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
778 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
779 omap_writew(reg, SOFT_REQ_REG);
780 if (!cpu_is_omap15xx())
781 omap_writew(0, SOFT_REQ_REG2);
782
783 /* By default all idlect1 clocks are allowed to idle */
784 arm_idlect1_mask = ~0;
785
786 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
787 clk_preinit(c->lk.clk);
788
789 cpu_mask = 0;
790 if (cpu_is_omap1710())
791 cpu_mask |= CK_1710;
792 if (cpu_is_omap16xx())
793 cpu_mask |= CK_16XX;
794 if (cpu_is_omap1510())
795 cpu_mask |= CK_1510;
796 if (cpu_is_omap7xx())
797 cpu_mask |= CK_7XX;
798 if (cpu_is_omap310())
799 cpu_mask |= CK_310;
800
801 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
802 if (c->cpu & cpu_mask) {
803 clkdev_add(&c->lk);
804 clk_register(c->lk.clk);
805 }
806
807 /* Pointers to these clocks are needed by code in clock.c */
808 api_ck_p = clk_get(NULL, "api_ck");
809 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
810 ck_ref_p = clk_get(NULL, "ck_ref");
811
812 if (cpu_is_omap7xx())
813 ck_ref.rate = 13000000;
814 if (cpu_is_omap16xx() && crystal_type == 2)
815 ck_ref.rate = 19200000;
816
817 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
818 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
819 omap_readw(ARM_CKCTL));
820
821 /* We want to be in syncronous scalable mode */
822 omap_writew(0x1000, ARM_SYSST);
823
824
825 /*
826 * Initially use the values set by bootloader. Determine PLL rate and
827 * recalculate dependent clocks as if kernel had changed PLL or
828 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
829 * after the SRAM is initialized.
830 */
831 {
832 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
833
834 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
835 if (pll_ctl_val & 0x10) {
836 /* PLL enabled, apply multiplier and divisor */
837 if (pll_ctl_val & 0xf80)
838 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
839 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
840 } else {
841 /* PLL disabled, apply bypass divisor */
842 switch (pll_ctl_val & 0xc) {
843 case 0:
844 break;
845 case 0x4:
846 ck_dpll1.rate /= 2;
847 break;
848 default:
849 ck_dpll1.rate /= 4;
850 break;
851 }
852 }
853 }
854 propagate_rate(&ck_dpll1);
855 /* Cache rates for clocks connected to ck_ref (not dpll1) */
856 propagate_rate(&ck_ref);
857 omap1_show_rates();
858 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
859 /* Select slicer output as OMAP input clock */
860 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
861 OMAP7XX_PCC_UPLD_CTRL);
862 }
863
864 /* Amstrad Delta wants BCLK high when inactive */
865 if (machine_is_ams_delta())
866 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
867 (1 << SDW_MCLK_INV_BIT),
868 ULPD_CLOCK_CTRL);
869
870 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
871 /* (on 730, bit 13 must not be cleared) */
872 if (cpu_is_omap7xx())
873 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
874 else
875 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
876
877 /* Put DSP/MPUI into reset until needed */
878 omap_writew(0, ARM_RSTCT1);
879 omap_writew(1, ARM_RSTCT2);
880 omap_writew(0x400, ARM_IDLECT1);
881
882 /*
883 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
884 * of the ARM_IDLECT2 register must be set to zero. The power-on
885 * default value of this bit is one.
886 */
887 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
888
889 /*
890 * Only enable those clocks we will need, let the drivers
891 * enable other clocks as necessary
892 */
893 clk_enable(&armper_ck.clk);
894 clk_enable(&armxor_ck.clk);
895 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
896
897 if (cpu_is_omap15xx())
898 clk_enable(&arm_gpio_ck);
899
900 return 0;
901}
902
903#define OMAP1_DPLL1_SANE_VALUE 60000000
904
905void __init omap1_clk_late_init(void)
906{
907 unsigned long rate = ck_dpll1.rate;
908
909 /* Find the highest supported frequency and enable it */
910 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
911 pr_err("System frequencies not set, using default. Check your config.\n");
912 /*
913 * Reprogramming the DPLL is tricky, it must be done from SRAM.
914 */
915 omap_sram_reprogram_clock(0x2290, 0x0005);
916 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
917 }
918 propagate_rate(&ck_dpll1);
919 omap1_show_rates();
920 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
921}