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1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/prefetch.h>
22#include <linux/usb.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26
27#include "musb_core.h"
28
29struct tusb6010_glue {
30 struct device *dev;
31 struct platform_device *musb;
32};
33
34static void tusb_musb_set_vbus(struct musb *musb, int is_on);
35
36#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
37#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
38
39/*
40 * Checks the revision. We need to use the DMA register as 3.0 does not
41 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
42 */
43u8 tusb_get_revision(struct musb *musb)
44{
45 void __iomem *tbase = musb->ctrl_base;
46 u32 die_id;
47 u8 rev;
48
49 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
50 if (TUSB_REV_MAJOR(rev) == 3) {
51 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
52 TUSB_DIDR1_HI));
53 if (die_id >= TUSB_DIDR1_HI_REV_31)
54 rev |= 1;
55 }
56
57 return rev;
58}
59
60static int tusb_print_revision(struct musb *musb)
61{
62 void __iomem *tbase = musb->ctrl_base;
63 u8 rev;
64
65 rev = tusb_get_revision(musb);
66
67 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
68 "prcm",
69 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
70 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 "int",
72 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
73 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 "gpio",
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 "dma",
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 "dieid",
81 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
82 "rev",
83 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
84
85 return tusb_get_revision(musb);
86}
87
88#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
89 | TUSB_PHY_OTG_CTRL_TESTM0)
90
91/*
92 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
93 * Disables power detection in PHY for the duration of idle.
94 */
95static void tusb_wbus_quirk(struct musb *musb, int enabled)
96{
97 void __iomem *tbase = musb->ctrl_base;
98 static u32 phy_otg_ctrl, phy_otg_ena;
99 u32 tmp;
100
101 if (enabled) {
102 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
103 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
104 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
105 | phy_otg_ena | WBUS_QUIRK_MASK;
106 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
107 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
108 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
109 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
110 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
112 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
113 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
114 & TUSB_PHY_OTG_CTRL_TESTM2) {
115 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
116 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
117 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
118 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
119 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
121 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
122 phy_otg_ctrl = 0;
123 phy_otg_ena = 0;
124 }
125}
126
127/*
128 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
129 * so both loading and unloading FIFOs need explicit byte counts.
130 */
131
132static inline void
133tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
134{
135 u32 val;
136 int i;
137
138 if (len > 4) {
139 for (i = 0; i < (len >> 2); i++) {
140 memcpy(&val, buf, 4);
141 musb_writel(fifo, 0, val);
142 buf += 4;
143 }
144 len %= 4;
145 }
146 if (len > 0) {
147 /* Write the rest 1 - 3 bytes to FIFO */
148 memcpy(&val, buf, len);
149 musb_writel(fifo, 0, val);
150 }
151}
152
153static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
154 void __iomem *buf, u16 len)
155{
156 u32 val;
157 int i;
158
159 if (len > 4) {
160 for (i = 0; i < (len >> 2); i++) {
161 val = musb_readl(fifo, 0);
162 memcpy(buf, &val, 4);
163 buf += 4;
164 }
165 len %= 4;
166 }
167 if (len > 0) {
168 /* Read the rest 1 - 3 bytes from FIFO */
169 val = musb_readl(fifo, 0);
170 memcpy(buf, &val, len);
171 }
172}
173
174void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
175{
176 struct musb *musb = hw_ep->musb;
177 void __iomem *ep_conf = hw_ep->conf;
178 void __iomem *fifo = hw_ep->fifo;
179 u8 epnum = hw_ep->epnum;
180
181 prefetch(buf);
182
183 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
184 'T', epnum, fifo, len, buf);
185
186 if (epnum)
187 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
188 TUSB_EP_CONFIG_XFR_SIZE(len));
189 else
190 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
191 TUSB_EP0_CONFIG_XFR_SIZE(len));
192
193 if (likely((0x01 & (unsigned long) buf) == 0)) {
194
195 /* Best case is 32bit-aligned destination address */
196 if ((0x02 & (unsigned long) buf) == 0) {
197 if (len >= 4) {
198 writesl(fifo, buf, len >> 2);
199 buf += (len & ~0x03);
200 len &= 0x03;
201 }
202 } else {
203 if (len >= 2) {
204 u32 val;
205 int i;
206
207 /* Cannot use writesw, fifo is 32-bit */
208 for (i = 0; i < (len >> 2); i++) {
209 val = (u32)(*(u16 *)buf);
210 buf += 2;
211 val |= (*(u16 *)buf) << 16;
212 buf += 2;
213 musb_writel(fifo, 0, val);
214 }
215 len &= 0x03;
216 }
217 }
218 }
219
220 if (len > 0)
221 tusb_fifo_write_unaligned(fifo, buf, len);
222}
223
224void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
225{
226 struct musb *musb = hw_ep->musb;
227 void __iomem *ep_conf = hw_ep->conf;
228 void __iomem *fifo = hw_ep->fifo;
229 u8 epnum = hw_ep->epnum;
230
231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
232 'R', epnum, fifo, len, buf);
233
234 if (epnum)
235 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
236 TUSB_EP_CONFIG_XFR_SIZE(len));
237 else
238 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
239
240 if (likely((0x01 & (unsigned long) buf) == 0)) {
241
242 /* Best case is 32bit-aligned destination address */
243 if ((0x02 & (unsigned long) buf) == 0) {
244 if (len >= 4) {
245 readsl(fifo, buf, len >> 2);
246 buf += (len & ~0x03);
247 len &= 0x03;
248 }
249 } else {
250 if (len >= 2) {
251 u32 val;
252 int i;
253
254 /* Cannot use readsw, fifo is 32-bit */
255 for (i = 0; i < (len >> 2); i++) {
256 val = musb_readl(fifo, 0);
257 *(u16 *)buf = (u16)(val & 0xffff);
258 buf += 2;
259 *(u16 *)buf = (u16)(val >> 16);
260 buf += 2;
261 }
262 len &= 0x03;
263 }
264 }
265 }
266
267 if (len > 0)
268 tusb_fifo_read_unaligned(fifo, buf, len);
269}
270
271static struct musb *the_musb;
272
273/* This is used by gadget drivers, and OTG transceiver logic, allowing
274 * at most mA current to be drawn from VBUS during a Default-B session
275 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
276 * mode), or low power Default-B sessions, something else supplies power.
277 * Caller must take care of locking.
278 */
279static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
280{
281 struct musb *musb = the_musb;
282 void __iomem *tbase = musb->ctrl_base;
283 u32 reg;
284
285 /* tps65030 seems to consume max 100mA, with maybe 60mA available
286 * (measured on one board) for things other than tps and tusb.
287 *
288 * Boards sharing the CPU clock with CLKIN will need to prevent
289 * certain idle sleep states while the USB link is active.
290 *
291 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
292 * The actual current usage would be very board-specific. For now,
293 * it's simpler to just use an aggregate (also board-specific).
294 */
295 if (x->default_a || mA < (musb->min_power << 1))
296 mA = 0;
297
298 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
299 if (mA) {
300 musb->is_bus_powered = 1;
301 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
302 } else {
303 musb->is_bus_powered = 0;
304 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
305 }
306 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
307
308 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
309 return 0;
310}
311
312/* workaround for issue 13: change clock during chip idle
313 * (to be fixed in rev3 silicon) ... symptoms include disconnect
314 * or looping suspend/resume cycles
315 */
316static void tusb_set_clock_source(struct musb *musb, unsigned mode)
317{
318 void __iomem *tbase = musb->ctrl_base;
319 u32 reg;
320
321 reg = musb_readl(tbase, TUSB_PRCM_CONF);
322 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
323
324 /* 0 = refclk (clkin, XI)
325 * 1 = PHY 60 MHz (internal PLL)
326 * 2 = not supported
327 * 3 = what?
328 */
329 if (mode > 0)
330 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
331
332 musb_writel(tbase, TUSB_PRCM_CONF, reg);
333
334 /* FIXME tusb6010_platform_retime(mode == 0); */
335}
336
337/*
338 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
339 * Other code ensures that we idle unless we're connected _and_ the
340 * USB link is not suspended ... and tells us the relevant wakeup
341 * events. SW_EN for voltage is handled separately.
342 */
343static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
344{
345 void __iomem *tbase = musb->ctrl_base;
346 u32 reg;
347
348 if ((wakeup_enables & TUSB_PRCM_WBUS)
349 && (tusb_get_revision(musb) == TUSB_REV_30))
350 tusb_wbus_quirk(musb, 1);
351
352 tusb_set_clock_source(musb, 0);
353
354 wakeup_enables |= TUSB_PRCM_WNORCS;
355 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
356
357 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
358 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
359 * Presumably that's mostly to save power, hence WID is immaterial ...
360 */
361
362 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
363 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
364 if (is_host_active(musb)) {
365 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
366 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
367 } else {
368 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
369 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
370 }
371 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
372 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
373
374 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
375}
376
377/*
378 * Updates cable VBUS status. Caller must take care of locking.
379 */
380static int tusb_musb_vbus_status(struct musb *musb)
381{
382 void __iomem *tbase = musb->ctrl_base;
383 u32 otg_stat, prcm_mngmt;
384 int ret = 0;
385
386 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
387 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
388
389 /* Temporarily enable VBUS detection if it was disabled for
390 * suspend mode. Unless it's enabled otg_stat and devctl will
391 * not show correct VBUS state.
392 */
393 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
394 u32 tmp = prcm_mngmt;
395 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
396 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
397 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
398 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
399 }
400
401 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
402 ret = 1;
403
404 return ret;
405}
406
407static struct timer_list musb_idle_timer;
408
409static void musb_do_idle(unsigned long _musb)
410{
411 struct musb *musb = (void *)_musb;
412 unsigned long flags;
413
414 spin_lock_irqsave(&musb->lock, flags);
415
416 switch (musb->xceiv->state) {
417 case OTG_STATE_A_WAIT_BCON:
418 if ((musb->a_wait_bcon != 0)
419 && (musb->idle_timeout == 0
420 || time_after(jiffies, musb->idle_timeout))) {
421 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
422 otg_state_string(musb->xceiv->state));
423 }
424 /* FALLTHROUGH */
425 case OTG_STATE_A_IDLE:
426 tusb_musb_set_vbus(musb, 0);
427 default:
428 break;
429 }
430
431 if (!musb->is_active) {
432 u32 wakeups;
433
434 /* wait until khubd handles port change status */
435 if (is_host_active(musb) && (musb->port1_status >> 16))
436 goto done;
437
438 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
439 wakeups = 0;
440 } else {
441 wakeups = TUSB_PRCM_WHOSTDISCON
442 | TUSB_PRCM_WBUS
443 | TUSB_PRCM_WVBUS;
444 if (is_otg_enabled(musb))
445 wakeups |= TUSB_PRCM_WID;
446 }
447 tusb_allow_idle(musb, wakeups);
448 }
449done:
450 spin_unlock_irqrestore(&musb->lock, flags);
451}
452
453/*
454 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
455 * like "disconnected" or "suspended". We'll be woken out of it by
456 * connect, resume, or disconnect.
457 *
458 * Needs to be called as the last function everywhere where there is
459 * register access to TUSB6010 because of NOR flash wake-up.
460 * Caller should own controller spinlock.
461 *
462 * Delay because peripheral enables D+ pullup 3msec after SE0, and
463 * we don't want to treat that full speed J as a wakeup event.
464 * ... peripherals must draw only suspend current after 10 msec.
465 */
466static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
467{
468 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
469 static unsigned long last_timer;
470
471 if (timeout == 0)
472 timeout = default_timeout;
473
474 /* Never idle if active, or when VBUS timeout is not set as host */
475 if (musb->is_active || ((musb->a_wait_bcon == 0)
476 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
477 dev_dbg(musb->controller, "%s active, deleting timer\n",
478 otg_state_string(musb->xceiv->state));
479 del_timer(&musb_idle_timer);
480 last_timer = jiffies;
481 return;
482 }
483
484 if (time_after(last_timer, timeout)) {
485 if (!timer_pending(&musb_idle_timer))
486 last_timer = timeout;
487 else {
488 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
489 return;
490 }
491 }
492 last_timer = timeout;
493
494 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
495 otg_state_string(musb->xceiv->state),
496 (unsigned long)jiffies_to_msecs(timeout - jiffies));
497 mod_timer(&musb_idle_timer, timeout);
498}
499
500/* ticks of 60 MHz clock */
501#define DEVCLOCK 60000000
502#define OTG_TIMER_MS(msecs) ((msecs) \
503 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
504 | TUSB_DEV_OTG_TIMER_ENABLE) \
505 : 0)
506
507static void tusb_musb_set_vbus(struct musb *musb, int is_on)
508{
509 void __iomem *tbase = musb->ctrl_base;
510 u32 conf, prcm, timer;
511 u8 devctl;
512
513 /* HDRC controls CPEN, but beware current surges during device
514 * connect. They can trigger transient overcurrent conditions
515 * that must be ignored.
516 */
517
518 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
519 conf = musb_readl(tbase, TUSB_DEV_CONF);
520 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
521
522 if (is_on) {
523 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
524 musb->xceiv->default_a = 1;
525 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
526 devctl |= MUSB_DEVCTL_SESSION;
527
528 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
529 MUSB_HST_MODE(musb);
530 } else {
531 u32 otg_stat;
532
533 timer = 0;
534
535 /* If ID pin is grounded, we want to be a_idle */
536 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
537 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
538 switch (musb->xceiv->state) {
539 case OTG_STATE_A_WAIT_VRISE:
540 case OTG_STATE_A_WAIT_BCON:
541 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
542 break;
543 case OTG_STATE_A_WAIT_VFALL:
544 musb->xceiv->state = OTG_STATE_A_IDLE;
545 break;
546 default:
547 musb->xceiv->state = OTG_STATE_A_IDLE;
548 }
549 musb->is_active = 0;
550 musb->xceiv->default_a = 1;
551 MUSB_HST_MODE(musb);
552 } else {
553 musb->is_active = 0;
554 musb->xceiv->default_a = 0;
555 musb->xceiv->state = OTG_STATE_B_IDLE;
556 MUSB_DEV_MODE(musb);
557 }
558
559 devctl &= ~MUSB_DEVCTL_SESSION;
560 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
561 }
562 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
563
564 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
565 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
566 musb_writel(tbase, TUSB_DEV_CONF, conf);
567 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
568
569 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
570 otg_state_string(musb->xceiv->state),
571 musb_readb(musb->mregs, MUSB_DEVCTL),
572 musb_readl(tbase, TUSB_DEV_OTG_STAT),
573 conf, prcm);
574}
575
576/*
577 * Sets the mode to OTG, peripheral or host by changing the ID detection.
578 * Caller must take care of locking.
579 *
580 * Note that if a mini-A cable is plugged in the ID line will stay down as
581 * the weak ID pull-up is not able to pull the ID up.
582 *
583 * REVISIT: It would be possible to add support for changing between host
584 * and peripheral modes in non-OTG configurations by reconfiguring hardware
585 * and then setting musb->board_mode. For now, only support OTG mode.
586 */
587static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
588{
589 void __iomem *tbase = musb->ctrl_base;
590 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
591
592 if (musb->board_mode != MUSB_OTG) {
593 ERR("Changing mode currently only supported in OTG mode\n");
594 return -EINVAL;
595 }
596
597 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
598 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
599 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
600 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
601
602 switch (musb_mode) {
603
604 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
605 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
606 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
607 dev_conf |= TUSB_DEV_CONF_ID_SEL;
608 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
609 break;
610 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
611 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
612 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
613 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
614 break;
615 case MUSB_OTG: /* Use PHY ID detection */
616 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
617 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
618 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
619 break;
620
621 default:
622 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
623 return -EINVAL;
624 }
625
626 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
627 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
628 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
629 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
630 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
631
632 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
633 if ((musb_mode == MUSB_PERIPHERAL) &&
634 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
635 INFO("Cannot be peripheral with mini-A cable "
636 "otg_stat: %08x\n", otg_stat);
637
638 return 0;
639}
640
641static inline unsigned long
642tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
643{
644 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
645 unsigned long idle_timeout = 0;
646
647 /* ID pin */
648 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
649 int default_a;
650
651 if (is_otg_enabled(musb))
652 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
653 else
654 default_a = is_host_enabled(musb);
655 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
656 musb->xceiv->default_a = default_a;
657 tusb_musb_set_vbus(musb, default_a);
658
659 /* Don't allow idling immediately */
660 if (default_a)
661 idle_timeout = jiffies + (HZ * 3);
662 }
663
664 /* VBUS state change */
665 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
666
667 /* B-dev state machine: no vbus ~= disconnect */
668 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
669 || !is_host_enabled(musb)) {
670 /* ? musb_root_disconnect(musb); */
671 musb->port1_status &=
672 ~(USB_PORT_STAT_CONNECTION
673 | USB_PORT_STAT_ENABLE
674 | USB_PORT_STAT_LOW_SPEED
675 | USB_PORT_STAT_HIGH_SPEED
676 | USB_PORT_STAT_TEST
677 );
678
679 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
680 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
681 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
682 /* INTR_DISCONNECT can hide... */
683 musb->xceiv->state = OTG_STATE_B_IDLE;
684 musb->int_usb |= MUSB_INTR_DISCONNECT;
685 }
686 musb->is_active = 0;
687 }
688 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
689 otg_state_string(musb->xceiv->state), otg_stat);
690 idle_timeout = jiffies + (1 * HZ);
691 schedule_work(&musb->irq_work);
692
693 } else /* A-dev state machine */ {
694 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
695 otg_state_string(musb->xceiv->state), otg_stat);
696
697 switch (musb->xceiv->state) {
698 case OTG_STATE_A_IDLE:
699 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
700 musb_platform_set_vbus(musb, 1);
701
702 /* CONNECT can wake if a_wait_bcon is set */
703 if (musb->a_wait_bcon != 0)
704 musb->is_active = 0;
705 else
706 musb->is_active = 1;
707
708 /*
709 * OPT FS A TD.4.6 needs few seconds for
710 * A_WAIT_VRISE
711 */
712 idle_timeout = jiffies + (2 * HZ);
713
714 break;
715 case OTG_STATE_A_WAIT_VRISE:
716 /* ignore; A-session-valid < VBUS_VALID/2,
717 * we monitor this with the timer
718 */
719 break;
720 case OTG_STATE_A_WAIT_VFALL:
721 /* REVISIT this irq triggers during short
722 * spikes caused by enumeration ...
723 */
724 if (musb->vbuserr_retry) {
725 musb->vbuserr_retry--;
726 tusb_musb_set_vbus(musb, 1);
727 } else {
728 musb->vbuserr_retry
729 = VBUSERR_RETRY_COUNT;
730 tusb_musb_set_vbus(musb, 0);
731 }
732 break;
733 default:
734 break;
735 }
736 }
737 }
738
739 /* OTG timer expiration */
740 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
741 u8 devctl;
742
743 dev_dbg(musb->controller, "%s timer, %03x\n",
744 otg_state_string(musb->xceiv->state), otg_stat);
745
746 switch (musb->xceiv->state) {
747 case OTG_STATE_A_WAIT_VRISE:
748 /* VBUS has probably been valid for a while now,
749 * but may well have bounced out of range a bit
750 */
751 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
752 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
753 if ((devctl & MUSB_DEVCTL_VBUS)
754 != MUSB_DEVCTL_VBUS) {
755 dev_dbg(musb->controller, "devctl %02x\n", devctl);
756 break;
757 }
758 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
759 musb->is_active = 0;
760 idle_timeout = jiffies
761 + msecs_to_jiffies(musb->a_wait_bcon);
762 } else {
763 /* REVISIT report overcurrent to hub? */
764 ERR("vbus too slow, devctl %02x\n", devctl);
765 tusb_musb_set_vbus(musb, 0);
766 }
767 break;
768 case OTG_STATE_A_WAIT_BCON:
769 if (musb->a_wait_bcon != 0)
770 idle_timeout = jiffies
771 + msecs_to_jiffies(musb->a_wait_bcon);
772 break;
773 case OTG_STATE_A_SUSPEND:
774 break;
775 case OTG_STATE_B_WAIT_ACON:
776 break;
777 default:
778 break;
779 }
780 }
781 schedule_work(&musb->irq_work);
782
783 return idle_timeout;
784}
785
786static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
787{
788 struct musb *musb = __hci;
789 void __iomem *tbase = musb->ctrl_base;
790 unsigned long flags, idle_timeout = 0;
791 u32 int_mask, int_src;
792
793 spin_lock_irqsave(&musb->lock, flags);
794
795 /* Mask all interrupts to allow using both edge and level GPIO irq */
796 int_mask = musb_readl(tbase, TUSB_INT_MASK);
797 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
798
799 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
800 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
801
802 musb->int_usb = (u8) int_src;
803
804 /* Acknowledge wake-up source interrupts */
805 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
806 u32 reg;
807 u32 i;
808
809 if (tusb_get_revision(musb) == TUSB_REV_30)
810 tusb_wbus_quirk(musb, 0);
811
812 /* there are issues re-locking the PLL on wakeup ... */
813
814 /* work around issue 8 */
815 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
816 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
817 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
818 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
819 if (reg == i)
820 break;
821 dev_dbg(musb->controller, "TUSB NOR not ready\n");
822 }
823
824 /* work around issue 13 (2nd half) */
825 tusb_set_clock_source(musb, 1);
826
827 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
828 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
829 if (reg & ~TUSB_PRCM_WNORCS) {
830 musb->is_active = 1;
831 schedule_work(&musb->irq_work);
832 }
833 dev_dbg(musb->controller, "wake %sactive %02x\n",
834 musb->is_active ? "" : "in", reg);
835
836 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
837 }
838
839 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
840 del_timer(&musb_idle_timer);
841
842 /* OTG state change reports (annoyingly) not issued by Mentor core */
843 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
844 | TUSB_INT_SRC_OTG_TIMEOUT
845 | TUSB_INT_SRC_ID_STATUS_CHNG))
846 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
847
848 /* TX dma callback must be handled here, RX dma callback is
849 * handled in tusb_omap_dma_cb.
850 */
851 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
852 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
853 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
854
855 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
856 real_dma_src = ~real_dma_src & dma_src;
857 if (tusb_dma_omap() && real_dma_src) {
858 int tx_source = (real_dma_src & 0xffff);
859 int i;
860
861 for (i = 1; i <= 15; i++) {
862 if (tx_source & (1 << i)) {
863 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
864 musb_dma_completion(musb, i, 1);
865 }
866 }
867 }
868 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
869 }
870
871 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
872 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
873 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
874
875 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
876 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
877 musb->int_tx = (musb_src & 0xffff);
878 } else {
879 musb->int_rx = 0;
880 musb->int_tx = 0;
881 }
882
883 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
884 musb_interrupt(musb);
885
886 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
887 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
888 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
889
890 tusb_musb_try_idle(musb, idle_timeout);
891
892 musb_writel(tbase, TUSB_INT_MASK, int_mask);
893 spin_unlock_irqrestore(&musb->lock, flags);
894
895 return IRQ_HANDLED;
896}
897
898static int dma_off;
899
900/*
901 * Enables TUSB6010. Caller must take care of locking.
902 * REVISIT:
903 * - Check what is unnecessary in MGC_HdrcStart()
904 */
905static void tusb_musb_enable(struct musb *musb)
906{
907 void __iomem *tbase = musb->ctrl_base;
908
909 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
910 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
911 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
912
913 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
914 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
915 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
916 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
917
918 /* Clear all subsystem interrups */
919 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
920 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
921 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
922
923 /* Acknowledge pending interrupt(s) */
924 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
925
926 /* Only 0 clock cycles for minimum interrupt de-assertion time and
927 * interrupt polarity active low seems to work reliably here */
928 musb_writel(tbase, TUSB_INT_CTRL_CONF,
929 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
930
931 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
932
933 /* maybe force into the Default-A OTG state machine */
934 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
935 & TUSB_DEV_OTG_STAT_ID_STATUS))
936 musb_writel(tbase, TUSB_INT_SRC_SET,
937 TUSB_INT_SRC_ID_STATUS_CHNG);
938
939 if (is_dma_capable() && dma_off)
940 printk(KERN_WARNING "%s %s: dma not reactivated\n",
941 __FILE__, __func__);
942 else
943 dma_off = 1;
944}
945
946/*
947 * Disables TUSB6010. Caller must take care of locking.
948 */
949static void tusb_musb_disable(struct musb *musb)
950{
951 void __iomem *tbase = musb->ctrl_base;
952
953 /* FIXME stop DMA, IRQs, timers, ... */
954
955 /* disable all IRQs */
956 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
957 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
958 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
959 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
960
961 del_timer(&musb_idle_timer);
962
963 if (is_dma_capable() && !dma_off) {
964 printk(KERN_WARNING "%s %s: dma still active\n",
965 __FILE__, __func__);
966 dma_off = 1;
967 }
968}
969
970/*
971 * Sets up TUSB6010 CPU interface specific signals and registers
972 * Note: Settings optimized for OMAP24xx
973 */
974static void tusb_setup_cpu_interface(struct musb *musb)
975{
976 void __iomem *tbase = musb->ctrl_base;
977
978 /*
979 * Disable GPIO[5:0] pullups (used as output DMA requests)
980 * Don't disable GPIO[7:6] as they are needed for wake-up.
981 */
982 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
983
984 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
985 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
986
987 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
988 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
989
990 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
991 * de-assertion time 2 system clocks p 62 */
992 musb_writel(tbase, TUSB_DMA_REQ_CONF,
993 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
994 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
995 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
996
997 /* Set 0 wait count for synchronous burst access */
998 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
999}
1000
1001static int tusb_musb_start(struct musb *musb)
1002{
1003 void __iomem *tbase = musb->ctrl_base;
1004 int ret = 0;
1005 unsigned long flags;
1006 u32 reg;
1007
1008 if (musb->board_set_power)
1009 ret = musb->board_set_power(1);
1010 if (ret != 0) {
1011 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1012 return ret;
1013 }
1014
1015 spin_lock_irqsave(&musb->lock, flags);
1016
1017 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1018 TUSB_PROD_TEST_RESET_VAL) {
1019 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1020 goto err;
1021 }
1022
1023 ret = tusb_print_revision(musb);
1024 if (ret < 2) {
1025 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1026 ret);
1027 goto err;
1028 }
1029
1030 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1031 * NOR FLASH interface is used */
1032 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1033
1034 /* Select PHY free running 60MHz as a system clock */
1035 tusb_set_clock_source(musb, 1);
1036
1037 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1038 * power saving, enable VBus detect and session end comparators,
1039 * enable IDpullup, enable VBus charging */
1040 musb_writel(tbase, TUSB_PRCM_MNGMT,
1041 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1042 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1043 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1044 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1045 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1046 tusb_setup_cpu_interface(musb);
1047
1048 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1049 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1050 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1051 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1052
1053 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1054 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1055 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1056
1057 spin_unlock_irqrestore(&musb->lock, flags);
1058
1059 return 0;
1060
1061err:
1062 spin_unlock_irqrestore(&musb->lock, flags);
1063
1064 if (musb->board_set_power)
1065 musb->board_set_power(0);
1066
1067 return -ENODEV;
1068}
1069
1070static int tusb_musb_init(struct musb *musb)
1071{
1072 struct platform_device *pdev;
1073 struct resource *mem;
1074 void __iomem *sync = NULL;
1075 int ret;
1076
1077 usb_nop_xceiv_register();
1078 musb->xceiv = otg_get_transceiver();
1079 if (!musb->xceiv)
1080 return -ENODEV;
1081
1082 pdev = to_platform_device(musb->controller);
1083
1084 /* dma address for async dma */
1085 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086 musb->async = mem->start;
1087
1088 /* dma address for sync dma */
1089 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1090 if (!mem) {
1091 pr_debug("no sync dma resource?\n");
1092 ret = -ENODEV;
1093 goto done;
1094 }
1095 musb->sync = mem->start;
1096
1097 sync = ioremap(mem->start, resource_size(mem));
1098 if (!sync) {
1099 pr_debug("ioremap for sync failed\n");
1100 ret = -ENOMEM;
1101 goto done;
1102 }
1103 musb->sync_va = sync;
1104
1105 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1106 * FIFOs at 0x600, TUSB at 0x800
1107 */
1108 musb->mregs += TUSB_BASE_OFFSET;
1109
1110 ret = tusb_musb_start(musb);
1111 if (ret) {
1112 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1113 ret);
1114 goto done;
1115 }
1116 musb->isr = tusb_musb_interrupt;
1117
1118 if (is_peripheral_enabled(musb)) {
1119 musb->xceiv->set_power = tusb_draw_power;
1120 the_musb = musb;
1121 }
1122
1123 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1124
1125done:
1126 if (ret < 0) {
1127 if (sync)
1128 iounmap(sync);
1129
1130 otg_put_transceiver(musb->xceiv);
1131 usb_nop_xceiv_unregister();
1132 }
1133 return ret;
1134}
1135
1136static int tusb_musb_exit(struct musb *musb)
1137{
1138 del_timer_sync(&musb_idle_timer);
1139 the_musb = NULL;
1140
1141 if (musb->board_set_power)
1142 musb->board_set_power(0);
1143
1144 iounmap(musb->sync_va);
1145
1146 otg_put_transceiver(musb->xceiv);
1147 usb_nop_xceiv_unregister();
1148 return 0;
1149}
1150
1151static const struct musb_platform_ops tusb_ops = {
1152 .init = tusb_musb_init,
1153 .exit = tusb_musb_exit,
1154
1155 .enable = tusb_musb_enable,
1156 .disable = tusb_musb_disable,
1157
1158 .set_mode = tusb_musb_set_mode,
1159 .try_idle = tusb_musb_try_idle,
1160
1161 .vbus_status = tusb_musb_vbus_status,
1162 .set_vbus = tusb_musb_set_vbus,
1163};
1164
1165static u64 tusb_dmamask = DMA_BIT_MASK(32);
1166
1167static int __init tusb_probe(struct platform_device *pdev)
1168{
1169 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1170 struct platform_device *musb;
1171 struct tusb6010_glue *glue;
1172
1173 int ret = -ENOMEM;
1174
1175 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1176 if (!glue) {
1177 dev_err(&pdev->dev, "failed to allocate glue context\n");
1178 goto err0;
1179 }
1180
1181 musb = platform_device_alloc("musb-hdrc", -1);
1182 if (!musb) {
1183 dev_err(&pdev->dev, "failed to allocate musb device\n");
1184 goto err1;
1185 }
1186
1187 musb->dev.parent = &pdev->dev;
1188 musb->dev.dma_mask = &tusb_dmamask;
1189 musb->dev.coherent_dma_mask = tusb_dmamask;
1190
1191 glue->dev = &pdev->dev;
1192 glue->musb = musb;
1193
1194 pdata->platform_ops = &tusb_ops;
1195
1196 platform_set_drvdata(pdev, glue);
1197
1198 ret = platform_device_add_resources(musb, pdev->resource,
1199 pdev->num_resources);
1200 if (ret) {
1201 dev_err(&pdev->dev, "failed to add resources\n");
1202 goto err2;
1203 }
1204
1205 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1206 if (ret) {
1207 dev_err(&pdev->dev, "failed to add platform_data\n");
1208 goto err2;
1209 }
1210
1211 ret = platform_device_add(musb);
1212 if (ret) {
1213 dev_err(&pdev->dev, "failed to register musb device\n");
1214 goto err1;
1215 }
1216
1217 return 0;
1218
1219err2:
1220 platform_device_put(musb);
1221
1222err1:
1223 kfree(glue);
1224
1225err0:
1226 return ret;
1227}
1228
1229static int __exit tusb_remove(struct platform_device *pdev)
1230{
1231 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1232
1233 platform_device_del(glue->musb);
1234 platform_device_put(glue->musb);
1235 kfree(glue);
1236
1237 return 0;
1238}
1239
1240static struct platform_driver tusb_driver = {
1241 .remove = __exit_p(tusb_remove),
1242 .driver = {
1243 .name = "musb-tusb",
1244 },
1245};
1246
1247MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1248MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1249MODULE_LICENSE("GPL v2");
1250
1251static int __init tusb_init(void)
1252{
1253 return platform_driver_probe(&tusb_driver, tusb_probe);
1254}
1255subsys_initcall(tusb_init);
1256
1257static void __exit tusb_exit(void)
1258{
1259 platform_driver_unregister(&tusb_driver);
1260}
1261module_exit(tusb_exit);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * TUSB6010 USB 2.0 OTG Dual Role controller
4 *
5 * Copyright (C) 2006 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 *
8 * Notes:
9 * - Driver assumes that interface to external host (main CPU) is
10 * configured for NOR FLASH interface instead of VLYNQ serial
11 * interface.
12 */
13
14#include <linux/gpio/consumer.h>
15#include <linux/delay.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/prefetch.h>
21#include <linux/usb.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/iopoll.h>
25#include <linux/device.h>
26#include <linux/platform_device.h>
27#include <linux/dma-mapping.h>
28#include <linux/usb/usb_phy_generic.h>
29
30#include "musb_core.h"
31
32struct tusb6010_glue {
33 struct device *dev;
34 struct platform_device *musb;
35 struct platform_device *phy;
36 struct gpio_desc *enable;
37 struct gpio_desc *intpin;
38};
39
40static void tusb_musb_set_vbus(struct musb *musb, int is_on);
41
42#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
43#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
44
45/*
46 * Checks the revision. We need to use the DMA register as 3.0 does not
47 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
48 */
49static u8 tusb_get_revision(struct musb *musb)
50{
51 void __iomem *tbase = musb->ctrl_base;
52 u32 die_id;
53 u8 rev;
54
55 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
56 if (TUSB_REV_MAJOR(rev) == 3) {
57 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
58 TUSB_DIDR1_HI));
59 if (die_id >= TUSB_DIDR1_HI_REV_31)
60 rev |= 1;
61 }
62
63 return rev;
64}
65
66static void tusb_print_revision(struct musb *musb)
67{
68 void __iomem *tbase = musb->ctrl_base;
69 u8 rev;
70
71 rev = musb->tusb_revision;
72
73 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
74 "prcm",
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
77 "int",
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
80 "gpio",
81 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
82 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
83 "dma",
84 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
85 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
86 "dieid",
87 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
88 "rev",
89 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
90}
91
92#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
93 | TUSB_PHY_OTG_CTRL_TESTM0)
94
95/*
96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
97 * Disables power detection in PHY for the duration of idle.
98 */
99static void tusb_wbus_quirk(struct musb *musb, int enabled)
100{
101 void __iomem *tbase = musb->ctrl_base;
102 static u32 phy_otg_ctrl, phy_otg_ena;
103 u32 tmp;
104
105 if (enabled) {
106 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
107 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
108 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
109 | phy_otg_ena | WBUS_QUIRK_MASK;
110 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
111 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
112 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
113 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
115 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
116 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
117 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
118 & TUSB_PHY_OTG_CTRL_TESTM2) {
119 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
120 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
121 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
122 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
123 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
124 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
125 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
126 phy_otg_ctrl = 0;
127 phy_otg_ena = 0;
128 }
129}
130
131static u32 tusb_fifo_offset(u8 epnum)
132{
133 return 0x200 + (epnum * 0x20);
134}
135
136static u32 tusb_ep_offset(u8 epnum, u16 offset)
137{
138 return 0x10 + offset;
139}
140
141/* TUSB mapping: "flat" plus ep0 special cases */
142static void tusb_ep_select(void __iomem *mbase, u8 epnum)
143{
144 musb_writeb(mbase, MUSB_INDEX, epnum);
145}
146
147/*
148 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
149 */
150static u8 tusb_readb(void __iomem *addr, u32 offset)
151{
152 u16 tmp;
153 u8 val;
154
155 tmp = __raw_readw(addr + (offset & ~1));
156 if (offset & 1)
157 val = (tmp >> 8);
158 else
159 val = tmp & 0xff;
160
161 return val;
162}
163
164static void tusb_writeb(void __iomem *addr, u32 offset, u8 data)
165{
166 u16 tmp;
167
168 tmp = __raw_readw(addr + (offset & ~1));
169 if (offset & 1)
170 tmp = (data << 8) | (tmp & 0xff);
171 else
172 tmp = (tmp & 0xff00) | data;
173
174 __raw_writew(tmp, addr + (offset & ~1));
175}
176
177/*
178 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
179 * so both loading and unloading FIFOs need explicit byte counts.
180 */
181
182static inline void
183tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
184{
185 u32 val;
186 int i;
187
188 if (len > 4) {
189 for (i = 0; i < (len >> 2); i++) {
190 memcpy(&val, buf, 4);
191 musb_writel(fifo, 0, val);
192 buf += 4;
193 }
194 len %= 4;
195 }
196 if (len > 0) {
197 /* Write the rest 1 - 3 bytes to FIFO */
198 val = 0;
199 memcpy(&val, buf, len);
200 musb_writel(fifo, 0, val);
201 }
202}
203
204static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
205 void *buf, u16 len)
206{
207 u32 val;
208 int i;
209
210 if (len > 4) {
211 for (i = 0; i < (len >> 2); i++) {
212 val = musb_readl(fifo, 0);
213 memcpy(buf, &val, 4);
214 buf += 4;
215 }
216 len %= 4;
217 }
218 if (len > 0) {
219 /* Read the rest 1 - 3 bytes from FIFO */
220 val = musb_readl(fifo, 0);
221 memcpy(buf, &val, len);
222 }
223}
224
225static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
226{
227 struct musb *musb = hw_ep->musb;
228 void __iomem *ep_conf = hw_ep->conf;
229 void __iomem *fifo = hw_ep->fifo;
230 u8 epnum = hw_ep->epnum;
231
232 prefetch(buf);
233
234 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
235 'T', epnum, fifo, len, buf);
236
237 if (epnum)
238 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
239 TUSB_EP_CONFIG_XFR_SIZE(len));
240 else
241 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
242 TUSB_EP0_CONFIG_XFR_SIZE(len));
243
244 if (likely((0x01 & (unsigned long) buf) == 0)) {
245
246 /* Best case is 32bit-aligned destination address */
247 if ((0x02 & (unsigned long) buf) == 0) {
248 if (len >= 4) {
249 iowrite32_rep(fifo, buf, len >> 2);
250 buf += (len & ~0x03);
251 len &= 0x03;
252 }
253 } else {
254 if (len >= 2) {
255 u32 val;
256 int i;
257
258 /* Cannot use writesw, fifo is 32-bit */
259 for (i = 0; i < (len >> 2); i++) {
260 val = (u32)(*(u16 *)buf);
261 buf += 2;
262 val |= (*(u16 *)buf) << 16;
263 buf += 2;
264 musb_writel(fifo, 0, val);
265 }
266 len &= 0x03;
267 }
268 }
269 }
270
271 if (len > 0)
272 tusb_fifo_write_unaligned(fifo, buf, len);
273}
274
275static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
276{
277 struct musb *musb = hw_ep->musb;
278 void __iomem *ep_conf = hw_ep->conf;
279 void __iomem *fifo = hw_ep->fifo;
280 u8 epnum = hw_ep->epnum;
281
282 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
283 'R', epnum, fifo, len, buf);
284
285 if (epnum)
286 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
287 TUSB_EP_CONFIG_XFR_SIZE(len));
288 else
289 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
290
291 if (likely((0x01 & (unsigned long) buf) == 0)) {
292
293 /* Best case is 32bit-aligned destination address */
294 if ((0x02 & (unsigned long) buf) == 0) {
295 if (len >= 4) {
296 ioread32_rep(fifo, buf, len >> 2);
297 buf += (len & ~0x03);
298 len &= 0x03;
299 }
300 } else {
301 if (len >= 2) {
302 u32 val;
303 int i;
304
305 /* Cannot use readsw, fifo is 32-bit */
306 for (i = 0; i < (len >> 2); i++) {
307 val = musb_readl(fifo, 0);
308 *(u16 *)buf = (u16)(val & 0xffff);
309 buf += 2;
310 *(u16 *)buf = (u16)(val >> 16);
311 buf += 2;
312 }
313 len &= 0x03;
314 }
315 }
316 }
317
318 if (len > 0)
319 tusb_fifo_read_unaligned(fifo, buf, len);
320}
321
322static struct musb *the_musb;
323
324/* This is used by gadget drivers, and OTG transceiver logic, allowing
325 * at most mA current to be drawn from VBUS during a Default-B session
326 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
327 * mode), or low power Default-B sessions, something else supplies power.
328 * Caller must take care of locking.
329 */
330static int tusb_draw_power(struct usb_phy *x, unsigned mA)
331{
332 struct musb *musb = the_musb;
333 void __iomem *tbase = musb->ctrl_base;
334 u32 reg;
335
336 /* tps65030 seems to consume max 100mA, with maybe 60mA available
337 * (measured on one board) for things other than tps and tusb.
338 *
339 * Boards sharing the CPU clock with CLKIN will need to prevent
340 * certain idle sleep states while the USB link is active.
341 *
342 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
343 * The actual current usage would be very board-specific. For now,
344 * it's simpler to just use an aggregate (also board-specific).
345 */
346 if (x->otg->default_a || mA < (musb->min_power << 1))
347 mA = 0;
348
349 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
350 if (mA) {
351 musb->is_bus_powered = 1;
352 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
353 } else {
354 musb->is_bus_powered = 0;
355 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
356 }
357 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
358
359 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
360 return 0;
361}
362
363/* workaround for issue 13: change clock during chip idle
364 * (to be fixed in rev3 silicon) ... symptoms include disconnect
365 * or looping suspend/resume cycles
366 */
367static void tusb_set_clock_source(struct musb *musb, unsigned mode)
368{
369 void __iomem *tbase = musb->ctrl_base;
370 u32 reg;
371
372 reg = musb_readl(tbase, TUSB_PRCM_CONF);
373 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
374
375 /* 0 = refclk (clkin, XI)
376 * 1 = PHY 60 MHz (internal PLL)
377 * 2 = not supported
378 * 3 = what?
379 */
380 if (mode > 0)
381 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
382
383 musb_writel(tbase, TUSB_PRCM_CONF, reg);
384
385 /* FIXME tusb6010_platform_retime(mode == 0); */
386}
387
388/*
389 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
390 * Other code ensures that we idle unless we're connected _and_ the
391 * USB link is not suspended ... and tells us the relevant wakeup
392 * events. SW_EN for voltage is handled separately.
393 */
394static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
395{
396 void __iomem *tbase = musb->ctrl_base;
397 u32 reg;
398
399 if ((wakeup_enables & TUSB_PRCM_WBUS)
400 && (musb->tusb_revision == TUSB_REV_30))
401 tusb_wbus_quirk(musb, 1);
402
403 tusb_set_clock_source(musb, 0);
404
405 wakeup_enables |= TUSB_PRCM_WNORCS;
406 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
407
408 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
409 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
410 * Presumably that's mostly to save power, hence WID is immaterial ...
411 */
412
413 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
414 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
415 if (is_host_active(musb)) {
416 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
417 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
418 } else {
419 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
420 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
421 }
422 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
423 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
424
425 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
426}
427
428/*
429 * Updates cable VBUS status. Caller must take care of locking.
430 */
431static int tusb_musb_vbus_status(struct musb *musb)
432{
433 void __iomem *tbase = musb->ctrl_base;
434 u32 otg_stat, prcm_mngmt;
435 int ret = 0;
436
437 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
438 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
439
440 /* Temporarily enable VBUS detection if it was disabled for
441 * suspend mode. Unless it's enabled otg_stat and devctl will
442 * not show correct VBUS state.
443 */
444 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
445 u32 tmp = prcm_mngmt;
446 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
447 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
448 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
449 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
450 }
451
452 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
453 ret = 1;
454
455 return ret;
456}
457
458static void musb_do_idle(struct timer_list *t)
459{
460 struct musb *musb = from_timer(musb, t, dev_timer);
461 unsigned long flags;
462
463 spin_lock_irqsave(&musb->lock, flags);
464
465 switch (musb->xceiv->otg->state) {
466 case OTG_STATE_A_WAIT_BCON:
467 if ((musb->a_wait_bcon != 0)
468 && (musb->idle_timeout == 0
469 || time_after(jiffies, musb->idle_timeout))) {
470 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
471 usb_otg_state_string(musb->xceiv->otg->state));
472 }
473 fallthrough;
474 case OTG_STATE_A_IDLE:
475 tusb_musb_set_vbus(musb, 0);
476 break;
477 default:
478 break;
479 }
480
481 if (!musb->is_active) {
482 u32 wakeups;
483
484 /* wait until hub_wq handles port change status */
485 if (is_host_active(musb) && (musb->port1_status >> 16))
486 goto done;
487
488 if (!musb->gadget_driver) {
489 wakeups = 0;
490 } else {
491 wakeups = TUSB_PRCM_WHOSTDISCON
492 | TUSB_PRCM_WBUS
493 | TUSB_PRCM_WVBUS;
494 wakeups |= TUSB_PRCM_WID;
495 }
496 tusb_allow_idle(musb, wakeups);
497 }
498done:
499 spin_unlock_irqrestore(&musb->lock, flags);
500}
501
502/*
503 * Maybe put TUSB6010 into idle mode depending on USB link status,
504 * like "disconnected" or "suspended". We'll be woken out of it by
505 * connect, resume, or disconnect.
506 *
507 * Needs to be called as the last function everywhere where there is
508 * register access to TUSB6010 because of NOR flash wake-up.
509 * Caller should own controller spinlock.
510 *
511 * Delay because peripheral enables D+ pullup 3msec after SE0, and
512 * we don't want to treat that full speed J as a wakeup event.
513 * ... peripherals must draw only suspend current after 10 msec.
514 */
515static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
516{
517 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
518 static unsigned long last_timer;
519
520 if (timeout == 0)
521 timeout = default_timeout;
522
523 /* Never idle if active, or when VBUS timeout is not set as host */
524 if (musb->is_active || ((musb->a_wait_bcon == 0)
525 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
526 dev_dbg(musb->controller, "%s active, deleting timer\n",
527 usb_otg_state_string(musb->xceiv->otg->state));
528 del_timer(&musb->dev_timer);
529 last_timer = jiffies;
530 return;
531 }
532
533 if (time_after(last_timer, timeout)) {
534 if (!timer_pending(&musb->dev_timer))
535 last_timer = timeout;
536 else {
537 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
538 return;
539 }
540 }
541 last_timer = timeout;
542
543 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
544 usb_otg_state_string(musb->xceiv->otg->state),
545 (unsigned long)jiffies_to_msecs(timeout - jiffies));
546 mod_timer(&musb->dev_timer, timeout);
547}
548
549/* ticks of 60 MHz clock */
550#define DEVCLOCK 60000000
551#define OTG_TIMER_MS(msecs) ((msecs) \
552 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
553 | TUSB_DEV_OTG_TIMER_ENABLE) \
554 : 0)
555
556static void tusb_musb_set_vbus(struct musb *musb, int is_on)
557{
558 void __iomem *tbase = musb->ctrl_base;
559 u32 conf, prcm, timer;
560 u8 devctl;
561 struct usb_otg *otg = musb->xceiv->otg;
562
563 /* HDRC controls CPEN, but beware current surges during device
564 * connect. They can trigger transient overcurrent conditions
565 * that must be ignored.
566 */
567
568 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
569 conf = musb_readl(tbase, TUSB_DEV_CONF);
570 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
571
572 if (is_on) {
573 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
574 otg->default_a = 1;
575 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
576 devctl |= MUSB_DEVCTL_SESSION;
577
578 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
579 MUSB_HST_MODE(musb);
580 } else {
581 u32 otg_stat;
582
583 timer = 0;
584
585 /* If ID pin is grounded, we want to be a_idle */
586 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
587 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
588 switch (musb->xceiv->otg->state) {
589 case OTG_STATE_A_WAIT_VRISE:
590 case OTG_STATE_A_WAIT_BCON:
591 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
592 break;
593 case OTG_STATE_A_WAIT_VFALL:
594 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
595 break;
596 default:
597 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
598 }
599 musb->is_active = 0;
600 otg->default_a = 1;
601 MUSB_HST_MODE(musb);
602 } else {
603 musb->is_active = 0;
604 otg->default_a = 0;
605 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
606 MUSB_DEV_MODE(musb);
607 }
608
609 devctl &= ~MUSB_DEVCTL_SESSION;
610 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
611 }
612 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
613
614 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
615 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
616 musb_writel(tbase, TUSB_DEV_CONF, conf);
617 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
618
619 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
620 usb_otg_state_string(musb->xceiv->otg->state),
621 musb_readb(musb->mregs, MUSB_DEVCTL),
622 musb_readl(tbase, TUSB_DEV_OTG_STAT),
623 conf, prcm);
624}
625
626/*
627 * Sets the mode to OTG, peripheral or host by changing the ID detection.
628 * Caller must take care of locking.
629 *
630 * Note that if a mini-A cable is plugged in the ID line will stay down as
631 * the weak ID pull-up is not able to pull the ID up.
632 */
633static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
634{
635 void __iomem *tbase = musb->ctrl_base;
636 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
637
638 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
639 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
640 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
641 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
642
643 switch (musb_mode) {
644
645 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
646 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
647 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
648 dev_conf |= TUSB_DEV_CONF_ID_SEL;
649 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
650 break;
651 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
652 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
653 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
654 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
655 break;
656 case MUSB_OTG: /* Use PHY ID detection */
657 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
658 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
659 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
660 break;
661
662 default:
663 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
664 return -EINVAL;
665 }
666
667 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
668 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
669 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
670 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
671 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
672
673 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
674 if ((musb_mode == MUSB_PERIPHERAL) &&
675 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
676 INFO("Cannot be peripheral with mini-A cable "
677 "otg_stat: %08x\n", otg_stat);
678
679 return 0;
680}
681
682static inline unsigned long
683tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
684{
685 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
686 unsigned long idle_timeout = 0;
687 struct usb_otg *otg = musb->xceiv->otg;
688
689 /* ID pin */
690 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
691 int default_a;
692
693 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
694 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
695 otg->default_a = default_a;
696 tusb_musb_set_vbus(musb, default_a);
697
698 /* Don't allow idling immediately */
699 if (default_a)
700 idle_timeout = jiffies + (HZ * 3);
701 }
702
703 /* VBUS state change */
704 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
705
706 /* B-dev state machine: no vbus ~= disconnect */
707 if (!otg->default_a) {
708 /* ? musb_root_disconnect(musb); */
709 musb->port1_status &=
710 ~(USB_PORT_STAT_CONNECTION
711 | USB_PORT_STAT_ENABLE
712 | USB_PORT_STAT_LOW_SPEED
713 | USB_PORT_STAT_HIGH_SPEED
714 | USB_PORT_STAT_TEST
715 );
716
717 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
718 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
719 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
720 /* INTR_DISCONNECT can hide... */
721 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
722 musb->int_usb |= MUSB_INTR_DISCONNECT;
723 }
724 musb->is_active = 0;
725 }
726 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
727 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
728 idle_timeout = jiffies + (1 * HZ);
729 schedule_delayed_work(&musb->irq_work, 0);
730
731 } else /* A-dev state machine */ {
732 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
733 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
734
735 switch (musb->xceiv->otg->state) {
736 case OTG_STATE_A_IDLE:
737 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
738 musb_platform_set_vbus(musb, 1);
739
740 /* CONNECT can wake if a_wait_bcon is set */
741 if (musb->a_wait_bcon != 0)
742 musb->is_active = 0;
743 else
744 musb->is_active = 1;
745
746 /*
747 * OPT FS A TD.4.6 needs few seconds for
748 * A_WAIT_VRISE
749 */
750 idle_timeout = jiffies + (2 * HZ);
751
752 break;
753 case OTG_STATE_A_WAIT_VRISE:
754 /* ignore; A-session-valid < VBUS_VALID/2,
755 * we monitor this with the timer
756 */
757 break;
758 case OTG_STATE_A_WAIT_VFALL:
759 /* REVISIT this irq triggers during short
760 * spikes caused by enumeration ...
761 */
762 if (musb->vbuserr_retry) {
763 musb->vbuserr_retry--;
764 tusb_musb_set_vbus(musb, 1);
765 } else {
766 musb->vbuserr_retry
767 = VBUSERR_RETRY_COUNT;
768 tusb_musb_set_vbus(musb, 0);
769 }
770 break;
771 default:
772 break;
773 }
774 }
775 }
776
777 /* OTG timer expiration */
778 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
779 u8 devctl;
780
781 dev_dbg(musb->controller, "%s timer, %03x\n",
782 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
783
784 switch (musb->xceiv->otg->state) {
785 case OTG_STATE_A_WAIT_VRISE:
786 /* VBUS has probably been valid for a while now,
787 * but may well have bounced out of range a bit
788 */
789 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
790 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
791 if ((devctl & MUSB_DEVCTL_VBUS)
792 != MUSB_DEVCTL_VBUS) {
793 dev_dbg(musb->controller, "devctl %02x\n", devctl);
794 break;
795 }
796 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
797 musb->is_active = 0;
798 idle_timeout = jiffies
799 + msecs_to_jiffies(musb->a_wait_bcon);
800 } else {
801 /* REVISIT report overcurrent to hub? */
802 ERR("vbus too slow, devctl %02x\n", devctl);
803 tusb_musb_set_vbus(musb, 0);
804 }
805 break;
806 case OTG_STATE_A_WAIT_BCON:
807 if (musb->a_wait_bcon != 0)
808 idle_timeout = jiffies
809 + msecs_to_jiffies(musb->a_wait_bcon);
810 break;
811 case OTG_STATE_A_SUSPEND:
812 break;
813 case OTG_STATE_B_WAIT_ACON:
814 break;
815 default:
816 break;
817 }
818 }
819 schedule_delayed_work(&musb->irq_work, 0);
820
821 return idle_timeout;
822}
823
824static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
825{
826 struct musb *musb = __hci;
827 void __iomem *tbase = musb->ctrl_base;
828 unsigned long flags, idle_timeout = 0;
829 u32 int_mask, int_src;
830
831 spin_lock_irqsave(&musb->lock, flags);
832
833 /* Mask all interrupts to allow using both edge and level GPIO irq */
834 int_mask = musb_readl(tbase, TUSB_INT_MASK);
835 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
836
837 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
838 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
839
840 musb->int_usb = (u8) int_src;
841
842 /* Acknowledge wake-up source interrupts */
843 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
844 u32 reg;
845 u32 i;
846
847 if (musb->tusb_revision == TUSB_REV_30)
848 tusb_wbus_quirk(musb, 0);
849
850 /* there are issues re-locking the PLL on wakeup ... */
851
852 /* work around issue 8 */
853 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
854 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
855 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
856 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
857 if (reg == i)
858 break;
859 dev_dbg(musb->controller, "TUSB NOR not ready\n");
860 }
861
862 /* work around issue 13 (2nd half) */
863 tusb_set_clock_source(musb, 1);
864
865 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
866 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
867 if (reg & ~TUSB_PRCM_WNORCS) {
868 musb->is_active = 1;
869 schedule_delayed_work(&musb->irq_work, 0);
870 }
871 dev_dbg(musb->controller, "wake %sactive %02x\n",
872 musb->is_active ? "" : "in", reg);
873
874 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
875 }
876
877 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
878 del_timer(&musb->dev_timer);
879
880 /* OTG state change reports (annoyingly) not issued by Mentor core */
881 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
882 | TUSB_INT_SRC_OTG_TIMEOUT
883 | TUSB_INT_SRC_ID_STATUS_CHNG))
884 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
885
886 /*
887 * Just clear the DMA interrupt if it comes as the completion for both
888 * TX and RX is handled by the DMA callback in tusb6010_omap
889 */
890 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
891 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
892
893 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
894 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
895 }
896
897 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
898 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
899 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
900
901 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
902 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
903 musb->int_tx = (musb_src & 0xffff);
904 } else {
905 musb->int_rx = 0;
906 musb->int_tx = 0;
907 }
908
909 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
910 musb_interrupt(musb);
911
912 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
913 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
914 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
915
916 tusb_musb_try_idle(musb, idle_timeout);
917
918 musb_writel(tbase, TUSB_INT_MASK, int_mask);
919 spin_unlock_irqrestore(&musb->lock, flags);
920
921 return IRQ_HANDLED;
922}
923
924static int dma_off;
925
926/*
927 * Enables TUSB6010. Caller must take care of locking.
928 * REVISIT:
929 * - Check what is unnecessary in MGC_HdrcStart()
930 */
931static void tusb_musb_enable(struct musb *musb)
932{
933 void __iomem *tbase = musb->ctrl_base;
934
935 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
936 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
937 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
938
939 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
940 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
941 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
942 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
943
944 /* Clear all subsystem interrups */
945 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
946 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
947 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
948
949 /* Acknowledge pending interrupt(s) */
950 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
951
952 /* Only 0 clock cycles for minimum interrupt de-assertion time and
953 * interrupt polarity active low seems to work reliably here */
954 musb_writel(tbase, TUSB_INT_CTRL_CONF,
955 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
956
957 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
958
959 /* maybe force into the Default-A OTG state machine */
960 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
961 & TUSB_DEV_OTG_STAT_ID_STATUS))
962 musb_writel(tbase, TUSB_INT_SRC_SET,
963 TUSB_INT_SRC_ID_STATUS_CHNG);
964
965 if (is_dma_capable() && dma_off)
966 printk(KERN_WARNING "%s %s: dma not reactivated\n",
967 __FILE__, __func__);
968 else
969 dma_off = 1;
970}
971
972/*
973 * Disables TUSB6010. Caller must take care of locking.
974 */
975static void tusb_musb_disable(struct musb *musb)
976{
977 void __iomem *tbase = musb->ctrl_base;
978
979 /* FIXME stop DMA, IRQs, timers, ... */
980
981 /* disable all IRQs */
982 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
983 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
984 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
985 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
986
987 del_timer(&musb->dev_timer);
988
989 if (is_dma_capable() && !dma_off) {
990 printk(KERN_WARNING "%s %s: dma still active\n",
991 __FILE__, __func__);
992 dma_off = 1;
993 }
994}
995
996/*
997 * Sets up TUSB6010 CPU interface specific signals and registers
998 * Note: Settings optimized for OMAP24xx
999 */
1000static void tusb_setup_cpu_interface(struct musb *musb)
1001{
1002 void __iomem *tbase = musb->ctrl_base;
1003
1004 /*
1005 * Disable GPIO[5:0] pullups (used as output DMA requests)
1006 * Don't disable GPIO[7:6] as they are needed for wake-up.
1007 */
1008 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1009
1010 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1011 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1012
1013 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1014 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1015
1016 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1017 * de-assertion time 2 system clocks p 62 */
1018 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1019 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1020 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1021 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1022
1023 /* Set 0 wait count for synchronous burst access */
1024 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1025}
1026
1027static int tusb_musb_start(struct musb *musb)
1028{
1029 struct tusb6010_glue *glue = dev_get_drvdata(musb->controller->parent);
1030 void __iomem *tbase = musb->ctrl_base;
1031 unsigned long flags;
1032 u32 reg;
1033 int ret;
1034
1035 /*
1036 * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
1037 * 1.5 V voltage regulators of PM companion chip. Companion chip will then
1038 * provide then PGOOD signal to TUSB6010 which will release it from reset.
1039 */
1040 gpiod_set_value(glue->enable, 1);
1041
1042 /* Wait for 100ms until TUSB6010 pulls INT pin down */
1043 ret = read_poll_timeout(gpiod_get_value, reg, !reg, 5000, 100000, true,
1044 glue->intpin);
1045 if (ret) {
1046 pr_err("tusb: Powerup response failed\n");
1047 return ret;
1048 }
1049
1050 spin_lock_irqsave(&musb->lock, flags);
1051
1052 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1053 TUSB_PROD_TEST_RESET_VAL) {
1054 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1055 goto err;
1056 }
1057
1058 musb->tusb_revision = tusb_get_revision(musb);
1059 tusb_print_revision(musb);
1060 if (musb->tusb_revision < 2) {
1061 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1062 musb->tusb_revision);
1063 goto err;
1064 }
1065
1066 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1067 * NOR FLASH interface is used */
1068 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1069
1070 /* Select PHY free running 60MHz as a system clock */
1071 tusb_set_clock_source(musb, 1);
1072
1073 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1074 * power saving, enable VBus detect and session end comparators,
1075 * enable IDpullup, enable VBus charging */
1076 musb_writel(tbase, TUSB_PRCM_MNGMT,
1077 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1078 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1079 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1080 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1081 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1082 tusb_setup_cpu_interface(musb);
1083
1084 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1085 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1086 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1087 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1088
1089 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1090 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1091 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1092
1093 spin_unlock_irqrestore(&musb->lock, flags);
1094
1095 return 0;
1096
1097err:
1098 spin_unlock_irqrestore(&musb->lock, flags);
1099
1100 gpiod_set_value(glue->enable, 0);
1101 msleep(10);
1102
1103 return -ENODEV;
1104}
1105
1106static int tusb_musb_init(struct musb *musb)
1107{
1108 struct platform_device *pdev;
1109 struct resource *mem;
1110 void __iomem *sync = NULL;
1111 int ret;
1112
1113 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1114 if (IS_ERR_OR_NULL(musb->xceiv))
1115 return -EPROBE_DEFER;
1116
1117 pdev = to_platform_device(musb->controller);
1118
1119 /* dma address for async dma */
1120 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 if (!mem) {
1122 pr_debug("no async dma resource?\n");
1123 ret = -ENODEV;
1124 goto done;
1125 }
1126 musb->async = mem->start;
1127
1128 /* dma address for sync dma */
1129 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1130 if (!mem) {
1131 pr_debug("no sync dma resource?\n");
1132 ret = -ENODEV;
1133 goto done;
1134 }
1135 musb->sync = mem->start;
1136
1137 sync = ioremap(mem->start, resource_size(mem));
1138 if (!sync) {
1139 pr_debug("ioremap for sync failed\n");
1140 ret = -ENOMEM;
1141 goto done;
1142 }
1143 musb->sync_va = sync;
1144
1145 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1146 * FIFOs at 0x600, TUSB at 0x800
1147 */
1148 musb->mregs += TUSB_BASE_OFFSET;
1149
1150 ret = tusb_musb_start(musb);
1151 if (ret) {
1152 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1153 ret);
1154 goto done;
1155 }
1156 musb->isr = tusb_musb_interrupt;
1157
1158 musb->xceiv->set_power = tusb_draw_power;
1159 the_musb = musb;
1160
1161 timer_setup(&musb->dev_timer, musb_do_idle, 0);
1162
1163done:
1164 if (ret < 0) {
1165 if (sync)
1166 iounmap(sync);
1167
1168 usb_put_phy(musb->xceiv);
1169 }
1170 return ret;
1171}
1172
1173static int tusb_musb_exit(struct musb *musb)
1174{
1175 struct tusb6010_glue *glue = dev_get_drvdata(musb->controller->parent);
1176
1177 del_timer_sync(&musb->dev_timer);
1178 the_musb = NULL;
1179
1180 gpiod_set_value(glue->enable, 0);
1181 msleep(10);
1182
1183 iounmap(musb->sync_va);
1184
1185 usb_put_phy(musb->xceiv);
1186 return 0;
1187}
1188
1189static const struct musb_platform_ops tusb_ops = {
1190 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB |
1191 MUSB_G_NO_SKB_RESERVE,
1192 .init = tusb_musb_init,
1193 .exit = tusb_musb_exit,
1194
1195 .ep_offset = tusb_ep_offset,
1196 .ep_select = tusb_ep_select,
1197 .fifo_offset = tusb_fifo_offset,
1198 .readb = tusb_readb,
1199 .writeb = tusb_writeb,
1200 .read_fifo = tusb_read_fifo,
1201 .write_fifo = tusb_write_fifo,
1202#ifdef CONFIG_USB_TUSB_OMAP_DMA
1203 .dma_init = tusb_dma_controller_create,
1204 .dma_exit = tusb_dma_controller_destroy,
1205#endif
1206 .enable = tusb_musb_enable,
1207 .disable = tusb_musb_disable,
1208
1209 .set_mode = tusb_musb_set_mode,
1210 .try_idle = tusb_musb_try_idle,
1211
1212 .vbus_status = tusb_musb_vbus_status,
1213 .set_vbus = tusb_musb_set_vbus,
1214};
1215
1216static const struct platform_device_info tusb_dev_info = {
1217 .name = "musb-hdrc",
1218 .id = PLATFORM_DEVID_AUTO,
1219 .dma_mask = DMA_BIT_MASK(32),
1220};
1221
1222static int tusb_probe(struct platform_device *pdev)
1223{
1224 struct resource musb_resources[3];
1225 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1226 struct platform_device *musb;
1227 struct tusb6010_glue *glue;
1228 struct platform_device_info pinfo;
1229 int ret;
1230
1231 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1232 if (!glue)
1233 return -ENOMEM;
1234
1235 glue->dev = &pdev->dev;
1236
1237 glue->enable = devm_gpiod_get(glue->dev, "enable", GPIOD_OUT_LOW);
1238 if (IS_ERR(glue->enable))
1239 return dev_err_probe(glue->dev, PTR_ERR(glue->enable),
1240 "could not obtain power on/off GPIO\n");
1241 glue->intpin = devm_gpiod_get(glue->dev, "int", GPIOD_IN);
1242 if (IS_ERR(glue->intpin))
1243 return dev_err_probe(glue->dev, PTR_ERR(glue->intpin),
1244 "could not obtain INT GPIO\n");
1245
1246 pdata->platform_ops = &tusb_ops;
1247
1248 usb_phy_generic_register();
1249 platform_set_drvdata(pdev, glue);
1250
1251 memset(musb_resources, 0x00, sizeof(*musb_resources) *
1252 ARRAY_SIZE(musb_resources));
1253
1254 musb_resources[0].name = pdev->resource[0].name;
1255 musb_resources[0].start = pdev->resource[0].start;
1256 musb_resources[0].end = pdev->resource[0].end;
1257 musb_resources[0].flags = pdev->resource[0].flags;
1258
1259 musb_resources[1].name = pdev->resource[1].name;
1260 musb_resources[1].start = pdev->resource[1].start;
1261 musb_resources[1].end = pdev->resource[1].end;
1262 musb_resources[1].flags = pdev->resource[1].flags;
1263
1264 musb_resources[2] = DEFINE_RES_IRQ_NAMED(gpiod_to_irq(glue->intpin), "mc");
1265
1266 pinfo = tusb_dev_info;
1267 pinfo.parent = &pdev->dev;
1268 pinfo.res = musb_resources;
1269 pinfo.num_res = ARRAY_SIZE(musb_resources);
1270 pinfo.data = pdata;
1271 pinfo.size_data = sizeof(*pdata);
1272
1273 glue->musb = musb = platform_device_register_full(&pinfo);
1274 if (IS_ERR(musb)) {
1275 ret = PTR_ERR(musb);
1276 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1277 return ret;
1278 }
1279
1280 return 0;
1281}
1282
1283static void tusb_remove(struct platform_device *pdev)
1284{
1285 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1286
1287 platform_device_unregister(glue->musb);
1288 usb_phy_generic_unregister(glue->phy);
1289}
1290
1291static struct platform_driver tusb_driver = {
1292 .probe = tusb_probe,
1293 .remove = tusb_remove,
1294 .driver = {
1295 .name = "musb-tusb",
1296 },
1297};
1298
1299MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1300MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1301MODULE_LICENSE("GPL v2");
1302module_platform_driver(tusb_driver);