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1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/prefetch.h>
22#include <linux/usb.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26
27#include "musb_core.h"
28
29struct tusb6010_glue {
30 struct device *dev;
31 struct platform_device *musb;
32};
33
34static void tusb_musb_set_vbus(struct musb *musb, int is_on);
35
36#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
37#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
38
39/*
40 * Checks the revision. We need to use the DMA register as 3.0 does not
41 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
42 */
43u8 tusb_get_revision(struct musb *musb)
44{
45 void __iomem *tbase = musb->ctrl_base;
46 u32 die_id;
47 u8 rev;
48
49 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
50 if (TUSB_REV_MAJOR(rev) == 3) {
51 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
52 TUSB_DIDR1_HI));
53 if (die_id >= TUSB_DIDR1_HI_REV_31)
54 rev |= 1;
55 }
56
57 return rev;
58}
59
60static int tusb_print_revision(struct musb *musb)
61{
62 void __iomem *tbase = musb->ctrl_base;
63 u8 rev;
64
65 rev = tusb_get_revision(musb);
66
67 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
68 "prcm",
69 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
70 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 "int",
72 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
73 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 "gpio",
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 "dma",
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 "dieid",
81 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
82 "rev",
83 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
84
85 return tusb_get_revision(musb);
86}
87
88#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
89 | TUSB_PHY_OTG_CTRL_TESTM0)
90
91/*
92 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
93 * Disables power detection in PHY for the duration of idle.
94 */
95static void tusb_wbus_quirk(struct musb *musb, int enabled)
96{
97 void __iomem *tbase = musb->ctrl_base;
98 static u32 phy_otg_ctrl, phy_otg_ena;
99 u32 tmp;
100
101 if (enabled) {
102 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
103 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
104 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
105 | phy_otg_ena | WBUS_QUIRK_MASK;
106 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
107 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
108 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
109 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
110 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
112 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
113 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
114 & TUSB_PHY_OTG_CTRL_TESTM2) {
115 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
116 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
117 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
118 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
119 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
121 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
122 phy_otg_ctrl = 0;
123 phy_otg_ena = 0;
124 }
125}
126
127/*
128 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
129 * so both loading and unloading FIFOs need explicit byte counts.
130 */
131
132static inline void
133tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
134{
135 u32 val;
136 int i;
137
138 if (len > 4) {
139 for (i = 0; i < (len >> 2); i++) {
140 memcpy(&val, buf, 4);
141 musb_writel(fifo, 0, val);
142 buf += 4;
143 }
144 len %= 4;
145 }
146 if (len > 0) {
147 /* Write the rest 1 - 3 bytes to FIFO */
148 memcpy(&val, buf, len);
149 musb_writel(fifo, 0, val);
150 }
151}
152
153static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
154 void __iomem *buf, u16 len)
155{
156 u32 val;
157 int i;
158
159 if (len > 4) {
160 for (i = 0; i < (len >> 2); i++) {
161 val = musb_readl(fifo, 0);
162 memcpy(buf, &val, 4);
163 buf += 4;
164 }
165 len %= 4;
166 }
167 if (len > 0) {
168 /* Read the rest 1 - 3 bytes from FIFO */
169 val = musb_readl(fifo, 0);
170 memcpy(buf, &val, len);
171 }
172}
173
174void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
175{
176 struct musb *musb = hw_ep->musb;
177 void __iomem *ep_conf = hw_ep->conf;
178 void __iomem *fifo = hw_ep->fifo;
179 u8 epnum = hw_ep->epnum;
180
181 prefetch(buf);
182
183 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
184 'T', epnum, fifo, len, buf);
185
186 if (epnum)
187 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
188 TUSB_EP_CONFIG_XFR_SIZE(len));
189 else
190 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
191 TUSB_EP0_CONFIG_XFR_SIZE(len));
192
193 if (likely((0x01 & (unsigned long) buf) == 0)) {
194
195 /* Best case is 32bit-aligned destination address */
196 if ((0x02 & (unsigned long) buf) == 0) {
197 if (len >= 4) {
198 writesl(fifo, buf, len >> 2);
199 buf += (len & ~0x03);
200 len &= 0x03;
201 }
202 } else {
203 if (len >= 2) {
204 u32 val;
205 int i;
206
207 /* Cannot use writesw, fifo is 32-bit */
208 for (i = 0; i < (len >> 2); i++) {
209 val = (u32)(*(u16 *)buf);
210 buf += 2;
211 val |= (*(u16 *)buf) << 16;
212 buf += 2;
213 musb_writel(fifo, 0, val);
214 }
215 len &= 0x03;
216 }
217 }
218 }
219
220 if (len > 0)
221 tusb_fifo_write_unaligned(fifo, buf, len);
222}
223
224void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
225{
226 struct musb *musb = hw_ep->musb;
227 void __iomem *ep_conf = hw_ep->conf;
228 void __iomem *fifo = hw_ep->fifo;
229 u8 epnum = hw_ep->epnum;
230
231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
232 'R', epnum, fifo, len, buf);
233
234 if (epnum)
235 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
236 TUSB_EP_CONFIG_XFR_SIZE(len));
237 else
238 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
239
240 if (likely((0x01 & (unsigned long) buf) == 0)) {
241
242 /* Best case is 32bit-aligned destination address */
243 if ((0x02 & (unsigned long) buf) == 0) {
244 if (len >= 4) {
245 readsl(fifo, buf, len >> 2);
246 buf += (len & ~0x03);
247 len &= 0x03;
248 }
249 } else {
250 if (len >= 2) {
251 u32 val;
252 int i;
253
254 /* Cannot use readsw, fifo is 32-bit */
255 for (i = 0; i < (len >> 2); i++) {
256 val = musb_readl(fifo, 0);
257 *(u16 *)buf = (u16)(val & 0xffff);
258 buf += 2;
259 *(u16 *)buf = (u16)(val >> 16);
260 buf += 2;
261 }
262 len &= 0x03;
263 }
264 }
265 }
266
267 if (len > 0)
268 tusb_fifo_read_unaligned(fifo, buf, len);
269}
270
271static struct musb *the_musb;
272
273/* This is used by gadget drivers, and OTG transceiver logic, allowing
274 * at most mA current to be drawn from VBUS during a Default-B session
275 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
276 * mode), or low power Default-B sessions, something else supplies power.
277 * Caller must take care of locking.
278 */
279static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
280{
281 struct musb *musb = the_musb;
282 void __iomem *tbase = musb->ctrl_base;
283 u32 reg;
284
285 /* tps65030 seems to consume max 100mA, with maybe 60mA available
286 * (measured on one board) for things other than tps and tusb.
287 *
288 * Boards sharing the CPU clock with CLKIN will need to prevent
289 * certain idle sleep states while the USB link is active.
290 *
291 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
292 * The actual current usage would be very board-specific. For now,
293 * it's simpler to just use an aggregate (also board-specific).
294 */
295 if (x->default_a || mA < (musb->min_power << 1))
296 mA = 0;
297
298 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
299 if (mA) {
300 musb->is_bus_powered = 1;
301 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
302 } else {
303 musb->is_bus_powered = 0;
304 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
305 }
306 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
307
308 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
309 return 0;
310}
311
312/* workaround for issue 13: change clock during chip idle
313 * (to be fixed in rev3 silicon) ... symptoms include disconnect
314 * or looping suspend/resume cycles
315 */
316static void tusb_set_clock_source(struct musb *musb, unsigned mode)
317{
318 void __iomem *tbase = musb->ctrl_base;
319 u32 reg;
320
321 reg = musb_readl(tbase, TUSB_PRCM_CONF);
322 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
323
324 /* 0 = refclk (clkin, XI)
325 * 1 = PHY 60 MHz (internal PLL)
326 * 2 = not supported
327 * 3 = what?
328 */
329 if (mode > 0)
330 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
331
332 musb_writel(tbase, TUSB_PRCM_CONF, reg);
333
334 /* FIXME tusb6010_platform_retime(mode == 0); */
335}
336
337/*
338 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
339 * Other code ensures that we idle unless we're connected _and_ the
340 * USB link is not suspended ... and tells us the relevant wakeup
341 * events. SW_EN for voltage is handled separately.
342 */
343static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
344{
345 void __iomem *tbase = musb->ctrl_base;
346 u32 reg;
347
348 if ((wakeup_enables & TUSB_PRCM_WBUS)
349 && (tusb_get_revision(musb) == TUSB_REV_30))
350 tusb_wbus_quirk(musb, 1);
351
352 tusb_set_clock_source(musb, 0);
353
354 wakeup_enables |= TUSB_PRCM_WNORCS;
355 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
356
357 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
358 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
359 * Presumably that's mostly to save power, hence WID is immaterial ...
360 */
361
362 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
363 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
364 if (is_host_active(musb)) {
365 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
366 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
367 } else {
368 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
369 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
370 }
371 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
372 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
373
374 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
375}
376
377/*
378 * Updates cable VBUS status. Caller must take care of locking.
379 */
380static int tusb_musb_vbus_status(struct musb *musb)
381{
382 void __iomem *tbase = musb->ctrl_base;
383 u32 otg_stat, prcm_mngmt;
384 int ret = 0;
385
386 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
387 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
388
389 /* Temporarily enable VBUS detection if it was disabled for
390 * suspend mode. Unless it's enabled otg_stat and devctl will
391 * not show correct VBUS state.
392 */
393 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
394 u32 tmp = prcm_mngmt;
395 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
396 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
397 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
398 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
399 }
400
401 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
402 ret = 1;
403
404 return ret;
405}
406
407static struct timer_list musb_idle_timer;
408
409static void musb_do_idle(unsigned long _musb)
410{
411 struct musb *musb = (void *)_musb;
412 unsigned long flags;
413
414 spin_lock_irqsave(&musb->lock, flags);
415
416 switch (musb->xceiv->state) {
417 case OTG_STATE_A_WAIT_BCON:
418 if ((musb->a_wait_bcon != 0)
419 && (musb->idle_timeout == 0
420 || time_after(jiffies, musb->idle_timeout))) {
421 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
422 otg_state_string(musb->xceiv->state));
423 }
424 /* FALLTHROUGH */
425 case OTG_STATE_A_IDLE:
426 tusb_musb_set_vbus(musb, 0);
427 default:
428 break;
429 }
430
431 if (!musb->is_active) {
432 u32 wakeups;
433
434 /* wait until khubd handles port change status */
435 if (is_host_active(musb) && (musb->port1_status >> 16))
436 goto done;
437
438 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
439 wakeups = 0;
440 } else {
441 wakeups = TUSB_PRCM_WHOSTDISCON
442 | TUSB_PRCM_WBUS
443 | TUSB_PRCM_WVBUS;
444 if (is_otg_enabled(musb))
445 wakeups |= TUSB_PRCM_WID;
446 }
447 tusb_allow_idle(musb, wakeups);
448 }
449done:
450 spin_unlock_irqrestore(&musb->lock, flags);
451}
452
453/*
454 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
455 * like "disconnected" or "suspended". We'll be woken out of it by
456 * connect, resume, or disconnect.
457 *
458 * Needs to be called as the last function everywhere where there is
459 * register access to TUSB6010 because of NOR flash wake-up.
460 * Caller should own controller spinlock.
461 *
462 * Delay because peripheral enables D+ pullup 3msec after SE0, and
463 * we don't want to treat that full speed J as a wakeup event.
464 * ... peripherals must draw only suspend current after 10 msec.
465 */
466static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
467{
468 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
469 static unsigned long last_timer;
470
471 if (timeout == 0)
472 timeout = default_timeout;
473
474 /* Never idle if active, or when VBUS timeout is not set as host */
475 if (musb->is_active || ((musb->a_wait_bcon == 0)
476 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
477 dev_dbg(musb->controller, "%s active, deleting timer\n",
478 otg_state_string(musb->xceiv->state));
479 del_timer(&musb_idle_timer);
480 last_timer = jiffies;
481 return;
482 }
483
484 if (time_after(last_timer, timeout)) {
485 if (!timer_pending(&musb_idle_timer))
486 last_timer = timeout;
487 else {
488 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
489 return;
490 }
491 }
492 last_timer = timeout;
493
494 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
495 otg_state_string(musb->xceiv->state),
496 (unsigned long)jiffies_to_msecs(timeout - jiffies));
497 mod_timer(&musb_idle_timer, timeout);
498}
499
500/* ticks of 60 MHz clock */
501#define DEVCLOCK 60000000
502#define OTG_TIMER_MS(msecs) ((msecs) \
503 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
504 | TUSB_DEV_OTG_TIMER_ENABLE) \
505 : 0)
506
507static void tusb_musb_set_vbus(struct musb *musb, int is_on)
508{
509 void __iomem *tbase = musb->ctrl_base;
510 u32 conf, prcm, timer;
511 u8 devctl;
512
513 /* HDRC controls CPEN, but beware current surges during device
514 * connect. They can trigger transient overcurrent conditions
515 * that must be ignored.
516 */
517
518 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
519 conf = musb_readl(tbase, TUSB_DEV_CONF);
520 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
521
522 if (is_on) {
523 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
524 musb->xceiv->default_a = 1;
525 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
526 devctl |= MUSB_DEVCTL_SESSION;
527
528 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
529 MUSB_HST_MODE(musb);
530 } else {
531 u32 otg_stat;
532
533 timer = 0;
534
535 /* If ID pin is grounded, we want to be a_idle */
536 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
537 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
538 switch (musb->xceiv->state) {
539 case OTG_STATE_A_WAIT_VRISE:
540 case OTG_STATE_A_WAIT_BCON:
541 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
542 break;
543 case OTG_STATE_A_WAIT_VFALL:
544 musb->xceiv->state = OTG_STATE_A_IDLE;
545 break;
546 default:
547 musb->xceiv->state = OTG_STATE_A_IDLE;
548 }
549 musb->is_active = 0;
550 musb->xceiv->default_a = 1;
551 MUSB_HST_MODE(musb);
552 } else {
553 musb->is_active = 0;
554 musb->xceiv->default_a = 0;
555 musb->xceiv->state = OTG_STATE_B_IDLE;
556 MUSB_DEV_MODE(musb);
557 }
558
559 devctl &= ~MUSB_DEVCTL_SESSION;
560 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
561 }
562 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
563
564 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
565 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
566 musb_writel(tbase, TUSB_DEV_CONF, conf);
567 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
568
569 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
570 otg_state_string(musb->xceiv->state),
571 musb_readb(musb->mregs, MUSB_DEVCTL),
572 musb_readl(tbase, TUSB_DEV_OTG_STAT),
573 conf, prcm);
574}
575
576/*
577 * Sets the mode to OTG, peripheral or host by changing the ID detection.
578 * Caller must take care of locking.
579 *
580 * Note that if a mini-A cable is plugged in the ID line will stay down as
581 * the weak ID pull-up is not able to pull the ID up.
582 *
583 * REVISIT: It would be possible to add support for changing between host
584 * and peripheral modes in non-OTG configurations by reconfiguring hardware
585 * and then setting musb->board_mode. For now, only support OTG mode.
586 */
587static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
588{
589 void __iomem *tbase = musb->ctrl_base;
590 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
591
592 if (musb->board_mode != MUSB_OTG) {
593 ERR("Changing mode currently only supported in OTG mode\n");
594 return -EINVAL;
595 }
596
597 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
598 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
599 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
600 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
601
602 switch (musb_mode) {
603
604 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
605 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
606 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
607 dev_conf |= TUSB_DEV_CONF_ID_SEL;
608 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
609 break;
610 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
611 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
612 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
613 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
614 break;
615 case MUSB_OTG: /* Use PHY ID detection */
616 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
617 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
618 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
619 break;
620
621 default:
622 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
623 return -EINVAL;
624 }
625
626 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
627 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
628 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
629 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
630 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
631
632 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
633 if ((musb_mode == MUSB_PERIPHERAL) &&
634 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
635 INFO("Cannot be peripheral with mini-A cable "
636 "otg_stat: %08x\n", otg_stat);
637
638 return 0;
639}
640
641static inline unsigned long
642tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
643{
644 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
645 unsigned long idle_timeout = 0;
646
647 /* ID pin */
648 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
649 int default_a;
650
651 if (is_otg_enabled(musb))
652 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
653 else
654 default_a = is_host_enabled(musb);
655 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
656 musb->xceiv->default_a = default_a;
657 tusb_musb_set_vbus(musb, default_a);
658
659 /* Don't allow idling immediately */
660 if (default_a)
661 idle_timeout = jiffies + (HZ * 3);
662 }
663
664 /* VBUS state change */
665 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
666
667 /* B-dev state machine: no vbus ~= disconnect */
668 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
669 || !is_host_enabled(musb)) {
670 /* ? musb_root_disconnect(musb); */
671 musb->port1_status &=
672 ~(USB_PORT_STAT_CONNECTION
673 | USB_PORT_STAT_ENABLE
674 | USB_PORT_STAT_LOW_SPEED
675 | USB_PORT_STAT_HIGH_SPEED
676 | USB_PORT_STAT_TEST
677 );
678
679 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
680 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
681 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
682 /* INTR_DISCONNECT can hide... */
683 musb->xceiv->state = OTG_STATE_B_IDLE;
684 musb->int_usb |= MUSB_INTR_DISCONNECT;
685 }
686 musb->is_active = 0;
687 }
688 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
689 otg_state_string(musb->xceiv->state), otg_stat);
690 idle_timeout = jiffies + (1 * HZ);
691 schedule_work(&musb->irq_work);
692
693 } else /* A-dev state machine */ {
694 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
695 otg_state_string(musb->xceiv->state), otg_stat);
696
697 switch (musb->xceiv->state) {
698 case OTG_STATE_A_IDLE:
699 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
700 musb_platform_set_vbus(musb, 1);
701
702 /* CONNECT can wake if a_wait_bcon is set */
703 if (musb->a_wait_bcon != 0)
704 musb->is_active = 0;
705 else
706 musb->is_active = 1;
707
708 /*
709 * OPT FS A TD.4.6 needs few seconds for
710 * A_WAIT_VRISE
711 */
712 idle_timeout = jiffies + (2 * HZ);
713
714 break;
715 case OTG_STATE_A_WAIT_VRISE:
716 /* ignore; A-session-valid < VBUS_VALID/2,
717 * we monitor this with the timer
718 */
719 break;
720 case OTG_STATE_A_WAIT_VFALL:
721 /* REVISIT this irq triggers during short
722 * spikes caused by enumeration ...
723 */
724 if (musb->vbuserr_retry) {
725 musb->vbuserr_retry--;
726 tusb_musb_set_vbus(musb, 1);
727 } else {
728 musb->vbuserr_retry
729 = VBUSERR_RETRY_COUNT;
730 tusb_musb_set_vbus(musb, 0);
731 }
732 break;
733 default:
734 break;
735 }
736 }
737 }
738
739 /* OTG timer expiration */
740 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
741 u8 devctl;
742
743 dev_dbg(musb->controller, "%s timer, %03x\n",
744 otg_state_string(musb->xceiv->state), otg_stat);
745
746 switch (musb->xceiv->state) {
747 case OTG_STATE_A_WAIT_VRISE:
748 /* VBUS has probably been valid for a while now,
749 * but may well have bounced out of range a bit
750 */
751 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
752 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
753 if ((devctl & MUSB_DEVCTL_VBUS)
754 != MUSB_DEVCTL_VBUS) {
755 dev_dbg(musb->controller, "devctl %02x\n", devctl);
756 break;
757 }
758 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
759 musb->is_active = 0;
760 idle_timeout = jiffies
761 + msecs_to_jiffies(musb->a_wait_bcon);
762 } else {
763 /* REVISIT report overcurrent to hub? */
764 ERR("vbus too slow, devctl %02x\n", devctl);
765 tusb_musb_set_vbus(musb, 0);
766 }
767 break;
768 case OTG_STATE_A_WAIT_BCON:
769 if (musb->a_wait_bcon != 0)
770 idle_timeout = jiffies
771 + msecs_to_jiffies(musb->a_wait_bcon);
772 break;
773 case OTG_STATE_A_SUSPEND:
774 break;
775 case OTG_STATE_B_WAIT_ACON:
776 break;
777 default:
778 break;
779 }
780 }
781 schedule_work(&musb->irq_work);
782
783 return idle_timeout;
784}
785
786static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
787{
788 struct musb *musb = __hci;
789 void __iomem *tbase = musb->ctrl_base;
790 unsigned long flags, idle_timeout = 0;
791 u32 int_mask, int_src;
792
793 spin_lock_irqsave(&musb->lock, flags);
794
795 /* Mask all interrupts to allow using both edge and level GPIO irq */
796 int_mask = musb_readl(tbase, TUSB_INT_MASK);
797 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
798
799 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
800 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
801
802 musb->int_usb = (u8) int_src;
803
804 /* Acknowledge wake-up source interrupts */
805 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
806 u32 reg;
807 u32 i;
808
809 if (tusb_get_revision(musb) == TUSB_REV_30)
810 tusb_wbus_quirk(musb, 0);
811
812 /* there are issues re-locking the PLL on wakeup ... */
813
814 /* work around issue 8 */
815 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
816 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
817 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
818 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
819 if (reg == i)
820 break;
821 dev_dbg(musb->controller, "TUSB NOR not ready\n");
822 }
823
824 /* work around issue 13 (2nd half) */
825 tusb_set_clock_source(musb, 1);
826
827 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
828 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
829 if (reg & ~TUSB_PRCM_WNORCS) {
830 musb->is_active = 1;
831 schedule_work(&musb->irq_work);
832 }
833 dev_dbg(musb->controller, "wake %sactive %02x\n",
834 musb->is_active ? "" : "in", reg);
835
836 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
837 }
838
839 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
840 del_timer(&musb_idle_timer);
841
842 /* OTG state change reports (annoyingly) not issued by Mentor core */
843 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
844 | TUSB_INT_SRC_OTG_TIMEOUT
845 | TUSB_INT_SRC_ID_STATUS_CHNG))
846 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
847
848 /* TX dma callback must be handled here, RX dma callback is
849 * handled in tusb_omap_dma_cb.
850 */
851 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
852 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
853 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
854
855 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
856 real_dma_src = ~real_dma_src & dma_src;
857 if (tusb_dma_omap() && real_dma_src) {
858 int tx_source = (real_dma_src & 0xffff);
859 int i;
860
861 for (i = 1; i <= 15; i++) {
862 if (tx_source & (1 << i)) {
863 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
864 musb_dma_completion(musb, i, 1);
865 }
866 }
867 }
868 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
869 }
870
871 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
872 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
873 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
874
875 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
876 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
877 musb->int_tx = (musb_src & 0xffff);
878 } else {
879 musb->int_rx = 0;
880 musb->int_tx = 0;
881 }
882
883 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
884 musb_interrupt(musb);
885
886 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
887 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
888 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
889
890 tusb_musb_try_idle(musb, idle_timeout);
891
892 musb_writel(tbase, TUSB_INT_MASK, int_mask);
893 spin_unlock_irqrestore(&musb->lock, flags);
894
895 return IRQ_HANDLED;
896}
897
898static int dma_off;
899
900/*
901 * Enables TUSB6010. Caller must take care of locking.
902 * REVISIT:
903 * - Check what is unnecessary in MGC_HdrcStart()
904 */
905static void tusb_musb_enable(struct musb *musb)
906{
907 void __iomem *tbase = musb->ctrl_base;
908
909 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
910 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
911 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
912
913 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
914 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
915 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
916 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
917
918 /* Clear all subsystem interrups */
919 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
920 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
921 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
922
923 /* Acknowledge pending interrupt(s) */
924 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
925
926 /* Only 0 clock cycles for minimum interrupt de-assertion time and
927 * interrupt polarity active low seems to work reliably here */
928 musb_writel(tbase, TUSB_INT_CTRL_CONF,
929 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
930
931 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
932
933 /* maybe force into the Default-A OTG state machine */
934 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
935 & TUSB_DEV_OTG_STAT_ID_STATUS))
936 musb_writel(tbase, TUSB_INT_SRC_SET,
937 TUSB_INT_SRC_ID_STATUS_CHNG);
938
939 if (is_dma_capable() && dma_off)
940 printk(KERN_WARNING "%s %s: dma not reactivated\n",
941 __FILE__, __func__);
942 else
943 dma_off = 1;
944}
945
946/*
947 * Disables TUSB6010. Caller must take care of locking.
948 */
949static void tusb_musb_disable(struct musb *musb)
950{
951 void __iomem *tbase = musb->ctrl_base;
952
953 /* FIXME stop DMA, IRQs, timers, ... */
954
955 /* disable all IRQs */
956 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
957 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
958 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
959 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
960
961 del_timer(&musb_idle_timer);
962
963 if (is_dma_capable() && !dma_off) {
964 printk(KERN_WARNING "%s %s: dma still active\n",
965 __FILE__, __func__);
966 dma_off = 1;
967 }
968}
969
970/*
971 * Sets up TUSB6010 CPU interface specific signals and registers
972 * Note: Settings optimized for OMAP24xx
973 */
974static void tusb_setup_cpu_interface(struct musb *musb)
975{
976 void __iomem *tbase = musb->ctrl_base;
977
978 /*
979 * Disable GPIO[5:0] pullups (used as output DMA requests)
980 * Don't disable GPIO[7:6] as they are needed for wake-up.
981 */
982 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
983
984 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
985 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
986
987 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
988 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
989
990 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
991 * de-assertion time 2 system clocks p 62 */
992 musb_writel(tbase, TUSB_DMA_REQ_CONF,
993 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
994 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
995 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
996
997 /* Set 0 wait count for synchronous burst access */
998 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
999}
1000
1001static int tusb_musb_start(struct musb *musb)
1002{
1003 void __iomem *tbase = musb->ctrl_base;
1004 int ret = 0;
1005 unsigned long flags;
1006 u32 reg;
1007
1008 if (musb->board_set_power)
1009 ret = musb->board_set_power(1);
1010 if (ret != 0) {
1011 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1012 return ret;
1013 }
1014
1015 spin_lock_irqsave(&musb->lock, flags);
1016
1017 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1018 TUSB_PROD_TEST_RESET_VAL) {
1019 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1020 goto err;
1021 }
1022
1023 ret = tusb_print_revision(musb);
1024 if (ret < 2) {
1025 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1026 ret);
1027 goto err;
1028 }
1029
1030 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1031 * NOR FLASH interface is used */
1032 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1033
1034 /* Select PHY free running 60MHz as a system clock */
1035 tusb_set_clock_source(musb, 1);
1036
1037 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1038 * power saving, enable VBus detect and session end comparators,
1039 * enable IDpullup, enable VBus charging */
1040 musb_writel(tbase, TUSB_PRCM_MNGMT,
1041 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1042 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1043 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1044 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1045 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1046 tusb_setup_cpu_interface(musb);
1047
1048 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1049 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1050 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1051 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1052
1053 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1054 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1055 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1056
1057 spin_unlock_irqrestore(&musb->lock, flags);
1058
1059 return 0;
1060
1061err:
1062 spin_unlock_irqrestore(&musb->lock, flags);
1063
1064 if (musb->board_set_power)
1065 musb->board_set_power(0);
1066
1067 return -ENODEV;
1068}
1069
1070static int tusb_musb_init(struct musb *musb)
1071{
1072 struct platform_device *pdev;
1073 struct resource *mem;
1074 void __iomem *sync = NULL;
1075 int ret;
1076
1077 usb_nop_xceiv_register();
1078 musb->xceiv = otg_get_transceiver();
1079 if (!musb->xceiv)
1080 return -ENODEV;
1081
1082 pdev = to_platform_device(musb->controller);
1083
1084 /* dma address for async dma */
1085 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086 musb->async = mem->start;
1087
1088 /* dma address for sync dma */
1089 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1090 if (!mem) {
1091 pr_debug("no sync dma resource?\n");
1092 ret = -ENODEV;
1093 goto done;
1094 }
1095 musb->sync = mem->start;
1096
1097 sync = ioremap(mem->start, resource_size(mem));
1098 if (!sync) {
1099 pr_debug("ioremap for sync failed\n");
1100 ret = -ENOMEM;
1101 goto done;
1102 }
1103 musb->sync_va = sync;
1104
1105 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1106 * FIFOs at 0x600, TUSB at 0x800
1107 */
1108 musb->mregs += TUSB_BASE_OFFSET;
1109
1110 ret = tusb_musb_start(musb);
1111 if (ret) {
1112 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1113 ret);
1114 goto done;
1115 }
1116 musb->isr = tusb_musb_interrupt;
1117
1118 if (is_peripheral_enabled(musb)) {
1119 musb->xceiv->set_power = tusb_draw_power;
1120 the_musb = musb;
1121 }
1122
1123 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1124
1125done:
1126 if (ret < 0) {
1127 if (sync)
1128 iounmap(sync);
1129
1130 otg_put_transceiver(musb->xceiv);
1131 usb_nop_xceiv_unregister();
1132 }
1133 return ret;
1134}
1135
1136static int tusb_musb_exit(struct musb *musb)
1137{
1138 del_timer_sync(&musb_idle_timer);
1139 the_musb = NULL;
1140
1141 if (musb->board_set_power)
1142 musb->board_set_power(0);
1143
1144 iounmap(musb->sync_va);
1145
1146 otg_put_transceiver(musb->xceiv);
1147 usb_nop_xceiv_unregister();
1148 return 0;
1149}
1150
1151static const struct musb_platform_ops tusb_ops = {
1152 .init = tusb_musb_init,
1153 .exit = tusb_musb_exit,
1154
1155 .enable = tusb_musb_enable,
1156 .disable = tusb_musb_disable,
1157
1158 .set_mode = tusb_musb_set_mode,
1159 .try_idle = tusb_musb_try_idle,
1160
1161 .vbus_status = tusb_musb_vbus_status,
1162 .set_vbus = tusb_musb_set_vbus,
1163};
1164
1165static u64 tusb_dmamask = DMA_BIT_MASK(32);
1166
1167static int __init tusb_probe(struct platform_device *pdev)
1168{
1169 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1170 struct platform_device *musb;
1171 struct tusb6010_glue *glue;
1172
1173 int ret = -ENOMEM;
1174
1175 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1176 if (!glue) {
1177 dev_err(&pdev->dev, "failed to allocate glue context\n");
1178 goto err0;
1179 }
1180
1181 musb = platform_device_alloc("musb-hdrc", -1);
1182 if (!musb) {
1183 dev_err(&pdev->dev, "failed to allocate musb device\n");
1184 goto err1;
1185 }
1186
1187 musb->dev.parent = &pdev->dev;
1188 musb->dev.dma_mask = &tusb_dmamask;
1189 musb->dev.coherent_dma_mask = tusb_dmamask;
1190
1191 glue->dev = &pdev->dev;
1192 glue->musb = musb;
1193
1194 pdata->platform_ops = &tusb_ops;
1195
1196 platform_set_drvdata(pdev, glue);
1197
1198 ret = platform_device_add_resources(musb, pdev->resource,
1199 pdev->num_resources);
1200 if (ret) {
1201 dev_err(&pdev->dev, "failed to add resources\n");
1202 goto err2;
1203 }
1204
1205 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1206 if (ret) {
1207 dev_err(&pdev->dev, "failed to add platform_data\n");
1208 goto err2;
1209 }
1210
1211 ret = platform_device_add(musb);
1212 if (ret) {
1213 dev_err(&pdev->dev, "failed to register musb device\n");
1214 goto err1;
1215 }
1216
1217 return 0;
1218
1219err2:
1220 platform_device_put(musb);
1221
1222err1:
1223 kfree(glue);
1224
1225err0:
1226 return ret;
1227}
1228
1229static int __exit tusb_remove(struct platform_device *pdev)
1230{
1231 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1232
1233 platform_device_del(glue->musb);
1234 platform_device_put(glue->musb);
1235 kfree(glue);
1236
1237 return 0;
1238}
1239
1240static struct platform_driver tusb_driver = {
1241 .remove = __exit_p(tusb_remove),
1242 .driver = {
1243 .name = "musb-tusb",
1244 },
1245};
1246
1247MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1248MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1249MODULE_LICENSE("GPL v2");
1250
1251static int __init tusb_init(void)
1252{
1253 return platform_driver_probe(&tusb_driver, tusb_probe);
1254}
1255subsys_initcall(tusb_init);
1256
1257static void __exit tusb_exit(void)
1258{
1259 platform_driver_unregister(&tusb_driver);
1260}
1261module_exit(tusb_exit);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * TUSB6010 USB 2.0 OTG Dual Role controller
4 *
5 * Copyright (C) 2006 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 *
8 * Notes:
9 * - Driver assumes that interface to external host (main CPU) is
10 * configured for NOR FLASH interface instead of VLYNQ serial
11 * interface.
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/prefetch.h>
19#include <linux/usb.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/platform_device.h>
24#include <linux/dma-mapping.h>
25#include <linux/usb/usb_phy_generic.h>
26
27#include "musb_core.h"
28
29struct tusb6010_glue {
30 struct device *dev;
31 struct platform_device *musb;
32 struct platform_device *phy;
33};
34
35static void tusb_musb_set_vbus(struct musb *musb, int is_on);
36
37#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
38#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
39
40/*
41 * Checks the revision. We need to use the DMA register as 3.0 does not
42 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
43 */
44static u8 tusb_get_revision(struct musb *musb)
45{
46 void __iomem *tbase = musb->ctrl_base;
47 u32 die_id;
48 u8 rev;
49
50 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
51 if (TUSB_REV_MAJOR(rev) == 3) {
52 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
53 TUSB_DIDR1_HI));
54 if (die_id >= TUSB_DIDR1_HI_REV_31)
55 rev |= 1;
56 }
57
58 return rev;
59}
60
61static void tusb_print_revision(struct musb *musb)
62{
63 void __iomem *tbase = musb->ctrl_base;
64 u8 rev;
65
66 rev = musb->tusb_revision;
67
68 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
69 "prcm",
70 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
72 "int",
73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
75 "gpio",
76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
78 "dma",
79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
81 "dieid",
82 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
83 "rev",
84 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
85}
86
87#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
88 | TUSB_PHY_OTG_CTRL_TESTM0)
89
90/*
91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
92 * Disables power detection in PHY for the duration of idle.
93 */
94static void tusb_wbus_quirk(struct musb *musb, int enabled)
95{
96 void __iomem *tbase = musb->ctrl_base;
97 static u32 phy_otg_ctrl, phy_otg_ena;
98 u32 tmp;
99
100 if (enabled) {
101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
104 | phy_otg_ena | WBUS_QUIRK_MASK;
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
113 & TUSB_PHY_OTG_CTRL_TESTM2) {
114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0;
122 phy_otg_ena = 0;
123 }
124}
125
126static u32 tusb_fifo_offset(u8 epnum)
127{
128 return 0x200 + (epnum * 0x20);
129}
130
131static u32 tusb_ep_offset(u8 epnum, u16 offset)
132{
133 return 0x10 + offset;
134}
135
136/* TUSB mapping: "flat" plus ep0 special cases */
137static void tusb_ep_select(void __iomem *mbase, u8 epnum)
138{
139 musb_writeb(mbase, MUSB_INDEX, epnum);
140}
141
142/*
143 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
144 */
145static u8 tusb_readb(const void __iomem *addr, unsigned offset)
146{
147 u16 tmp;
148 u8 val;
149
150 tmp = __raw_readw(addr + (offset & ~1));
151 if (offset & 1)
152 val = (tmp >> 8);
153 else
154 val = tmp & 0xff;
155
156 return val;
157}
158
159static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data)
160{
161 u16 tmp;
162
163 tmp = __raw_readw(addr + (offset & ~1));
164 if (offset & 1)
165 tmp = (data << 8) | (tmp & 0xff);
166 else
167 tmp = (tmp & 0xff00) | data;
168
169 __raw_writew(tmp, addr + (offset & ~1));
170}
171
172/*
173 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
174 * so both loading and unloading FIFOs need explicit byte counts.
175 */
176
177static inline void
178tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
179{
180 u32 val;
181 int i;
182
183 if (len > 4) {
184 for (i = 0; i < (len >> 2); i++) {
185 memcpy(&val, buf, 4);
186 musb_writel(fifo, 0, val);
187 buf += 4;
188 }
189 len %= 4;
190 }
191 if (len > 0) {
192 /* Write the rest 1 - 3 bytes to FIFO */
193 memcpy(&val, buf, len);
194 musb_writel(fifo, 0, val);
195 }
196}
197
198static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
199 void *buf, u16 len)
200{
201 u32 val;
202 int i;
203
204 if (len > 4) {
205 for (i = 0; i < (len >> 2); i++) {
206 val = musb_readl(fifo, 0);
207 memcpy(buf, &val, 4);
208 buf += 4;
209 }
210 len %= 4;
211 }
212 if (len > 0) {
213 /* Read the rest 1 - 3 bytes from FIFO */
214 val = musb_readl(fifo, 0);
215 memcpy(buf, &val, len);
216 }
217}
218
219static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
220{
221 struct musb *musb = hw_ep->musb;
222 void __iomem *ep_conf = hw_ep->conf;
223 void __iomem *fifo = hw_ep->fifo;
224 u8 epnum = hw_ep->epnum;
225
226 prefetch(buf);
227
228 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'T', epnum, fifo, len, buf);
230
231 if (epnum)
232 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
233 TUSB_EP_CONFIG_XFR_SIZE(len));
234 else
235 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
236 TUSB_EP0_CONFIG_XFR_SIZE(len));
237
238 if (likely((0x01 & (unsigned long) buf) == 0)) {
239
240 /* Best case is 32bit-aligned destination address */
241 if ((0x02 & (unsigned long) buf) == 0) {
242 if (len >= 4) {
243 iowrite32_rep(fifo, buf, len >> 2);
244 buf += (len & ~0x03);
245 len &= 0x03;
246 }
247 } else {
248 if (len >= 2) {
249 u32 val;
250 int i;
251
252 /* Cannot use writesw, fifo is 32-bit */
253 for (i = 0; i < (len >> 2); i++) {
254 val = (u32)(*(u16 *)buf);
255 buf += 2;
256 val |= (*(u16 *)buf) << 16;
257 buf += 2;
258 musb_writel(fifo, 0, val);
259 }
260 len &= 0x03;
261 }
262 }
263 }
264
265 if (len > 0)
266 tusb_fifo_write_unaligned(fifo, buf, len);
267}
268
269static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
270{
271 struct musb *musb = hw_ep->musb;
272 void __iomem *ep_conf = hw_ep->conf;
273 void __iomem *fifo = hw_ep->fifo;
274 u8 epnum = hw_ep->epnum;
275
276 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
277 'R', epnum, fifo, len, buf);
278
279 if (epnum)
280 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
281 TUSB_EP_CONFIG_XFR_SIZE(len));
282 else
283 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
284
285 if (likely((0x01 & (unsigned long) buf) == 0)) {
286
287 /* Best case is 32bit-aligned destination address */
288 if ((0x02 & (unsigned long) buf) == 0) {
289 if (len >= 4) {
290 ioread32_rep(fifo, buf, len >> 2);
291 buf += (len & ~0x03);
292 len &= 0x03;
293 }
294 } else {
295 if (len >= 2) {
296 u32 val;
297 int i;
298
299 /* Cannot use readsw, fifo is 32-bit */
300 for (i = 0; i < (len >> 2); i++) {
301 val = musb_readl(fifo, 0);
302 *(u16 *)buf = (u16)(val & 0xffff);
303 buf += 2;
304 *(u16 *)buf = (u16)(val >> 16);
305 buf += 2;
306 }
307 len &= 0x03;
308 }
309 }
310 }
311
312 if (len > 0)
313 tusb_fifo_read_unaligned(fifo, buf, len);
314}
315
316static struct musb *the_musb;
317
318/* This is used by gadget drivers, and OTG transceiver logic, allowing
319 * at most mA current to be drawn from VBUS during a Default-B session
320 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
321 * mode), or low power Default-B sessions, something else supplies power.
322 * Caller must take care of locking.
323 */
324static int tusb_draw_power(struct usb_phy *x, unsigned mA)
325{
326 struct musb *musb = the_musb;
327 void __iomem *tbase = musb->ctrl_base;
328 u32 reg;
329
330 /* tps65030 seems to consume max 100mA, with maybe 60mA available
331 * (measured on one board) for things other than tps and tusb.
332 *
333 * Boards sharing the CPU clock with CLKIN will need to prevent
334 * certain idle sleep states while the USB link is active.
335 *
336 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
337 * The actual current usage would be very board-specific. For now,
338 * it's simpler to just use an aggregate (also board-specific).
339 */
340 if (x->otg->default_a || mA < (musb->min_power << 1))
341 mA = 0;
342
343 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
344 if (mA) {
345 musb->is_bus_powered = 1;
346 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
347 } else {
348 musb->is_bus_powered = 0;
349 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
350 }
351 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
352
353 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
354 return 0;
355}
356
357/* workaround for issue 13: change clock during chip idle
358 * (to be fixed in rev3 silicon) ... symptoms include disconnect
359 * or looping suspend/resume cycles
360 */
361static void tusb_set_clock_source(struct musb *musb, unsigned mode)
362{
363 void __iomem *tbase = musb->ctrl_base;
364 u32 reg;
365
366 reg = musb_readl(tbase, TUSB_PRCM_CONF);
367 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
368
369 /* 0 = refclk (clkin, XI)
370 * 1 = PHY 60 MHz (internal PLL)
371 * 2 = not supported
372 * 3 = what?
373 */
374 if (mode > 0)
375 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
376
377 musb_writel(tbase, TUSB_PRCM_CONF, reg);
378
379 /* FIXME tusb6010_platform_retime(mode == 0); */
380}
381
382/*
383 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
384 * Other code ensures that we idle unless we're connected _and_ the
385 * USB link is not suspended ... and tells us the relevant wakeup
386 * events. SW_EN for voltage is handled separately.
387 */
388static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
389{
390 void __iomem *tbase = musb->ctrl_base;
391 u32 reg;
392
393 if ((wakeup_enables & TUSB_PRCM_WBUS)
394 && (musb->tusb_revision == TUSB_REV_30))
395 tusb_wbus_quirk(musb, 1);
396
397 tusb_set_clock_source(musb, 0);
398
399 wakeup_enables |= TUSB_PRCM_WNORCS;
400 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
401
402 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
403 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
404 * Presumably that's mostly to save power, hence WID is immaterial ...
405 */
406
407 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
408 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
409 if (is_host_active(musb)) {
410 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
411 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
412 } else {
413 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
414 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
415 }
416 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
417 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
418
419 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
420}
421
422/*
423 * Updates cable VBUS status. Caller must take care of locking.
424 */
425static int tusb_musb_vbus_status(struct musb *musb)
426{
427 void __iomem *tbase = musb->ctrl_base;
428 u32 otg_stat, prcm_mngmt;
429 int ret = 0;
430
431 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
432 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
433
434 /* Temporarily enable VBUS detection if it was disabled for
435 * suspend mode. Unless it's enabled otg_stat and devctl will
436 * not show correct VBUS state.
437 */
438 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
439 u32 tmp = prcm_mngmt;
440 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
441 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
442 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
443 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
444 }
445
446 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
447 ret = 1;
448
449 return ret;
450}
451
452static void musb_do_idle(struct timer_list *t)
453{
454 struct musb *musb = from_timer(musb, t, dev_timer);
455 unsigned long flags;
456
457 spin_lock_irqsave(&musb->lock, flags);
458
459 switch (musb->xceiv->otg->state) {
460 case OTG_STATE_A_WAIT_BCON:
461 if ((musb->a_wait_bcon != 0)
462 && (musb->idle_timeout == 0
463 || time_after(jiffies, musb->idle_timeout))) {
464 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
465 usb_otg_state_string(musb->xceiv->otg->state));
466 }
467 /* FALLTHROUGH */
468 case OTG_STATE_A_IDLE:
469 tusb_musb_set_vbus(musb, 0);
470 default:
471 break;
472 }
473
474 if (!musb->is_active) {
475 u32 wakeups;
476
477 /* wait until hub_wq handles port change status */
478 if (is_host_active(musb) && (musb->port1_status >> 16))
479 goto done;
480
481 if (!musb->gadget_driver) {
482 wakeups = 0;
483 } else {
484 wakeups = TUSB_PRCM_WHOSTDISCON
485 | TUSB_PRCM_WBUS
486 | TUSB_PRCM_WVBUS;
487 wakeups |= TUSB_PRCM_WID;
488 }
489 tusb_allow_idle(musb, wakeups);
490 }
491done:
492 spin_unlock_irqrestore(&musb->lock, flags);
493}
494
495/*
496 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
497 * like "disconnected" or "suspended". We'll be woken out of it by
498 * connect, resume, or disconnect.
499 *
500 * Needs to be called as the last function everywhere where there is
501 * register access to TUSB6010 because of NOR flash wake-up.
502 * Caller should own controller spinlock.
503 *
504 * Delay because peripheral enables D+ pullup 3msec after SE0, and
505 * we don't want to treat that full speed J as a wakeup event.
506 * ... peripherals must draw only suspend current after 10 msec.
507 */
508static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
509{
510 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
511 static unsigned long last_timer;
512
513 if (timeout == 0)
514 timeout = default_timeout;
515
516 /* Never idle if active, or when VBUS timeout is not set as host */
517 if (musb->is_active || ((musb->a_wait_bcon == 0)
518 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
519 dev_dbg(musb->controller, "%s active, deleting timer\n",
520 usb_otg_state_string(musb->xceiv->otg->state));
521 del_timer(&musb->dev_timer);
522 last_timer = jiffies;
523 return;
524 }
525
526 if (time_after(last_timer, timeout)) {
527 if (!timer_pending(&musb->dev_timer))
528 last_timer = timeout;
529 else {
530 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
531 return;
532 }
533 }
534 last_timer = timeout;
535
536 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
537 usb_otg_state_string(musb->xceiv->otg->state),
538 (unsigned long)jiffies_to_msecs(timeout - jiffies));
539 mod_timer(&musb->dev_timer, timeout);
540}
541
542/* ticks of 60 MHz clock */
543#define DEVCLOCK 60000000
544#define OTG_TIMER_MS(msecs) ((msecs) \
545 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
546 | TUSB_DEV_OTG_TIMER_ENABLE) \
547 : 0)
548
549static void tusb_musb_set_vbus(struct musb *musb, int is_on)
550{
551 void __iomem *tbase = musb->ctrl_base;
552 u32 conf, prcm, timer;
553 u8 devctl;
554 struct usb_otg *otg = musb->xceiv->otg;
555
556 /* HDRC controls CPEN, but beware current surges during device
557 * connect. They can trigger transient overcurrent conditions
558 * that must be ignored.
559 */
560
561 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
562 conf = musb_readl(tbase, TUSB_DEV_CONF);
563 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
564
565 if (is_on) {
566 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
567 otg->default_a = 1;
568 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
569 devctl |= MUSB_DEVCTL_SESSION;
570
571 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
572 MUSB_HST_MODE(musb);
573 } else {
574 u32 otg_stat;
575
576 timer = 0;
577
578 /* If ID pin is grounded, we want to be a_idle */
579 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
580 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
581 switch (musb->xceiv->otg->state) {
582 case OTG_STATE_A_WAIT_VRISE:
583 case OTG_STATE_A_WAIT_BCON:
584 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
585 break;
586 case OTG_STATE_A_WAIT_VFALL:
587 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
588 break;
589 default:
590 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
591 }
592 musb->is_active = 0;
593 otg->default_a = 1;
594 MUSB_HST_MODE(musb);
595 } else {
596 musb->is_active = 0;
597 otg->default_a = 0;
598 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
599 MUSB_DEV_MODE(musb);
600 }
601
602 devctl &= ~MUSB_DEVCTL_SESSION;
603 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
604 }
605 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
606
607 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
608 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
609 musb_writel(tbase, TUSB_DEV_CONF, conf);
610 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
611
612 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
613 usb_otg_state_string(musb->xceiv->otg->state),
614 musb_readb(musb->mregs, MUSB_DEVCTL),
615 musb_readl(tbase, TUSB_DEV_OTG_STAT),
616 conf, prcm);
617}
618
619/*
620 * Sets the mode to OTG, peripheral or host by changing the ID detection.
621 * Caller must take care of locking.
622 *
623 * Note that if a mini-A cable is plugged in the ID line will stay down as
624 * the weak ID pull-up is not able to pull the ID up.
625 */
626static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
627{
628 void __iomem *tbase = musb->ctrl_base;
629 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
630
631 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
632 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
633 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
634 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
635
636 switch (musb_mode) {
637
638 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
639 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
640 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
641 dev_conf |= TUSB_DEV_CONF_ID_SEL;
642 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
643 break;
644 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
645 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
646 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
647 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
648 break;
649 case MUSB_OTG: /* Use PHY ID detection */
650 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
651 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
652 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
653 break;
654
655 default:
656 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
657 return -EINVAL;
658 }
659
660 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
661 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
662 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
663 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
664 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
665
666 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
667 if ((musb_mode == MUSB_PERIPHERAL) &&
668 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
669 INFO("Cannot be peripheral with mini-A cable "
670 "otg_stat: %08x\n", otg_stat);
671
672 return 0;
673}
674
675static inline unsigned long
676tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
677{
678 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
679 unsigned long idle_timeout = 0;
680 struct usb_otg *otg = musb->xceiv->otg;
681
682 /* ID pin */
683 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
684 int default_a;
685
686 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
687 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
688 otg->default_a = default_a;
689 tusb_musb_set_vbus(musb, default_a);
690
691 /* Don't allow idling immediately */
692 if (default_a)
693 idle_timeout = jiffies + (HZ * 3);
694 }
695
696 /* VBUS state change */
697 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
698
699 /* B-dev state machine: no vbus ~= disconnect */
700 if (!otg->default_a) {
701 /* ? musb_root_disconnect(musb); */
702 musb->port1_status &=
703 ~(USB_PORT_STAT_CONNECTION
704 | USB_PORT_STAT_ENABLE
705 | USB_PORT_STAT_LOW_SPEED
706 | USB_PORT_STAT_HIGH_SPEED
707 | USB_PORT_STAT_TEST
708 );
709
710 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
711 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
712 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
713 /* INTR_DISCONNECT can hide... */
714 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
715 musb->int_usb |= MUSB_INTR_DISCONNECT;
716 }
717 musb->is_active = 0;
718 }
719 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
720 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
721 idle_timeout = jiffies + (1 * HZ);
722 schedule_delayed_work(&musb->irq_work, 0);
723
724 } else /* A-dev state machine */ {
725 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
726 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
727
728 switch (musb->xceiv->otg->state) {
729 case OTG_STATE_A_IDLE:
730 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
731 musb_platform_set_vbus(musb, 1);
732
733 /* CONNECT can wake if a_wait_bcon is set */
734 if (musb->a_wait_bcon != 0)
735 musb->is_active = 0;
736 else
737 musb->is_active = 1;
738
739 /*
740 * OPT FS A TD.4.6 needs few seconds for
741 * A_WAIT_VRISE
742 */
743 idle_timeout = jiffies + (2 * HZ);
744
745 break;
746 case OTG_STATE_A_WAIT_VRISE:
747 /* ignore; A-session-valid < VBUS_VALID/2,
748 * we monitor this with the timer
749 */
750 break;
751 case OTG_STATE_A_WAIT_VFALL:
752 /* REVISIT this irq triggers during short
753 * spikes caused by enumeration ...
754 */
755 if (musb->vbuserr_retry) {
756 musb->vbuserr_retry--;
757 tusb_musb_set_vbus(musb, 1);
758 } else {
759 musb->vbuserr_retry
760 = VBUSERR_RETRY_COUNT;
761 tusb_musb_set_vbus(musb, 0);
762 }
763 break;
764 default:
765 break;
766 }
767 }
768 }
769
770 /* OTG timer expiration */
771 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
772 u8 devctl;
773
774 dev_dbg(musb->controller, "%s timer, %03x\n",
775 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
776
777 switch (musb->xceiv->otg->state) {
778 case OTG_STATE_A_WAIT_VRISE:
779 /* VBUS has probably been valid for a while now,
780 * but may well have bounced out of range a bit
781 */
782 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
783 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
784 if ((devctl & MUSB_DEVCTL_VBUS)
785 != MUSB_DEVCTL_VBUS) {
786 dev_dbg(musb->controller, "devctl %02x\n", devctl);
787 break;
788 }
789 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
790 musb->is_active = 0;
791 idle_timeout = jiffies
792 + msecs_to_jiffies(musb->a_wait_bcon);
793 } else {
794 /* REVISIT report overcurrent to hub? */
795 ERR("vbus too slow, devctl %02x\n", devctl);
796 tusb_musb_set_vbus(musb, 0);
797 }
798 break;
799 case OTG_STATE_A_WAIT_BCON:
800 if (musb->a_wait_bcon != 0)
801 idle_timeout = jiffies
802 + msecs_to_jiffies(musb->a_wait_bcon);
803 break;
804 case OTG_STATE_A_SUSPEND:
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 break;
808 default:
809 break;
810 }
811 }
812 schedule_delayed_work(&musb->irq_work, 0);
813
814 return idle_timeout;
815}
816
817static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
818{
819 struct musb *musb = __hci;
820 void __iomem *tbase = musb->ctrl_base;
821 unsigned long flags, idle_timeout = 0;
822 u32 int_mask, int_src;
823
824 spin_lock_irqsave(&musb->lock, flags);
825
826 /* Mask all interrupts to allow using both edge and level GPIO irq */
827 int_mask = musb_readl(tbase, TUSB_INT_MASK);
828 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
829
830 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
831 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
832
833 musb->int_usb = (u8) int_src;
834
835 /* Acknowledge wake-up source interrupts */
836 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
837 u32 reg;
838 u32 i;
839
840 if (musb->tusb_revision == TUSB_REV_30)
841 tusb_wbus_quirk(musb, 0);
842
843 /* there are issues re-locking the PLL on wakeup ... */
844
845 /* work around issue 8 */
846 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
847 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
848 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
849 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
850 if (reg == i)
851 break;
852 dev_dbg(musb->controller, "TUSB NOR not ready\n");
853 }
854
855 /* work around issue 13 (2nd half) */
856 tusb_set_clock_source(musb, 1);
857
858 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
859 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
860 if (reg & ~TUSB_PRCM_WNORCS) {
861 musb->is_active = 1;
862 schedule_delayed_work(&musb->irq_work, 0);
863 }
864 dev_dbg(musb->controller, "wake %sactive %02x\n",
865 musb->is_active ? "" : "in", reg);
866
867 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
868 }
869
870 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
871 del_timer(&musb->dev_timer);
872
873 /* OTG state change reports (annoyingly) not issued by Mentor core */
874 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
875 | TUSB_INT_SRC_OTG_TIMEOUT
876 | TUSB_INT_SRC_ID_STATUS_CHNG))
877 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
878
879 /*
880 * Just clear the DMA interrupt if it comes as the completion for both
881 * TX and RX is handled by the DMA callback in tusb6010_omap
882 */
883 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
884 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
885
886 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
887 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
888 }
889
890 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
891 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
892 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
893
894 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
895 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
896 musb->int_tx = (musb_src & 0xffff);
897 } else {
898 musb->int_rx = 0;
899 musb->int_tx = 0;
900 }
901
902 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
903 musb_interrupt(musb);
904
905 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
906 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
907 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
908
909 tusb_musb_try_idle(musb, idle_timeout);
910
911 musb_writel(tbase, TUSB_INT_MASK, int_mask);
912 spin_unlock_irqrestore(&musb->lock, flags);
913
914 return IRQ_HANDLED;
915}
916
917static int dma_off;
918
919/*
920 * Enables TUSB6010. Caller must take care of locking.
921 * REVISIT:
922 * - Check what is unnecessary in MGC_HdrcStart()
923 */
924static void tusb_musb_enable(struct musb *musb)
925{
926 void __iomem *tbase = musb->ctrl_base;
927
928 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
929 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
930 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
931
932 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
933 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
934 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
935 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
936
937 /* Clear all subsystem interrups */
938 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
939 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
940 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
941
942 /* Acknowledge pending interrupt(s) */
943 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
944
945 /* Only 0 clock cycles for minimum interrupt de-assertion time and
946 * interrupt polarity active low seems to work reliably here */
947 musb_writel(tbase, TUSB_INT_CTRL_CONF,
948 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
949
950 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
951
952 /* maybe force into the Default-A OTG state machine */
953 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
954 & TUSB_DEV_OTG_STAT_ID_STATUS))
955 musb_writel(tbase, TUSB_INT_SRC_SET,
956 TUSB_INT_SRC_ID_STATUS_CHNG);
957
958 if (is_dma_capable() && dma_off)
959 printk(KERN_WARNING "%s %s: dma not reactivated\n",
960 __FILE__, __func__);
961 else
962 dma_off = 1;
963}
964
965/*
966 * Disables TUSB6010. Caller must take care of locking.
967 */
968static void tusb_musb_disable(struct musb *musb)
969{
970 void __iomem *tbase = musb->ctrl_base;
971
972 /* FIXME stop DMA, IRQs, timers, ... */
973
974 /* disable all IRQs */
975 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
976 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
977 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
978 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
979
980 del_timer(&musb->dev_timer);
981
982 if (is_dma_capable() && !dma_off) {
983 printk(KERN_WARNING "%s %s: dma still active\n",
984 __FILE__, __func__);
985 dma_off = 1;
986 }
987}
988
989/*
990 * Sets up TUSB6010 CPU interface specific signals and registers
991 * Note: Settings optimized for OMAP24xx
992 */
993static void tusb_setup_cpu_interface(struct musb *musb)
994{
995 void __iomem *tbase = musb->ctrl_base;
996
997 /*
998 * Disable GPIO[5:0] pullups (used as output DMA requests)
999 * Don't disable GPIO[7:6] as they are needed for wake-up.
1000 */
1001 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1002
1003 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1004 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1005
1006 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1007 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1008
1009 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1010 * de-assertion time 2 system clocks p 62 */
1011 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1012 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1013 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1014 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1015
1016 /* Set 0 wait count for synchronous burst access */
1017 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1018}
1019
1020static int tusb_musb_start(struct musb *musb)
1021{
1022 void __iomem *tbase = musb->ctrl_base;
1023 int ret = 0;
1024 unsigned long flags;
1025 u32 reg;
1026
1027 if (musb->board_set_power)
1028 ret = musb->board_set_power(1);
1029 if (ret != 0) {
1030 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1031 return ret;
1032 }
1033
1034 spin_lock_irqsave(&musb->lock, flags);
1035
1036 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1037 TUSB_PROD_TEST_RESET_VAL) {
1038 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1039 goto err;
1040 }
1041
1042 musb->tusb_revision = tusb_get_revision(musb);
1043 tusb_print_revision(musb);
1044 if (musb->tusb_revision < 2) {
1045 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1046 musb->tusb_revision);
1047 goto err;
1048 }
1049
1050 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1051 * NOR FLASH interface is used */
1052 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1053
1054 /* Select PHY free running 60MHz as a system clock */
1055 tusb_set_clock_source(musb, 1);
1056
1057 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1058 * power saving, enable VBus detect and session end comparators,
1059 * enable IDpullup, enable VBus charging */
1060 musb_writel(tbase, TUSB_PRCM_MNGMT,
1061 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1062 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1063 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1064 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1065 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1066 tusb_setup_cpu_interface(musb);
1067
1068 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1069 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1070 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1071 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1072
1073 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1074 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1075 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1076
1077 spin_unlock_irqrestore(&musb->lock, flags);
1078
1079 return 0;
1080
1081err:
1082 spin_unlock_irqrestore(&musb->lock, flags);
1083
1084 if (musb->board_set_power)
1085 musb->board_set_power(0);
1086
1087 return -ENODEV;
1088}
1089
1090static int tusb_musb_init(struct musb *musb)
1091{
1092 struct platform_device *pdev;
1093 struct resource *mem;
1094 void __iomem *sync = NULL;
1095 int ret;
1096
1097 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1098 if (IS_ERR_OR_NULL(musb->xceiv))
1099 return -EPROBE_DEFER;
1100
1101 pdev = to_platform_device(musb->controller);
1102
1103 /* dma address for async dma */
1104 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105 musb->async = mem->start;
1106
1107 /* dma address for sync dma */
1108 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1109 if (!mem) {
1110 pr_debug("no sync dma resource?\n");
1111 ret = -ENODEV;
1112 goto done;
1113 }
1114 musb->sync = mem->start;
1115
1116 sync = ioremap(mem->start, resource_size(mem));
1117 if (!sync) {
1118 pr_debug("ioremap for sync failed\n");
1119 ret = -ENOMEM;
1120 goto done;
1121 }
1122 musb->sync_va = sync;
1123
1124 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1125 * FIFOs at 0x600, TUSB at 0x800
1126 */
1127 musb->mregs += TUSB_BASE_OFFSET;
1128
1129 ret = tusb_musb_start(musb);
1130 if (ret) {
1131 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1132 ret);
1133 goto done;
1134 }
1135 musb->isr = tusb_musb_interrupt;
1136
1137 musb->xceiv->set_power = tusb_draw_power;
1138 the_musb = musb;
1139
1140 timer_setup(&musb->dev_timer, musb_do_idle, 0);
1141
1142done:
1143 if (ret < 0) {
1144 if (sync)
1145 iounmap(sync);
1146
1147 usb_put_phy(musb->xceiv);
1148 }
1149 return ret;
1150}
1151
1152static int tusb_musb_exit(struct musb *musb)
1153{
1154 del_timer_sync(&musb->dev_timer);
1155 the_musb = NULL;
1156
1157 if (musb->board_set_power)
1158 musb->board_set_power(0);
1159
1160 iounmap(musb->sync_va);
1161
1162 usb_put_phy(musb->xceiv);
1163 return 0;
1164}
1165
1166static const struct musb_platform_ops tusb_ops = {
1167 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB |
1168 MUSB_G_NO_SKB_RESERVE,
1169 .init = tusb_musb_init,
1170 .exit = tusb_musb_exit,
1171
1172 .ep_offset = tusb_ep_offset,
1173 .ep_select = tusb_ep_select,
1174 .fifo_offset = tusb_fifo_offset,
1175 .readb = tusb_readb,
1176 .writeb = tusb_writeb,
1177 .read_fifo = tusb_read_fifo,
1178 .write_fifo = tusb_write_fifo,
1179#ifdef CONFIG_USB_TUSB_OMAP_DMA
1180 .dma_init = tusb_dma_controller_create,
1181 .dma_exit = tusb_dma_controller_destroy,
1182#endif
1183 .enable = tusb_musb_enable,
1184 .disable = tusb_musb_disable,
1185
1186 .set_mode = tusb_musb_set_mode,
1187 .try_idle = tusb_musb_try_idle,
1188
1189 .vbus_status = tusb_musb_vbus_status,
1190 .set_vbus = tusb_musb_set_vbus,
1191};
1192
1193static const struct platform_device_info tusb_dev_info = {
1194 .name = "musb-hdrc",
1195 .id = PLATFORM_DEVID_AUTO,
1196 .dma_mask = DMA_BIT_MASK(32),
1197};
1198
1199static int tusb_probe(struct platform_device *pdev)
1200{
1201 struct resource musb_resources[3];
1202 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1203 struct platform_device *musb;
1204 struct tusb6010_glue *glue;
1205 struct platform_device_info pinfo;
1206 int ret;
1207
1208 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1209 if (!glue)
1210 return -ENOMEM;
1211
1212 glue->dev = &pdev->dev;
1213
1214 pdata->platform_ops = &tusb_ops;
1215
1216 usb_phy_generic_register();
1217 platform_set_drvdata(pdev, glue);
1218
1219 memset(musb_resources, 0x00, sizeof(*musb_resources) *
1220 ARRAY_SIZE(musb_resources));
1221
1222 musb_resources[0].name = pdev->resource[0].name;
1223 musb_resources[0].start = pdev->resource[0].start;
1224 musb_resources[0].end = pdev->resource[0].end;
1225 musb_resources[0].flags = pdev->resource[0].flags;
1226
1227 musb_resources[1].name = pdev->resource[1].name;
1228 musb_resources[1].start = pdev->resource[1].start;
1229 musb_resources[1].end = pdev->resource[1].end;
1230 musb_resources[1].flags = pdev->resource[1].flags;
1231
1232 musb_resources[2].name = pdev->resource[2].name;
1233 musb_resources[2].start = pdev->resource[2].start;
1234 musb_resources[2].end = pdev->resource[2].end;
1235 musb_resources[2].flags = pdev->resource[2].flags;
1236
1237 pinfo = tusb_dev_info;
1238 pinfo.parent = &pdev->dev;
1239 pinfo.res = musb_resources;
1240 pinfo.num_res = ARRAY_SIZE(musb_resources);
1241 pinfo.data = pdata;
1242 pinfo.size_data = sizeof(*pdata);
1243
1244 glue->musb = musb = platform_device_register_full(&pinfo);
1245 if (IS_ERR(musb)) {
1246 ret = PTR_ERR(musb);
1247 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1248 return ret;
1249 }
1250
1251 return 0;
1252}
1253
1254static int tusb_remove(struct platform_device *pdev)
1255{
1256 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1257
1258 platform_device_unregister(glue->musb);
1259 usb_phy_generic_unregister(glue->phy);
1260
1261 return 0;
1262}
1263
1264static struct platform_driver tusb_driver = {
1265 .probe = tusb_probe,
1266 .remove = tusb_remove,
1267 .driver = {
1268 .name = "musb-tusb",
1269 },
1270};
1271
1272MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1273MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1274MODULE_LICENSE("GPL v2");
1275module_platform_driver(tusb_driver);