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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dma-resv.h>
28#include <linux/i2c.h>
29#include <linux/input.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <drm/display/drm_dp_helper.h>
36#include <drm/display/drm_dp_tunnel.h>
37#include <drm/drm_atomic.h>
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_atomic_uapi.h>
40#include <drm/drm_damage_helper.h>
41#include <drm/drm_edid.h>
42#include <drm/drm_fixed.h>
43#include <drm/drm_fourcc.h>
44#include <drm/drm_probe_helper.h>
45#include <drm/drm_rect.h>
46#include <drm/drm_vblank.h>
47
48#include "g4x_dp.h"
49#include "g4x_hdmi.h"
50#include "hsw_ips.h"
51#include "i915_config.h"
52#include "i915_drv.h"
53#include "i915_reg.h"
54#include "i915_utils.h"
55#include "i9xx_plane.h"
56#include "i9xx_plane_regs.h"
57#include "i9xx_wm.h"
58#include "intel_atomic.h"
59#include "intel_atomic_plane.h"
60#include "intel_audio.h"
61#include "intel_bo.h"
62#include "intel_bw.h"
63#include "intel_cdclk.h"
64#include "intel_clock_gating.h"
65#include "intel_color.h"
66#include "intel_crt.h"
67#include "intel_crtc.h"
68#include "intel_crtc_state_dump.h"
69#include "intel_cursor_regs.h"
70#include "intel_cx0_phy.h"
71#include "intel_cursor.h"
72#include "intel_ddi.h"
73#include "intel_de.h"
74#include "intel_display_driver.h"
75#include "intel_display_power.h"
76#include "intel_display_types.h"
77#include "intel_dmc.h"
78#include "intel_dp.h"
79#include "intel_dp_link_training.h"
80#include "intel_dp_mst.h"
81#include "intel_dp_tunnel.h"
82#include "intel_dpll.h"
83#include "intel_dpll_mgr.h"
84#include "intel_dpt.h"
85#include "intel_dpt_common.h"
86#include "intel_drrs.h"
87#include "intel_dsb.h"
88#include "intel_dsi.h"
89#include "intel_dvo.h"
90#include "intel_fb.h"
91#include "intel_fbc.h"
92#include "intel_fdi.h"
93#include "intel_fifo_underrun.h"
94#include "intel_frontbuffer.h"
95#include "intel_hdmi.h"
96#include "intel_hotplug.h"
97#include "intel_link_bw.h"
98#include "intel_lvds.h"
99#include "intel_lvds_regs.h"
100#include "intel_modeset_setup.h"
101#include "intel_modeset_verify.h"
102#include "intel_overlay.h"
103#include "intel_panel.h"
104#include "intel_pch_display.h"
105#include "intel_pch_refclk.h"
106#include "intel_pcode.h"
107#include "intel_pipe_crc.h"
108#include "intel_plane_initial.h"
109#include "intel_pmdemand.h"
110#include "intel_pps.h"
111#include "intel_psr.h"
112#include "intel_psr_regs.h"
113#include "intel_sdvo.h"
114#include "intel_snps_phy.h"
115#include "intel_tc.h"
116#include "intel_tdf.h"
117#include "intel_tv.h"
118#include "intel_vblank.h"
119#include "intel_vdsc.h"
120#include "intel_vdsc_regs.h"
121#include "intel_vga.h"
122#include "intel_vrr.h"
123#include "intel_wm.h"
124#include "skl_scaler.h"
125#include "skl_universal_plane.h"
126#include "skl_universal_plane_regs.h"
127#include "skl_watermark.h"
128#include "vlv_dpio_phy_regs.h"
129#include "vlv_dsi.h"
130#include "vlv_dsi_pll.h"
131#include "vlv_dsi_regs.h"
132#include "vlv_sideband.h"
133
134static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
135static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
136static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
137static void bdw_set_pipe_misc(struct intel_dsb *dsb,
138 const struct intel_crtc_state *crtc_state);
139
140/* returns HPLL frequency in kHz */
141int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
142{
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148
149 return vco_freq[hpll_freq] * 1000;
150}
151
152int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154{
155 u32 val;
156 int divider;
157
158 val = vlv_cck_read(dev_priv, reg);
159 divider = val & CCK_FREQUENCY_VALUES;
160
161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
162 (divider << CCK_FREQUENCY_STATUS_SHIFT),
163 "%s change in progress\n", name);
164
165 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
166}
167
168int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
169 const char *name, u32 reg)
170{
171 int hpll;
172
173 vlv_cck_get(dev_priv);
174
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
177
178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
179
180 vlv_cck_put(dev_priv);
181
182 return hpll;
183}
184
185void intel_update_czclk(struct drm_i915_private *dev_priv)
186{
187 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
188 return;
189
190 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
191 CCK_CZ_CLOCK_CONTROL);
192
193 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
194 dev_priv->czclk_freq);
195}
196
197static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
198{
199 return (crtc_state->active_planes &
200 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
201}
202
203/* WA Display #0827: Gen9:all */
204static void
205skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
206{
207 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
208 DUPS1_GATING_DIS | DUPS2_GATING_DIS,
209 enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
210}
211
212/* Wa_2006604312:icl,ehl */
213static void
214icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
215 bool enable)
216{
217 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
218 DPFR_GATING_DIS,
219 enable ? DPFR_GATING_DIS : 0);
220}
221
222/* Wa_1604331009:icl,jsl,ehl */
223static void
224icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
225 bool enable)
226{
227 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
228 CURSOR_GATING_DIS,
229 enable ? CURSOR_GATING_DIS : 0);
230}
231
232static bool
233is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
234{
235 return crtc_state->master_transcoder != INVALID_TRANSCODER;
236}
237
238bool
239is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
240{
241 return crtc_state->sync_mode_slaves_mask != 0;
242}
243
244bool
245is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
246{
247 return is_trans_port_sync_master(crtc_state) ||
248 is_trans_port_sync_slave(crtc_state);
249}
250
251static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
252{
253 return ffs(crtc_state->joiner_pipes) - 1;
254}
255
256/*
257 * The following helper functions, despite being named for bigjoiner,
258 * are applicable to both bigjoiner and uncompressed joiner configurations.
259 */
260static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
261{
262 return hweight8(crtc_state->joiner_pipes) >= 2;
263}
264
265static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
266{
267 if (!is_bigjoiner(crtc_state))
268 return 0;
269
270 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));
271}
272
273static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
274{
275 if (!is_bigjoiner(crtc_state))
276 return 0;
277
278 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));
279}
280
281bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
282{
283 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
284
285 if (!is_bigjoiner(crtc_state))
286 return false;
287
288 return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
289}
290
291bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
292{
293 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
294
295 if (!is_bigjoiner(crtc_state))
296 return false;
297
298 return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
299}
300
301u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)
302{
303 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
304
305 if (!is_bigjoiner(crtc_state))
306 return BIT(crtc->pipe);
307
308 return bigjoiner_primary_pipes(crtc_state);
309}
310
311u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)
312{
313 return bigjoiner_secondary_pipes(crtc_state);
314}
315
316bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
317{
318 return intel_crtc_num_joined_pipes(crtc_state) >= 4;
319}
320
321static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
322{
323 if (!intel_crtc_is_ultrajoiner(crtc_state))
324 return 0;
325
326 return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));
327}
328
329bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
330{
331 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
332
333 return intel_crtc_is_ultrajoiner(crtc_state) &&
334 BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
335}
336
337/*
338 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or
339 * any other logic, so lets just add helper function to
340 * at least hide this hassle..
341 */
342static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)
343{
344 if (!intel_crtc_is_ultrajoiner(crtc_state))
345 return 0;
346
347 return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));
348}
349
350bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
351{
352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
353
354 return intel_crtc_is_ultrajoiner(crtc_state) &&
355 BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
356}
357
358u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
359{
360 if (crtc_state->joiner_pipes)
361 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
362 else
363 return 0;
364}
365
366bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
367{
368 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
369
370 return crtc_state->joiner_pipes &&
371 crtc->pipe != joiner_primary_pipe(crtc_state);
372}
373
374bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
375{
376 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
377
378 return crtc_state->joiner_pipes &&
379 crtc->pipe == joiner_primary_pipe(crtc_state);
380}
381
382int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)
383{
384 return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
385}
386
387u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
388{
389 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
390
391 return BIT(crtc->pipe) | crtc_state->joiner_pipes;
392}
393
394struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
395{
396 struct intel_display *display = to_intel_display(crtc_state);
397
398 if (intel_crtc_is_joiner_secondary(crtc_state))
399 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));
400 else
401 return to_intel_crtc(crtc_state->uapi.crtc);
402}
403
404static void
405intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
406{
407 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
408 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
409
410 if (DISPLAY_VER(dev_priv) >= 4) {
411 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
412
413 /* Wait for the Pipe State to go off */
414 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
415 TRANSCONF_STATE_ENABLE, 100))
416 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
417 } else {
418 intel_wait_for_pipe_scanline_stopped(crtc);
419 }
420}
421
422void assert_transcoder(struct drm_i915_private *dev_priv,
423 enum transcoder cpu_transcoder, bool state)
424{
425 struct intel_display *display = &dev_priv->display;
426 bool cur_state;
427 enum intel_display_power_domain power_domain;
428 intel_wakeref_t wakeref;
429
430 /* we keep both pipes enabled on 830 */
431 if (IS_I830(dev_priv))
432 state = true;
433
434 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
435 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
436 if (wakeref) {
437 u32 val = intel_de_read(dev_priv,
438 TRANSCONF(dev_priv, cpu_transcoder));
439 cur_state = !!(val & TRANSCONF_ENABLE);
440
441 intel_display_power_put(dev_priv, power_domain, wakeref);
442 } else {
443 cur_state = false;
444 }
445
446 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
447 "transcoder %s assertion failure (expected %s, current %s)\n",
448 transcoder_name(cpu_transcoder), str_on_off(state),
449 str_on_off(cur_state));
450}
451
452static void assert_plane(struct intel_plane *plane, bool state)
453{
454 struct intel_display *display = to_intel_display(plane->base.dev);
455 enum pipe pipe;
456 bool cur_state;
457
458 cur_state = plane->get_hw_state(plane, &pipe);
459
460 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
461 "%s assertion failure (expected %s, current %s)\n",
462 plane->base.name, str_on_off(state),
463 str_on_off(cur_state));
464}
465
466#define assert_plane_enabled(p) assert_plane(p, true)
467#define assert_plane_disabled(p) assert_plane(p, false)
468
469static void assert_planes_disabled(struct intel_crtc *crtc)
470{
471 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
472 struct intel_plane *plane;
473
474 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
475 assert_plane_disabled(plane);
476}
477
478void vlv_wait_port_ready(struct intel_display *display,
479 struct intel_digital_port *dig_port,
480 unsigned int expected_mask)
481{
482 u32 port_mask;
483 i915_reg_t dpll_reg;
484
485 switch (dig_port->base.port) {
486 default:
487 MISSING_CASE(dig_port->base.port);
488 fallthrough;
489 case PORT_B:
490 port_mask = DPLL_PORTB_READY_MASK;
491 dpll_reg = DPLL(display, 0);
492 break;
493 case PORT_C:
494 port_mask = DPLL_PORTC_READY_MASK;
495 dpll_reg = DPLL(display, 0);
496 expected_mask <<= 4;
497 break;
498 case PORT_D:
499 port_mask = DPLL_PORTD_READY_MASK;
500 dpll_reg = DPIO_PHY_STATUS;
501 break;
502 }
503
504 if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
505 drm_WARN(display->drm, 1,
506 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
507 dig_port->base.base.base.id, dig_port->base.base.name,
508 intel_de_read(display, dpll_reg) & port_mask,
509 expected_mask);
510}
511
512void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
513{
514 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
516 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
517 enum pipe pipe = crtc->pipe;
518 u32 val;
519
520 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
521
522 assert_planes_disabled(crtc);
523
524 /*
525 * A pipe without a PLL won't actually be able to drive bits from
526 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
527 * need the check.
528 */
529 if (HAS_GMCH(dev_priv)) {
530 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
531 assert_dsi_pll_enabled(dev_priv);
532 else
533 assert_pll_enabled(dev_priv, pipe);
534 } else {
535 if (new_crtc_state->has_pch_encoder) {
536 /* if driving the PCH, we need FDI enabled */
537 assert_fdi_rx_pll_enabled(dev_priv,
538 intel_crtc_pch_transcoder(crtc));
539 assert_fdi_tx_pll_enabled(dev_priv,
540 (enum pipe) cpu_transcoder);
541 }
542 /* FIXME: assert CPU port conditions for SNB+ */
543 }
544
545 /* Wa_22012358565:adl-p */
546 if (DISPLAY_VER(dev_priv) == 13)
547 intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
548 0, PIPE_ARB_USE_PROG_SLOTS);
549
550 if (DISPLAY_VER(dev_priv) >= 14) {
551 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
552 u32 set = 0;
553
554 if (DISPLAY_VER(dev_priv) == 14)
555 set |= DP_FEC_BS_JITTER_WA;
556
557 intel_de_rmw(dev_priv,
558 hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
559 clear, set);
560 }
561
562 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
563 if (val & TRANSCONF_ENABLE) {
564 /* we keep both pipes enabled on 830 */
565 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
566 return;
567 }
568
569 /* Wa_1409098942:adlp+ */
570 if (DISPLAY_VER(dev_priv) >= 13 &&
571 new_crtc_state->dsc.compression_enable) {
572 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
573 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
574 TRANSCONF_PIXEL_COUNT_SCALING_X4);
575 }
576
577 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
578 val | TRANSCONF_ENABLE);
579 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
580
581 /*
582 * Until the pipe starts PIPEDSL reads will return a stale value,
583 * which causes an apparent vblank timestamp jump when PIPEDSL
584 * resets to its proper value. That also messes up the frame count
585 * when it's derived from the timestamps. So let's wait for the
586 * pipe to start properly before we call drm_crtc_vblank_on()
587 */
588 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
589 intel_wait_for_pipe_scanline_moving(crtc);
590}
591
592void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
593{
594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
595 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
596 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
597 enum pipe pipe = crtc->pipe;
598 u32 val;
599
600 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
601
602 /*
603 * Make sure planes won't keep trying to pump pixels to us,
604 * or we might hang the display.
605 */
606 assert_planes_disabled(crtc);
607
608 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
609 if ((val & TRANSCONF_ENABLE) == 0)
610 return;
611
612 /*
613 * Double wide has implications for planes
614 * so best keep it disabled when not needed.
615 */
616 if (old_crtc_state->double_wide)
617 val &= ~TRANSCONF_DOUBLE_WIDE;
618
619 /* Don't disable pipe or pipe PLLs if needed */
620 if (!IS_I830(dev_priv))
621 val &= ~TRANSCONF_ENABLE;
622
623 /* Wa_1409098942:adlp+ */
624 if (DISPLAY_VER(dev_priv) >= 13 &&
625 old_crtc_state->dsc.compression_enable)
626 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
627
628 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
629
630 if (DISPLAY_VER(dev_priv) >= 12)
631 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
632 FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
633
634 if ((val & TRANSCONF_ENABLE) == 0)
635 intel_wait_for_pipe_off(old_crtc_state);
636}
637
638unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
639{
640 unsigned int size = 0;
641 int i;
642
643 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
644 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
645
646 return size;
647}
648
649unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
650{
651 unsigned int size = 0;
652 int i;
653
654 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
655 unsigned int plane_size;
656
657 if (rem_info->plane[i].linear)
658 plane_size = rem_info->plane[i].size;
659 else
660 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
661
662 if (plane_size == 0)
663 continue;
664
665 if (rem_info->plane_alignment)
666 size = ALIGN(size, rem_info->plane_alignment);
667
668 size += plane_size;
669 }
670
671 return size;
672}
673
674bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
675{
676 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
677 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
678
679 return DISPLAY_VER(dev_priv) < 4 ||
680 (plane->fbc && !plane_state->no_fbc_reason &&
681 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
682}
683
684/*
685 * Convert the x/y offsets into a linear offset.
686 * Only valid with 0/180 degree rotation, which is fine since linear
687 * offset is only used with linear buffers on pre-hsw and tiled buffers
688 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
689 */
690u32 intel_fb_xy_to_linear(int x, int y,
691 const struct intel_plane_state *state,
692 int color_plane)
693{
694 const struct drm_framebuffer *fb = state->hw.fb;
695 unsigned int cpp = fb->format->cpp[color_plane];
696 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
697
698 return y * pitch + x * cpp;
699}
700
701/*
702 * Add the x/y offsets derived from fb->offsets[] to the user
703 * specified plane src x/y offsets. The resulting x/y offsets
704 * specify the start of scanout from the beginning of the gtt mapping.
705 */
706void intel_add_fb_offsets(int *x, int *y,
707 const struct intel_plane_state *state,
708 int color_plane)
709
710{
711 *x += state->view.color_plane[color_plane].x;
712 *y += state->view.color_plane[color_plane].y;
713}
714
715u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
716 u32 pixel_format, u64 modifier)
717{
718 struct intel_crtc *crtc;
719 struct intel_plane *plane;
720
721 if (!HAS_DISPLAY(dev_priv))
722 return 0;
723
724 /*
725 * We assume the primary plane for pipe A has
726 * the highest stride limits of them all,
727 * if in case pipe A is disabled, use the first pipe from pipe_mask.
728 */
729 crtc = intel_first_crtc(dev_priv);
730 if (!crtc)
731 return 0;
732
733 plane = to_intel_plane(crtc->base.primary);
734
735 return plane->max_stride(plane, pixel_format, modifier,
736 DRM_MODE_ROTATE_0);
737}
738
739void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
740 struct intel_plane_state *plane_state,
741 bool visible)
742{
743 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
744
745 plane_state->uapi.visible = visible;
746
747 if (visible)
748 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
749 else
750 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
751}
752
753void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
754{
755 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
756 struct drm_plane *plane;
757
758 /*
759 * Active_planes aliases if multiple "primary" or cursor planes
760 * have been used on the same (or wrong) pipe. plane_mask uses
761 * unique ids, hence we can use that to reconstruct active_planes.
762 */
763 crtc_state->enabled_planes = 0;
764 crtc_state->active_planes = 0;
765
766 drm_for_each_plane_mask(plane, &dev_priv->drm,
767 crtc_state->uapi.plane_mask) {
768 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
769 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
770 }
771}
772
773void intel_plane_disable_noatomic(struct intel_crtc *crtc,
774 struct intel_plane *plane)
775{
776 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
777 struct intel_crtc_state *crtc_state =
778 to_intel_crtc_state(crtc->base.state);
779 struct intel_plane_state *plane_state =
780 to_intel_plane_state(plane->base.state);
781
782 drm_dbg_kms(&dev_priv->drm,
783 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
784 plane->base.base.id, plane->base.name,
785 crtc->base.base.id, crtc->base.name);
786
787 intel_set_plane_visible(crtc_state, plane_state, false);
788 intel_plane_fixup_bitmasks(crtc_state);
789 crtc_state->data_rate[plane->id] = 0;
790 crtc_state->data_rate_y[plane->id] = 0;
791 crtc_state->rel_data_rate[plane->id] = 0;
792 crtc_state->rel_data_rate_y[plane->id] = 0;
793 crtc_state->min_cdclk[plane->id] = 0;
794
795 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
796 hsw_ips_disable(crtc_state)) {
797 crtc_state->ips_enabled = false;
798 intel_crtc_wait_for_next_vblank(crtc);
799 }
800
801 /*
802 * Vblank time updates from the shadow to live plane control register
803 * are blocked if the memory self-refresh mode is active at that
804 * moment. So to make sure the plane gets truly disabled, disable
805 * first the self-refresh mode. The self-refresh enable bit in turn
806 * will be checked/applied by the HW only at the next frame start
807 * event which is after the vblank start event, so we need to have a
808 * wait-for-vblank between disabling the plane and the pipe.
809 */
810 if (HAS_GMCH(dev_priv) &&
811 intel_set_memory_cxsr(dev_priv, false))
812 intel_crtc_wait_for_next_vblank(crtc);
813
814 /*
815 * Gen2 reports pipe underruns whenever all planes are disabled.
816 * So disable underrun reporting before all the planes get disabled.
817 */
818 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
819 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
820
821 intel_plane_disable_arm(NULL, plane, crtc_state);
822 intel_crtc_wait_for_next_vblank(crtc);
823}
824
825unsigned int
826intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
827{
828 int x = 0, y = 0;
829
830 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
831 plane_state->view.color_plane[0].offset, 0);
832
833 return y;
834}
835
836static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
837{
838 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
839 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
840 enum pipe pipe = crtc->pipe;
841 u32 tmp;
842
843 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
844
845 /*
846 * Display WA #1153: icl
847 * enable hardware to bypass the alpha math
848 * and rounding for per-pixel values 00 and 0xff
849 */
850 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
851 /*
852 * Display WA # 1605353570: icl
853 * Set the pixel rounding bit to 1 for allowing
854 * passthrough of Frame buffer pixels unmodified
855 * across pipe
856 */
857 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
858
859 /*
860 * Underrun recovery must always be disabled on display 13+.
861 * DG2 chicken bit meaning is inverted compared to other platforms.
862 */
863 if (IS_DG2(dev_priv))
864 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
865 else if ((DISPLAY_VER(dev_priv) >= 13) && (DISPLAY_VER(dev_priv) < 30))
866 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
867
868 /* Wa_14010547955:dg2 */
869 if (IS_DG2(dev_priv))
870 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
871
872 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
873}
874
875bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
876{
877 struct drm_crtc *crtc;
878 bool cleanup_done;
879
880 drm_for_each_crtc(crtc, &dev_priv->drm) {
881 struct drm_crtc_commit *commit;
882 spin_lock(&crtc->commit_lock);
883 commit = list_first_entry_or_null(&crtc->commit_list,
884 struct drm_crtc_commit, commit_entry);
885 cleanup_done = commit ?
886 try_wait_for_completion(&commit->cleanup_done) : true;
887 spin_unlock(&crtc->commit_lock);
888
889 if (cleanup_done)
890 continue;
891
892 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
893
894 return true;
895 }
896
897 return false;
898}
899
900/*
901 * Finds the encoder associated with the given CRTC. This can only be
902 * used when we know that the CRTC isn't feeding multiple encoders!
903 */
904struct intel_encoder *
905intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
906 const struct intel_crtc_state *crtc_state)
907{
908 const struct drm_connector_state *connector_state;
909 const struct drm_connector *connector;
910 struct intel_encoder *encoder = NULL;
911 struct intel_crtc *primary_crtc;
912 int num_encoders = 0;
913 int i;
914
915 primary_crtc = intel_primary_crtc(crtc_state);
916
917 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
918 if (connector_state->crtc != &primary_crtc->base)
919 continue;
920
921 encoder = to_intel_encoder(connector_state->best_encoder);
922 num_encoders++;
923 }
924
925 drm_WARN(state->base.dev, num_encoders != 1,
926 "%d encoders for pipe %c\n",
927 num_encoders, pipe_name(primary_crtc->pipe));
928
929 return encoder;
930}
931
932static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
933{
934 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
936 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
937 enum pipe pipe = crtc->pipe;
938 int width = drm_rect_width(dst);
939 int height = drm_rect_height(dst);
940 int x = dst->x1;
941 int y = dst->y1;
942
943 if (!crtc_state->pch_pfit.enabled)
944 return;
945
946 /* Force use of hard-coded filter coefficients
947 * as some pre-programmed values are broken,
948 * e.g. x201.
949 */
950 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
951 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
952 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
953 else
954 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
955 PF_FILTER_MED_3x3);
956 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
957 PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
958 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
959 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
960}
961
962static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
963{
964 if (crtc->overlay)
965 (void) intel_overlay_switch_off(crtc->overlay);
966
967 /* Let userspace switch the overlay on again. In most cases userspace
968 * has to recompute where to put it anyway.
969 */
970}
971
972static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
973{
974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
975
976 if (!crtc_state->nv12_planes)
977 return false;
978
979 /* WA Display #0827: Gen9:all */
980 if (DISPLAY_VER(dev_priv) == 9)
981 return true;
982
983 return false;
984}
985
986static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
987{
988 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
989
990 /* Wa_2006604312:icl,ehl */
991 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
992 return true;
993
994 return false;
995}
996
997static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
998{
999 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1000
1001 /* Wa_1604331009:icl,jsl,ehl */
1002 if (is_hdr_mode(crtc_state) &&
1003 crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1004 DISPLAY_VER(dev_priv) == 11)
1005 return true;
1006
1007 return false;
1008}
1009
1010static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1011 enum pipe pipe, bool enable)
1012{
1013 if (DISPLAY_VER(i915) == 9) {
1014 /*
1015 * "Plane N strech max must be programmed to 11b (x1)
1016 * when Async flips are enabled on that plane."
1017 */
1018 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1019 SKL_PLANE1_STRETCH_MAX_MASK,
1020 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1021 } else {
1022 /* Also needed on HSW/BDW albeit undocumented */
1023 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1024 HSW_PRI_STRETCH_MAX_MASK,
1025 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1026 }
1027}
1028
1029static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1030{
1031 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1032
1033 return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1034 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1035}
1036
1037static void intel_encoders_audio_enable(struct intel_atomic_state *state,
1038 struct intel_crtc *crtc)
1039{
1040 const struct intel_crtc_state *crtc_state =
1041 intel_atomic_get_new_crtc_state(state, crtc);
1042 const struct drm_connector_state *conn_state;
1043 struct drm_connector *conn;
1044 int i;
1045
1046 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1047 struct intel_encoder *encoder =
1048 to_intel_encoder(conn_state->best_encoder);
1049
1050 if (conn_state->crtc != &crtc->base)
1051 continue;
1052
1053 if (encoder->audio_enable)
1054 encoder->audio_enable(encoder, crtc_state, conn_state);
1055 }
1056}
1057
1058static void intel_encoders_audio_disable(struct intel_atomic_state *state,
1059 struct intel_crtc *crtc)
1060{
1061 const struct intel_crtc_state *old_crtc_state =
1062 intel_atomic_get_old_crtc_state(state, crtc);
1063 const struct drm_connector_state *old_conn_state;
1064 struct drm_connector *conn;
1065 int i;
1066
1067 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1068 struct intel_encoder *encoder =
1069 to_intel_encoder(old_conn_state->best_encoder);
1070
1071 if (old_conn_state->crtc != &crtc->base)
1072 continue;
1073
1074 if (encoder->audio_disable)
1075 encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
1076 }
1077}
1078
1079#define is_enabling(feature, old_crtc_state, new_crtc_state) \
1080 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
1081 (new_crtc_state)->feature)
1082#define is_disabling(feature, old_crtc_state, new_crtc_state) \
1083 ((old_crtc_state)->feature && \
1084 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
1085
1086static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1087 const struct intel_crtc_state *new_crtc_state)
1088{
1089 if (!new_crtc_state->hw.active)
1090 return false;
1091
1092 return is_enabling(active_planes, old_crtc_state, new_crtc_state);
1093}
1094
1095static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1096 const struct intel_crtc_state *new_crtc_state)
1097{
1098 if (!old_crtc_state->hw.active)
1099 return false;
1100
1101 return is_disabling(active_planes, old_crtc_state, new_crtc_state);
1102}
1103
1104static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
1105 const struct intel_crtc_state *new_crtc_state)
1106{
1107 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
1108 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
1109 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
1110 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
1111 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
1112}
1113
1114static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
1115 const struct intel_crtc_state *new_crtc_state)
1116{
1117 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
1118 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
1119}
1120
1121static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
1122 struct intel_crtc *crtc)
1123{
1124 const struct intel_crtc_state *old_crtc_state =
1125 intel_atomic_get_old_crtc_state(state, crtc);
1126 const struct intel_crtc_state *new_crtc_state =
1127 intel_atomic_get_new_crtc_state(state, crtc);
1128
1129 if (!new_crtc_state->hw.active)
1130 return false;
1131
1132 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1133 (new_crtc_state->vrr.enable &&
1134 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1135 vrr_params_changed(old_crtc_state, new_crtc_state)));
1136}
1137
1138bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
1139 struct intel_crtc *crtc)
1140{
1141 const struct intel_crtc_state *old_crtc_state =
1142 intel_atomic_get_old_crtc_state(state, crtc);
1143 const struct intel_crtc_state *new_crtc_state =
1144 intel_atomic_get_new_crtc_state(state, crtc);
1145
1146 if (!old_crtc_state->hw.active)
1147 return false;
1148
1149 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1150 (old_crtc_state->vrr.enable &&
1151 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1152 vrr_params_changed(old_crtc_state, new_crtc_state)));
1153}
1154
1155static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
1156 const struct intel_crtc_state *new_crtc_state)
1157{
1158 if (!new_crtc_state->hw.active)
1159 return false;
1160
1161 return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
1162 (new_crtc_state->has_audio &&
1163 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1164}
1165
1166static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
1167 const struct intel_crtc_state *new_crtc_state)
1168{
1169 if (!old_crtc_state->hw.active)
1170 return false;
1171
1172 return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
1173 (old_crtc_state->has_audio &&
1174 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1175}
1176
1177#undef is_disabling
1178#undef is_enabling
1179
1180static void intel_post_plane_update(struct intel_atomic_state *state,
1181 struct intel_crtc *crtc)
1182{
1183 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1184 const struct intel_crtc_state *old_crtc_state =
1185 intel_atomic_get_old_crtc_state(state, crtc);
1186 const struct intel_crtc_state *new_crtc_state =
1187 intel_atomic_get_new_crtc_state(state, crtc);
1188 enum pipe pipe = crtc->pipe;
1189
1190 intel_psr_post_plane_update(state, crtc);
1191
1192 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1193
1194 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1195 intel_update_watermarks(dev_priv);
1196
1197 intel_fbc_post_update(state, crtc);
1198
1199 if (needs_async_flip_vtd_wa(old_crtc_state) &&
1200 !needs_async_flip_vtd_wa(new_crtc_state))
1201 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1202
1203 if (needs_nv12_wa(old_crtc_state) &&
1204 !needs_nv12_wa(new_crtc_state))
1205 skl_wa_827(dev_priv, pipe, false);
1206
1207 if (needs_scalerclk_wa(old_crtc_state) &&
1208 !needs_scalerclk_wa(new_crtc_state))
1209 icl_wa_scalerclkgating(dev_priv, pipe, false);
1210
1211 if (needs_cursorclk_wa(old_crtc_state) &&
1212 !needs_cursorclk_wa(new_crtc_state))
1213 icl_wa_cursorclkgating(dev_priv, pipe, false);
1214
1215 if (intel_crtc_needs_color_update(new_crtc_state))
1216 intel_color_post_update(new_crtc_state);
1217
1218 if (audio_enabling(old_crtc_state, new_crtc_state))
1219 intel_encoders_audio_enable(state, crtc);
1220}
1221
1222static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
1223 struct intel_crtc *crtc)
1224{
1225 const struct intel_crtc_state *new_crtc_state =
1226 intel_atomic_get_new_crtc_state(state, crtc);
1227
1228 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
1229 hsw_ips_post_update(state, crtc);
1230
1231 /*
1232 * Activate DRRS after state readout to avoid
1233 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
1234 */
1235 intel_drrs_activate(new_crtc_state);
1236}
1237
1238static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1239 struct intel_crtc *crtc)
1240{
1241 const struct intel_crtc_state *crtc_state =
1242 intel_atomic_get_new_crtc_state(state, crtc);
1243 u8 update_planes = crtc_state->update_planes;
1244 const struct intel_plane_state __maybe_unused *plane_state;
1245 struct intel_plane *plane;
1246 int i;
1247
1248 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1249 if (plane->pipe == crtc->pipe &&
1250 update_planes & BIT(plane->id))
1251 plane->enable_flip_done(plane);
1252 }
1253}
1254
1255static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1256 struct intel_crtc *crtc)
1257{
1258 const struct intel_crtc_state *crtc_state =
1259 intel_atomic_get_new_crtc_state(state, crtc);
1260 u8 update_planes = crtc_state->update_planes;
1261 const struct intel_plane_state __maybe_unused *plane_state;
1262 struct intel_plane *plane;
1263 int i;
1264
1265 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1266 if (plane->pipe == crtc->pipe &&
1267 update_planes & BIT(plane->id))
1268 plane->disable_flip_done(plane);
1269 }
1270}
1271
1272static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1273 struct intel_crtc *crtc)
1274{
1275 const struct intel_crtc_state *old_crtc_state =
1276 intel_atomic_get_old_crtc_state(state, crtc);
1277 const struct intel_crtc_state *new_crtc_state =
1278 intel_atomic_get_new_crtc_state(state, crtc);
1279 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1280 ~new_crtc_state->async_flip_planes;
1281 const struct intel_plane_state *old_plane_state;
1282 struct intel_plane *plane;
1283 bool need_vbl_wait = false;
1284 int i;
1285
1286 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1287 if (plane->need_async_flip_toggle_wa &&
1288 plane->pipe == crtc->pipe &&
1289 disable_async_flip_planes & BIT(plane->id)) {
1290 /*
1291 * Apart from the async flip bit we want to
1292 * preserve the old state for the plane.
1293 */
1294 intel_plane_async_flip(NULL, plane,
1295 old_crtc_state, old_plane_state, false);
1296 need_vbl_wait = true;
1297 }
1298 }
1299
1300 if (need_vbl_wait)
1301 intel_crtc_wait_for_next_vblank(crtc);
1302}
1303
1304static void intel_pre_plane_update(struct intel_atomic_state *state,
1305 struct intel_crtc *crtc)
1306{
1307 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1308 const struct intel_crtc_state *old_crtc_state =
1309 intel_atomic_get_old_crtc_state(state, crtc);
1310 const struct intel_crtc_state *new_crtc_state =
1311 intel_atomic_get_new_crtc_state(state, crtc);
1312 enum pipe pipe = crtc->pipe;
1313
1314 if (intel_crtc_vrr_disabling(state, crtc)) {
1315 intel_vrr_disable(old_crtc_state);
1316 intel_crtc_update_active_timings(old_crtc_state, false);
1317 }
1318
1319 if (audio_disabling(old_crtc_state, new_crtc_state))
1320 intel_encoders_audio_disable(state, crtc);
1321
1322 intel_drrs_deactivate(old_crtc_state);
1323
1324 intel_psr_pre_plane_update(state, crtc);
1325
1326 if (hsw_ips_pre_update(state, crtc))
1327 intel_crtc_wait_for_next_vblank(crtc);
1328
1329 if (intel_fbc_pre_update(state, crtc))
1330 intel_crtc_wait_for_next_vblank(crtc);
1331
1332 if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1333 needs_async_flip_vtd_wa(new_crtc_state))
1334 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1335
1336 /* Display WA 827 */
1337 if (!needs_nv12_wa(old_crtc_state) &&
1338 needs_nv12_wa(new_crtc_state))
1339 skl_wa_827(dev_priv, pipe, true);
1340
1341 /* Wa_2006604312:icl,ehl */
1342 if (!needs_scalerclk_wa(old_crtc_state) &&
1343 needs_scalerclk_wa(new_crtc_state))
1344 icl_wa_scalerclkgating(dev_priv, pipe, true);
1345
1346 /* Wa_1604331009:icl,jsl,ehl */
1347 if (!needs_cursorclk_wa(old_crtc_state) &&
1348 needs_cursorclk_wa(new_crtc_state))
1349 icl_wa_cursorclkgating(dev_priv, pipe, true);
1350
1351 /*
1352 * Vblank time updates from the shadow to live plane control register
1353 * are blocked if the memory self-refresh mode is active at that
1354 * moment. So to make sure the plane gets truly disabled, disable
1355 * first the self-refresh mode. The self-refresh enable bit in turn
1356 * will be checked/applied by the HW only at the next frame start
1357 * event which is after the vblank start event, so we need to have a
1358 * wait-for-vblank between disabling the plane and the pipe.
1359 */
1360 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1361 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1362 intel_crtc_wait_for_next_vblank(crtc);
1363
1364 /*
1365 * IVB workaround: must disable low power watermarks for at least
1366 * one frame before enabling scaling. LP watermarks can be re-enabled
1367 * when scaling is disabled.
1368 *
1369 * WaCxSRDisabledForSpriteScaling:ivb
1370 */
1371 if (!HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1372 new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))
1373 intel_crtc_wait_for_next_vblank(crtc);
1374
1375 /*
1376 * If we're doing a modeset we don't need to do any
1377 * pre-vblank watermark programming here.
1378 */
1379 if (!intel_crtc_needs_modeset(new_crtc_state)) {
1380 /*
1381 * For platforms that support atomic watermarks, program the
1382 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
1383 * will be the intermediate values that are safe for both pre- and
1384 * post- vblank; when vblank happens, the 'active' values will be set
1385 * to the final 'target' values and we'll do this again to get the
1386 * optimal watermarks. For gen9+ platforms, the values we program here
1387 * will be the final target values which will get automatically latched
1388 * at vblank time; no further programming will be necessary.
1389 *
1390 * If a platform hasn't been transitioned to atomic watermarks yet,
1391 * we'll continue to update watermarks the old way, if flags tell
1392 * us to.
1393 */
1394 if (!intel_initial_watermarks(state, crtc))
1395 if (new_crtc_state->update_wm_pre)
1396 intel_update_watermarks(dev_priv);
1397 }
1398
1399 /*
1400 * Gen2 reports pipe underruns whenever all planes are disabled.
1401 * So disable underrun reporting before all the planes get disabled.
1402 *
1403 * We do this after .initial_watermarks() so that we have a
1404 * chance of catching underruns with the intermediate watermarks
1405 * vs. the old plane configuration.
1406 */
1407 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1408 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1409
1410 /*
1411 * WA for platforms where async address update enable bit
1412 * is double buffered and only latched at start of vblank.
1413 */
1414 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1415 intel_crtc_async_flip_disable_wa(state, crtc);
1416}
1417
1418static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1419 struct intel_crtc *crtc)
1420{
1421 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1422 const struct intel_crtc_state *new_crtc_state =
1423 intel_atomic_get_new_crtc_state(state, crtc);
1424 unsigned int update_mask = new_crtc_state->update_planes;
1425 const struct intel_plane_state *old_plane_state;
1426 struct intel_plane *plane;
1427 unsigned fb_bits = 0;
1428 int i;
1429
1430 intel_crtc_dpms_overlay_disable(crtc);
1431
1432 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1433 if (crtc->pipe != plane->pipe ||
1434 !(update_mask & BIT(plane->id)))
1435 continue;
1436
1437 intel_plane_disable_arm(NULL, plane, new_crtc_state);
1438
1439 if (old_plane_state->uapi.visible)
1440 fb_bits |= plane->frontbuffer_bit;
1441 }
1442
1443 intel_frontbuffer_flip(dev_priv, fb_bits);
1444}
1445
1446static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1447{
1448 struct drm_i915_private *i915 = to_i915(state->base.dev);
1449 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1450 struct intel_crtc *crtc;
1451 int i;
1452
1453 /*
1454 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1455 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1456 */
1457 if (i915->display.dpll.mgr) {
1458 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1459 if (intel_crtc_needs_modeset(new_crtc_state))
1460 continue;
1461
1462 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1463 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1464 }
1465 }
1466}
1467
1468static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1469 struct intel_crtc *crtc)
1470{
1471 const struct intel_crtc_state *crtc_state =
1472 intel_atomic_get_new_crtc_state(state, crtc);
1473 const struct drm_connector_state *conn_state;
1474 struct drm_connector *conn;
1475 int i;
1476
1477 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1478 struct intel_encoder *encoder =
1479 to_intel_encoder(conn_state->best_encoder);
1480
1481 if (conn_state->crtc != &crtc->base)
1482 continue;
1483
1484 if (encoder->pre_pll_enable)
1485 encoder->pre_pll_enable(state, encoder,
1486 crtc_state, conn_state);
1487 }
1488}
1489
1490static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1491 struct intel_crtc *crtc)
1492{
1493 const struct intel_crtc_state *crtc_state =
1494 intel_atomic_get_new_crtc_state(state, crtc);
1495 const struct drm_connector_state *conn_state;
1496 struct drm_connector *conn;
1497 int i;
1498
1499 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1500 struct intel_encoder *encoder =
1501 to_intel_encoder(conn_state->best_encoder);
1502
1503 if (conn_state->crtc != &crtc->base)
1504 continue;
1505
1506 if (encoder->pre_enable)
1507 encoder->pre_enable(state, encoder,
1508 crtc_state, conn_state);
1509 }
1510}
1511
1512static void intel_encoders_enable(struct intel_atomic_state *state,
1513 struct intel_crtc *crtc)
1514{
1515 const struct intel_crtc_state *crtc_state =
1516 intel_atomic_get_new_crtc_state(state, crtc);
1517 const struct drm_connector_state *conn_state;
1518 struct drm_connector *conn;
1519 int i;
1520
1521 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1522 struct intel_encoder *encoder =
1523 to_intel_encoder(conn_state->best_encoder);
1524
1525 if (conn_state->crtc != &crtc->base)
1526 continue;
1527
1528 if (encoder->enable)
1529 encoder->enable(state, encoder,
1530 crtc_state, conn_state);
1531 intel_opregion_notify_encoder(encoder, true);
1532 }
1533}
1534
1535static void intel_encoders_disable(struct intel_atomic_state *state,
1536 struct intel_crtc *crtc)
1537{
1538 const struct intel_crtc_state *old_crtc_state =
1539 intel_atomic_get_old_crtc_state(state, crtc);
1540 const struct drm_connector_state *old_conn_state;
1541 struct drm_connector *conn;
1542 int i;
1543
1544 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1545 struct intel_encoder *encoder =
1546 to_intel_encoder(old_conn_state->best_encoder);
1547
1548 if (old_conn_state->crtc != &crtc->base)
1549 continue;
1550
1551 intel_opregion_notify_encoder(encoder, false);
1552 if (encoder->disable)
1553 encoder->disable(state, encoder,
1554 old_crtc_state, old_conn_state);
1555 }
1556}
1557
1558static void intel_encoders_post_disable(struct intel_atomic_state *state,
1559 struct intel_crtc *crtc)
1560{
1561 const struct intel_crtc_state *old_crtc_state =
1562 intel_atomic_get_old_crtc_state(state, crtc);
1563 const struct drm_connector_state *old_conn_state;
1564 struct drm_connector *conn;
1565 int i;
1566
1567 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1568 struct intel_encoder *encoder =
1569 to_intel_encoder(old_conn_state->best_encoder);
1570
1571 if (old_conn_state->crtc != &crtc->base)
1572 continue;
1573
1574 if (encoder->post_disable)
1575 encoder->post_disable(state, encoder,
1576 old_crtc_state, old_conn_state);
1577 }
1578}
1579
1580static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1581 struct intel_crtc *crtc)
1582{
1583 const struct intel_crtc_state *old_crtc_state =
1584 intel_atomic_get_old_crtc_state(state, crtc);
1585 const struct drm_connector_state *old_conn_state;
1586 struct drm_connector *conn;
1587 int i;
1588
1589 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1590 struct intel_encoder *encoder =
1591 to_intel_encoder(old_conn_state->best_encoder);
1592
1593 if (old_conn_state->crtc != &crtc->base)
1594 continue;
1595
1596 if (encoder->post_pll_disable)
1597 encoder->post_pll_disable(state, encoder,
1598 old_crtc_state, old_conn_state);
1599 }
1600}
1601
1602static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1603 struct intel_crtc *crtc)
1604{
1605 const struct intel_crtc_state *crtc_state =
1606 intel_atomic_get_new_crtc_state(state, crtc);
1607 const struct drm_connector_state *conn_state;
1608 struct drm_connector *conn;
1609 int i;
1610
1611 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1612 struct intel_encoder *encoder =
1613 to_intel_encoder(conn_state->best_encoder);
1614
1615 if (conn_state->crtc != &crtc->base)
1616 continue;
1617
1618 if (encoder->update_pipe)
1619 encoder->update_pipe(state, encoder,
1620 crtc_state, conn_state);
1621 }
1622}
1623
1624static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1625{
1626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1628
1629 if (crtc_state->has_pch_encoder) {
1630 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1631 &crtc_state->fdi_m_n);
1632 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1633 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1634 &crtc_state->dp_m_n);
1635 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1636 &crtc_state->dp_m2_n2);
1637 }
1638
1639 intel_set_transcoder_timings(crtc_state);
1640
1641 ilk_set_pipeconf(crtc_state);
1642}
1643
1644static void ilk_crtc_enable(struct intel_atomic_state *state,
1645 struct intel_crtc *crtc)
1646{
1647 const struct intel_crtc_state *new_crtc_state =
1648 intel_atomic_get_new_crtc_state(state, crtc);
1649 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1650 enum pipe pipe = crtc->pipe;
1651
1652 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1653 return;
1654
1655 /*
1656 * Sometimes spurious CPU pipe underruns happen during FDI
1657 * training, at least with VGA+HDMI cloning. Suppress them.
1658 *
1659 * On ILK we get an occasional spurious CPU pipe underruns
1660 * between eDP port A enable and vdd enable. Also PCH port
1661 * enable seems to result in the occasional CPU pipe underrun.
1662 *
1663 * Spurious PCH underruns also occur during PCH enabling.
1664 */
1665 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1666 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1667
1668 ilk_configure_cpu_transcoder(new_crtc_state);
1669
1670 intel_set_pipe_src_size(new_crtc_state);
1671
1672 crtc->active = true;
1673
1674 intel_encoders_pre_enable(state, crtc);
1675
1676 if (new_crtc_state->has_pch_encoder) {
1677 ilk_pch_pre_enable(state, crtc);
1678 } else {
1679 assert_fdi_tx_disabled(dev_priv, pipe);
1680 assert_fdi_rx_disabled(dev_priv, pipe);
1681 }
1682
1683 ilk_pfit_enable(new_crtc_state);
1684
1685 /*
1686 * On ILK+ LUT must be loaded before the pipe is running but with
1687 * clocks enabled
1688 */
1689 intel_color_modeset(new_crtc_state);
1690
1691 intel_initial_watermarks(state, crtc);
1692 intel_enable_transcoder(new_crtc_state);
1693
1694 if (new_crtc_state->has_pch_encoder)
1695 ilk_pch_enable(state, crtc);
1696
1697 intel_crtc_vblank_on(new_crtc_state);
1698
1699 intel_encoders_enable(state, crtc);
1700
1701 if (HAS_PCH_CPT(dev_priv))
1702 intel_wait_for_pipe_scanline_moving(crtc);
1703
1704 /*
1705 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1706 * And a second vblank wait is needed at least on ILK with
1707 * some interlaced HDMI modes. Let's do the double wait always
1708 * in case there are more corner cases we don't know about.
1709 */
1710 if (new_crtc_state->has_pch_encoder) {
1711 intel_crtc_wait_for_next_vblank(crtc);
1712 intel_crtc_wait_for_next_vblank(crtc);
1713 }
1714 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1715 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1716}
1717
1718/* Display WA #1180: WaDisableScalarClockGating: glk */
1719static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
1720{
1721 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1722
1723 return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled;
1724}
1725
1726static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1727{
1728 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1729 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1730
1731 intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe),
1732 mask, enable ? mask : 0);
1733}
1734
1735static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1736{
1737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1739
1740 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1741 HSW_LINETIME(crtc_state->linetime) |
1742 HSW_IPS_LINETIME(crtc_state->ips_linetime));
1743}
1744
1745static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1746{
1747 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1748 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1749
1750 intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder),
1751 HSW_FRAME_START_DELAY_MASK,
1752 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1753}
1754
1755static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1756{
1757 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1758 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1759 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1760
1761 if (crtc_state->has_pch_encoder) {
1762 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1763 &crtc_state->fdi_m_n);
1764 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1765 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1766 &crtc_state->dp_m_n);
1767 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1768 &crtc_state->dp_m2_n2);
1769 }
1770
1771 intel_set_transcoder_timings(crtc_state);
1772 if (HAS_VRR(dev_priv))
1773 intel_vrr_set_transcoder_timings(crtc_state);
1774
1775 if (cpu_transcoder != TRANSCODER_EDP)
1776 intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
1777 crtc_state->pixel_multiplier - 1);
1778
1779 hsw_set_frame_start_delay(crtc_state);
1780
1781 hsw_set_transconf(crtc_state);
1782}
1783
1784static void hsw_crtc_enable(struct intel_atomic_state *state,
1785 struct intel_crtc *crtc)
1786{
1787 struct intel_display *display = to_intel_display(state);
1788 const struct intel_crtc_state *new_crtc_state =
1789 intel_atomic_get_new_crtc_state(state, crtc);
1790 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1791 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1792 struct intel_crtc *pipe_crtc;
1793 int i;
1794
1795 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1796 return;
1797 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i)
1798 intel_dmc_enable_pipe(display, pipe_crtc->pipe);
1799
1800 intel_encoders_pre_pll_enable(state, crtc);
1801
1802 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1803 const struct intel_crtc_state *pipe_crtc_state =
1804 intel_atomic_get_new_crtc_state(state, pipe_crtc);
1805
1806 if (pipe_crtc_state->shared_dpll)
1807 intel_enable_shared_dpll(pipe_crtc_state);
1808 }
1809
1810 intel_encoders_pre_enable(state, crtc);
1811
1812 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1813 const struct intel_crtc_state *pipe_crtc_state =
1814 intel_atomic_get_new_crtc_state(state, pipe_crtc);
1815
1816 intel_dsc_enable(pipe_crtc_state);
1817
1818 if (HAS_UNCOMPRESSED_JOINER(dev_priv))
1819 intel_uncompressed_joiner_enable(pipe_crtc_state);
1820
1821 intel_set_pipe_src_size(pipe_crtc_state);
1822
1823 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1824 bdw_set_pipe_misc(NULL, pipe_crtc_state);
1825 }
1826
1827 if (!transcoder_is_dsi(cpu_transcoder))
1828 hsw_configure_cpu_transcoder(new_crtc_state);
1829
1830 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1831 const struct intel_crtc_state *pipe_crtc_state =
1832 intel_atomic_get_new_crtc_state(state, pipe_crtc);
1833
1834 pipe_crtc->active = true;
1835
1836 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state))
1837 glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);
1838
1839 if (DISPLAY_VER(dev_priv) >= 9)
1840 skl_pfit_enable(pipe_crtc_state);
1841 else
1842 ilk_pfit_enable(pipe_crtc_state);
1843
1844 /*
1845 * On ILK+ LUT must be loaded before the pipe is running but with
1846 * clocks enabled
1847 */
1848 intel_color_modeset(pipe_crtc_state);
1849
1850 hsw_set_linetime_wm(pipe_crtc_state);
1851
1852 if (DISPLAY_VER(dev_priv) >= 11)
1853 icl_set_pipe_chicken(pipe_crtc_state);
1854
1855 intel_initial_watermarks(state, pipe_crtc);
1856 }
1857
1858 intel_encoders_enable(state, crtc);
1859
1860 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1861 const struct intel_crtc_state *pipe_crtc_state =
1862 intel_atomic_get_new_crtc_state(state, pipe_crtc);
1863 enum pipe hsw_workaround_pipe;
1864
1865 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) {
1866 intel_crtc_wait_for_next_vblank(pipe_crtc);
1867 glk_pipe_scaler_clock_gating_wa(pipe_crtc, false);
1868 }
1869
1870 /*
1871 * If we change the relative order between pipe/planes
1872 * enabling, we need to change the workaround.
1873 */
1874 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
1875 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1876 struct intel_crtc *wa_crtc =
1877 intel_crtc_for_pipe(display, hsw_workaround_pipe);
1878
1879 intel_crtc_wait_for_next_vblank(wa_crtc);
1880 intel_crtc_wait_for_next_vblank(wa_crtc);
1881 }
1882 }
1883}
1884
1885void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1886{
1887 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1888 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1889 enum pipe pipe = crtc->pipe;
1890
1891 /* To avoid upsetting the power well on haswell only disable the pfit if
1892 * it's in use. The hw state code will make sure we get this right. */
1893 if (!old_crtc_state->pch_pfit.enabled)
1894 return;
1895
1896 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1897 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1898 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1899}
1900
1901static void ilk_crtc_disable(struct intel_atomic_state *state,
1902 struct intel_crtc *crtc)
1903{
1904 const struct intel_crtc_state *old_crtc_state =
1905 intel_atomic_get_old_crtc_state(state, crtc);
1906 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1907 enum pipe pipe = crtc->pipe;
1908
1909 /*
1910 * Sometimes spurious CPU pipe underruns happen when the
1911 * pipe is already disabled, but FDI RX/TX is still enabled.
1912 * Happens at least with VGA+HDMI cloning. Suppress them.
1913 */
1914 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1915 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1916
1917 intel_encoders_disable(state, crtc);
1918
1919 intel_crtc_vblank_off(old_crtc_state);
1920
1921 intel_disable_transcoder(old_crtc_state);
1922
1923 ilk_pfit_disable(old_crtc_state);
1924
1925 if (old_crtc_state->has_pch_encoder)
1926 ilk_pch_disable(state, crtc);
1927
1928 intel_encoders_post_disable(state, crtc);
1929
1930 if (old_crtc_state->has_pch_encoder)
1931 ilk_pch_post_disable(state, crtc);
1932
1933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1934 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1935
1936 intel_disable_shared_dpll(old_crtc_state);
1937}
1938
1939static void hsw_crtc_disable(struct intel_atomic_state *state,
1940 struct intel_crtc *crtc)
1941{
1942 struct intel_display *display = to_intel_display(state);
1943 const struct intel_crtc_state *old_crtc_state =
1944 intel_atomic_get_old_crtc_state(state, crtc);
1945 struct intel_crtc *pipe_crtc;
1946 int i;
1947
1948 /*
1949 * FIXME collapse everything to one hook.
1950 * Need care with mst->ddi interactions.
1951 */
1952 intel_encoders_disable(state, crtc);
1953 intel_encoders_post_disable(state, crtc);
1954
1955 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1956 const struct intel_crtc_state *old_pipe_crtc_state =
1957 intel_atomic_get_old_crtc_state(state, pipe_crtc);
1958
1959 intel_disable_shared_dpll(old_pipe_crtc_state);
1960 }
1961
1962 intel_encoders_post_pll_disable(state, crtc);
1963
1964 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i)
1965 intel_dmc_disable_pipe(display, pipe_crtc->pipe);
1966}
1967
1968static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1969{
1970 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1971 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1972
1973 if (!crtc_state->gmch_pfit.control)
1974 return;
1975
1976 /*
1977 * The panel fitter should only be adjusted whilst the pipe is disabled,
1978 * according to register description and PRM.
1979 */
1980 drm_WARN_ON(&dev_priv->drm,
1981 intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
1982 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1983
1984 intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
1985 crtc_state->gmch_pfit.pgm_ratios);
1986 intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
1987 crtc_state->gmch_pfit.control);
1988
1989 /* Border color in case we don't scale up to the full screen. Black by
1990 * default, change to something else for debugging. */
1991 intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
1992}
1993
1994/* Prefer intel_encoder_is_combo() */
1995bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1996{
1997 if (phy == PHY_NONE)
1998 return false;
1999 else if (IS_ALDERLAKE_S(dev_priv))
2000 return phy <= PHY_E;
2001 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
2002 return phy <= PHY_D;
2003 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
2004 return phy <= PHY_C;
2005 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
2006 return phy <= PHY_B;
2007 else
2008 /*
2009 * DG2 outputs labelled as "combo PHY" in the bspec use
2010 * SNPS PHYs with completely different programming,
2011 * hence we always return false here.
2012 */
2013 return false;
2014}
2015
2016/* Prefer intel_encoder_is_tc() */
2017bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
2018{
2019 /*
2020 * Discrete GPU phy's are not attached to FIA's to support TC
2021 * subsystem Legacy or non-legacy, and only support native DP/HDMI
2022 */
2023 if (IS_DGFX(dev_priv))
2024 return false;
2025
2026 if (DISPLAY_VER(dev_priv) >= 13)
2027 return phy >= PHY_F && phy <= PHY_I;
2028 else if (IS_TIGERLAKE(dev_priv))
2029 return phy >= PHY_D && phy <= PHY_I;
2030 else if (IS_ICELAKE(dev_priv))
2031 return phy >= PHY_C && phy <= PHY_F;
2032
2033 return false;
2034}
2035
2036/* Prefer intel_encoder_is_snps() */
2037bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
2038{
2039 /*
2040 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
2041 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
2042 */
2043 return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
2044}
2045
2046/* Prefer intel_encoder_to_phy() */
2047enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
2048{
2049 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
2050 return PHY_D + port - PORT_D_XELPD;
2051 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
2052 return PHY_F + port - PORT_TC1;
2053 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
2054 return PHY_B + port - PORT_TC1;
2055 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
2056 return PHY_C + port - PORT_TC1;
2057 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
2058 port == PORT_D)
2059 return PHY_A;
2060
2061 return PHY_A + port - PORT_A;
2062}
2063
2064/* Prefer intel_encoder_to_tc() */
2065enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
2066{
2067 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
2068 return TC_PORT_NONE;
2069
2070 if (DISPLAY_VER(dev_priv) >= 12)
2071 return TC_PORT_1 + port - PORT_TC1;
2072 else
2073 return TC_PORT_1 + port - PORT_C;
2074}
2075
2076enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
2077{
2078 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2079
2080 return intel_port_to_phy(i915, encoder->port);
2081}
2082
2083bool intel_encoder_is_combo(struct intel_encoder *encoder)
2084{
2085 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2086
2087 return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder));
2088}
2089
2090bool intel_encoder_is_snps(struct intel_encoder *encoder)
2091{
2092 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2093
2094 return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder));
2095}
2096
2097bool intel_encoder_is_tc(struct intel_encoder *encoder)
2098{
2099 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2100
2101 return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder));
2102}
2103
2104enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
2105{
2106 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2107
2108 return intel_port_to_tc(i915, encoder->port);
2109}
2110
2111enum intel_display_power_domain
2112intel_aux_power_domain(struct intel_digital_port *dig_port)
2113{
2114 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
2115
2116 if (intel_tc_port_in_tbt_alt_mode(dig_port))
2117 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
2118
2119 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
2120}
2121
2122static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2123 struct intel_power_domain_mask *mask)
2124{
2125 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2126 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2127 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2128 struct drm_encoder *encoder;
2129 enum pipe pipe = crtc->pipe;
2130
2131 bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2132
2133 if (!crtc_state->hw.active)
2134 return;
2135
2136 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
2137 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2138 if (crtc_state->pch_pfit.enabled ||
2139 crtc_state->pch_pfit.force_thru)
2140 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2141
2142 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2143 crtc_state->uapi.encoder_mask) {
2144 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2145
2146 set_bit(intel_encoder->power_domain, mask->bits);
2147 }
2148
2149 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2150 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2151
2152 if (crtc_state->shared_dpll)
2153 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2154
2155 if (crtc_state->dsc.compression_enable)
2156 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2157}
2158
2159void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2160 struct intel_power_domain_mask *old_domains)
2161{
2162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2163 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2164 enum intel_display_power_domain domain;
2165 struct intel_power_domain_mask domains, new_domains;
2166
2167 get_crtc_power_domains(crtc_state, &domains);
2168
2169 bitmap_andnot(new_domains.bits,
2170 domains.bits,
2171 crtc->enabled_power_domains.mask.bits,
2172 POWER_DOMAIN_NUM);
2173 bitmap_andnot(old_domains->bits,
2174 crtc->enabled_power_domains.mask.bits,
2175 domains.bits,
2176 POWER_DOMAIN_NUM);
2177
2178 for_each_power_domain(domain, &new_domains)
2179 intel_display_power_get_in_set(dev_priv,
2180 &crtc->enabled_power_domains,
2181 domain);
2182}
2183
2184void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2185 struct intel_power_domain_mask *domains)
2186{
2187 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2188 &crtc->enabled_power_domains,
2189 domains);
2190}
2191
2192static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2193{
2194 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2195 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2196
2197 if (intel_crtc_has_dp_encoder(crtc_state)) {
2198 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2199 &crtc_state->dp_m_n);
2200 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2201 &crtc_state->dp_m2_n2);
2202 }
2203
2204 intel_set_transcoder_timings(crtc_state);
2205
2206 i9xx_set_pipeconf(crtc_state);
2207}
2208
2209static void valleyview_crtc_enable(struct intel_atomic_state *state,
2210 struct intel_crtc *crtc)
2211{
2212 const struct intel_crtc_state *new_crtc_state =
2213 intel_atomic_get_new_crtc_state(state, crtc);
2214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2215 enum pipe pipe = crtc->pipe;
2216
2217 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2218 return;
2219
2220 i9xx_configure_cpu_transcoder(new_crtc_state);
2221
2222 intel_set_pipe_src_size(new_crtc_state);
2223
2224 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
2225
2226 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2227 intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
2228 CHV_BLEND_LEGACY);
2229 intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0);
2230 }
2231
2232 crtc->active = true;
2233
2234 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2235
2236 intel_encoders_pre_pll_enable(state, crtc);
2237
2238 if (IS_CHERRYVIEW(dev_priv))
2239 chv_enable_pll(new_crtc_state);
2240 else
2241 vlv_enable_pll(new_crtc_state);
2242
2243 intel_encoders_pre_enable(state, crtc);
2244
2245 i9xx_pfit_enable(new_crtc_state);
2246
2247 intel_color_modeset(new_crtc_state);
2248
2249 intel_initial_watermarks(state, crtc);
2250 intel_enable_transcoder(new_crtc_state);
2251
2252 intel_crtc_vblank_on(new_crtc_state);
2253
2254 intel_encoders_enable(state, crtc);
2255}
2256
2257static void i9xx_crtc_enable(struct intel_atomic_state *state,
2258 struct intel_crtc *crtc)
2259{
2260 const struct intel_crtc_state *new_crtc_state =
2261 intel_atomic_get_new_crtc_state(state, crtc);
2262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2263 enum pipe pipe = crtc->pipe;
2264
2265 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2266 return;
2267
2268 i9xx_configure_cpu_transcoder(new_crtc_state);
2269
2270 intel_set_pipe_src_size(new_crtc_state);
2271
2272 crtc->active = true;
2273
2274 if (DISPLAY_VER(dev_priv) != 2)
2275 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2276
2277 intel_encoders_pre_enable(state, crtc);
2278
2279 i9xx_enable_pll(new_crtc_state);
2280
2281 i9xx_pfit_enable(new_crtc_state);
2282
2283 intel_color_modeset(new_crtc_state);
2284
2285 if (!intel_initial_watermarks(state, crtc))
2286 intel_update_watermarks(dev_priv);
2287 intel_enable_transcoder(new_crtc_state);
2288
2289 intel_crtc_vblank_on(new_crtc_state);
2290
2291 intel_encoders_enable(state, crtc);
2292
2293 /* prevents spurious underruns */
2294 if (DISPLAY_VER(dev_priv) == 2)
2295 intel_crtc_wait_for_next_vblank(crtc);
2296}
2297
2298static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2299{
2300 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2301 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2302
2303 if (!old_crtc_state->gmch_pfit.control)
2304 return;
2305
2306 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2307
2308 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2309 intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
2310 intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
2311}
2312
2313static void i9xx_crtc_disable(struct intel_atomic_state *state,
2314 struct intel_crtc *crtc)
2315{
2316 struct intel_display *display = to_intel_display(state);
2317 struct drm_i915_private *dev_priv = to_i915(display->drm);
2318 struct intel_crtc_state *old_crtc_state =
2319 intel_atomic_get_old_crtc_state(state, crtc);
2320 enum pipe pipe = crtc->pipe;
2321
2322 /*
2323 * On gen2 planes are double buffered but the pipe isn't, so we must
2324 * wait for planes to fully turn off before disabling the pipe.
2325 */
2326 if (DISPLAY_VER(dev_priv) == 2)
2327 intel_crtc_wait_for_next_vblank(crtc);
2328
2329 intel_encoders_disable(state, crtc);
2330
2331 intel_crtc_vblank_off(old_crtc_state);
2332
2333 intel_disable_transcoder(old_crtc_state);
2334
2335 i9xx_pfit_disable(old_crtc_state);
2336
2337 intel_encoders_post_disable(state, crtc);
2338
2339 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2340 if (IS_CHERRYVIEW(dev_priv))
2341 chv_disable_pll(dev_priv, pipe);
2342 else if (IS_VALLEYVIEW(dev_priv))
2343 vlv_disable_pll(dev_priv, pipe);
2344 else
2345 i9xx_disable_pll(old_crtc_state);
2346 }
2347
2348 intel_encoders_post_pll_disable(state, crtc);
2349
2350 if (DISPLAY_VER(dev_priv) != 2)
2351 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2352
2353 if (!dev_priv->display.funcs.wm->initial_watermarks)
2354 intel_update_watermarks(dev_priv);
2355
2356 /* clock the pipe down to 640x480@60 to potentially save power */
2357 if (IS_I830(dev_priv))
2358 i830_enable_pipe(display, pipe);
2359}
2360
2361void intel_encoder_destroy(struct drm_encoder *encoder)
2362{
2363 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2364
2365 drm_encoder_cleanup(encoder);
2366 kfree(intel_encoder);
2367}
2368
2369static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2370{
2371 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2372
2373 /* GDG double wide on either pipe, otherwise pipe A only */
2374 return DISPLAY_VER(dev_priv) < 4 &&
2375 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2376}
2377
2378static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2379{
2380 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2381 struct drm_rect src;
2382
2383 /*
2384 * We only use IF-ID interlacing. If we ever use
2385 * PF-ID we'll need to adjust the pixel_rate here.
2386 */
2387
2388 if (!crtc_state->pch_pfit.enabled)
2389 return pixel_rate;
2390
2391 drm_rect_init(&src, 0, 0,
2392 drm_rect_width(&crtc_state->pipe_src) << 16,
2393 drm_rect_height(&crtc_state->pipe_src) << 16);
2394
2395 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2396 pixel_rate);
2397}
2398
2399static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2400 const struct drm_display_mode *timings)
2401{
2402 mode->hdisplay = timings->crtc_hdisplay;
2403 mode->htotal = timings->crtc_htotal;
2404 mode->hsync_start = timings->crtc_hsync_start;
2405 mode->hsync_end = timings->crtc_hsync_end;
2406
2407 mode->vdisplay = timings->crtc_vdisplay;
2408 mode->vtotal = timings->crtc_vtotal;
2409 mode->vsync_start = timings->crtc_vsync_start;
2410 mode->vsync_end = timings->crtc_vsync_end;
2411
2412 mode->flags = timings->flags;
2413 mode->type = DRM_MODE_TYPE_DRIVER;
2414
2415 mode->clock = timings->crtc_clock;
2416
2417 drm_mode_set_name(mode);
2418}
2419
2420static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2421{
2422 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2423
2424 if (HAS_GMCH(dev_priv))
2425 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2426 crtc_state->pixel_rate =
2427 crtc_state->hw.pipe_mode.crtc_clock;
2428 else
2429 crtc_state->pixel_rate =
2430 ilk_pipe_pixel_rate(crtc_state);
2431}
2432
2433static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2434 struct drm_display_mode *mode)
2435{
2436 int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2437
2438 if (num_pipes == 1)
2439 return;
2440
2441 mode->crtc_clock /= num_pipes;
2442 mode->crtc_hdisplay /= num_pipes;
2443 mode->crtc_hblank_start /= num_pipes;
2444 mode->crtc_hblank_end /= num_pipes;
2445 mode->crtc_hsync_start /= num_pipes;
2446 mode->crtc_hsync_end /= num_pipes;
2447 mode->crtc_htotal /= num_pipes;
2448}
2449
2450static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2451 struct drm_display_mode *mode)
2452{
2453 int overlap = crtc_state->splitter.pixel_overlap;
2454 int n = crtc_state->splitter.link_count;
2455
2456 if (!crtc_state->splitter.enable)
2457 return;
2458
2459 /*
2460 * eDP MSO uses segment timings from EDID for transcoder
2461 * timings, but full mode for everything else.
2462 *
2463 * h_full = (h_segment - pixel_overlap) * link_count
2464 */
2465 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2466 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2467 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2468 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2469 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2470 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2471 mode->crtc_clock *= n;
2472}
2473
2474static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2475{
2476 struct drm_display_mode *mode = &crtc_state->hw.mode;
2477 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2478 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2479
2480 /*
2481 * Start with the adjusted_mode crtc timings, which
2482 * have been filled with the transcoder timings.
2483 */
2484 drm_mode_copy(pipe_mode, adjusted_mode);
2485
2486 /* Expand MSO per-segment transcoder timings to full */
2487 intel_splitter_adjust_timings(crtc_state, pipe_mode);
2488
2489 /*
2490 * We want the full numbers in adjusted_mode normal timings,
2491 * adjusted_mode crtc timings are left with the raw transcoder
2492 * timings.
2493 */
2494 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2495
2496 /* Populate the "user" mode with full numbers */
2497 drm_mode_copy(mode, pipe_mode);
2498 intel_mode_from_crtc_timings(mode, mode);
2499 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2500 intel_crtc_num_joined_pipes(crtc_state);
2501 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2502
2503 /* Derive per-pipe timings in case joiner is used */
2504 intel_joiner_adjust_timings(crtc_state, pipe_mode);
2505 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2506
2507 intel_crtc_compute_pixel_rate(crtc_state);
2508}
2509
2510void intel_encoder_get_config(struct intel_encoder *encoder,
2511 struct intel_crtc_state *crtc_state)
2512{
2513 encoder->get_config(encoder, crtc_state);
2514
2515 intel_crtc_readout_derived_state(crtc_state);
2516}
2517
2518static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2519{
2520 int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2521 int width, height;
2522
2523 if (num_pipes == 1)
2524 return;
2525
2526 width = drm_rect_width(&crtc_state->pipe_src);
2527 height = drm_rect_height(&crtc_state->pipe_src);
2528
2529 drm_rect_init(&crtc_state->pipe_src, 0, 0,
2530 width / num_pipes, height);
2531}
2532
2533static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2534{
2535 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2536 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2537
2538 intel_joiner_compute_pipe_src(crtc_state);
2539
2540 /*
2541 * Pipe horizontal size must be even in:
2542 * - DVO ganged mode
2543 * - LVDS dual channel mode
2544 * - Double wide pipe
2545 */
2546 if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2547 if (crtc_state->double_wide) {
2548 drm_dbg_kms(&i915->drm,
2549 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2550 crtc->base.base.id, crtc->base.name);
2551 return -EINVAL;
2552 }
2553
2554 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2555 intel_is_dual_link_lvds(i915)) {
2556 drm_dbg_kms(&i915->drm,
2557 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2558 crtc->base.base.id, crtc->base.name);
2559 return -EINVAL;
2560 }
2561 }
2562
2563 return 0;
2564}
2565
2566static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2567{
2568 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2569 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2570 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2571 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2572 int clock_limit = i915->display.cdclk.max_dotclk_freq;
2573
2574 /*
2575 * Start with the adjusted_mode crtc timings, which
2576 * have been filled with the transcoder timings.
2577 */
2578 drm_mode_copy(pipe_mode, adjusted_mode);
2579
2580 /* Expand MSO per-segment transcoder timings to full */
2581 intel_splitter_adjust_timings(crtc_state, pipe_mode);
2582
2583 /* Derive per-pipe timings in case joiner is used */
2584 intel_joiner_adjust_timings(crtc_state, pipe_mode);
2585 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2586
2587 if (DISPLAY_VER(i915) < 4) {
2588 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2589
2590 /*
2591 * Enable double wide mode when the dot clock
2592 * is > 90% of the (display) core speed.
2593 */
2594 if (intel_crtc_supports_double_wide(crtc) &&
2595 pipe_mode->crtc_clock > clock_limit) {
2596 clock_limit = i915->display.cdclk.max_dotclk_freq;
2597 crtc_state->double_wide = true;
2598 }
2599 }
2600
2601 if (pipe_mode->crtc_clock > clock_limit) {
2602 drm_dbg_kms(&i915->drm,
2603 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2604 crtc->base.base.id, crtc->base.name,
2605 pipe_mode->crtc_clock, clock_limit,
2606 str_yes_no(crtc_state->double_wide));
2607 return -EINVAL;
2608 }
2609
2610 return 0;
2611}
2612
2613static bool intel_crtc_needs_wa_14015401596(struct intel_crtc_state *crtc_state)
2614{
2615 struct intel_display *display = to_intel_display(crtc_state);
2616 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2617
2618 return intel_vrr_possible(crtc_state) && crtc_state->has_psr &&
2619 adjusted_mode->crtc_vblank_start == adjusted_mode->crtc_vdisplay &&
2620 IS_DISPLAY_VER(display, 13, 14);
2621}
2622
2623static int intel_crtc_compute_config(struct intel_atomic_state *state,
2624 struct intel_crtc *crtc)
2625{
2626 struct intel_crtc_state *crtc_state =
2627 intel_atomic_get_new_crtc_state(state, crtc);
2628 struct drm_display_mode *adjusted_mode =
2629 &crtc_state->hw.adjusted_mode;
2630 int ret;
2631
2632 /* Wa_14015401596 */
2633 if (intel_crtc_needs_wa_14015401596(crtc_state))
2634 adjusted_mode->crtc_vblank_start += 1;
2635
2636 ret = intel_dpll_crtc_compute_clock(state, crtc);
2637 if (ret)
2638 return ret;
2639
2640 ret = intel_crtc_compute_pipe_src(crtc_state);
2641 if (ret)
2642 return ret;
2643
2644 ret = intel_crtc_compute_pipe_mode(crtc_state);
2645 if (ret)
2646 return ret;
2647
2648 intel_crtc_compute_pixel_rate(crtc_state);
2649
2650 if (crtc_state->has_pch_encoder)
2651 return ilk_fdi_compute_config(crtc, crtc_state);
2652
2653 return 0;
2654}
2655
2656static void
2657intel_reduce_m_n_ratio(u32 *num, u32 *den)
2658{
2659 while (*num > DATA_LINK_M_N_MASK ||
2660 *den > DATA_LINK_M_N_MASK) {
2661 *num >>= 1;
2662 *den >>= 1;
2663 }
2664}
2665
2666static void compute_m_n(u32 *ret_m, u32 *ret_n,
2667 u32 m, u32 n, u32 constant_n)
2668{
2669 if (constant_n)
2670 *ret_n = constant_n;
2671 else
2672 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2673
2674 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2675 intel_reduce_m_n_ratio(ret_m, ret_n);
2676}
2677
2678void
2679intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2680 int pixel_clock, int link_clock,
2681 int bw_overhead,
2682 struct intel_link_m_n *m_n)
2683{
2684 u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
2685 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
2686 bw_overhead);
2687 u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
2688
2689 /*
2690 * Windows/BIOS uses fixed M/N values always. Follow suit.
2691 *
2692 * Also several DP dongles in particular seem to be fussy
2693 * about too large link M/N values. Presumably the 20bit
2694 * value used by Windows/BIOS is acceptable to everyone.
2695 */
2696 m_n->tu = 64;
2697 compute_m_n(&m_n->data_m, &m_n->data_n,
2698 data_m, data_n,
2699 0x8000000);
2700
2701 compute_m_n(&m_n->link_m, &m_n->link_n,
2702 pixel_clock, link_symbol_clock,
2703 0x80000);
2704}
2705
2706void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2707{
2708 /*
2709 * There may be no VBT; and if the BIOS enabled SSC we can
2710 * just keep using it to avoid unnecessary flicker. Whereas if the
2711 * BIOS isn't using it, don't assume it will work even if the VBT
2712 * indicates as much.
2713 */
2714 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2715 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2716 PCH_DREF_CONTROL) &
2717 DREF_SSC1_ENABLE;
2718
2719 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2720 drm_dbg_kms(&dev_priv->drm,
2721 "SSC %s by BIOS, overriding VBT which says %s\n",
2722 str_enabled_disabled(bios_lvds_use_ssc),
2723 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2724 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2725 }
2726 }
2727}
2728
2729void intel_zero_m_n(struct intel_link_m_n *m_n)
2730{
2731 /* corresponds to 0 register value */
2732 memset(m_n, 0, sizeof(*m_n));
2733 m_n->tu = 1;
2734}
2735
2736void intel_set_m_n(struct drm_i915_private *i915,
2737 const struct intel_link_m_n *m_n,
2738 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2739 i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2740{
2741 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2742 intel_de_write(i915, data_n_reg, m_n->data_n);
2743 intel_de_write(i915, link_m_reg, m_n->link_m);
2744 /*
2745 * On BDW+ writing LINK_N arms the double buffered update
2746 * of all the M/N registers, so it must be written last.
2747 */
2748 intel_de_write(i915, link_n_reg, m_n->link_n);
2749}
2750
2751bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2752 enum transcoder transcoder)
2753{
2754 if (IS_HASWELL(dev_priv))
2755 return transcoder == TRANSCODER_EDP;
2756
2757 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2758}
2759
2760void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2761 enum transcoder transcoder,
2762 const struct intel_link_m_n *m_n)
2763{
2764 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2765 enum pipe pipe = crtc->pipe;
2766
2767 if (DISPLAY_VER(dev_priv) >= 5)
2768 intel_set_m_n(dev_priv, m_n,
2769 PIPE_DATA_M1(dev_priv, transcoder),
2770 PIPE_DATA_N1(dev_priv, transcoder),
2771 PIPE_LINK_M1(dev_priv, transcoder),
2772 PIPE_LINK_N1(dev_priv, transcoder));
2773 else
2774 intel_set_m_n(dev_priv, m_n,
2775 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2776 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2777}
2778
2779void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2780 enum transcoder transcoder,
2781 const struct intel_link_m_n *m_n)
2782{
2783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2784
2785 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2786 return;
2787
2788 intel_set_m_n(dev_priv, m_n,
2789 PIPE_DATA_M2(dev_priv, transcoder),
2790 PIPE_DATA_N2(dev_priv, transcoder),
2791 PIPE_LINK_M2(dev_priv, transcoder),
2792 PIPE_LINK_N2(dev_priv, transcoder));
2793}
2794
2795static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2796{
2797 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2799 enum pipe pipe = crtc->pipe;
2800 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2801 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2802 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2803 int vsyncshift = 0;
2804
2805 /* We need to be careful not to changed the adjusted mode, for otherwise
2806 * the hw state checker will get angry at the mismatch. */
2807 crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2808 crtc_vtotal = adjusted_mode->crtc_vtotal;
2809 crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2810 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2811
2812 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2813 /* the chip adds 2 halflines automatically */
2814 crtc_vtotal -= 1;
2815 crtc_vblank_end -= 1;
2816
2817 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2818 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2819 else
2820 vsyncshift = adjusted_mode->crtc_hsync_start -
2821 adjusted_mode->crtc_htotal / 2;
2822 if (vsyncshift < 0)
2823 vsyncshift += adjusted_mode->crtc_htotal;
2824 }
2825
2826 /*
2827 * VBLANK_START no longer works on ADL+, instead we must use
2828 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2829 */
2830 if (DISPLAY_VER(dev_priv) >= 13) {
2831 intel_de_write(dev_priv,
2832 TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder),
2833 crtc_vblank_start - crtc_vdisplay);
2834
2835 /*
2836 * VBLANK_START not used by hw, just clear it
2837 * to make it stand out in register dumps.
2838 */
2839 crtc_vblank_start = 1;
2840 }
2841
2842 if (DISPLAY_VER(dev_priv) >= 4)
2843 intel_de_write(dev_priv,
2844 TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder),
2845 vsyncshift);
2846
2847 intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
2848 HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2849 HTOTAL(adjusted_mode->crtc_htotal - 1));
2850 intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
2851 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2852 HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2853 intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
2854 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2855 HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2856
2857 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
2858 VACTIVE(crtc_vdisplay - 1) |
2859 VTOTAL(crtc_vtotal - 1));
2860 intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
2861 VBLANK_START(crtc_vblank_start - 1) |
2862 VBLANK_END(crtc_vblank_end - 1));
2863 intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
2864 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2865 VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2866
2867 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2868 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2869 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2870 * bits. */
2871 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2872 (pipe == PIPE_B || pipe == PIPE_C))
2873 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
2874 VACTIVE(crtc_vdisplay - 1) |
2875 VTOTAL(crtc_vtotal - 1));
2876}
2877
2878static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2879{
2880 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2881 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2882 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2883 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2884 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2885
2886 crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2887 crtc_vtotal = adjusted_mode->crtc_vtotal;
2888 crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2889 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2890
2891 drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2892
2893 /*
2894 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2895 * But let's write it anyway to keep the state checker happy.
2896 */
2897 intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
2898 VBLANK_START(crtc_vblank_start - 1) |
2899 VBLANK_END(crtc_vblank_end - 1));
2900 /*
2901 * The double buffer latch point for TRANS_VTOTAL
2902 * is the transcoder's undelayed vblank.
2903 */
2904 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
2905 VACTIVE(crtc_vdisplay - 1) |
2906 VTOTAL(crtc_vtotal - 1));
2907}
2908
2909static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2910{
2911 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2913 int width = drm_rect_width(&crtc_state->pipe_src);
2914 int height = drm_rect_height(&crtc_state->pipe_src);
2915 enum pipe pipe = crtc->pipe;
2916
2917 /* pipesrc controls the size that is scaled from, which should
2918 * always be the user's requested size.
2919 */
2920 intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
2921 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2922}
2923
2924static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2925{
2926 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2927 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2928
2929 if (DISPLAY_VER(dev_priv) == 2)
2930 return false;
2931
2932 if (DISPLAY_VER(dev_priv) >= 9 ||
2933 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2934 return intel_de_read(dev_priv,
2935 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2936 else
2937 return intel_de_read(dev_priv,
2938 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2939}
2940
2941static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2942 struct intel_crtc_state *pipe_config)
2943{
2944 struct drm_device *dev = crtc->base.dev;
2945 struct drm_i915_private *dev_priv = to_i915(dev);
2946 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2947 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2948 u32 tmp;
2949
2950 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
2951 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2952 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2953
2954 if (!transcoder_is_dsi(cpu_transcoder)) {
2955 tmp = intel_de_read(dev_priv,
2956 TRANS_HBLANK(dev_priv, cpu_transcoder));
2957 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2958 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2959 }
2960
2961 tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
2962 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2963 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2964
2965 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
2966 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2967 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2968
2969 /* FIXME TGL+ DSI transcoders have this! */
2970 if (!transcoder_is_dsi(cpu_transcoder)) {
2971 tmp = intel_de_read(dev_priv,
2972 TRANS_VBLANK(dev_priv, cpu_transcoder));
2973 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2974 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2975 }
2976 tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder));
2977 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2978 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2979
2980 if (intel_pipe_is_interlaced(pipe_config)) {
2981 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2982 adjusted_mode->crtc_vtotal += 1;
2983 adjusted_mode->crtc_vblank_end += 1;
2984 }
2985
2986 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2987 adjusted_mode->crtc_vblank_start =
2988 adjusted_mode->crtc_vdisplay +
2989 intel_de_read(dev_priv,
2990 TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder));
2991}
2992
2993static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2994{
2995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2996 int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2997 enum pipe primary_pipe, pipe = crtc->pipe;
2998 int width;
2999
3000 if (num_pipes == 1)
3001 return;
3002
3003 primary_pipe = joiner_primary_pipe(crtc_state);
3004 width = drm_rect_width(&crtc_state->pipe_src);
3005
3006 drm_rect_translate_to(&crtc_state->pipe_src,
3007 (pipe - primary_pipe) * width, 0);
3008}
3009
3010static void intel_get_pipe_src_size(struct intel_crtc *crtc,
3011 struct intel_crtc_state *pipe_config)
3012{
3013 struct drm_device *dev = crtc->base.dev;
3014 struct drm_i915_private *dev_priv = to_i915(dev);
3015 u32 tmp;
3016
3017 tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));
3018
3019 drm_rect_init(&pipe_config->pipe_src, 0, 0,
3020 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
3021 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
3022
3023 intel_joiner_adjust_pipe_src(pipe_config);
3024}
3025
3026void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3027{
3028 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3029 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3030 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3031 u32 val = 0;
3032
3033 /*
3034 * - We keep both pipes enabled on 830
3035 * - During modeset the pipe is still disabled and must remain so
3036 * - During fastset the pipe is already enabled and must remain so
3037 */
3038 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
3039 val |= TRANSCONF_ENABLE;
3040
3041 if (crtc_state->double_wide)
3042 val |= TRANSCONF_DOUBLE_WIDE;
3043
3044 /* only g4x and later have fancy bpc/dither controls */
3045 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3046 IS_CHERRYVIEW(dev_priv)) {
3047 /* Bspec claims that we can't use dithering for 30bpp pipes. */
3048 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
3049 val |= TRANSCONF_DITHER_EN |
3050 TRANSCONF_DITHER_TYPE_SP;
3051
3052 switch (crtc_state->pipe_bpp) {
3053 default:
3054 /* Case prevented by intel_choose_pipe_bpp_dither. */
3055 MISSING_CASE(crtc_state->pipe_bpp);
3056 fallthrough;
3057 case 18:
3058 val |= TRANSCONF_BPC_6;
3059 break;
3060 case 24:
3061 val |= TRANSCONF_BPC_8;
3062 break;
3063 case 30:
3064 val |= TRANSCONF_BPC_10;
3065 break;
3066 }
3067 }
3068
3069 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3070 if (DISPLAY_VER(dev_priv) < 4 ||
3071 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3072 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
3073 else
3074 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
3075 } else {
3076 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
3077 }
3078
3079 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3080 crtc_state->limited_color_range)
3081 val |= TRANSCONF_COLOR_RANGE_SELECT;
3082
3083 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3084
3085 if (crtc_state->wgc_enable)
3086 val |= TRANSCONF_WGC_ENABLE;
3087
3088 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3089
3090 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
3091 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
3092}
3093
3094static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
3095{
3096 if (IS_I830(dev_priv))
3097 return false;
3098
3099 return DISPLAY_VER(dev_priv) >= 4 ||
3100 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
3101}
3102
3103static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
3104{
3105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3107 enum pipe pipe;
3108 u32 tmp;
3109
3110 if (!i9xx_has_pfit(dev_priv))
3111 return;
3112
3113 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
3114 if (!(tmp & PFIT_ENABLE))
3115 return;
3116
3117 /* Check whether the pfit is attached to our pipe. */
3118 if (DISPLAY_VER(dev_priv) >= 4)
3119 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
3120 else
3121 pipe = PIPE_B;
3122
3123 if (pipe != crtc->pipe)
3124 return;
3125
3126 crtc_state->gmch_pfit.control = tmp;
3127 crtc_state->gmch_pfit.pgm_ratios =
3128 intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
3129}
3130
3131static enum intel_output_format
3132bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
3133{
3134 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3135 u32 tmp;
3136
3137 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3138
3139 if (tmp & PIPE_MISC_YUV420_ENABLE) {
3140 /* We support 4:2:0 in full blend mode only */
3141 drm_WARN_ON(&dev_priv->drm,
3142 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3143
3144 return INTEL_OUTPUT_FORMAT_YCBCR420;
3145 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3146 return INTEL_OUTPUT_FORMAT_YCBCR444;
3147 } else {
3148 return INTEL_OUTPUT_FORMAT_RGB;
3149 }
3150}
3151
3152static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3153 struct intel_crtc_state *pipe_config)
3154{
3155 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3156 enum intel_display_power_domain power_domain;
3157 intel_wakeref_t wakeref;
3158 u32 tmp;
3159 bool ret;
3160
3161 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3162 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3163 if (!wakeref)
3164 return false;
3165
3166 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3167 pipe_config->sink_format = pipe_config->output_format;
3168 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3169 pipe_config->shared_dpll = NULL;
3170
3171 ret = false;
3172
3173 tmp = intel_de_read(dev_priv,
3174 TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
3175 if (!(tmp & TRANSCONF_ENABLE))
3176 goto out;
3177
3178 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3179 IS_CHERRYVIEW(dev_priv)) {
3180 switch (tmp & TRANSCONF_BPC_MASK) {
3181 case TRANSCONF_BPC_6:
3182 pipe_config->pipe_bpp = 18;
3183 break;
3184 case TRANSCONF_BPC_8:
3185 pipe_config->pipe_bpp = 24;
3186 break;
3187 case TRANSCONF_BPC_10:
3188 pipe_config->pipe_bpp = 30;
3189 break;
3190 default:
3191 MISSING_CASE(tmp);
3192 break;
3193 }
3194 }
3195
3196 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3197 (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3198 pipe_config->limited_color_range = true;
3199
3200 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3201
3202 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3203
3204 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3205 (tmp & TRANSCONF_WGC_ENABLE))
3206 pipe_config->wgc_enable = true;
3207
3208 intel_color_get_config(pipe_config);
3209
3210 if (DISPLAY_VER(dev_priv) < 4)
3211 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3212
3213 intel_get_transcoder_timings(crtc, pipe_config);
3214 intel_get_pipe_src_size(crtc, pipe_config);
3215
3216 i9xx_get_pfit_config(pipe_config);
3217
3218 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
3219
3220 if (DISPLAY_VER(dev_priv) >= 4) {
3221 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3222 pipe_config->pixel_multiplier =
3223 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3224 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3225 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3226 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3227 tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3228 pipe_config->pixel_multiplier =
3229 ((tmp & SDVO_MULTIPLIER_MASK)
3230 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3231 } else {
3232 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3233 * port and will be fixed up in the encoder->get_config
3234 * function. */
3235 pipe_config->pixel_multiplier = 1;
3236 }
3237
3238 if (IS_CHERRYVIEW(dev_priv))
3239 chv_crtc_clock_get(pipe_config);
3240 else if (IS_VALLEYVIEW(dev_priv))
3241 vlv_crtc_clock_get(pipe_config);
3242 else
3243 i9xx_crtc_clock_get(pipe_config);
3244
3245 /*
3246 * Normally the dotclock is filled in by the encoder .get_config()
3247 * but in case the pipe is enabled w/o any ports we need a sane
3248 * default.
3249 */
3250 pipe_config->hw.adjusted_mode.crtc_clock =
3251 pipe_config->port_clock / pipe_config->pixel_multiplier;
3252
3253 ret = true;
3254
3255out:
3256 intel_display_power_put(dev_priv, power_domain, wakeref);
3257
3258 return ret;
3259}
3260
3261void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3262{
3263 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3265 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3266 u32 val = 0;
3267
3268 /*
3269 * - During modeset the pipe is still disabled and must remain so
3270 * - During fastset the pipe is already enabled and must remain so
3271 */
3272 if (!intel_crtc_needs_modeset(crtc_state))
3273 val |= TRANSCONF_ENABLE;
3274
3275 switch (crtc_state->pipe_bpp) {
3276 default:
3277 /* Case prevented by intel_choose_pipe_bpp_dither. */
3278 MISSING_CASE(crtc_state->pipe_bpp);
3279 fallthrough;
3280 case 18:
3281 val |= TRANSCONF_BPC_6;
3282 break;
3283 case 24:
3284 val |= TRANSCONF_BPC_8;
3285 break;
3286 case 30:
3287 val |= TRANSCONF_BPC_10;
3288 break;
3289 case 36:
3290 val |= TRANSCONF_BPC_12;
3291 break;
3292 }
3293
3294 if (crtc_state->dither)
3295 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3296
3297 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3298 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3299 else
3300 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3301
3302 /*
3303 * This would end up with an odd purple hue over
3304 * the entire display. Make sure we don't do it.
3305 */
3306 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3307 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3308
3309 if (crtc_state->limited_color_range &&
3310 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3311 val |= TRANSCONF_COLOR_RANGE_SELECT;
3312
3313 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3314 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3315
3316 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3317
3318 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3319 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3320
3321 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
3322 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
3323}
3324
3325static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3326{
3327 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3328 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3329 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3330 u32 val = 0;
3331
3332 /*
3333 * - During modeset the pipe is still disabled and must remain so
3334 * - During fastset the pipe is already enabled and must remain so
3335 */
3336 if (!intel_crtc_needs_modeset(crtc_state))
3337 val |= TRANSCONF_ENABLE;
3338
3339 if (IS_HASWELL(dev_priv) && crtc_state->dither)
3340 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3341
3342 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3343 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3344 else
3345 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3346
3347 if (IS_HASWELL(dev_priv) &&
3348 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3349 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3350
3351 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
3352 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
3353}
3354
3355static void bdw_set_pipe_misc(struct intel_dsb *dsb,
3356 const struct intel_crtc_state *crtc_state)
3357{
3358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3359 struct intel_display *display = to_intel_display(crtc->base.dev);
3360 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3361 u32 val = 0;
3362
3363 switch (crtc_state->pipe_bpp) {
3364 case 18:
3365 val |= PIPE_MISC_BPC_6;
3366 break;
3367 case 24:
3368 val |= PIPE_MISC_BPC_8;
3369 break;
3370 case 30:
3371 val |= PIPE_MISC_BPC_10;
3372 break;
3373 case 36:
3374 /* Port output 12BPC defined for ADLP+ */
3375 if (DISPLAY_VER(dev_priv) >= 13)
3376 val |= PIPE_MISC_BPC_12_ADLP;
3377 break;
3378 default:
3379 MISSING_CASE(crtc_state->pipe_bpp);
3380 break;
3381 }
3382
3383 if (crtc_state->dither)
3384 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3385
3386 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3387 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3388 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3389
3390 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3391 val |= PIPE_MISC_YUV420_ENABLE |
3392 PIPE_MISC_YUV420_MODE_FULL_BLEND;
3393
3394 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3395 val |= PIPE_MISC_HDR_MODE_PRECISION;
3396
3397 if (DISPLAY_VER(dev_priv) >= 12)
3398 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3399
3400 /* allow PSR with sprite enabled */
3401 if (IS_BROADWELL(dev_priv))
3402 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3403
3404 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
3405}
3406
3407int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3408{
3409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3410 u32 tmp;
3411
3412 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3413
3414 switch (tmp & PIPE_MISC_BPC_MASK) {
3415 case PIPE_MISC_BPC_6:
3416 return 18;
3417 case PIPE_MISC_BPC_8:
3418 return 24;
3419 case PIPE_MISC_BPC_10:
3420 return 30;
3421 /*
3422 * PORT OUTPUT 12 BPC defined for ADLP+.
3423 *
3424 * TODO:
3425 * For previous platforms with DSI interface, bits 5:7
3426 * are used for storing pipe_bpp irrespective of dithering.
3427 * Since the value of 12 BPC is not defined for these bits
3428 * on older platforms, need to find a workaround for 12 BPC
3429 * MIPI DSI HW readout.
3430 */
3431 case PIPE_MISC_BPC_12_ADLP:
3432 if (DISPLAY_VER(dev_priv) >= 13)
3433 return 36;
3434 fallthrough;
3435 default:
3436 MISSING_CASE(tmp);
3437 return 0;
3438 }
3439}
3440
3441int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3442{
3443 /*
3444 * Account for spread spectrum to avoid
3445 * oversubscribing the link. Max center spread
3446 * is 2.5%; use 5% for safety's sake.
3447 */
3448 u32 bps = target_clock * bpp * 21 / 20;
3449 return DIV_ROUND_UP(bps, link_bw * 8);
3450}
3451
3452void intel_get_m_n(struct drm_i915_private *i915,
3453 struct intel_link_m_n *m_n,
3454 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3455 i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3456{
3457 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3458 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3459 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3460 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3461 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3462}
3463
3464void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3465 enum transcoder transcoder,
3466 struct intel_link_m_n *m_n)
3467{
3468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3469 enum pipe pipe = crtc->pipe;
3470
3471 if (DISPLAY_VER(dev_priv) >= 5)
3472 intel_get_m_n(dev_priv, m_n,
3473 PIPE_DATA_M1(dev_priv, transcoder),
3474 PIPE_DATA_N1(dev_priv, transcoder),
3475 PIPE_LINK_M1(dev_priv, transcoder),
3476 PIPE_LINK_N1(dev_priv, transcoder));
3477 else
3478 intel_get_m_n(dev_priv, m_n,
3479 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3480 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3481}
3482
3483void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3484 enum transcoder transcoder,
3485 struct intel_link_m_n *m_n)
3486{
3487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3488
3489 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3490 return;
3491
3492 intel_get_m_n(dev_priv, m_n,
3493 PIPE_DATA_M2(dev_priv, transcoder),
3494 PIPE_DATA_N2(dev_priv, transcoder),
3495 PIPE_LINK_M2(dev_priv, transcoder),
3496 PIPE_LINK_N2(dev_priv, transcoder));
3497}
3498
3499static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3500{
3501 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3502 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3503 u32 ctl, pos, size;
3504 enum pipe pipe;
3505
3506 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3507 if ((ctl & PF_ENABLE) == 0)
3508 return;
3509
3510 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3511 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3512 else
3513 pipe = crtc->pipe;
3514
3515 crtc_state->pch_pfit.enabled = true;
3516
3517 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3518 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3519
3520 drm_rect_init(&crtc_state->pch_pfit.dst,
3521 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3522 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3523 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3524 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3525
3526 /*
3527 * We currently do not free assignements of panel fitters on
3528 * ivb/hsw (since we don't use the higher upscaling modes which
3529 * differentiates them) so just WARN about this case for now.
3530 */
3531 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3532}
3533
3534static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3535 struct intel_crtc_state *pipe_config)
3536{
3537 struct drm_device *dev = crtc->base.dev;
3538 struct drm_i915_private *dev_priv = to_i915(dev);
3539 enum intel_display_power_domain power_domain;
3540 intel_wakeref_t wakeref;
3541 u32 tmp;
3542 bool ret;
3543
3544 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3545 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3546 if (!wakeref)
3547 return false;
3548
3549 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3550 pipe_config->shared_dpll = NULL;
3551
3552 ret = false;
3553 tmp = intel_de_read(dev_priv,
3554 TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
3555 if (!(tmp & TRANSCONF_ENABLE))
3556 goto out;
3557
3558 switch (tmp & TRANSCONF_BPC_MASK) {
3559 case TRANSCONF_BPC_6:
3560 pipe_config->pipe_bpp = 18;
3561 break;
3562 case TRANSCONF_BPC_8:
3563 pipe_config->pipe_bpp = 24;
3564 break;
3565 case TRANSCONF_BPC_10:
3566 pipe_config->pipe_bpp = 30;
3567 break;
3568 case TRANSCONF_BPC_12:
3569 pipe_config->pipe_bpp = 36;
3570 break;
3571 default:
3572 break;
3573 }
3574
3575 if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3576 pipe_config->limited_color_range = true;
3577
3578 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3579 case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3580 case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3581 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3582 break;
3583 default:
3584 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3585 break;
3586 }
3587
3588 pipe_config->sink_format = pipe_config->output_format;
3589
3590 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3591
3592 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3593
3594 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3595
3596 intel_color_get_config(pipe_config);
3597
3598 pipe_config->pixel_multiplier = 1;
3599
3600 ilk_pch_get_config(pipe_config);
3601
3602 intel_get_transcoder_timings(crtc, pipe_config);
3603 intel_get_pipe_src_size(crtc, pipe_config);
3604
3605 ilk_get_pfit_config(pipe_config);
3606
3607 ret = true;
3608
3609out:
3610 intel_display_power_put(dev_priv, power_domain, wakeref);
3611
3612 return ret;
3613}
3614
3615static u8 joiner_pipes(struct drm_i915_private *i915)
3616{
3617 u8 pipes;
3618
3619 if (DISPLAY_VER(i915) >= 12)
3620 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3621 else if (DISPLAY_VER(i915) >= 11)
3622 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3623 else
3624 pipes = 0;
3625
3626 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3627}
3628
3629static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3630 enum transcoder cpu_transcoder)
3631{
3632 enum intel_display_power_domain power_domain;
3633 intel_wakeref_t wakeref;
3634 u32 tmp = 0;
3635
3636 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3637
3638 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3639 tmp = intel_de_read(dev_priv,
3640 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
3641
3642 return tmp & TRANS_DDI_FUNC_ENABLE;
3643}
3644
3645static void enabled_uncompressed_joiner_pipes(struct intel_display *display,
3646 u8 *primary_pipes, u8 *secondary_pipes)
3647{
3648 struct drm_i915_private *i915 = to_i915(display->drm);
3649 struct intel_crtc *crtc;
3650
3651 *primary_pipes = 0;
3652 *secondary_pipes = 0;
3653
3654 if (!HAS_UNCOMPRESSED_JOINER(display))
3655 return;
3656
3657 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
3658 joiner_pipes(i915)) {
3659 enum intel_display_power_domain power_domain;
3660 enum pipe pipe = crtc->pipe;
3661 intel_wakeref_t wakeref;
3662
3663 power_domain = POWER_DOMAIN_PIPE(pipe);
3664 with_intel_display_power_if_enabled(i915, power_domain, wakeref) {
3665 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3666
3667 if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
3668 *primary_pipes |= BIT(pipe);
3669 if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
3670 *secondary_pipes |= BIT(pipe);
3671 }
3672 }
3673}
3674
3675static void enabled_bigjoiner_pipes(struct intel_display *display,
3676 u8 *primary_pipes, u8 *secondary_pipes)
3677{
3678 struct drm_i915_private *i915 = to_i915(display->drm);
3679 struct intel_crtc *crtc;
3680
3681 *primary_pipes = 0;
3682 *secondary_pipes = 0;
3683
3684 if (!HAS_BIGJOINER(display))
3685 return;
3686
3687 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
3688 joiner_pipes(i915)) {
3689 enum intel_display_power_domain power_domain;
3690 enum pipe pipe = crtc->pipe;
3691 intel_wakeref_t wakeref;
3692
3693 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);
3694 with_intel_display_power_if_enabled(i915, power_domain, wakeref) {
3695 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3696
3697 if (!(tmp & BIG_JOINER_ENABLE))
3698 continue;
3699
3700 if (tmp & PRIMARY_BIG_JOINER_ENABLE)
3701 *primary_pipes |= BIT(pipe);
3702 else
3703 *secondary_pipes |= BIT(pipe);
3704 }
3705 }
3706}
3707
3708static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes)
3709{
3710 u8 secondary_pipes = 0;
3711
3712 for (int i = 1; i < num_pipes; i++)
3713 secondary_pipes |= primary_pipes << i;
3714
3715 return secondary_pipes;
3716}
3717
3718static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes)
3719{
3720 return expected_secondary_pipes(uncompjoiner_primary_pipes, 2);
3721}
3722
3723static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes)
3724{
3725 return expected_secondary_pipes(bigjoiner_primary_pipes, 2);
3726}
3727
3728static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)
3729{
3730 primary_pipes &= GENMASK(pipe, 0);
3731
3732 return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
3733}
3734
3735static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes)
3736{
3737 return expected_secondary_pipes(ultrajoiner_primary_pipes, 4);
3738}
3739
3740static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes,
3741 u8 ultrajoiner_secondary_pipes)
3742{
3743 return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3;
3744}
3745
3746static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915,
3747 u8 *primary_pipes, u8 *secondary_pipes)
3748{
3749 struct intel_crtc *crtc;
3750
3751 *primary_pipes = 0;
3752 *secondary_pipes = 0;
3753
3754 if (!HAS_ULTRAJOINER(i915))
3755 return;
3756
3757 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
3758 joiner_pipes(i915)) {
3759 enum intel_display_power_domain power_domain;
3760 enum pipe pipe = crtc->pipe;
3761 intel_wakeref_t wakeref;
3762
3763 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);
3764 with_intel_display_power_if_enabled(i915, power_domain, wakeref) {
3765 u32 tmp = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
3766
3767 if (!(tmp & ULTRA_JOINER_ENABLE))
3768 continue;
3769
3770 if (tmp & PRIMARY_ULTRA_JOINER_ENABLE)
3771 *primary_pipes |= BIT(pipe);
3772 else
3773 *secondary_pipes |= BIT(pipe);
3774 }
3775 }
3776}
3777
3778static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
3779 enum pipe pipe,
3780 u8 *primary_pipe, u8 *secondary_pipes)
3781{
3782 struct intel_display *display = to_intel_display(&dev_priv->drm);
3783 u8 primary_ultrajoiner_pipes;
3784 u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes;
3785 u8 secondary_ultrajoiner_pipes;
3786 u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes;
3787 u8 ultrajoiner_pipes;
3788 u8 uncompressed_joiner_pipes, bigjoiner_pipes;
3789
3790 enabled_ultrajoiner_pipes(dev_priv, &primary_ultrajoiner_pipes,
3791 &secondary_ultrajoiner_pipes);
3792 /*
3793 * For some strange reason the last pipe in the set of four
3794 * shouldn't have ultrajoiner enable bit set in hardware.
3795 * Set the bit anyway to make life easier.
3796 */
3797 drm_WARN_ON(&dev_priv->drm,
3798 expected_secondary_pipes(primary_ultrajoiner_pipes, 3) !=
3799 secondary_ultrajoiner_pipes);
3800 secondary_ultrajoiner_pipes =
3801 fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes,
3802 secondary_ultrajoiner_pipes);
3803
3804 drm_WARN_ON(&dev_priv->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);
3805
3806 enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes,
3807 &secondary_uncompressed_joiner_pipes);
3808
3809 drm_WARN_ON(display->drm,
3810 (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0);
3811
3812 enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes,
3813 &secondary_bigjoiner_pipes);
3814
3815 drm_WARN_ON(display->drm,
3816 (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0);
3817
3818 ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes;
3819 uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes |
3820 secondary_uncompressed_joiner_pipes;
3821 bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes;
3822
3823 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,
3824 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n",
3825 ultrajoiner_pipes, bigjoiner_pipes);
3826
3827 drm_WARN(display->drm, secondary_ultrajoiner_pipes !=
3828 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3829 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n",
3830 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3831 secondary_ultrajoiner_pipes);
3832
3833 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,
3834 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n",
3835 uncompressed_joiner_pipes, bigjoiner_pipes);
3836
3837 drm_WARN(display->drm, secondary_bigjoiner_pipes !=
3838 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3839 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n",
3840 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3841 secondary_bigjoiner_pipes);
3842
3843 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=
3844 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3845 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n",
3846 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3847 secondary_uncompressed_joiner_pipes);
3848
3849 *primary_pipe = 0;
3850 *secondary_pipes = 0;
3851
3852 if (ultrajoiner_pipes & BIT(pipe)) {
3853 *primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes);
3854 *secondary_pipes = secondary_ultrajoiner_pipes &
3855 expected_ultrajoiner_secondary_pipes(*primary_pipe);
3856
3857 drm_WARN(display->drm,
3858 expected_ultrajoiner_secondary_pipes(*primary_pipe) !=
3859 *secondary_pipes,
3860 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3861 *primary_pipe,
3862 expected_ultrajoiner_secondary_pipes(*primary_pipe),
3863 *secondary_pipes);
3864 return;
3865 }
3866
3867 if (uncompressed_joiner_pipes & BIT(pipe)) {
3868 *primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes);
3869 *secondary_pipes = secondary_uncompressed_joiner_pipes &
3870 expected_uncompressed_joiner_secondary_pipes(*primary_pipe);
3871
3872 drm_WARN(display->drm,
3873 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) !=
3874 *secondary_pipes,
3875 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3876 *primary_pipe,
3877 expected_uncompressed_joiner_secondary_pipes(*primary_pipe),
3878 *secondary_pipes);
3879 return;
3880 }
3881
3882 if (bigjoiner_pipes & BIT(pipe)) {
3883 *primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes);
3884 *secondary_pipes = secondary_bigjoiner_pipes &
3885 expected_bigjoiner_secondary_pipes(*primary_pipe);
3886
3887 drm_WARN(display->drm,
3888 expected_bigjoiner_secondary_pipes(*primary_pipe) !=
3889 *secondary_pipes,
3890 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3891 *primary_pipe,
3892 expected_bigjoiner_secondary_pipes(*primary_pipe),
3893 *secondary_pipes);
3894 return;
3895 }
3896}
3897
3898static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3899{
3900 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3901
3902 if (DISPLAY_VER(i915) >= 11)
3903 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3904
3905 return panel_transcoder_mask;
3906}
3907
3908static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3909{
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = to_i915(dev);
3912 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3913 enum transcoder cpu_transcoder;
3914 u8 primary_pipe, secondary_pipes;
3915 u8 enabled_transcoders = 0;
3916
3917 /*
3918 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3919 * consistency and less surprising code; it's in always on power).
3920 */
3921 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3922 panel_transcoder_mask) {
3923 enum intel_display_power_domain power_domain;
3924 intel_wakeref_t wakeref;
3925 enum pipe trans_pipe;
3926 u32 tmp = 0;
3927
3928 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3929 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3930 tmp = intel_de_read(dev_priv,
3931 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
3932
3933 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3934 continue;
3935
3936 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3937 default:
3938 drm_WARN(dev, 1,
3939 "unknown pipe linked to transcoder %s\n",
3940 transcoder_name(cpu_transcoder));
3941 fallthrough;
3942 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3943 case TRANS_DDI_EDP_INPUT_A_ON:
3944 trans_pipe = PIPE_A;
3945 break;
3946 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3947 trans_pipe = PIPE_B;
3948 break;
3949 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3950 trans_pipe = PIPE_C;
3951 break;
3952 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3953 trans_pipe = PIPE_D;
3954 break;
3955 }
3956
3957 if (trans_pipe == crtc->pipe)
3958 enabled_transcoders |= BIT(cpu_transcoder);
3959 }
3960
3961 /* single pipe or joiner primary */
3962 cpu_transcoder = (enum transcoder) crtc->pipe;
3963 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3964 enabled_transcoders |= BIT(cpu_transcoder);
3965
3966 /* joiner secondary -> consider the primary pipe's transcoder as well */
3967 enabled_joiner_pipes(dev_priv, crtc->pipe, &primary_pipe, &secondary_pipes);
3968 if (secondary_pipes & BIT(crtc->pipe)) {
3969 cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;
3970 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3971 enabled_transcoders |= BIT(cpu_transcoder);
3972 }
3973
3974 return enabled_transcoders;
3975}
3976
3977static bool has_edp_transcoders(u8 enabled_transcoders)
3978{
3979 return enabled_transcoders & BIT(TRANSCODER_EDP);
3980}
3981
3982static bool has_dsi_transcoders(u8 enabled_transcoders)
3983{
3984 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3985 BIT(TRANSCODER_DSI_1));
3986}
3987
3988static bool has_pipe_transcoders(u8 enabled_transcoders)
3989{
3990 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3991 BIT(TRANSCODER_DSI_0) |
3992 BIT(TRANSCODER_DSI_1));
3993}
3994
3995static void assert_enabled_transcoders(struct drm_i915_private *i915,
3996 u8 enabled_transcoders)
3997{
3998 /* Only one type of transcoder please */
3999 drm_WARN_ON(&i915->drm,
4000 has_edp_transcoders(enabled_transcoders) +
4001 has_dsi_transcoders(enabled_transcoders) +
4002 has_pipe_transcoders(enabled_transcoders) > 1);
4003
4004 /* Only DSI transcoders can be ganged */
4005 drm_WARN_ON(&i915->drm,
4006 !has_dsi_transcoders(enabled_transcoders) &&
4007 !is_power_of_2(enabled_transcoders));
4008}
4009
4010static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
4011 struct intel_crtc_state *pipe_config,
4012 struct intel_display_power_domain_set *power_domain_set)
4013{
4014 struct drm_device *dev = crtc->base.dev;
4015 struct drm_i915_private *dev_priv = to_i915(dev);
4016 unsigned long enabled_transcoders;
4017 u32 tmp;
4018
4019 enabled_transcoders = hsw_enabled_transcoders(crtc);
4020 if (!enabled_transcoders)
4021 return false;
4022
4023 assert_enabled_transcoders(dev_priv, enabled_transcoders);
4024
4025 /*
4026 * With the exception of DSI we should only ever have
4027 * a single enabled transcoder. With DSI let's just
4028 * pick the first one.
4029 */
4030 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
4031
4032 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
4033 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
4034 return false;
4035
4036 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
4037 tmp = intel_de_read(dev_priv,
4038 TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));
4039
4040 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
4041 pipe_config->pch_pfit.force_thru = true;
4042 }
4043
4044 tmp = intel_de_read(dev_priv,
4045 TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
4046
4047 return tmp & TRANSCONF_ENABLE;
4048}
4049
4050static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
4051 struct intel_crtc_state *pipe_config,
4052 struct intel_display_power_domain_set *power_domain_set)
4053{
4054 struct intel_display *display = to_intel_display(crtc);
4055 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4056 enum transcoder cpu_transcoder;
4057 enum port port;
4058 u32 tmp;
4059
4060 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
4061 if (port == PORT_A)
4062 cpu_transcoder = TRANSCODER_DSI_A;
4063 else
4064 cpu_transcoder = TRANSCODER_DSI_C;
4065
4066 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
4067 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
4068 continue;
4069
4070 /*
4071 * The PLL needs to be enabled with a valid divider
4072 * configuration, otherwise accessing DSI registers will hang
4073 * the machine. See BSpec North Display Engine
4074 * registers/MIPI[BXT]. We can break out here early, since we
4075 * need the same DSI PLL to be enabled for both DSI ports.
4076 */
4077 if (!bxt_dsi_pll_is_enabled(dev_priv))
4078 break;
4079
4080 /* XXX: this works for video mode only */
4081 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
4082 if (!(tmp & DPI_ENABLE))
4083 continue;
4084
4085 tmp = intel_de_read(display, MIPI_CTRL(display, port));
4086 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
4087 continue;
4088
4089 pipe_config->cpu_transcoder = cpu_transcoder;
4090 break;
4091 }
4092
4093 return transcoder_is_dsi(pipe_config->cpu_transcoder);
4094}
4095
4096static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
4097{
4098 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4099 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4100 u8 primary_pipe, secondary_pipes;
4101 enum pipe pipe = crtc->pipe;
4102
4103 enabled_joiner_pipes(i915, pipe, &primary_pipe, &secondary_pipes);
4104
4105 if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)
4106 return;
4107
4108 crtc_state->joiner_pipes = primary_pipe | secondary_pipes;
4109}
4110
4111static bool hsw_get_pipe_config(struct intel_crtc *crtc,
4112 struct intel_crtc_state *pipe_config)
4113{
4114 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4115 bool active;
4116 u32 tmp;
4117
4118 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
4119 POWER_DOMAIN_PIPE(crtc->pipe)))
4120 return false;
4121
4122 pipe_config->shared_dpll = NULL;
4123
4124 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
4125
4126 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4127 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
4128 drm_WARN_ON(&dev_priv->drm, active);
4129 active = true;
4130 }
4131
4132 if (!active)
4133 goto out;
4134
4135 intel_joiner_get_config(pipe_config);
4136 intel_dsc_get_config(pipe_config);
4137
4138 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
4139 DISPLAY_VER(dev_priv) >= 11)
4140 intel_get_transcoder_timings(crtc, pipe_config);
4141
4142 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
4143 intel_vrr_get_config(pipe_config);
4144
4145 intel_get_pipe_src_size(crtc, pipe_config);
4146
4147 if (IS_HASWELL(dev_priv)) {
4148 u32 tmp = intel_de_read(dev_priv,
4149 TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
4150
4151 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
4152 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
4153 else
4154 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
4155 } else {
4156 pipe_config->output_format =
4157 bdw_get_pipe_misc_output_format(crtc);
4158 }
4159
4160 pipe_config->sink_format = pipe_config->output_format;
4161
4162 intel_color_get_config(pipe_config);
4163
4164 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
4165 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
4166 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4167 pipe_config->ips_linetime =
4168 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
4169
4170 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
4171 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4172 if (DISPLAY_VER(dev_priv) >= 9)
4173 skl_scaler_get_config(pipe_config);
4174 else
4175 ilk_get_pfit_config(pipe_config);
4176 }
4177
4178 hsw_ips_get_config(pipe_config);
4179
4180 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4181 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4182 pipe_config->pixel_multiplier =
4183 intel_de_read(dev_priv,
4184 TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;
4185 } else {
4186 pipe_config->pixel_multiplier = 1;
4187 }
4188
4189 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4190 tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));
4191
4192 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
4193 } else {
4194 /* no idea if this is correct */
4195 pipe_config->framestart_delay = 1;
4196 }
4197
4198out:
4199 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
4200
4201 return active;
4202}
4203
4204bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4205{
4206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4207 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4208
4209 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
4210 return false;
4211
4212 crtc_state->hw.active = true;
4213
4214 intel_crtc_readout_derived_state(crtc_state);
4215
4216 return true;
4217}
4218
4219int intel_dotclock_calculate(int link_freq,
4220 const struct intel_link_m_n *m_n)
4221{
4222 /*
4223 * The calculation for the data clock -> pixel clock is:
4224 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4225 * But we want to avoid losing precison if possible, so:
4226 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4227 *
4228 * and for link freq (10kbs units) -> pixel clock it is:
4229 * link_symbol_clock = link_freq * 10 / link_symbol_size
4230 * pixel_clock = (m * link_symbol_clock) / n
4231 * or for more precision:
4232 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
4233 */
4234
4235 if (!m_n->link_n)
4236 return 0;
4237
4238 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
4239 m_n->link_n * intel_dp_link_symbol_size(link_freq));
4240}
4241
4242int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4243{
4244 int dotclock;
4245
4246 if (intel_crtc_has_dp_encoder(pipe_config))
4247 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
4248 &pipe_config->dp_m_n);
4249 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4250 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4251 pipe_config->pipe_bpp);
4252 else
4253 dotclock = pipe_config->port_clock;
4254
4255 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4256 !intel_crtc_has_dp_encoder(pipe_config))
4257 dotclock *= 2;
4258
4259 if (pipe_config->pixel_multiplier)
4260 dotclock /= pipe_config->pixel_multiplier;
4261
4262 return dotclock;
4263}
4264
4265/* Returns the currently programmed mode of the given encoder. */
4266struct drm_display_mode *
4267intel_encoder_current_mode(struct intel_encoder *encoder)
4268{
4269 struct intel_display *display = to_intel_display(encoder);
4270 struct intel_crtc_state *crtc_state;
4271 struct drm_display_mode *mode;
4272 struct intel_crtc *crtc;
4273 enum pipe pipe;
4274
4275 if (!encoder->get_hw_state(encoder, &pipe))
4276 return NULL;
4277
4278 crtc = intel_crtc_for_pipe(display, pipe);
4279
4280 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4281 if (!mode)
4282 return NULL;
4283
4284 crtc_state = intel_crtc_state_alloc(crtc);
4285 if (!crtc_state) {
4286 kfree(mode);
4287 return NULL;
4288 }
4289
4290 if (!intel_crtc_get_pipe_config(crtc_state)) {
4291 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4292 kfree(mode);
4293 return NULL;
4294 }
4295
4296 intel_encoder_get_config(encoder, crtc_state);
4297
4298 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4299
4300 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4301
4302 return mode;
4303}
4304
4305static bool encoders_cloneable(const struct intel_encoder *a,
4306 const struct intel_encoder *b)
4307{
4308 /* masks could be asymmetric, so check both ways */
4309 return a == b || (a->cloneable & BIT(b->type) &&
4310 b->cloneable & BIT(a->type));
4311}
4312
4313static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4314 struct intel_crtc *crtc,
4315 struct intel_encoder *encoder)
4316{
4317 struct intel_encoder *source_encoder;
4318 struct drm_connector *connector;
4319 struct drm_connector_state *connector_state;
4320 int i;
4321
4322 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4323 if (connector_state->crtc != &crtc->base)
4324 continue;
4325
4326 source_encoder =
4327 to_intel_encoder(connector_state->best_encoder);
4328 if (!encoders_cloneable(encoder, source_encoder))
4329 return false;
4330 }
4331
4332 return true;
4333}
4334
4335static int icl_add_linked_planes(struct intel_atomic_state *state)
4336{
4337 struct intel_plane *plane, *linked;
4338 struct intel_plane_state *plane_state, *linked_plane_state;
4339 int i;
4340
4341 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4342 linked = plane_state->planar_linked_plane;
4343
4344 if (!linked)
4345 continue;
4346
4347 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4348 if (IS_ERR(linked_plane_state))
4349 return PTR_ERR(linked_plane_state);
4350
4351 drm_WARN_ON(state->base.dev,
4352 linked_plane_state->planar_linked_plane != plane);
4353 drm_WARN_ON(state->base.dev,
4354 linked_plane_state->planar_slave == plane_state->planar_slave);
4355 }
4356
4357 return 0;
4358}
4359
4360static int icl_check_nv12_planes(struct intel_atomic_state *state,
4361 struct intel_crtc *crtc)
4362{
4363 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4364 struct intel_crtc_state *crtc_state =
4365 intel_atomic_get_new_crtc_state(state, crtc);
4366 struct intel_plane *plane, *linked;
4367 struct intel_plane_state *plane_state;
4368 int i;
4369
4370 if (DISPLAY_VER(dev_priv) < 11)
4371 return 0;
4372
4373 /*
4374 * Destroy all old plane links and make the slave plane invisible
4375 * in the crtc_state->active_planes mask.
4376 */
4377 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4378 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4379 continue;
4380
4381 plane_state->planar_linked_plane = NULL;
4382 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4383 crtc_state->enabled_planes &= ~BIT(plane->id);
4384 crtc_state->active_planes &= ~BIT(plane->id);
4385 crtc_state->update_planes |= BIT(plane->id);
4386 crtc_state->data_rate[plane->id] = 0;
4387 crtc_state->rel_data_rate[plane->id] = 0;
4388 }
4389
4390 plane_state->planar_slave = false;
4391 }
4392
4393 if (!crtc_state->nv12_planes)
4394 return 0;
4395
4396 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4397 struct intel_plane_state *linked_state = NULL;
4398
4399 if (plane->pipe != crtc->pipe ||
4400 !(crtc_state->nv12_planes & BIT(plane->id)))
4401 continue;
4402
4403 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4404 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4405 continue;
4406
4407 if (crtc_state->active_planes & BIT(linked->id))
4408 continue;
4409
4410 linked_state = intel_atomic_get_plane_state(state, linked);
4411 if (IS_ERR(linked_state))
4412 return PTR_ERR(linked_state);
4413
4414 break;
4415 }
4416
4417 if (!linked_state) {
4418 drm_dbg_kms(&dev_priv->drm,
4419 "Need %d free Y planes for planar YUV\n",
4420 hweight8(crtc_state->nv12_planes));
4421
4422 return -EINVAL;
4423 }
4424
4425 plane_state->planar_linked_plane = linked;
4426
4427 linked_state->planar_slave = true;
4428 linked_state->planar_linked_plane = plane;
4429 crtc_state->enabled_planes |= BIT(linked->id);
4430 crtc_state->active_planes |= BIT(linked->id);
4431 crtc_state->update_planes |= BIT(linked->id);
4432 crtc_state->data_rate[linked->id] =
4433 crtc_state->data_rate_y[plane->id];
4434 crtc_state->rel_data_rate[linked->id] =
4435 crtc_state->rel_data_rate_y[plane->id];
4436 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4437 linked->base.name, plane->base.name);
4438
4439 /* Copy parameters to slave plane */
4440 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4441 linked_state->color_ctl = plane_state->color_ctl;
4442 linked_state->view = plane_state->view;
4443 linked_state->decrypt = plane_state->decrypt;
4444
4445 intel_plane_copy_hw_state(linked_state, plane_state);
4446 linked_state->uapi.src = plane_state->uapi.src;
4447 linked_state->uapi.dst = plane_state->uapi.dst;
4448
4449 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4450 if (linked->id == PLANE_7)
4451 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4452 else if (linked->id == PLANE_6)
4453 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4454 else if (linked->id == PLANE_5)
4455 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4456 else if (linked->id == PLANE_4)
4457 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4458 else
4459 MISSING_CASE(linked->id);
4460 }
4461 }
4462
4463 return 0;
4464}
4465
4466static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4467{
4468 const struct drm_display_mode *pipe_mode =
4469 &crtc_state->hw.pipe_mode;
4470 int linetime_wm;
4471
4472 if (!crtc_state->hw.enable)
4473 return 0;
4474
4475 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4476 pipe_mode->crtc_clock);
4477
4478 return min(linetime_wm, 0x1ff);
4479}
4480
4481static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4482 const struct intel_cdclk_state *cdclk_state)
4483{
4484 const struct drm_display_mode *pipe_mode =
4485 &crtc_state->hw.pipe_mode;
4486 int linetime_wm;
4487
4488 if (!crtc_state->hw.enable)
4489 return 0;
4490
4491 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4492 cdclk_state->logical.cdclk);
4493
4494 return min(linetime_wm, 0x1ff);
4495}
4496
4497static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4498{
4499 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4501 const struct drm_display_mode *pipe_mode =
4502 &crtc_state->hw.pipe_mode;
4503 int linetime_wm;
4504
4505 if (!crtc_state->hw.enable)
4506 return 0;
4507
4508 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4509 crtc_state->pixel_rate);
4510
4511 /* Display WA #1135: BXT:ALL GLK:ALL */
4512 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4513 skl_watermark_ipc_enabled(dev_priv))
4514 linetime_wm /= 2;
4515
4516 return min(linetime_wm, 0x1ff);
4517}
4518
4519static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4520 struct intel_crtc *crtc)
4521{
4522 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4523 struct intel_crtc_state *crtc_state =
4524 intel_atomic_get_new_crtc_state(state, crtc);
4525 const struct intel_cdclk_state *cdclk_state;
4526
4527 if (DISPLAY_VER(dev_priv) >= 9)
4528 crtc_state->linetime = skl_linetime_wm(crtc_state);
4529 else
4530 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4531
4532 if (!hsw_crtc_supports_ips(crtc))
4533 return 0;
4534
4535 cdclk_state = intel_atomic_get_cdclk_state(state);
4536 if (IS_ERR(cdclk_state))
4537 return PTR_ERR(cdclk_state);
4538
4539 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4540 cdclk_state);
4541
4542 return 0;
4543}
4544
4545static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4546 struct intel_crtc *crtc)
4547{
4548 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4549 struct intel_crtc_state *crtc_state =
4550 intel_atomic_get_new_crtc_state(state, crtc);
4551 int ret;
4552
4553 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4554 intel_crtc_needs_modeset(crtc_state) &&
4555 !crtc_state->hw.active)
4556 crtc_state->update_wm_post = true;
4557
4558 if (intel_crtc_needs_modeset(crtc_state)) {
4559 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4560 if (ret)
4561 return ret;
4562 }
4563
4564 ret = intel_color_check(state, crtc);
4565 if (ret)
4566 return ret;
4567
4568 ret = intel_wm_compute(state, crtc);
4569 if (ret) {
4570 drm_dbg_kms(&dev_priv->drm,
4571 "[CRTC:%d:%s] watermarks are invalid\n",
4572 crtc->base.base.id, crtc->base.name);
4573 return ret;
4574 }
4575
4576 if (DISPLAY_VER(dev_priv) >= 9) {
4577 if (intel_crtc_needs_modeset(crtc_state) ||
4578 intel_crtc_needs_fastset(crtc_state)) {
4579 ret = skl_update_scaler_crtc(crtc_state);
4580 if (ret)
4581 return ret;
4582 }
4583
4584 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4585 if (ret)
4586 return ret;
4587 }
4588
4589 if (HAS_IPS(dev_priv)) {
4590 ret = hsw_ips_compute_config(state, crtc);
4591 if (ret)
4592 return ret;
4593 }
4594
4595 if (DISPLAY_VER(dev_priv) >= 9 ||
4596 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4597 ret = hsw_compute_linetime_wm(state, crtc);
4598 if (ret)
4599 return ret;
4600
4601 }
4602
4603 ret = intel_psr2_sel_fetch_update(state, crtc);
4604 if (ret)
4605 return ret;
4606
4607 return 0;
4608}
4609
4610static int
4611compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4612 struct intel_crtc_state *crtc_state)
4613{
4614 struct drm_connector *connector = conn_state->connector;
4615 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4616 const struct drm_display_info *info = &connector->display_info;
4617 int bpp;
4618
4619 switch (conn_state->max_bpc) {
4620 case 6 ... 7:
4621 bpp = 6 * 3;
4622 break;
4623 case 8 ... 9:
4624 bpp = 8 * 3;
4625 break;
4626 case 10 ... 11:
4627 bpp = 10 * 3;
4628 break;
4629 case 12 ... 16:
4630 bpp = 12 * 3;
4631 break;
4632 default:
4633 MISSING_CASE(conn_state->max_bpc);
4634 return -EINVAL;
4635 }
4636
4637 if (bpp < crtc_state->pipe_bpp) {
4638 drm_dbg_kms(&i915->drm,
4639 "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4640 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4641 connector->base.id, connector->name,
4642 bpp, 3 * info->bpc,
4643 3 * conn_state->max_requested_bpc,
4644 crtc_state->pipe_bpp);
4645
4646 crtc_state->pipe_bpp = bpp;
4647 }
4648
4649 return 0;
4650}
4651
4652static int
4653compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4654 struct intel_crtc *crtc)
4655{
4656 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4657 struct intel_crtc_state *crtc_state =
4658 intel_atomic_get_new_crtc_state(state, crtc);
4659 struct drm_connector *connector;
4660 struct drm_connector_state *connector_state;
4661 int bpp, i;
4662
4663 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4664 IS_CHERRYVIEW(dev_priv)))
4665 bpp = 10*3;
4666 else if (DISPLAY_VER(dev_priv) >= 5)
4667 bpp = 12*3;
4668 else
4669 bpp = 8*3;
4670
4671 crtc_state->pipe_bpp = bpp;
4672
4673 /* Clamp display bpp to connector max bpp */
4674 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4675 int ret;
4676
4677 if (connector_state->crtc != &crtc->base)
4678 continue;
4679
4680 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4681 if (ret)
4682 return ret;
4683 }
4684
4685 return 0;
4686}
4687
4688static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4689{
4690 struct drm_device *dev = state->base.dev;
4691 struct drm_connector *connector;
4692 struct drm_connector_list_iter conn_iter;
4693 unsigned int used_ports = 0;
4694 unsigned int used_mst_ports = 0;
4695 bool ret = true;
4696
4697 /*
4698 * We're going to peek into connector->state,
4699 * hence connection_mutex must be held.
4700 */
4701 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4702
4703 /*
4704 * Walk the connector list instead of the encoder
4705 * list to detect the problem on ddi platforms
4706 * where there's just one encoder per digital port.
4707 */
4708 drm_connector_list_iter_begin(dev, &conn_iter);
4709 drm_for_each_connector_iter(connector, &conn_iter) {
4710 struct drm_connector_state *connector_state;
4711 struct intel_encoder *encoder;
4712
4713 connector_state =
4714 drm_atomic_get_new_connector_state(&state->base,
4715 connector);
4716 if (!connector_state)
4717 connector_state = connector->state;
4718
4719 if (!connector_state->best_encoder)
4720 continue;
4721
4722 encoder = to_intel_encoder(connector_state->best_encoder);
4723
4724 drm_WARN_ON(dev, !connector_state->crtc);
4725
4726 switch (encoder->type) {
4727 case INTEL_OUTPUT_DDI:
4728 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4729 break;
4730 fallthrough;
4731 case INTEL_OUTPUT_DP:
4732 case INTEL_OUTPUT_HDMI:
4733 case INTEL_OUTPUT_EDP:
4734 /* the same port mustn't appear more than once */
4735 if (used_ports & BIT(encoder->port))
4736 ret = false;
4737
4738 used_ports |= BIT(encoder->port);
4739 break;
4740 case INTEL_OUTPUT_DP_MST:
4741 used_mst_ports |=
4742 1 << encoder->port;
4743 break;
4744 default:
4745 break;
4746 }
4747 }
4748 drm_connector_list_iter_end(&conn_iter);
4749
4750 /* can't mix MST and SST/HDMI on the same port */
4751 if (used_ports & used_mst_ports)
4752 return false;
4753
4754 return ret;
4755}
4756
4757static void
4758intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4759 struct intel_crtc *crtc)
4760{
4761 struct intel_crtc_state *crtc_state =
4762 intel_atomic_get_new_crtc_state(state, crtc);
4763
4764 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4765
4766 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4767 crtc_state->uapi.degamma_lut);
4768 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4769 crtc_state->uapi.gamma_lut);
4770 drm_property_replace_blob(&crtc_state->hw.ctm,
4771 crtc_state->uapi.ctm);
4772}
4773
4774static void
4775intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4776 struct intel_crtc *crtc)
4777{
4778 struct intel_crtc_state *crtc_state =
4779 intel_atomic_get_new_crtc_state(state, crtc);
4780
4781 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4782
4783 crtc_state->hw.enable = crtc_state->uapi.enable;
4784 crtc_state->hw.active = crtc_state->uapi.active;
4785 drm_mode_copy(&crtc_state->hw.mode,
4786 &crtc_state->uapi.mode);
4787 drm_mode_copy(&crtc_state->hw.adjusted_mode,
4788 &crtc_state->uapi.adjusted_mode);
4789 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4790
4791 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4792}
4793
4794static void
4795copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4796 struct intel_crtc *secondary_crtc)
4797{
4798 struct intel_crtc_state *secondary_crtc_state =
4799 intel_atomic_get_new_crtc_state(state, secondary_crtc);
4800 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
4801 const struct intel_crtc_state *primary_crtc_state =
4802 intel_atomic_get_new_crtc_state(state, primary_crtc);
4803
4804 drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,
4805 primary_crtc_state->hw.degamma_lut);
4806 drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,
4807 primary_crtc_state->hw.gamma_lut);
4808 drm_property_replace_blob(&secondary_crtc_state->hw.ctm,
4809 primary_crtc_state->hw.ctm);
4810
4811 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
4812}
4813
4814static int
4815copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
4816 struct intel_crtc *secondary_crtc)
4817{
4818 struct intel_crtc_state *secondary_crtc_state =
4819 intel_atomic_get_new_crtc_state(state, secondary_crtc);
4820 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
4821 const struct intel_crtc_state *primary_crtc_state =
4822 intel_atomic_get_new_crtc_state(state, primary_crtc);
4823 struct intel_crtc_state *saved_state;
4824
4825 WARN_ON(primary_crtc_state->joiner_pipes !=
4826 secondary_crtc_state->joiner_pipes);
4827
4828 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4829 if (!saved_state)
4830 return -ENOMEM;
4831
4832 /* preserve some things from the slave's original crtc state */
4833 saved_state->uapi = secondary_crtc_state->uapi;
4834 saved_state->scaler_state = secondary_crtc_state->scaler_state;
4835 saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
4836 saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
4837
4838 intel_crtc_free_hw_state(secondary_crtc_state);
4839 if (secondary_crtc_state->dp_tunnel_ref.tunnel)
4840 drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);
4841 memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state));
4842 kfree(saved_state);
4843
4844 /* Re-init hw state */
4845 memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));
4846 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
4847 secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
4848 drm_mode_copy(&secondary_crtc_state->hw.mode,
4849 &primary_crtc_state->hw.mode);
4850 drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,
4851 &primary_crtc_state->hw.pipe_mode);
4852 drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,
4853 &primary_crtc_state->hw.adjusted_mode);
4854 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;
4855
4856 if (primary_crtc_state->dp_tunnel_ref.tunnel)
4857 drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,
4858 &secondary_crtc_state->dp_tunnel_ref);
4859
4860 copy_joiner_crtc_state_nomodeset(state, secondary_crtc);
4861
4862 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
4863 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
4864 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;
4865
4866 WARN_ON(primary_crtc_state->joiner_pipes !=
4867 secondary_crtc_state->joiner_pipes);
4868
4869 return 0;
4870}
4871
4872static int
4873intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4874 struct intel_crtc *crtc)
4875{
4876 struct intel_crtc_state *crtc_state =
4877 intel_atomic_get_new_crtc_state(state, crtc);
4878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4879 struct intel_crtc_state *saved_state;
4880
4881 saved_state = intel_crtc_state_alloc(crtc);
4882 if (!saved_state)
4883 return -ENOMEM;
4884
4885 /* free the old crtc_state->hw members */
4886 intel_crtc_free_hw_state(crtc_state);
4887
4888 intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
4889
4890 /* FIXME: before the switch to atomic started, a new pipe_config was
4891 * kzalloc'd. Code that depends on any field being zero should be
4892 * fixed, so that the crtc_state can be safely duplicated. For now,
4893 * only fields that are know to not cause problems are preserved. */
4894
4895 saved_state->uapi = crtc_state->uapi;
4896 saved_state->inherited = crtc_state->inherited;
4897 saved_state->scaler_state = crtc_state->scaler_state;
4898 saved_state->shared_dpll = crtc_state->shared_dpll;
4899 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4900 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4901 sizeof(saved_state->icl_port_dplls));
4902 saved_state->crc_enabled = crtc_state->crc_enabled;
4903 if (IS_G4X(dev_priv) ||
4904 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4905 saved_state->wm = crtc_state->wm;
4906
4907 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4908 kfree(saved_state);
4909
4910 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4911
4912 return 0;
4913}
4914
4915static int
4916intel_modeset_pipe_config(struct intel_atomic_state *state,
4917 struct intel_crtc *crtc,
4918 const struct intel_link_bw_limits *limits)
4919{
4920 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4921 struct intel_crtc_state *crtc_state =
4922 intel_atomic_get_new_crtc_state(state, crtc);
4923 struct drm_connector *connector;
4924 struct drm_connector_state *connector_state;
4925 int pipe_src_w, pipe_src_h;
4926 int base_bpp, ret, i;
4927
4928 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4929
4930 crtc_state->framestart_delay = 1;
4931
4932 /*
4933 * Sanitize sync polarity flags based on requested ones. If neither
4934 * positive or negative polarity is requested, treat this as meaning
4935 * negative polarity.
4936 */
4937 if (!(crtc_state->hw.adjusted_mode.flags &
4938 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4939 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4940
4941 if (!(crtc_state->hw.adjusted_mode.flags &
4942 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4943 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4944
4945 ret = compute_baseline_pipe_bpp(state, crtc);
4946 if (ret)
4947 return ret;
4948
4949 crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
4950 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4951
4952 if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
4953 drm_dbg_kms(&i915->drm,
4954 "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
4955 crtc->base.base.id, crtc->base.name,
4956 FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
4957 crtc_state->bw_constrained = true;
4958 }
4959
4960 base_bpp = crtc_state->pipe_bpp;
4961
4962 /*
4963 * Determine the real pipe dimensions. Note that stereo modes can
4964 * increase the actual pipe size due to the frame doubling and
4965 * insertion of additional space for blanks between the frame. This
4966 * is stored in the crtc timings. We use the requested mode to do this
4967 * computation to clearly distinguish it from the adjusted mode, which
4968 * can be changed by the connectors in the below retry loop.
4969 */
4970 drm_mode_get_hv_timing(&crtc_state->hw.mode,
4971 &pipe_src_w, &pipe_src_h);
4972 drm_rect_init(&crtc_state->pipe_src, 0, 0,
4973 pipe_src_w, pipe_src_h);
4974
4975 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4976 struct intel_encoder *encoder =
4977 to_intel_encoder(connector_state->best_encoder);
4978
4979 if (connector_state->crtc != &crtc->base)
4980 continue;
4981
4982 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4983 drm_dbg_kms(&i915->drm,
4984 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4985 encoder->base.base.id, encoder->base.name);
4986 return -EINVAL;
4987 }
4988
4989 /*
4990 * Determine output_types before calling the .compute_config()
4991 * hooks so that the hooks can use this information safely.
4992 */
4993 if (encoder->compute_output_type)
4994 crtc_state->output_types |=
4995 BIT(encoder->compute_output_type(encoder, crtc_state,
4996 connector_state));
4997 else
4998 crtc_state->output_types |= BIT(encoder->type);
4999 }
5000
5001 /* Ensure the port clock defaults are reset when retrying. */
5002 crtc_state->port_clock = 0;
5003 crtc_state->pixel_multiplier = 1;
5004
5005 /* Fill in default crtc timings, allow encoders to overwrite them. */
5006 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5007 CRTC_STEREO_DOUBLE);
5008
5009 /* Pass our mode to the connectors and the CRTC to give them a chance to
5010 * adjust it according to limitations or connector properties, and also
5011 * a chance to reject the mode entirely.
5012 */
5013 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5014 struct intel_encoder *encoder =
5015 to_intel_encoder(connector_state->best_encoder);
5016
5017 if (connector_state->crtc != &crtc->base)
5018 continue;
5019
5020 ret = encoder->compute_config(encoder, crtc_state,
5021 connector_state);
5022 if (ret == -EDEADLK)
5023 return ret;
5024 if (ret < 0) {
5025 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5026 encoder->base.base.id, encoder->base.name, ret);
5027 return ret;
5028 }
5029 }
5030
5031 /* Set default port clock if not overwritten by the encoder. Needs to be
5032 * done afterwards in case the encoder adjusts the mode. */
5033 if (!crtc_state->port_clock)
5034 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5035 * crtc_state->pixel_multiplier;
5036
5037 ret = intel_crtc_compute_config(state, crtc);
5038 if (ret == -EDEADLK)
5039 return ret;
5040 if (ret < 0) {
5041 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5042 crtc->base.base.id, crtc->base.name, ret);
5043 return ret;
5044 }
5045
5046 /* Dithering seems to not pass-through bits correctly when it should, so
5047 * only enable it on 6bpc panels and when its not a compliance
5048 * test requesting 6bpc video pattern.
5049 */
5050 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5051 !crtc_state->dither_force_disable;
5052 drm_dbg_kms(&i915->drm,
5053 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5054 crtc->base.base.id, crtc->base.name,
5055 base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5056
5057 return 0;
5058}
5059
5060static int
5061intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5062 struct intel_crtc *crtc)
5063{
5064 struct intel_crtc_state *crtc_state =
5065 intel_atomic_get_new_crtc_state(state, crtc);
5066 struct drm_connector_state *conn_state;
5067 struct drm_connector *connector;
5068 int i;
5069
5070 intel_vrr_compute_config_late(crtc_state);
5071
5072 for_each_new_connector_in_state(&state->base, connector,
5073 conn_state, i) {
5074 struct intel_encoder *encoder =
5075 to_intel_encoder(conn_state->best_encoder);
5076 int ret;
5077
5078 if (conn_state->crtc != &crtc->base ||
5079 !encoder->compute_config_late)
5080 continue;
5081
5082 ret = encoder->compute_config_late(encoder, crtc_state,
5083 conn_state);
5084 if (ret)
5085 return ret;
5086 }
5087
5088 return 0;
5089}
5090
5091bool intel_fuzzy_clock_check(int clock1, int clock2)
5092{
5093 int diff;
5094
5095 if (clock1 == clock2)
5096 return true;
5097
5098 if (!clock1 || !clock2)
5099 return false;
5100
5101 diff = abs(clock1 - clock2);
5102
5103 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5104 return true;
5105
5106 return false;
5107}
5108
5109static bool
5110intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5111 const struct intel_link_m_n *m2_n2)
5112{
5113 return m_n->tu == m2_n2->tu &&
5114 m_n->data_m == m2_n2->data_m &&
5115 m_n->data_n == m2_n2->data_n &&
5116 m_n->link_m == m2_n2->link_m &&
5117 m_n->link_n == m2_n2->link_n;
5118}
5119
5120static bool
5121intel_compare_infoframe(const union hdmi_infoframe *a,
5122 const union hdmi_infoframe *b)
5123{
5124 return memcmp(a, b, sizeof(*a)) == 0;
5125}
5126
5127static bool
5128intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5129 const struct drm_dp_vsc_sdp *b)
5130{
5131 return a->pixelformat == b->pixelformat &&
5132 a->colorimetry == b->colorimetry &&
5133 a->bpc == b->bpc &&
5134 a->dynamic_range == b->dynamic_range &&
5135 a->content_type == b->content_type;
5136}
5137
5138static bool
5139intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
5140 const struct drm_dp_as_sdp *b)
5141{
5142 return a->vtotal == b->vtotal &&
5143 a->target_rr == b->target_rr &&
5144 a->duration_incr_ms == b->duration_incr_ms &&
5145 a->duration_decr_ms == b->duration_decr_ms &&
5146 a->mode == b->mode;
5147}
5148
5149static bool
5150intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
5151{
5152 return memcmp(a, b, len) == 0;
5153}
5154
5155static void __printf(5, 6)
5156pipe_config_mismatch(struct drm_printer *p, bool fastset,
5157 const struct intel_crtc *crtc,
5158 const char *name, const char *format, ...)
5159{
5160 struct va_format vaf;
5161 va_list args;
5162
5163 va_start(args, format);
5164 vaf.fmt = format;
5165 vaf.va = &args;
5166
5167 if (fastset)
5168 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
5169 crtc->base.base.id, crtc->base.name, name, &vaf);
5170 else
5171 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n",
5172 crtc->base.base.id, crtc->base.name, name, &vaf);
5173
5174 va_end(args);
5175}
5176
5177static void
5178pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
5179 const struct intel_crtc *crtc,
5180 const char *name,
5181 const union hdmi_infoframe *a,
5182 const union hdmi_infoframe *b)
5183{
5184 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5185 const char *loglevel;
5186
5187 if (fastset) {
5188 if (!drm_debug_enabled(DRM_UT_KMS))
5189 return;
5190
5191 loglevel = KERN_DEBUG;
5192 } else {
5193 loglevel = KERN_ERR;
5194 }
5195
5196 pipe_config_mismatch(p, fastset, crtc, name, "infoframe");
5197
5198 drm_printf(p, "expected:\n");
5199 hdmi_infoframe_log(loglevel, i915->drm.dev, a);
5200 drm_printf(p, "found:\n");
5201 hdmi_infoframe_log(loglevel, i915->drm.dev, b);
5202}
5203
5204static void
5205pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
5206 const struct intel_crtc *crtc,
5207 const char *name,
5208 const struct drm_dp_vsc_sdp *a,
5209 const struct drm_dp_vsc_sdp *b)
5210{
5211 pipe_config_mismatch(p, fastset, crtc, name, "dp sdp");
5212
5213 drm_printf(p, "expected:\n");
5214 drm_dp_vsc_sdp_log(p, a);
5215 drm_printf(p, "found:\n");
5216 drm_dp_vsc_sdp_log(p, b);
5217}
5218
5219static void
5220pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,
5221 bool fastset, const char *name,
5222 const struct drm_dp_as_sdp *a,
5223 const struct drm_dp_as_sdp *b)
5224{
5225 struct drm_printer p;
5226
5227 if (fastset) {
5228 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);
5229
5230 drm_printf(&p, "fastset requirement not met in %s dp sdp\n", name);
5231 } else {
5232 p = drm_err_printer(&i915->drm, NULL);
5233
5234 drm_printf(&p, "mismatch in %s dp sdp\n", name);
5235 }
5236
5237 drm_printf(&p, "expected:\n");
5238 drm_dp_as_sdp_log(&p, a);
5239 drm_printf(&p, "found:\n");
5240 drm_dp_as_sdp_log(&p, b);
5241}
5242
5243/* Returns the length up to and including the last differing byte */
5244static size_t
5245memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
5246{
5247 int i;
5248
5249 for (i = len - 1; i >= 0; i--) {
5250 if (a[i] != b[i])
5251 return i + 1;
5252 }
5253
5254 return 0;
5255}
5256
5257static void
5258pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
5259 const struct intel_crtc *crtc,
5260 const char *name,
5261 const u8 *a, const u8 *b, size_t len)
5262{
5263 const char *loglevel;
5264
5265 if (fastset) {
5266 if (!drm_debug_enabled(DRM_UT_KMS))
5267 return;
5268
5269 loglevel = KERN_DEBUG;
5270 } else {
5271 loglevel = KERN_ERR;
5272 }
5273
5274 pipe_config_mismatch(p, fastset, crtc, name, "buffer");
5275
5276 /* only dump up to the last difference */
5277 len = memcmp_diff_len(a, b, len);
5278
5279 print_hex_dump(loglevel, "expected: ", DUMP_PREFIX_NONE,
5280 16, 0, a, len, false);
5281 print_hex_dump(loglevel, "found: ", DUMP_PREFIX_NONE,
5282 16, 0, b, len, false);
5283}
5284
5285static void
5286pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
5287 const struct intel_crtc *crtc,
5288 const char *name,
5289 const struct intel_dpll_hw_state *a,
5290 const struct intel_dpll_hw_state *b)
5291{
5292 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5293
5294 pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
5295
5296 drm_printf(p, "expected:\n");
5297 intel_dpll_dump_hw_state(i915, p, a);
5298 drm_printf(p, "found:\n");
5299 intel_dpll_dump_hw_state(i915, p, b);
5300}
5301
5302static void
5303pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
5304 const struct intel_crtc *crtc,
5305 const char *name,
5306 const struct intel_cx0pll_state *a,
5307 const struct intel_cx0pll_state *b)
5308{
5309 struct intel_display *display = to_intel_display(crtc);
5310 char *chipname = a->use_c10 ? "C10" : "C20";
5311
5312 pipe_config_mismatch(p, fastset, crtc, name, chipname);
5313
5314 drm_printf(p, "expected:\n");
5315 intel_cx0pll_dump_hw_state(display, a);
5316 drm_printf(p, "found:\n");
5317 intel_cx0pll_dump_hw_state(display, b);
5318}
5319
5320bool
5321intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5322 const struct intel_crtc_state *pipe_config,
5323 bool fastset)
5324{
5325 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5326 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5327 struct drm_printer p;
5328 bool ret = true;
5329
5330 if (fastset)
5331 p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL);
5332 else
5333 p = drm_err_printer(&dev_priv->drm, NULL);
5334
5335#define PIPE_CONF_CHECK_X(name) do { \
5336 if (current_config->name != pipe_config->name) { \
5337 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5338 __stringify(name) " is bool"); \
5339 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5340 "(expected 0x%08x, found 0x%08x)", \
5341 current_config->name, \
5342 pipe_config->name); \
5343 ret = false; \
5344 } \
5345} while (0)
5346
5347#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5348 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5349 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5350 __stringify(name) " is bool"); \
5351 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5352 "(expected 0x%08x, found 0x%08x)", \
5353 current_config->name & (mask), \
5354 pipe_config->name & (mask)); \
5355 ret = false; \
5356 } \
5357} while (0)
5358
5359#define PIPE_CONF_CHECK_I(name) do { \
5360 if (current_config->name != pipe_config->name) { \
5361 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5362 __stringify(name) " is bool"); \
5363 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5364 "(expected %i, found %i)", \
5365 current_config->name, \
5366 pipe_config->name); \
5367 ret = false; \
5368 } \
5369} while (0)
5370
5371#define PIPE_CONF_CHECK_LLI(name) do { \
5372 if (current_config->name != pipe_config->name) { \
5373 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5374 "(expected %lli, found %lli)", \
5375 current_config->name, \
5376 pipe_config->name); \
5377 ret = false; \
5378 } \
5379} while (0)
5380
5381#define PIPE_CONF_CHECK_BOOL(name) do { \
5382 if (current_config->name != pipe_config->name) { \
5383 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
5384 __stringify(name) " is not bool"); \
5385 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5386 "(expected %s, found %s)", \
5387 str_yes_no(current_config->name), \
5388 str_yes_no(pipe_config->name)); \
5389 ret = false; \
5390 } \
5391} while (0)
5392
5393#define PIPE_CONF_CHECK_P(name) do { \
5394 if (current_config->name != pipe_config->name) { \
5395 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5396 "(expected %p, found %p)", \
5397 current_config->name, \
5398 pipe_config->name); \
5399 ret = false; \
5400 } \
5401} while (0)
5402
5403#define PIPE_CONF_CHECK_M_N(name) do { \
5404 if (!intel_compare_link_m_n(¤t_config->name, \
5405 &pipe_config->name)) { \
5406 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5407 "(expected tu %i data %i/%i link %i/%i, " \
5408 "found tu %i, data %i/%i link %i/%i)", \
5409 current_config->name.tu, \
5410 current_config->name.data_m, \
5411 current_config->name.data_n, \
5412 current_config->name.link_m, \
5413 current_config->name.link_n, \
5414 pipe_config->name.tu, \
5415 pipe_config->name.data_m, \
5416 pipe_config->name.data_n, \
5417 pipe_config->name.link_m, \
5418 pipe_config->name.link_n); \
5419 ret = false; \
5420 } \
5421} while (0)
5422
5423#define PIPE_CONF_CHECK_PLL(name) do { \
5424 if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
5425 &pipe_config->name)) { \
5426 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5427 ¤t_config->name, \
5428 &pipe_config->name); \
5429 ret = false; \
5430 } \
5431} while (0)
5432
5433#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
5434 if (!intel_cx0pll_compare_hw_state(¤t_config->name, \
5435 &pipe_config->name)) { \
5436 pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
5437 ¤t_config->name, \
5438 &pipe_config->name); \
5439 ret = false; \
5440 } \
5441} while (0)
5442
5443#define PIPE_CONF_CHECK_TIMINGS(name) do { \
5444 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5445 PIPE_CONF_CHECK_I(name.crtc_htotal); \
5446 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5447 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5448 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5449 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5450 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5451 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5452 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5453 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5454 if (!fastset || !pipe_config->update_lrr) { \
5455 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5456 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5457 } \
5458} while (0)
5459
5460#define PIPE_CONF_CHECK_RECT(name) do { \
5461 PIPE_CONF_CHECK_I(name.x1); \
5462 PIPE_CONF_CHECK_I(name.x2); \
5463 PIPE_CONF_CHECK_I(name.y1); \
5464 PIPE_CONF_CHECK_I(name.y2); \
5465} while (0)
5466
5467#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5468 if ((current_config->name ^ pipe_config->name) & (mask)) { \
5469 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5470 "(%x) (expected %i, found %i)", \
5471 (mask), \
5472 current_config->name & (mask), \
5473 pipe_config->name & (mask)); \
5474 ret = false; \
5475 } \
5476} while (0)
5477
5478#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5479 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
5480 &pipe_config->infoframes.name)) { \
5481 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5482 ¤t_config->infoframes.name, \
5483 &pipe_config->infoframes.name); \
5484 ret = false; \
5485 } \
5486} while (0)
5487
5488#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5489 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
5490 &pipe_config->infoframes.name)) { \
5491 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5492 ¤t_config->infoframes.name, \
5493 &pipe_config->infoframes.name); \
5494 ret = false; \
5495 } \
5496} while (0)
5497
5498#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
5499 if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \
5500 &pipe_config->infoframes.name)) { \
5501 pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5502 ¤t_config->infoframes.name, \
5503 &pipe_config->infoframes.name); \
5504 ret = false; \
5505 } \
5506} while (0)
5507
5508#define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5509 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5510 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5511 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5512 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5513 current_config->name, \
5514 pipe_config->name, \
5515 (len)); \
5516 ret = false; \
5517 } \
5518} while (0)
5519
5520#define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5521 if (current_config->gamma_mode == pipe_config->gamma_mode && \
5522 !intel_color_lut_equal(current_config, \
5523 current_config->lut, pipe_config->lut, \
5524 is_pre_csc_lut)) { \
5525 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5526 "hw_state doesn't match sw_state"); \
5527 ret = false; \
5528 } \
5529} while (0)
5530
5531#define PIPE_CONF_CHECK_CSC(name) do { \
5532 PIPE_CONF_CHECK_X(name.preoff[0]); \
5533 PIPE_CONF_CHECK_X(name.preoff[1]); \
5534 PIPE_CONF_CHECK_X(name.preoff[2]); \
5535 PIPE_CONF_CHECK_X(name.coeff[0]); \
5536 PIPE_CONF_CHECK_X(name.coeff[1]); \
5537 PIPE_CONF_CHECK_X(name.coeff[2]); \
5538 PIPE_CONF_CHECK_X(name.coeff[3]); \
5539 PIPE_CONF_CHECK_X(name.coeff[4]); \
5540 PIPE_CONF_CHECK_X(name.coeff[5]); \
5541 PIPE_CONF_CHECK_X(name.coeff[6]); \
5542 PIPE_CONF_CHECK_X(name.coeff[7]); \
5543 PIPE_CONF_CHECK_X(name.coeff[8]); \
5544 PIPE_CONF_CHECK_X(name.postoff[0]); \
5545 PIPE_CONF_CHECK_X(name.postoff[1]); \
5546 PIPE_CONF_CHECK_X(name.postoff[2]); \
5547} while (0)
5548
5549#define PIPE_CONF_QUIRK(quirk) \
5550 ((current_config->quirks | pipe_config->quirks) & (quirk))
5551
5552 PIPE_CONF_CHECK_BOOL(hw.enable);
5553 PIPE_CONF_CHECK_BOOL(hw.active);
5554
5555 PIPE_CONF_CHECK_I(cpu_transcoder);
5556 PIPE_CONF_CHECK_I(mst_master_transcoder);
5557
5558 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5559 PIPE_CONF_CHECK_I(fdi_lanes);
5560 PIPE_CONF_CHECK_M_N(fdi_m_n);
5561
5562 PIPE_CONF_CHECK_I(lane_count);
5563 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5564
5565 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5566 if (!fastset || !pipe_config->update_m_n)
5567 PIPE_CONF_CHECK_M_N(dp_m_n);
5568 } else {
5569 PIPE_CONF_CHECK_M_N(dp_m_n);
5570 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5571 }
5572
5573 PIPE_CONF_CHECK_X(output_types);
5574
5575 PIPE_CONF_CHECK_I(framestart_delay);
5576 PIPE_CONF_CHECK_I(msa_timing_delay);
5577
5578 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5579 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5580
5581 PIPE_CONF_CHECK_I(pixel_multiplier);
5582
5583 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5584 DRM_MODE_FLAG_INTERLACE);
5585
5586 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5587 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5588 DRM_MODE_FLAG_PHSYNC);
5589 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5590 DRM_MODE_FLAG_NHSYNC);
5591 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5592 DRM_MODE_FLAG_PVSYNC);
5593 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5594 DRM_MODE_FLAG_NVSYNC);
5595 }
5596
5597 PIPE_CONF_CHECK_I(output_format);
5598 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5599 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5600 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5601 PIPE_CONF_CHECK_BOOL(limited_color_range);
5602
5603 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5604 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5605 PIPE_CONF_CHECK_BOOL(has_infoframe);
5606 PIPE_CONF_CHECK_BOOL(enhanced_framing);
5607 PIPE_CONF_CHECK_BOOL(fec_enable);
5608
5609 if (!fastset) {
5610 PIPE_CONF_CHECK_BOOL(has_audio);
5611 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5612 }
5613
5614 PIPE_CONF_CHECK_X(gmch_pfit.control);
5615 /* pfit ratios are autocomputed by the hw on gen4+ */
5616 if (DISPLAY_VER(dev_priv) < 4)
5617 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5618 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5619
5620 /*
5621 * Changing the EDP transcoder input mux
5622 * (A_ONOFF vs. A_ON) requires a full modeset.
5623 */
5624 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5625
5626 if (!fastset) {
5627 PIPE_CONF_CHECK_RECT(pipe_src);
5628
5629 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5630 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5631
5632 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5633 PIPE_CONF_CHECK_I(pixel_rate);
5634
5635 PIPE_CONF_CHECK_X(gamma_mode);
5636 if (IS_CHERRYVIEW(dev_priv))
5637 PIPE_CONF_CHECK_X(cgm_mode);
5638 else
5639 PIPE_CONF_CHECK_X(csc_mode);
5640 PIPE_CONF_CHECK_BOOL(gamma_enable);
5641 PIPE_CONF_CHECK_BOOL(csc_enable);
5642 PIPE_CONF_CHECK_BOOL(wgc_enable);
5643
5644 PIPE_CONF_CHECK_I(linetime);
5645 PIPE_CONF_CHECK_I(ips_linetime);
5646
5647 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5648 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5649
5650 PIPE_CONF_CHECK_CSC(csc);
5651 PIPE_CONF_CHECK_CSC(output_csc);
5652 }
5653
5654 /*
5655 * Panel replay has to be enabled before link training. PSR doesn't have
5656 * this requirement -> check these only if using panel replay
5657 */
5658 if (current_config->active_planes &&
5659 (current_config->has_panel_replay ||
5660 pipe_config->has_panel_replay)) {
5661 PIPE_CONF_CHECK_BOOL(has_psr);
5662 PIPE_CONF_CHECK_BOOL(has_sel_update);
5663 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5664 PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
5665 PIPE_CONF_CHECK_BOOL(has_panel_replay);
5666 }
5667
5668 PIPE_CONF_CHECK_BOOL(double_wide);
5669
5670 if (dev_priv->display.dpll.mgr)
5671 PIPE_CONF_CHECK_P(shared_dpll);
5672
5673 /* FIXME convert everything over the dpll_mgr */
5674 if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
5675 PIPE_CONF_CHECK_PLL(dpll_hw_state);
5676
5677 /* FIXME convert MTL+ platforms over to dpll_mgr */
5678 if (DISPLAY_VER(dev_priv) >= 14)
5679 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
5680
5681 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5682 PIPE_CONF_CHECK_X(dsi_pll.div);
5683
5684 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5685 PIPE_CONF_CHECK_I(pipe_bpp);
5686
5687 if (!fastset || !pipe_config->update_m_n) {
5688 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5689 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5690 }
5691 PIPE_CONF_CHECK_I(port_clock);
5692
5693 PIPE_CONF_CHECK_I(min_voltage_level);
5694
5695 if (current_config->has_psr || pipe_config->has_psr)
5696 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5697 ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5698 else
5699 PIPE_CONF_CHECK_X(infoframes.enable);
5700
5701 PIPE_CONF_CHECK_X(infoframes.gcp);
5702 PIPE_CONF_CHECK_INFOFRAME(avi);
5703 PIPE_CONF_CHECK_INFOFRAME(spd);
5704 PIPE_CONF_CHECK_INFOFRAME(hdmi);
5705 if (!fastset)
5706 PIPE_CONF_CHECK_INFOFRAME(drm);
5707 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5708 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5709
5710 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5711 PIPE_CONF_CHECK_I(master_transcoder);
5712 PIPE_CONF_CHECK_X(joiner_pipes);
5713
5714 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5715 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5716 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5717 PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5718 PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5719 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5720 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5721 PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5722 PIPE_CONF_CHECK_I(dsc.config.pic_width);
5723 PIPE_CONF_CHECK_I(dsc.config.pic_height);
5724 PIPE_CONF_CHECK_I(dsc.config.slice_width);
5725 PIPE_CONF_CHECK_I(dsc.config.slice_height);
5726 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5727 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5728 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5729 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5730 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5731 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5732 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5733 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5734 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5735 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5736 PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5737 PIPE_CONF_CHECK_I(dsc.config.final_offset);
5738 PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5739 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5740 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5741 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5742 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5743 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5744
5745 PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5746 PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
5747 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5748
5749 PIPE_CONF_CHECK_BOOL(splitter.enable);
5750 PIPE_CONF_CHECK_I(splitter.link_count);
5751 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5752
5753 if (!fastset) {
5754 PIPE_CONF_CHECK_BOOL(vrr.enable);
5755 PIPE_CONF_CHECK_I(vrr.vmin);
5756 PIPE_CONF_CHECK_I(vrr.vmax);
5757 PIPE_CONF_CHECK_I(vrr.flipline);
5758 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5759 PIPE_CONF_CHECK_I(vrr.guardband);
5760 PIPE_CONF_CHECK_I(vrr.vsync_start);
5761 PIPE_CONF_CHECK_I(vrr.vsync_end);
5762 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
5763 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
5764 PIPE_CONF_CHECK_BOOL(cmrr.enable);
5765 }
5766
5767#undef PIPE_CONF_CHECK_X
5768#undef PIPE_CONF_CHECK_I
5769#undef PIPE_CONF_CHECK_LLI
5770#undef PIPE_CONF_CHECK_BOOL
5771#undef PIPE_CONF_CHECK_P
5772#undef PIPE_CONF_CHECK_FLAGS
5773#undef PIPE_CONF_CHECK_COLOR_LUT
5774#undef PIPE_CONF_CHECK_TIMINGS
5775#undef PIPE_CONF_CHECK_RECT
5776#undef PIPE_CONF_QUIRK
5777
5778 return ret;
5779}
5780
5781static void
5782intel_verify_planes(struct intel_atomic_state *state)
5783{
5784 struct intel_plane *plane;
5785 const struct intel_plane_state *plane_state;
5786 int i;
5787
5788 for_each_new_intel_plane_in_state(state, plane,
5789 plane_state, i)
5790 assert_plane(plane, plane_state->planar_slave ||
5791 plane_state->uapi.visible);
5792}
5793
5794static int intel_modeset_pipe(struct intel_atomic_state *state,
5795 struct intel_crtc_state *crtc_state,
5796 const char *reason)
5797{
5798 struct drm_i915_private *i915 = to_i915(state->base.dev);
5799 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5800 int ret;
5801
5802 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5803 crtc->base.base.id, crtc->base.name, reason);
5804
5805 ret = drm_atomic_add_affected_connectors(&state->base,
5806 &crtc->base);
5807 if (ret)
5808 return ret;
5809
5810 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
5811 if (ret)
5812 return ret;
5813
5814 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5815 if (ret)
5816 return ret;
5817
5818 ret = intel_atomic_add_affected_planes(state, crtc);
5819 if (ret)
5820 return ret;
5821
5822 crtc_state->uapi.mode_changed = true;
5823
5824 return 0;
5825}
5826
5827/**
5828 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5829 * @state: intel atomic state
5830 * @reason: the reason for the full modeset
5831 * @mask: mask of pipes to modeset
5832 *
5833 * Add pipes in @mask to @state and force a full modeset on the enabled ones
5834 * due to the description in @reason.
5835 * This function can be called only before new plane states are computed.
5836 *
5837 * Returns 0 in case of success, negative error code otherwise.
5838 */
5839int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5840 const char *reason, u8 mask)
5841{
5842 struct drm_i915_private *i915 = to_i915(state->base.dev);
5843 struct intel_crtc *crtc;
5844
5845 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
5846 struct intel_crtc_state *crtc_state;
5847 int ret;
5848
5849 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5850 if (IS_ERR(crtc_state))
5851 return PTR_ERR(crtc_state);
5852
5853 if (!crtc_state->hw.enable ||
5854 intel_crtc_needs_modeset(crtc_state))
5855 continue;
5856
5857 ret = intel_modeset_pipe(state, crtc_state, reason);
5858 if (ret)
5859 return ret;
5860 }
5861
5862 return 0;
5863}
5864
5865static void
5866intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5867{
5868 crtc_state->uapi.mode_changed = true;
5869
5870 crtc_state->update_pipe = false;
5871 crtc_state->update_m_n = false;
5872 crtc_state->update_lrr = false;
5873}
5874
5875/**
5876 * intel_modeset_all_pipes_late - force a full modeset on all pipes
5877 * @state: intel atomic state
5878 * @reason: the reason for the full modeset
5879 *
5880 * Add all pipes to @state and force a full modeset on the active ones due to
5881 * the description in @reason.
5882 * This function can be called only after new plane states are computed already.
5883 *
5884 * Returns 0 in case of success, negative error code otherwise.
5885 */
5886int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5887 const char *reason)
5888{
5889 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5890 struct intel_crtc *crtc;
5891
5892 for_each_intel_crtc(&dev_priv->drm, crtc) {
5893 struct intel_crtc_state *crtc_state;
5894 int ret;
5895
5896 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5897 if (IS_ERR(crtc_state))
5898 return PTR_ERR(crtc_state);
5899
5900 if (!crtc_state->hw.active ||
5901 intel_crtc_needs_modeset(crtc_state))
5902 continue;
5903
5904 ret = intel_modeset_pipe(state, crtc_state, reason);
5905 if (ret)
5906 return ret;
5907
5908 intel_crtc_flag_modeset(crtc_state);
5909
5910 crtc_state->update_planes |= crtc_state->active_planes;
5911 crtc_state->async_flip_planes = 0;
5912 crtc_state->do_async_flip = false;
5913 }
5914
5915 return 0;
5916}
5917
5918int intel_modeset_commit_pipes(struct drm_i915_private *i915,
5919 u8 pipe_mask,
5920 struct drm_modeset_acquire_ctx *ctx)
5921{
5922 struct drm_atomic_state *state;
5923 struct intel_crtc *crtc;
5924 int ret;
5925
5926 state = drm_atomic_state_alloc(&i915->drm);
5927 if (!state)
5928 return -ENOMEM;
5929
5930 state->acquire_ctx = ctx;
5931 to_intel_atomic_state(state)->internal = true;
5932
5933 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
5934 struct intel_crtc_state *crtc_state =
5935 intel_atomic_get_crtc_state(state, crtc);
5936
5937 if (IS_ERR(crtc_state)) {
5938 ret = PTR_ERR(crtc_state);
5939 goto out;
5940 }
5941
5942 crtc_state->uapi.connectors_changed = true;
5943 }
5944
5945 ret = drm_atomic_commit(state);
5946out:
5947 drm_atomic_state_put(state);
5948
5949 return ret;
5950}
5951
5952/*
5953 * This implements the workaround described in the "notes" section of the mode
5954 * set sequence documentation. When going from no pipes or single pipe to
5955 * multiple pipes, and planes are enabled after the pipe, we need to wait at
5956 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5957 */
5958static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5959{
5960 struct intel_crtc_state *crtc_state;
5961 struct intel_crtc *crtc;
5962 struct intel_crtc_state *first_crtc_state = NULL;
5963 struct intel_crtc_state *other_crtc_state = NULL;
5964 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5965 int i;
5966
5967 /* look at all crtc's that are going to be enabled in during modeset */
5968 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5969 if (!crtc_state->hw.active ||
5970 !intel_crtc_needs_modeset(crtc_state))
5971 continue;
5972
5973 if (first_crtc_state) {
5974 other_crtc_state = crtc_state;
5975 break;
5976 } else {
5977 first_crtc_state = crtc_state;
5978 first_pipe = crtc->pipe;
5979 }
5980 }
5981
5982 /* No workaround needed? */
5983 if (!first_crtc_state)
5984 return 0;
5985
5986 /* w/a possibly needed, check how many crtc's are already enabled. */
5987 for_each_intel_crtc(state->base.dev, crtc) {
5988 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5989 if (IS_ERR(crtc_state))
5990 return PTR_ERR(crtc_state);
5991
5992 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5993
5994 if (!crtc_state->hw.active ||
5995 intel_crtc_needs_modeset(crtc_state))
5996 continue;
5997
5998 /* 2 or more enabled crtcs means no need for w/a */
5999 if (enabled_pipe != INVALID_PIPE)
6000 return 0;
6001
6002 enabled_pipe = crtc->pipe;
6003 }
6004
6005 if (enabled_pipe != INVALID_PIPE)
6006 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
6007 else if (other_crtc_state)
6008 other_crtc_state->hsw_workaround_pipe = first_pipe;
6009
6010 return 0;
6011}
6012
6013u8 intel_calc_active_pipes(struct intel_atomic_state *state,
6014 u8 active_pipes)
6015{
6016 const struct intel_crtc_state *crtc_state;
6017 struct intel_crtc *crtc;
6018 int i;
6019
6020 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6021 if (crtc_state->hw.active)
6022 active_pipes |= BIT(crtc->pipe);
6023 else
6024 active_pipes &= ~BIT(crtc->pipe);
6025 }
6026
6027 return active_pipes;
6028}
6029
6030static int intel_modeset_checks(struct intel_atomic_state *state)
6031{
6032 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6033
6034 state->modeset = true;
6035
6036 if (IS_HASWELL(dev_priv))
6037 return hsw_mode_set_planes_workaround(state);
6038
6039 return 0;
6040}
6041
6042static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
6043 struct intel_crtc_state *new_crtc_state)
6044{
6045 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6046 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6047
6048 /* only allow LRR when the timings stay within the VRR range */
6049 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
6050 new_crtc_state->update_lrr = false;
6051
6052 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
6053 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
6054 crtc->base.base.id, crtc->base.name);
6055 else
6056 new_crtc_state->uapi.mode_changed = false;
6057
6058 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
6059 &new_crtc_state->dp_m_n))
6060 new_crtc_state->update_m_n = false;
6061
6062 if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
6063 old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
6064 new_crtc_state->update_lrr = false;
6065
6066 if (intel_crtc_needs_modeset(new_crtc_state))
6067 intel_crtc_flag_modeset(new_crtc_state);
6068 else
6069 new_crtc_state->update_pipe = true;
6070}
6071
6072static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
6073 struct intel_crtc *crtc,
6074 u8 plane_ids_mask)
6075{
6076 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6077 struct intel_plane *plane;
6078
6079 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6080 struct intel_plane_state *plane_state;
6081
6082 if ((plane_ids_mask & BIT(plane->id)) == 0)
6083 continue;
6084
6085 plane_state = intel_atomic_get_plane_state(state, plane);
6086 if (IS_ERR(plane_state))
6087 return PTR_ERR(plane_state);
6088 }
6089
6090 return 0;
6091}
6092
6093int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
6094 struct intel_crtc *crtc)
6095{
6096 const struct intel_crtc_state *old_crtc_state =
6097 intel_atomic_get_old_crtc_state(state, crtc);
6098 const struct intel_crtc_state *new_crtc_state =
6099 intel_atomic_get_new_crtc_state(state, crtc);
6100
6101 return intel_crtc_add_planes_to_state(state, crtc,
6102 old_crtc_state->enabled_planes |
6103 new_crtc_state->enabled_planes);
6104}
6105
6106static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
6107{
6108 /* See {hsw,vlv,ivb}_plane_ratio() */
6109 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
6110 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6111 IS_IVYBRIDGE(dev_priv);
6112}
6113
6114static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
6115 struct intel_crtc *crtc,
6116 struct intel_crtc *other)
6117{
6118 const struct intel_plane_state __maybe_unused *plane_state;
6119 struct intel_plane *plane;
6120 u8 plane_ids = 0;
6121 int i;
6122
6123 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6124 if (plane->pipe == crtc->pipe)
6125 plane_ids |= BIT(plane->id);
6126 }
6127
6128 return intel_crtc_add_planes_to_state(state, other, plane_ids);
6129}
6130
6131static int intel_joiner_add_affected_planes(struct intel_atomic_state *state)
6132{
6133 struct drm_i915_private *i915 = to_i915(state->base.dev);
6134 const struct intel_crtc_state *crtc_state;
6135 struct intel_crtc *crtc;
6136 int i;
6137
6138 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6139 struct intel_crtc *other;
6140
6141 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6142 crtc_state->joiner_pipes) {
6143 int ret;
6144
6145 if (crtc == other)
6146 continue;
6147
6148 ret = intel_crtc_add_joiner_planes(state, crtc, other);
6149 if (ret)
6150 return ret;
6151 }
6152 }
6153
6154 return 0;
6155}
6156
6157static int intel_atomic_check_planes(struct intel_atomic_state *state)
6158{
6159 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6160 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6161 struct intel_plane_state __maybe_unused *plane_state;
6162 struct intel_plane *plane;
6163 struct intel_crtc *crtc;
6164 int i, ret;
6165
6166 ret = icl_add_linked_planes(state);
6167 if (ret)
6168 return ret;
6169
6170 ret = intel_joiner_add_affected_planes(state);
6171 if (ret)
6172 return ret;
6173
6174 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6175 ret = intel_plane_atomic_check(state, plane);
6176 if (ret) {
6177 drm_dbg_atomic(&dev_priv->drm,
6178 "[PLANE:%d:%s] atomic driver check failed\n",
6179 plane->base.base.id, plane->base.name);
6180 return ret;
6181 }
6182 }
6183
6184 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6185 new_crtc_state, i) {
6186 u8 old_active_planes, new_active_planes;
6187
6188 ret = icl_check_nv12_planes(state, crtc);
6189 if (ret)
6190 return ret;
6191
6192 /*
6193 * On some platforms the number of active planes affects
6194 * the planes' minimum cdclk calculation. Add such planes
6195 * to the state before we compute the minimum cdclk.
6196 */
6197 if (!active_planes_affects_min_cdclk(dev_priv))
6198 continue;
6199
6200 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6201 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6202
6203 if (hweight8(old_active_planes) == hweight8(new_active_planes))
6204 continue;
6205
6206 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6207 if (ret)
6208 return ret;
6209 }
6210
6211 return 0;
6212}
6213
6214static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6215{
6216 struct intel_crtc_state __maybe_unused *crtc_state;
6217 struct intel_crtc *crtc;
6218 int i;
6219
6220 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6221 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6222 int ret;
6223
6224 ret = intel_crtc_atomic_check(state, crtc);
6225 if (ret) {
6226 drm_dbg_atomic(&i915->drm,
6227 "[CRTC:%d:%s] atomic driver check failed\n",
6228 crtc->base.base.id, crtc->base.name);
6229 return ret;
6230 }
6231 }
6232
6233 return 0;
6234}
6235
6236static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6237 u8 transcoders)
6238{
6239 const struct intel_crtc_state *new_crtc_state;
6240 struct intel_crtc *crtc;
6241 int i;
6242
6243 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6244 if (new_crtc_state->hw.enable &&
6245 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6246 intel_crtc_needs_modeset(new_crtc_state))
6247 return true;
6248 }
6249
6250 return false;
6251}
6252
6253static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6254 u8 pipes)
6255{
6256 const struct intel_crtc_state *new_crtc_state;
6257 struct intel_crtc *crtc;
6258 int i;
6259
6260 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6261 if (new_crtc_state->hw.enable &&
6262 pipes & BIT(crtc->pipe) &&
6263 intel_crtc_needs_modeset(new_crtc_state))
6264 return true;
6265 }
6266
6267 return false;
6268}
6269
6270static int intel_atomic_check_joiner(struct intel_atomic_state *state,
6271 struct intel_crtc *primary_crtc)
6272{
6273 struct drm_i915_private *i915 = to_i915(state->base.dev);
6274 struct intel_crtc_state *primary_crtc_state =
6275 intel_atomic_get_new_crtc_state(state, primary_crtc);
6276 struct intel_crtc *secondary_crtc;
6277
6278 if (!primary_crtc_state->joiner_pipes)
6279 return 0;
6280
6281 /* sanity check */
6282 if (drm_WARN_ON(&i915->drm,
6283 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
6284 return -EINVAL;
6285
6286 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) {
6287 drm_dbg_kms(&i915->drm,
6288 "[CRTC:%d:%s] Cannot act as joiner primary "
6289 "(need 0x%x as pipes, only 0x%x possible)\n",
6290 primary_crtc->base.base.id, primary_crtc->base.name,
6291 primary_crtc_state->joiner_pipes, joiner_pipes(i915));
6292 return -EINVAL;
6293 }
6294
6295 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
6296 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
6297 struct intel_crtc_state *secondary_crtc_state;
6298 int ret;
6299
6300 secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);
6301 if (IS_ERR(secondary_crtc_state))
6302 return PTR_ERR(secondary_crtc_state);
6303
6304 /* primary being enabled, secondary was already configured? */
6305 if (secondary_crtc_state->uapi.enable) {
6306 drm_dbg_kms(&i915->drm,
6307 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
6308 "[CRTC:%d:%s] claiming this CRTC for joiner.\n",
6309 secondary_crtc->base.base.id, secondary_crtc->base.name,
6310 primary_crtc->base.base.id, primary_crtc->base.name);
6311 return -EINVAL;
6312 }
6313
6314 /*
6315 * The state copy logic assumes the primary crtc gets processed
6316 * before the secondary crtc during the main compute_config loop.
6317 * This works because the crtcs are created in pipe order,
6318 * and the hardware requires primary pipe < secondary pipe as well.
6319 * Should that change we need to rethink the logic.
6320 */
6321 if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
6322 drm_crtc_index(&secondary_crtc->base)))
6323 return -EINVAL;
6324
6325 drm_dbg_kms(&i915->drm,
6326 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
6327 secondary_crtc->base.base.id, secondary_crtc->base.name,
6328 primary_crtc->base.base.id, primary_crtc->base.name);
6329
6330 secondary_crtc_state->joiner_pipes =
6331 primary_crtc_state->joiner_pipes;
6332
6333 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
6334 if (ret)
6335 return ret;
6336 }
6337
6338 return 0;
6339}
6340
6341static void kill_joiner_secondaries(struct intel_atomic_state *state,
6342 struct intel_crtc *primary_crtc)
6343{
6344 struct drm_i915_private *i915 = to_i915(state->base.dev);
6345 struct intel_crtc_state *primary_crtc_state =
6346 intel_atomic_get_new_crtc_state(state, primary_crtc);
6347 struct intel_crtc *secondary_crtc;
6348
6349 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
6350 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
6351 struct intel_crtc_state *secondary_crtc_state =
6352 intel_atomic_get_new_crtc_state(state, secondary_crtc);
6353
6354 secondary_crtc_state->joiner_pipes = 0;
6355
6356 intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc);
6357 }
6358
6359 primary_crtc_state->joiner_pipes = 0;
6360}
6361
6362/**
6363 * DOC: asynchronous flip implementation
6364 *
6365 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6366 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6367 * Correspondingly, support is currently added for primary plane only.
6368 *
6369 * Async flip can only change the plane surface address, so anything else
6370 * changing is rejected from the intel_async_flip_check_hw() function.
6371 * Once this check is cleared, flip done interrupt is enabled using
6372 * the intel_crtc_enable_flip_done() function.
6373 *
6374 * As soon as the surface address register is written, flip done interrupt is
6375 * generated and the requested events are sent to the usersapce in the interrupt
6376 * handler itself. The timestamp and sequence sent during the flip done event
6377 * correspond to the last vblank and have no relation to the actual time when
6378 * the flip done event was sent.
6379 */
6380static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6381 struct intel_crtc *crtc)
6382{
6383 struct drm_i915_private *i915 = to_i915(state->base.dev);
6384 const struct intel_crtc_state *new_crtc_state =
6385 intel_atomic_get_new_crtc_state(state, crtc);
6386 const struct intel_plane_state *old_plane_state;
6387 struct intel_plane_state *new_plane_state;
6388 struct intel_plane *plane;
6389 int i;
6390
6391 if (!new_crtc_state->uapi.async_flip)
6392 return 0;
6393
6394 if (!new_crtc_state->uapi.active) {
6395 drm_dbg_kms(&i915->drm,
6396 "[CRTC:%d:%s] not active\n",
6397 crtc->base.base.id, crtc->base.name);
6398 return -EINVAL;
6399 }
6400
6401 if (intel_crtc_needs_modeset(new_crtc_state)) {
6402 drm_dbg_kms(&i915->drm,
6403 "[CRTC:%d:%s] modeset required\n",
6404 crtc->base.base.id, crtc->base.name);
6405 return -EINVAL;
6406 }
6407
6408 /*
6409 * FIXME: joiner+async flip is busted currently.
6410 * Remove this check once the issues are fixed.
6411 */
6412 if (new_crtc_state->joiner_pipes) {
6413 drm_dbg_kms(&i915->drm,
6414 "[CRTC:%d:%s] async flip disallowed with joiner\n",
6415 crtc->base.base.id, crtc->base.name);
6416 return -EINVAL;
6417 }
6418
6419 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6420 new_plane_state, i) {
6421 if (plane->pipe != crtc->pipe)
6422 continue;
6423
6424 /*
6425 * TODO: Async flip is only supported through the page flip IOCTL
6426 * as of now. So support currently added for primary plane only.
6427 * Support for other planes on platforms on which supports
6428 * this(vlv/chv and icl+) should be added when async flip is
6429 * enabled in the atomic IOCTL path.
6430 */
6431 if (!plane->async_flip) {
6432 drm_dbg_kms(&i915->drm,
6433 "[PLANE:%d:%s] async flip not supported\n",
6434 plane->base.base.id, plane->base.name);
6435 return -EINVAL;
6436 }
6437
6438 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6439 drm_dbg_kms(&i915->drm,
6440 "[PLANE:%d:%s] no old or new framebuffer\n",
6441 plane->base.base.id, plane->base.name);
6442 return -EINVAL;
6443 }
6444 }
6445
6446 return 0;
6447}
6448
6449static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6450{
6451 struct drm_i915_private *i915 = to_i915(state->base.dev);
6452 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6453 const struct intel_plane_state *new_plane_state, *old_plane_state;
6454 struct intel_plane *plane;
6455 int i;
6456
6457 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6458 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6459
6460 if (!new_crtc_state->uapi.async_flip)
6461 return 0;
6462
6463 if (!new_crtc_state->hw.active) {
6464 drm_dbg_kms(&i915->drm,
6465 "[CRTC:%d:%s] not active\n",
6466 crtc->base.base.id, crtc->base.name);
6467 return -EINVAL;
6468 }
6469
6470 if (intel_crtc_needs_modeset(new_crtc_state)) {
6471 drm_dbg_kms(&i915->drm,
6472 "[CRTC:%d:%s] modeset required\n",
6473 crtc->base.base.id, crtc->base.name);
6474 return -EINVAL;
6475 }
6476
6477 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6478 drm_dbg_kms(&i915->drm,
6479 "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6480 crtc->base.base.id, crtc->base.name);
6481 return -EINVAL;
6482 }
6483
6484 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6485 new_plane_state, i) {
6486 if (plane->pipe != crtc->pipe)
6487 continue;
6488
6489 /*
6490 * Only async flip capable planes should be in the state
6491 * if we're really about to ask the hardware to perform
6492 * an async flip. We should never get this far otherwise.
6493 */
6494 if (drm_WARN_ON(&i915->drm,
6495 new_crtc_state->do_async_flip && !plane->async_flip))
6496 return -EINVAL;
6497
6498 /*
6499 * Only check async flip capable planes other planes
6500 * may be involved in the initial commit due to
6501 * the wm0/ddb optimization.
6502 *
6503 * TODO maybe should track which planes actually
6504 * were requested to do the async flip...
6505 */
6506 if (!plane->async_flip)
6507 continue;
6508
6509 /*
6510 * FIXME: This check is kept generic for all platforms.
6511 * Need to verify this for all gen9 platforms to enable
6512 * this selectively if required.
6513 */
6514 switch (new_plane_state->hw.fb->modifier) {
6515 case DRM_FORMAT_MOD_LINEAR:
6516 /*
6517 * FIXME: Async on Linear buffer is supported on ICL as
6518 * but with additional alignment and fbc restrictions
6519 * need to be taken care of. These aren't applicable for
6520 * gen12+.
6521 */
6522 if (DISPLAY_VER(i915) < 12) {
6523 drm_dbg_kms(&i915->drm,
6524 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6525 plane->base.base.id, plane->base.name,
6526 new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
6527 return -EINVAL;
6528 }
6529 break;
6530
6531 case I915_FORMAT_MOD_X_TILED:
6532 case I915_FORMAT_MOD_Y_TILED:
6533 case I915_FORMAT_MOD_Yf_TILED:
6534 case I915_FORMAT_MOD_4_TILED:
6535 case I915_FORMAT_MOD_4_TILED_BMG_CCS:
6536 case I915_FORMAT_MOD_4_TILED_LNL_CCS:
6537 break;
6538 default:
6539 drm_dbg_kms(&i915->drm,
6540 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6541 plane->base.base.id, plane->base.name,
6542 new_plane_state->hw.fb->modifier);
6543 return -EINVAL;
6544 }
6545
6546 if (new_plane_state->hw.fb->format->num_planes > 1) {
6547 drm_dbg_kms(&i915->drm,
6548 "[PLANE:%d:%s] Planar formats do not support async flips\n",
6549 plane->base.base.id, plane->base.name);
6550 return -EINVAL;
6551 }
6552
6553 /*
6554 * We turn the first async flip request into a sync flip
6555 * so that we can reconfigure the plane (eg. change modifier).
6556 */
6557 if (!new_crtc_state->do_async_flip)
6558 continue;
6559
6560 if (old_plane_state->view.color_plane[0].mapping_stride !=
6561 new_plane_state->view.color_plane[0].mapping_stride) {
6562 drm_dbg_kms(&i915->drm,
6563 "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6564 plane->base.base.id, plane->base.name);
6565 return -EINVAL;
6566 }
6567
6568 if (old_plane_state->hw.fb->modifier !=
6569 new_plane_state->hw.fb->modifier) {
6570 drm_dbg_kms(&i915->drm,
6571 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6572 plane->base.base.id, plane->base.name);
6573 return -EINVAL;
6574 }
6575
6576 if (old_plane_state->hw.fb->format !=
6577 new_plane_state->hw.fb->format) {
6578 drm_dbg_kms(&i915->drm,
6579 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6580 plane->base.base.id, plane->base.name);
6581 return -EINVAL;
6582 }
6583
6584 if (old_plane_state->hw.rotation !=
6585 new_plane_state->hw.rotation) {
6586 drm_dbg_kms(&i915->drm,
6587 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6588 plane->base.base.id, plane->base.name);
6589 return -EINVAL;
6590 }
6591
6592 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6593 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6594 drm_dbg_kms(&i915->drm,
6595 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6596 plane->base.base.id, plane->base.name);
6597 return -EINVAL;
6598 }
6599
6600 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6601 drm_dbg_kms(&i915->drm,
6602 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6603 plane->base.base.id, plane->base.name);
6604 return -EINVAL;
6605 }
6606
6607 if (old_plane_state->hw.pixel_blend_mode !=
6608 new_plane_state->hw.pixel_blend_mode) {
6609 drm_dbg_kms(&i915->drm,
6610 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6611 plane->base.base.id, plane->base.name);
6612 return -EINVAL;
6613 }
6614
6615 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6616 drm_dbg_kms(&i915->drm,
6617 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6618 plane->base.base.id, plane->base.name);
6619 return -EINVAL;
6620 }
6621
6622 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6623 drm_dbg_kms(&i915->drm,
6624 "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6625 plane->base.base.id, plane->base.name);
6626 return -EINVAL;
6627 }
6628
6629 /* plane decryption is allow to change only in synchronous flips */
6630 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6631 drm_dbg_kms(&i915->drm,
6632 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6633 plane->base.base.id, plane->base.name);
6634 return -EINVAL;
6635 }
6636 }
6637
6638 return 0;
6639}
6640
6641static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
6642{
6643 struct drm_i915_private *i915 = to_i915(state->base.dev);
6644 const struct intel_plane_state *plane_state;
6645 struct intel_crtc_state *crtc_state;
6646 struct intel_plane *plane;
6647 struct intel_crtc *crtc;
6648 u8 affected_pipes = 0;
6649 u8 modeset_pipes = 0;
6650 int i;
6651
6652 /*
6653 * Any plane which is in use by the joiner needs its crtc.
6654 * Pull those in first as this will not have happened yet
6655 * if the plane remains disabled according to uapi.
6656 */
6657 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6658 crtc = to_intel_crtc(plane_state->hw.crtc);
6659 if (!crtc)
6660 continue;
6661
6662 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6663 if (IS_ERR(crtc_state))
6664 return PTR_ERR(crtc_state);
6665 }
6666
6667 /* Now pull in all joined crtcs */
6668 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6669 affected_pipes |= crtc_state->joiner_pipes;
6670 if (intel_crtc_needs_modeset(crtc_state))
6671 modeset_pipes |= crtc_state->joiner_pipes;
6672 }
6673
6674 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6675 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6676 if (IS_ERR(crtc_state))
6677 return PTR_ERR(crtc_state);
6678 }
6679
6680 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6681 int ret;
6682
6683 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6684
6685 crtc_state->uapi.mode_changed = true;
6686
6687 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6688 if (ret)
6689 return ret;
6690
6691 ret = intel_atomic_add_affected_planes(state, crtc);
6692 if (ret)
6693 return ret;
6694 }
6695
6696 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6697 /* Kill old joiner link, we may re-establish afterwards */
6698 if (intel_crtc_needs_modeset(crtc_state) &&
6699 intel_crtc_is_joiner_primary(crtc_state))
6700 kill_joiner_secondaries(state, crtc);
6701 }
6702
6703 return 0;
6704}
6705
6706static int intel_atomic_check_config(struct intel_atomic_state *state,
6707 struct intel_link_bw_limits *limits,
6708 enum pipe *failed_pipe)
6709{
6710 struct drm_i915_private *i915 = to_i915(state->base.dev);
6711 struct intel_crtc_state *new_crtc_state;
6712 struct intel_crtc *crtc;
6713 int ret;
6714 int i;
6715
6716 *failed_pipe = INVALID_PIPE;
6717
6718 ret = intel_joiner_add_affected_crtcs(state);
6719 if (ret)
6720 return ret;
6721
6722 ret = intel_fdi_add_affected_crtcs(state);
6723 if (ret)
6724 return ret;
6725
6726 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6727 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6728 if (intel_crtc_is_joiner_secondary(new_crtc_state))
6729 copy_joiner_crtc_state_nomodeset(state, crtc);
6730 else
6731 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6732 continue;
6733 }
6734
6735 if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6736 continue;
6737
6738 ret = intel_crtc_prepare_cleared_state(state, crtc);
6739 if (ret)
6740 goto fail;
6741
6742 if (!new_crtc_state->hw.enable)
6743 continue;
6744
6745 ret = intel_modeset_pipe_config(state, crtc, limits);
6746 if (ret)
6747 goto fail;
6748 }
6749
6750 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6751 if (!intel_crtc_needs_modeset(new_crtc_state))
6752 continue;
6753
6754 if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6755 continue;
6756
6757 if (!new_crtc_state->hw.enable)
6758 continue;
6759
6760 ret = intel_modeset_pipe_config_late(state, crtc);
6761 if (ret)
6762 goto fail;
6763 }
6764
6765fail:
6766 if (ret)
6767 *failed_pipe = crtc->pipe;
6768
6769 return ret;
6770}
6771
6772static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6773{
6774 struct intel_link_bw_limits new_limits;
6775 struct intel_link_bw_limits old_limits;
6776 int ret;
6777
6778 intel_link_bw_init_limits(state, &new_limits);
6779 old_limits = new_limits;
6780
6781 while (true) {
6782 enum pipe failed_pipe;
6783
6784 ret = intel_atomic_check_config(state, &new_limits,
6785 &failed_pipe);
6786 if (ret) {
6787 /*
6788 * The bpp limit for a pipe is below the minimum it supports, set the
6789 * limit to the minimum and recalculate the config.
6790 */
6791 if (ret == -EINVAL &&
6792 intel_link_bw_set_bpp_limit_for_pipe(state,
6793 &old_limits,
6794 &new_limits,
6795 failed_pipe))
6796 continue;
6797
6798 break;
6799 }
6800
6801 old_limits = new_limits;
6802
6803 ret = intel_link_bw_atomic_check(state, &new_limits);
6804 if (ret != -EAGAIN)
6805 break;
6806 }
6807
6808 return ret;
6809}
6810/**
6811 * intel_atomic_check - validate state object
6812 * @dev: drm device
6813 * @_state: state to validate
6814 */
6815int intel_atomic_check(struct drm_device *dev,
6816 struct drm_atomic_state *_state)
6817{
6818 struct drm_i915_private *dev_priv = to_i915(dev);
6819 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6820 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6821 struct intel_crtc *crtc;
6822 int ret, i;
6823 bool any_ms = false;
6824
6825 if (!intel_display_driver_check_access(dev_priv))
6826 return -ENODEV;
6827
6828 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6829 new_crtc_state, i) {
6830 /*
6831 * crtc's state no longer considered to be inherited
6832 * after the first userspace/client initiated commit.
6833 */
6834 if (!state->internal)
6835 new_crtc_state->inherited = false;
6836
6837 if (new_crtc_state->inherited != old_crtc_state->inherited)
6838 new_crtc_state->uapi.mode_changed = true;
6839
6840 if (new_crtc_state->uapi.scaling_filter !=
6841 old_crtc_state->uapi.scaling_filter)
6842 new_crtc_state->uapi.mode_changed = true;
6843 }
6844
6845 intel_vrr_check_modeset(state);
6846
6847 ret = drm_atomic_helper_check_modeset(dev, &state->base);
6848 if (ret)
6849 goto fail;
6850
6851 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6852 ret = intel_async_flip_check_uapi(state, crtc);
6853 if (ret)
6854 return ret;
6855 }
6856
6857 ret = intel_atomic_check_config_and_link(state);
6858 if (ret)
6859 goto fail;
6860
6861 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6862 if (!intel_crtc_needs_modeset(new_crtc_state))
6863 continue;
6864
6865 if (intel_crtc_is_joiner_secondary(new_crtc_state)) {
6866 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6867 continue;
6868 }
6869
6870 ret = intel_atomic_check_joiner(state, crtc);
6871 if (ret)
6872 goto fail;
6873 }
6874
6875 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6876 new_crtc_state, i) {
6877 if (!intel_crtc_needs_modeset(new_crtc_state))
6878 continue;
6879
6880 intel_joiner_adjust_pipe_src(new_crtc_state);
6881
6882 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6883 }
6884
6885 /**
6886 * Check if fastset is allowed by external dependencies like other
6887 * pipes and transcoders.
6888 *
6889 * Right now it only forces a fullmodeset when the MST master
6890 * transcoder did not changed but the pipe of the master transcoder
6891 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6892 * in case of port synced crtcs, if one of the synced crtcs
6893 * needs a full modeset, all other synced crtcs should be
6894 * forced a full modeset.
6895 */
6896 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6897 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6898 continue;
6899
6900 if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6901 intel_crtc_flag_modeset(new_crtc_state);
6902
6903 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6904 enum transcoder master = new_crtc_state->mst_master_transcoder;
6905
6906 if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6907 intel_crtc_flag_modeset(new_crtc_state);
6908 }
6909
6910 if (is_trans_port_sync_mode(new_crtc_state)) {
6911 u8 trans = new_crtc_state->sync_mode_slaves_mask;
6912
6913 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6914 trans |= BIT(new_crtc_state->master_transcoder);
6915
6916 if (intel_cpu_transcoders_need_modeset(state, trans))
6917 intel_crtc_flag_modeset(new_crtc_state);
6918 }
6919
6920 if (new_crtc_state->joiner_pipes) {
6921 if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))
6922 intel_crtc_flag_modeset(new_crtc_state);
6923 }
6924 }
6925
6926 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6927 new_crtc_state, i) {
6928 if (!intel_crtc_needs_modeset(new_crtc_state))
6929 continue;
6930
6931 any_ms = true;
6932
6933 intel_release_shared_dplls(state, crtc);
6934 }
6935
6936 if (any_ms && !check_digital_port_conflicts(state)) {
6937 drm_dbg_kms(&dev_priv->drm,
6938 "rejecting conflicting digital port configuration\n");
6939 ret = -EINVAL;
6940 goto fail;
6941 }
6942
6943 ret = intel_atomic_check_planes(state);
6944 if (ret)
6945 goto fail;
6946
6947 ret = intel_compute_global_watermarks(state);
6948 if (ret)
6949 goto fail;
6950
6951 ret = intel_bw_atomic_check(state);
6952 if (ret)
6953 goto fail;
6954
6955 ret = intel_cdclk_atomic_check(state, &any_ms);
6956 if (ret)
6957 goto fail;
6958
6959 if (intel_any_crtc_needs_modeset(state))
6960 any_ms = true;
6961
6962 if (any_ms) {
6963 ret = intel_modeset_checks(state);
6964 if (ret)
6965 goto fail;
6966
6967 ret = intel_modeset_calc_cdclk(state);
6968 if (ret)
6969 return ret;
6970 }
6971
6972 ret = intel_pmdemand_atomic_check(state);
6973 if (ret)
6974 goto fail;
6975
6976 ret = intel_atomic_check_crtcs(state);
6977 if (ret)
6978 goto fail;
6979
6980 ret = intel_fbc_atomic_check(state);
6981 if (ret)
6982 goto fail;
6983
6984 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6985 new_crtc_state, i) {
6986 intel_color_assert_luts(new_crtc_state);
6987
6988 ret = intel_async_flip_check_hw(state, crtc);
6989 if (ret)
6990 goto fail;
6991
6992 /* Either full modeset or fastset (or neither), never both */
6993 drm_WARN_ON(&dev_priv->drm,
6994 intel_crtc_needs_modeset(new_crtc_state) &&
6995 intel_crtc_needs_fastset(new_crtc_state));
6996
6997 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6998 !intel_crtc_needs_fastset(new_crtc_state))
6999 continue;
7000
7001 intel_crtc_state_dump(new_crtc_state, state,
7002 intel_crtc_needs_modeset(new_crtc_state) ?
7003 "modeset" : "fastset");
7004 }
7005
7006 return 0;
7007
7008 fail:
7009 if (ret == -EDEADLK)
7010 return ret;
7011
7012 /*
7013 * FIXME would probably be nice to know which crtc specifically
7014 * caused the failure, in cases where we can pinpoint it.
7015 */
7016 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7017 new_crtc_state, i)
7018 intel_crtc_state_dump(new_crtc_state, state, "failed");
7019
7020 return ret;
7021}
7022
7023static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
7024{
7025 int ret;
7026
7027 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
7028 if (ret < 0)
7029 return ret;
7030
7031 return 0;
7032}
7033
7034void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
7035 struct intel_crtc_state *crtc_state)
7036{
7037 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7038
7039 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
7040 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7041
7042 if (crtc_state->has_pch_encoder) {
7043 enum pipe pch_transcoder =
7044 intel_crtc_pch_transcoder(crtc);
7045
7046 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
7047 }
7048}
7049
7050static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
7051 const struct intel_crtc_state *new_crtc_state)
7052{
7053 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7054 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7055
7056 /*
7057 * Update pipe size and adjust fitter if needed: the reason for this is
7058 * that in compute_mode_changes we check the native mode (not the pfit
7059 * mode) to see if we can flip rather than do a full mode set. In the
7060 * fastboot case, we'll flip, but if we don't update the pipesrc and
7061 * pfit state, we'll end up with a big fb scanned out into the wrong
7062 * sized surface.
7063 */
7064 intel_set_pipe_src_size(new_crtc_state);
7065
7066 /* on skylake this is done by detaching scalers */
7067 if (DISPLAY_VER(dev_priv) >= 9) {
7068 if (new_crtc_state->pch_pfit.enabled)
7069 skl_pfit_enable(new_crtc_state);
7070 } else if (HAS_PCH_SPLIT(dev_priv)) {
7071 if (new_crtc_state->pch_pfit.enabled)
7072 ilk_pfit_enable(new_crtc_state);
7073 else if (old_crtc_state->pch_pfit.enabled)
7074 ilk_pfit_disable(old_crtc_state);
7075 }
7076
7077 /*
7078 * The register is supposedly single buffered so perhaps
7079 * not 100% correct to do this here. But SKL+ calculate
7080 * this based on the adjust pixel rate so pfit changes do
7081 * affect it and so it must be updated for fastsets.
7082 * HSW/BDW only really need this here for fastboot, after
7083 * that the value should not change without a full modeset.
7084 */
7085 if (DISPLAY_VER(dev_priv) >= 9 ||
7086 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7087 hsw_set_linetime_wm(new_crtc_state);
7088
7089 if (new_crtc_state->update_m_n)
7090 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
7091 &new_crtc_state->dp_m_n);
7092
7093 if (new_crtc_state->update_lrr)
7094 intel_set_transcoder_timings_lrr(new_crtc_state);
7095}
7096
7097static void commit_pipe_pre_planes(struct intel_atomic_state *state,
7098 struct intel_crtc *crtc)
7099{
7100 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7101 const struct intel_crtc_state *old_crtc_state =
7102 intel_atomic_get_old_crtc_state(state, crtc);
7103 const struct intel_crtc_state *new_crtc_state =
7104 intel_atomic_get_new_crtc_state(state, crtc);
7105 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7106
7107 /*
7108 * During modesets pipe configuration was programmed as the
7109 * CRTC was enabled.
7110 */
7111 if (!modeset && !new_crtc_state->use_dsb) {
7112 if (intel_crtc_needs_color_update(new_crtc_state))
7113 intel_color_commit_arm(NULL, new_crtc_state);
7114
7115 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7116 bdw_set_pipe_misc(NULL, new_crtc_state);
7117
7118 if (intel_crtc_needs_fastset(new_crtc_state))
7119 intel_pipe_fastset(old_crtc_state, new_crtc_state);
7120 }
7121
7122 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
7123
7124 intel_atomic_update_watermarks(state, crtc);
7125}
7126
7127static void commit_pipe_post_planes(struct intel_atomic_state *state,
7128 struct intel_crtc *crtc)
7129{
7130 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7131 const struct intel_crtc_state *new_crtc_state =
7132 intel_atomic_get_new_crtc_state(state, crtc);
7133
7134 /*
7135 * Disable the scaler(s) after the plane(s) so that we don't
7136 * get a catastrophic underrun even if the two operations
7137 * end up happening in two different frames.
7138 */
7139 if (DISPLAY_VER(dev_priv) >= 9 &&
7140 !intel_crtc_needs_modeset(new_crtc_state))
7141 skl_detach_scalers(new_crtc_state);
7142
7143 if (intel_crtc_vrr_enabling(state, crtc))
7144 intel_vrr_enable(new_crtc_state);
7145}
7146
7147static void intel_enable_crtc(struct intel_atomic_state *state,
7148 struct intel_crtc *crtc)
7149{
7150 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7151 const struct intel_crtc_state *new_crtc_state =
7152 intel_atomic_get_new_crtc_state(state, crtc);
7153 struct intel_crtc *pipe_crtc;
7154
7155 if (!intel_crtc_needs_modeset(new_crtc_state))
7156 return;
7157
7158 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
7159 intel_crtc_joined_pipe_mask(new_crtc_state)) {
7160 const struct intel_crtc_state *pipe_crtc_state =
7161 intel_atomic_get_new_crtc_state(state, pipe_crtc);
7162
7163 /* VRR will be enable later, if required */
7164 intel_crtc_update_active_timings(pipe_crtc_state, false);
7165 }
7166
7167 dev_priv->display.funcs.display->crtc_enable(state, crtc);
7168
7169 /* vblanks work again, re-enable pipe CRC. */
7170 intel_crtc_enable_pipe_crc(crtc);
7171}
7172
7173static void intel_pre_update_crtc(struct intel_atomic_state *state,
7174 struct intel_crtc *crtc)
7175{
7176 struct drm_i915_private *i915 = to_i915(state->base.dev);
7177 const struct intel_crtc_state *old_crtc_state =
7178 intel_atomic_get_old_crtc_state(state, crtc);
7179 struct intel_crtc_state *new_crtc_state =
7180 intel_atomic_get_new_crtc_state(state, crtc);
7181 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7182
7183 if (old_crtc_state->inherited ||
7184 intel_crtc_needs_modeset(new_crtc_state)) {
7185 if (HAS_DPT(i915))
7186 intel_dpt_configure(crtc);
7187 }
7188
7189 if (!modeset) {
7190 if (new_crtc_state->preload_luts &&
7191 intel_crtc_needs_color_update(new_crtc_state))
7192 intel_color_load_luts(new_crtc_state);
7193
7194 intel_pre_plane_update(state, crtc);
7195
7196 if (intel_crtc_needs_fastset(new_crtc_state))
7197 intel_encoders_update_pipe(state, crtc);
7198
7199 if (DISPLAY_VER(i915) >= 11 &&
7200 intel_crtc_needs_fastset(new_crtc_state))
7201 icl_set_pipe_chicken(new_crtc_state);
7202
7203 if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
7204 cmrr_params_changed(old_crtc_state, new_crtc_state))
7205 intel_vrr_set_transcoder_timings(new_crtc_state);
7206 }
7207
7208 intel_fbc_update(state, crtc);
7209
7210 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
7211
7212 if (!modeset &&
7213 intel_crtc_needs_color_update(new_crtc_state) &&
7214 !new_crtc_state->use_dsb)
7215 intel_color_commit_noarm(NULL, new_crtc_state);
7216
7217 if (!new_crtc_state->use_dsb)
7218 intel_crtc_planes_update_noarm(NULL, state, crtc);
7219}
7220
7221static void intel_update_crtc(struct intel_atomic_state *state,
7222 struct intel_crtc *crtc)
7223{
7224 const struct intel_crtc_state *old_crtc_state =
7225 intel_atomic_get_old_crtc_state(state, crtc);
7226 struct intel_crtc_state *new_crtc_state =
7227 intel_atomic_get_new_crtc_state(state, crtc);
7228
7229 if (new_crtc_state->use_dsb) {
7230 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
7231
7232 intel_dsb_commit(new_crtc_state->dsb_commit, false);
7233 } else {
7234 /* Perform vblank evasion around commit operation */
7235 intel_pipe_update_start(state, crtc);
7236
7237 if (new_crtc_state->dsb_commit)
7238 intel_dsb_commit(new_crtc_state->dsb_commit, false);
7239
7240 commit_pipe_pre_planes(state, crtc);
7241
7242 intel_crtc_planes_update_arm(NULL, state, crtc);
7243
7244 commit_pipe_post_planes(state, crtc);
7245
7246 intel_pipe_update_end(state, crtc);
7247 }
7248
7249 /*
7250 * VRR/Seamless M/N update may need to update frame timings.
7251 *
7252 * FIXME Should be synchronized with the start of vblank somehow...
7253 */
7254 if (intel_crtc_vrr_enabling(state, crtc) ||
7255 new_crtc_state->update_m_n || new_crtc_state->update_lrr)
7256 intel_crtc_update_active_timings(new_crtc_state,
7257 new_crtc_state->vrr.enable);
7258
7259 /*
7260 * We usually enable FIFO underrun interrupts as part of the
7261 * CRTC enable sequence during modesets. But when we inherit a
7262 * valid pipe configuration from the BIOS we need to take care
7263 * of enabling them on the CRTC's first fastset.
7264 */
7265 if (intel_crtc_needs_fastset(new_crtc_state) &&
7266 old_crtc_state->inherited)
7267 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
7268}
7269
7270static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
7271 struct intel_crtc *crtc)
7272{
7273 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7274 const struct intel_crtc_state *old_crtc_state =
7275 intel_atomic_get_old_crtc_state(state, crtc);
7276 struct intel_crtc *pipe_crtc;
7277
7278 /*
7279 * We need to disable pipe CRC before disabling the pipe,
7280 * or we race against vblank off.
7281 */
7282 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
7283 intel_crtc_joined_pipe_mask(old_crtc_state))
7284 intel_crtc_disable_pipe_crc(pipe_crtc);
7285
7286 dev_priv->display.funcs.display->crtc_disable(state, crtc);
7287
7288 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
7289 intel_crtc_joined_pipe_mask(old_crtc_state)) {
7290 const struct intel_crtc_state *new_pipe_crtc_state =
7291 intel_atomic_get_new_crtc_state(state, pipe_crtc);
7292
7293 pipe_crtc->active = false;
7294 intel_fbc_disable(pipe_crtc);
7295
7296 if (!new_pipe_crtc_state->hw.active)
7297 intel_initial_watermarks(state, pipe_crtc);
7298 }
7299}
7300
7301static void intel_commit_modeset_disables(struct intel_atomic_state *state)
7302{
7303 struct drm_i915_private *i915 = to_i915(state->base.dev);
7304 const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7305 struct intel_crtc *crtc;
7306 u8 disable_pipes = 0;
7307 int i;
7308
7309 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7310 new_crtc_state, i) {
7311 if (!intel_crtc_needs_modeset(new_crtc_state))
7312 continue;
7313
7314 /*
7315 * Needs to be done even for pipes
7316 * that weren't enabled previously.
7317 */
7318 intel_pre_plane_update(state, crtc);
7319
7320 if (!old_crtc_state->hw.active)
7321 continue;
7322
7323 disable_pipes |= BIT(crtc->pipe);
7324 }
7325
7326 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
7327 if ((disable_pipes & BIT(crtc->pipe)) == 0)
7328 continue;
7329
7330 intel_crtc_disable_planes(state, crtc);
7331
7332 drm_vblank_work_flush_all(&crtc->base);
7333 }
7334
7335 /* Only disable port sync and MST slaves */
7336 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
7337 if ((disable_pipes & BIT(crtc->pipe)) == 0)
7338 continue;
7339
7340 if (intel_crtc_is_joiner_secondary(old_crtc_state))
7341 continue;
7342
7343 /* In case of Transcoder port Sync master slave CRTCs can be
7344 * assigned in any order and we need to make sure that
7345 * slave CRTCs are disabled first and then master CRTC since
7346 * Slave vblanks are masked till Master Vblanks.
7347 */
7348 if (!is_trans_port_sync_slave(old_crtc_state) &&
7349 !intel_dp_mst_is_slave_trans(old_crtc_state))
7350 continue;
7351
7352 intel_old_crtc_state_disables(state, crtc);
7353
7354 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
7355 }
7356
7357 /* Disable everything else left on */
7358 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
7359 if ((disable_pipes & BIT(crtc->pipe)) == 0)
7360 continue;
7361
7362 if (intel_crtc_is_joiner_secondary(old_crtc_state))
7363 continue;
7364
7365 intel_old_crtc_state_disables(state, crtc);
7366
7367 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
7368 }
7369
7370 drm_WARN_ON(&i915->drm, disable_pipes);
7371}
7372
7373static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7374{
7375 struct intel_crtc_state *new_crtc_state;
7376 struct intel_crtc *crtc;
7377 int i;
7378
7379 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7380 if (!new_crtc_state->hw.active)
7381 continue;
7382
7383 intel_enable_crtc(state, crtc);
7384 intel_pre_update_crtc(state, crtc);
7385 }
7386
7387 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7388 if (!new_crtc_state->hw.active)
7389 continue;
7390
7391 intel_update_crtc(state, crtc);
7392 }
7393}
7394
7395static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7396{
7397 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7398 struct intel_crtc *crtc;
7399 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7400 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7401 u8 update_pipes = 0, modeset_pipes = 0;
7402 int i;
7403
7404 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7405 enum pipe pipe = crtc->pipe;
7406
7407 if (!new_crtc_state->hw.active)
7408 continue;
7409
7410 /* ignore allocations for crtc's that have been turned off. */
7411 if (!intel_crtc_needs_modeset(new_crtc_state)) {
7412 entries[pipe] = old_crtc_state->wm.skl.ddb;
7413 update_pipes |= BIT(pipe);
7414 } else {
7415 modeset_pipes |= BIT(pipe);
7416 }
7417 }
7418
7419 /*
7420 * Whenever the number of active pipes changes, we need to make sure we
7421 * update the pipes in the right order so that their ddb allocations
7422 * never overlap with each other between CRTC updates. Otherwise we'll
7423 * cause pipe underruns and other bad stuff.
7424 *
7425 * So first lets enable all pipes that do not need a fullmodeset as
7426 * those don't have any external dependency.
7427 */
7428 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7429 enum pipe pipe = crtc->pipe;
7430
7431 if ((update_pipes & BIT(pipe)) == 0)
7432 continue;
7433
7434 intel_pre_update_crtc(state, crtc);
7435 }
7436
7437 intel_dbuf_mbus_pre_ddb_update(state);
7438
7439 while (update_pipes) {
7440 /*
7441 * Commit in reverse order to make joiner primary
7442 * send the uapi events after secondaries are done.
7443 */
7444 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
7445 new_crtc_state, i) {
7446 enum pipe pipe = crtc->pipe;
7447
7448 if ((update_pipes & BIT(pipe)) == 0)
7449 continue;
7450
7451 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7452 entries, I915_MAX_PIPES, pipe))
7453 continue;
7454
7455 entries[pipe] = new_crtc_state->wm.skl.ddb;
7456 update_pipes &= ~BIT(pipe);
7457
7458 intel_update_crtc(state, crtc);
7459
7460 /*
7461 * If this is an already active pipe, it's DDB changed,
7462 * and this isn't the last pipe that needs updating
7463 * then we need to wait for a vblank to pass for the
7464 * new ddb allocation to take effect.
7465 */
7466 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7467 &old_crtc_state->wm.skl.ddb) &&
7468 (update_pipes | modeset_pipes))
7469 intel_crtc_wait_for_next_vblank(crtc);
7470 }
7471 }
7472
7473 intel_dbuf_mbus_post_ddb_update(state);
7474
7475 update_pipes = modeset_pipes;
7476
7477 /*
7478 * Enable all pipes that needs a modeset and do not depends on other
7479 * pipes
7480 */
7481 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7482 enum pipe pipe = crtc->pipe;
7483
7484 if ((modeset_pipes & BIT(pipe)) == 0)
7485 continue;
7486
7487 if (intel_crtc_is_joiner_secondary(new_crtc_state))
7488 continue;
7489
7490 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7491 is_trans_port_sync_master(new_crtc_state))
7492 continue;
7493
7494 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7495
7496 intel_enable_crtc(state, crtc);
7497 }
7498
7499 /*
7500 * Then we enable all remaining pipes that depend on other
7501 * pipes: MST slaves and port sync masters
7502 */
7503 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7504 enum pipe pipe = crtc->pipe;
7505
7506 if ((modeset_pipes & BIT(pipe)) == 0)
7507 continue;
7508
7509 if (intel_crtc_is_joiner_secondary(new_crtc_state))
7510 continue;
7511
7512 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7513
7514 intel_enable_crtc(state, crtc);
7515 }
7516
7517 /*
7518 * Finally we do the plane updates/etc. for all pipes that got enabled.
7519 */
7520 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7521 enum pipe pipe = crtc->pipe;
7522
7523 if ((update_pipes & BIT(pipe)) == 0)
7524 continue;
7525
7526 intel_pre_update_crtc(state, crtc);
7527 }
7528
7529 /*
7530 * Commit in reverse order to make joiner primary
7531 * send the uapi events after secondaries are done.
7532 */
7533 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7534 enum pipe pipe = crtc->pipe;
7535
7536 if ((update_pipes & BIT(pipe)) == 0)
7537 continue;
7538
7539 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7540 entries, I915_MAX_PIPES, pipe));
7541
7542 entries[pipe] = new_crtc_state->wm.skl.ddb;
7543 update_pipes &= ~BIT(pipe);
7544
7545 intel_update_crtc(state, crtc);
7546 }
7547
7548 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7549 drm_WARN_ON(&dev_priv->drm, update_pipes);
7550}
7551
7552static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7553{
7554 struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
7555 struct drm_plane *plane;
7556 struct drm_plane_state *new_plane_state;
7557 int ret, i;
7558
7559 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
7560 if (new_plane_state->fence) {
7561 ret = dma_fence_wait_timeout(new_plane_state->fence, false,
7562 i915_fence_timeout(i915));
7563 if (ret <= 0)
7564 break;
7565
7566 dma_fence_put(new_plane_state->fence);
7567 new_plane_state->fence = NULL;
7568 }
7569 }
7570}
7571
7572static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
7573{
7574 if (crtc_state->dsb_commit)
7575 intel_dsb_wait(crtc_state->dsb_commit);
7576
7577 intel_color_wait_commit(crtc_state);
7578}
7579
7580static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)
7581{
7582 if (crtc_state->dsb_commit) {
7583 intel_dsb_cleanup(crtc_state->dsb_commit);
7584 crtc_state->dsb_commit = NULL;
7585 }
7586
7587 intel_color_cleanup_commit(crtc_state);
7588}
7589
7590static void intel_atomic_cleanup_work(struct work_struct *work)
7591{
7592 struct intel_atomic_state *state =
7593 container_of(work, struct intel_atomic_state, base.commit_work);
7594 struct drm_i915_private *i915 = to_i915(state->base.dev);
7595 struct intel_crtc_state *old_crtc_state;
7596 struct intel_crtc *crtc;
7597 int i;
7598
7599 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7600 intel_atomic_dsb_cleanup(old_crtc_state);
7601
7602 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7603 drm_atomic_helper_commit_cleanup_done(&state->base);
7604 drm_atomic_state_put(&state->base);
7605}
7606
7607static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7608{
7609 struct drm_i915_private *i915 = to_i915(state->base.dev);
7610 struct intel_plane *plane;
7611 struct intel_plane_state *plane_state;
7612 int i;
7613
7614 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7615 struct drm_framebuffer *fb = plane_state->hw.fb;
7616 int cc_plane;
7617 int ret;
7618
7619 if (!fb)
7620 continue;
7621
7622 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7623 if (cc_plane < 0)
7624 continue;
7625
7626 /*
7627 * The layout of the fast clear color value expected by HW
7628 * (the DRM ABI requiring this value to be located in fb at
7629 * offset 0 of cc plane, plane #2 previous generations or
7630 * plane #1 for flat ccs):
7631 * - 4 x 4 bytes per-channel value
7632 * (in surface type specific float/int format provided by the fb user)
7633 * - 8 bytes native color value used by the display
7634 * (converted/written by GPU during a fast clear operation using the
7635 * above per-channel values)
7636 *
7637 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7638 * caller made sure that the object is synced wrt. the related color clear value
7639 * GPU write on it.
7640 */
7641 ret = intel_bo_read_from_page(intel_fb_bo(fb),
7642 fb->offsets[cc_plane] + 16,
7643 &plane_state->ccval,
7644 sizeof(plane_state->ccval));
7645 /* The above could only fail if the FB obj has an unexpected backing store type. */
7646 drm_WARN_ON(&i915->drm, ret);
7647 }
7648}
7649
7650static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
7651 struct intel_crtc *crtc)
7652{
7653 intel_color_prepare_commit(state, crtc);
7654}
7655
7656static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
7657 struct intel_crtc *crtc)
7658{
7659 const struct intel_crtc_state *old_crtc_state =
7660 intel_atomic_get_old_crtc_state(state, crtc);
7661 struct intel_crtc_state *new_crtc_state =
7662 intel_atomic_get_new_crtc_state(state, crtc);
7663
7664 if (!new_crtc_state->hw.active)
7665 return;
7666
7667 if (state->base.legacy_cursor_update)
7668 return;
7669
7670 /* FIXME deal with everything */
7671 new_crtc_state->use_dsb =
7672 new_crtc_state->update_planes &&
7673 !new_crtc_state->vrr.enable &&
7674 !new_crtc_state->do_async_flip &&
7675 !new_crtc_state->has_psr &&
7676 !new_crtc_state->scaler_state.scaler_users &&
7677 !old_crtc_state->scaler_state.scaler_users &&
7678 !intel_crtc_needs_modeset(new_crtc_state) &&
7679 !intel_crtc_needs_fastset(new_crtc_state);
7680
7681 if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
7682 return;
7683
7684 /*
7685 * Rough estimate:
7686 * ~64 registers per each plane * 8 planes = 512
7687 * Double that for pipe stuff and other overhead.
7688 */
7689 new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
7690 new_crtc_state->use_dsb ? 1024 : 16);
7691 if (!new_crtc_state->dsb_commit) {
7692 new_crtc_state->use_dsb = false;
7693 intel_color_cleanup_commit(new_crtc_state);
7694 return;
7695 }
7696
7697 if (new_crtc_state->use_dsb) {
7698 if (intel_crtc_needs_color_update(new_crtc_state))
7699 intel_color_commit_noarm(new_crtc_state->dsb_commit,
7700 new_crtc_state);
7701 intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
7702 state, crtc);
7703
7704 intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
7705
7706 if (intel_crtc_needs_color_update(new_crtc_state))
7707 intel_color_commit_arm(new_crtc_state->dsb_commit,
7708 new_crtc_state);
7709 bdw_set_pipe_misc(new_crtc_state->dsb_commit,
7710 new_crtc_state);
7711 intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,
7712 state, crtc);
7713
7714 if (!new_crtc_state->dsb_color_vblank) {
7715 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
7716 intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
7717 intel_dsb_interrupt(new_crtc_state->dsb_commit);
7718 }
7719 }
7720
7721 if (new_crtc_state->dsb_color_vblank)
7722 intel_dsb_chain(state, new_crtc_state->dsb_commit,
7723 new_crtc_state->dsb_color_vblank, true);
7724
7725 intel_dsb_finish(new_crtc_state->dsb_commit);
7726}
7727
7728static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7729{
7730 struct drm_device *dev = state->base.dev;
7731 struct drm_i915_private *dev_priv = to_i915(dev);
7732 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7733 struct intel_crtc *crtc;
7734 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7735 intel_wakeref_t wakeref = NULL;
7736 int i;
7737
7738 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7739 intel_atomic_dsb_prepare(state, crtc);
7740
7741 intel_atomic_commit_fence_wait(state);
7742
7743 intel_td_flush(dev_priv);
7744
7745 intel_atomic_prepare_plane_clear_colors(state);
7746
7747 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7748 intel_atomic_dsb_finish(state, crtc);
7749
7750 drm_atomic_helper_wait_for_dependencies(&state->base);
7751 drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7752 intel_atomic_global_state_wait_for_dependencies(state);
7753
7754 /*
7755 * During full modesets we write a lot of registers, wait
7756 * for PLLs, etc. Doing that while DC states are enabled
7757 * is not a good idea.
7758 *
7759 * During fastsets and other updates we also need to
7760 * disable DC states due to the following scenario:
7761 * 1. DC5 exit and PSR exit happen
7762 * 2. Some or all _noarm() registers are written
7763 * 3. Due to some long delay PSR is re-entered
7764 * 4. DC5 entry -> DMC saves the already written new
7765 * _noarm() registers and the old not yet written
7766 * _arm() registers
7767 * 5. DC5 exit -> DMC restores a mixture of old and
7768 * new register values and arms the update
7769 * 6. PSR exit -> hardware latches a mixture of old and
7770 * new register values -> corrupted frame, or worse
7771 * 7. New _arm() registers are finally written
7772 * 8. Hardware finally latches a complete set of new
7773 * register values, and subsequent frames will be OK again
7774 *
7775 * Also note that due to the pipe CSC hardware issues on
7776 * SKL/GLK DC states must remain off until the pipe CSC
7777 * state readout has happened. Otherwise we risk corrupting
7778 * the CSC latched register values with the readout (see
7779 * skl_read_csc() and skl_color_commit_noarm()).
7780 */
7781 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7782
7783 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7784 new_crtc_state, i) {
7785 if (intel_crtc_needs_modeset(new_crtc_state) ||
7786 intel_crtc_needs_fastset(new_crtc_state))
7787 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7788 }
7789
7790 intel_commit_modeset_disables(state);
7791
7792 intel_dp_tunnel_atomic_alloc_bw(state);
7793
7794 /* FIXME: Eventually get rid of our crtc->config pointer */
7795 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7796 crtc->config = new_crtc_state;
7797
7798 /*
7799 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7800 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7801 * index, cdclk/ddiclk frequencies are supposed to be configured before
7802 * the cdclk config is set.
7803 */
7804 intel_pmdemand_pre_plane_update(state);
7805
7806 if (state->modeset) {
7807 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7808
7809 intel_set_cdclk_pre_plane_update(state);
7810
7811 intel_modeset_verify_disabled(state);
7812 }
7813
7814 intel_sagv_pre_plane_update(state);
7815
7816 /* Complete the events for pipes that have now been disabled */
7817 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7818 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7819
7820 /* Complete events for now disable pipes here. */
7821 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7822 spin_lock_irq(&dev->event_lock);
7823 drm_crtc_send_vblank_event(&crtc->base,
7824 new_crtc_state->uapi.event);
7825 spin_unlock_irq(&dev->event_lock);
7826
7827 new_crtc_state->uapi.event = NULL;
7828 }
7829 }
7830
7831 intel_encoders_update_prepare(state);
7832
7833 intel_dbuf_pre_plane_update(state);
7834
7835 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7836 if (new_crtc_state->do_async_flip)
7837 intel_crtc_enable_flip_done(state, crtc);
7838 }
7839
7840 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7841 dev_priv->display.funcs.display->commit_modeset_enables(state);
7842
7843 if (state->modeset)
7844 intel_set_cdclk_post_plane_update(state);
7845
7846 intel_wait_for_vblank_workers(state);
7847
7848 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7849 * already, but still need the state for the delayed optimization. To
7850 * fix this:
7851 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7852 * - schedule that vblank worker _before_ calling hw_done
7853 * - at the start of commit_tail, cancel it _synchrously
7854 * - switch over to the vblank wait helper in the core after that since
7855 * we don't need out special handling any more.
7856 */
7857 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7858
7859 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7860 if (new_crtc_state->do_async_flip)
7861 intel_crtc_disable_flip_done(state, crtc);
7862
7863 intel_atomic_dsb_wait_commit(new_crtc_state);
7864 }
7865
7866 /*
7867 * Now that the vblank has passed, we can go ahead and program the
7868 * optimal watermarks on platforms that need two-step watermark
7869 * programming.
7870 *
7871 * TODO: Move this (and other cleanup) to an async worker eventually.
7872 */
7873 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7874 new_crtc_state, i) {
7875 /*
7876 * Gen2 reports pipe underruns whenever all planes are disabled.
7877 * So re-enable underrun reporting after some planes get enabled.
7878 *
7879 * We do this before .optimize_watermarks() so that we have a
7880 * chance of catching underruns with the intermediate watermarks
7881 * vs. the new plane configuration.
7882 */
7883 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7884 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7885
7886 intel_optimize_watermarks(state, crtc);
7887 }
7888
7889 intel_dbuf_post_plane_update(state);
7890
7891 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7892 intel_post_plane_update(state, crtc);
7893
7894 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7895
7896 intel_modeset_verify_crtc(state, crtc);
7897
7898 intel_post_plane_update_after_readout(state, crtc);
7899
7900 /*
7901 * DSB cleanup is done in cleanup_work aligning with framebuffer
7902 * cleanup. So copy and reset the dsb structure to sync with
7903 * commit_done and later do dsb cleanup in cleanup_work.
7904 *
7905 * FIXME get rid of this funny new->old swapping
7906 */
7907 old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);
7908 old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
7909 }
7910
7911 /* Underruns don't always raise interrupts, so check manually */
7912 intel_check_cpu_fifo_underruns(dev_priv);
7913 intel_check_pch_fifo_underruns(dev_priv);
7914
7915 if (state->modeset)
7916 intel_verify_planes(state);
7917
7918 intel_sagv_post_plane_update(state);
7919 intel_pmdemand_post_plane_update(state);
7920
7921 drm_atomic_helper_commit_hw_done(&state->base);
7922 intel_atomic_global_state_commit_done(state);
7923
7924 if (state->modeset) {
7925 /* As one of the primary mmio accessors, KMS has a high
7926 * likelihood of triggering bugs in unclaimed access. After we
7927 * finish modesetting, see if an error has been flagged, and if
7928 * so enable debugging for the next modeset - and hope we catch
7929 * the culprit.
7930 */
7931 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7932 }
7933 /*
7934 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7935 * toggling overhead at and above 60 FPS.
7936 */
7937 intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7938 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7939
7940 /*
7941 * Defer the cleanup of the old state to a separate worker to not
7942 * impede the current task (userspace for blocking modesets) that
7943 * are executed inline. For out-of-line asynchronous modesets/flips,
7944 * deferring to a new worker seems overkill, but we would place a
7945 * schedule point (cond_resched()) here anyway to keep latencies
7946 * down.
7947 */
7948 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7949 queue_work(system_highpri_wq, &state->base.commit_work);
7950}
7951
7952static void intel_atomic_commit_work(struct work_struct *work)
7953{
7954 struct intel_atomic_state *state =
7955 container_of(work, struct intel_atomic_state, base.commit_work);
7956
7957 intel_atomic_commit_tail(state);
7958}
7959
7960static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7961{
7962 struct intel_plane_state *old_plane_state, *new_plane_state;
7963 struct intel_plane *plane;
7964 int i;
7965
7966 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7967 new_plane_state, i)
7968 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7969 to_intel_frontbuffer(new_plane_state->hw.fb),
7970 plane->frontbuffer_bit);
7971}
7972
7973static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
7974{
7975 int ret;
7976
7977 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7978 if (ret)
7979 return ret;
7980
7981 ret = intel_atomic_global_state_setup_commit(state);
7982 if (ret)
7983 return ret;
7984
7985 return 0;
7986}
7987
7988static int intel_atomic_swap_state(struct intel_atomic_state *state)
7989{
7990 int ret;
7991
7992 ret = drm_atomic_helper_swap_state(&state->base, true);
7993 if (ret)
7994 return ret;
7995
7996 intel_atomic_swap_global_state(state);
7997
7998 intel_shared_dpll_swap_state(state);
7999
8000 intel_atomic_track_fbs(state);
8001
8002 return 0;
8003}
8004
8005int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
8006 bool nonblock)
8007{
8008 struct intel_atomic_state *state = to_intel_atomic_state(_state);
8009 struct drm_i915_private *dev_priv = to_i915(dev);
8010 int ret = 0;
8011
8012 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
8013
8014 /*
8015 * The intel_legacy_cursor_update() fast path takes care
8016 * of avoiding the vblank waits for simple cursor
8017 * movement and flips. For cursor on/off and size changes,
8018 * we want to perform the vblank waits so that watermark
8019 * updates happen during the correct frames. Gen9+ have
8020 * double buffered watermarks and so shouldn't need this.
8021 *
8022 * Unset state->legacy_cursor_update before the call to
8023 * drm_atomic_helper_setup_commit() because otherwise
8024 * drm_atomic_helper_wait_for_flip_done() is a noop and
8025 * we get FIFO underruns because we didn't wait
8026 * for vblank.
8027 *
8028 * FIXME doing watermarks and fb cleanup from a vblank worker
8029 * (assuming we had any) would solve these problems.
8030 */
8031 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
8032 struct intel_crtc_state *new_crtc_state;
8033 struct intel_crtc *crtc;
8034 int i;
8035
8036 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
8037 if (new_crtc_state->wm.need_postvbl_update ||
8038 new_crtc_state->update_wm_post)
8039 state->base.legacy_cursor_update = false;
8040 }
8041
8042 ret = intel_atomic_prepare_commit(state);
8043 if (ret) {
8044 drm_dbg_atomic(&dev_priv->drm,
8045 "Preparing state failed with %i\n", ret);
8046 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
8047 return ret;
8048 }
8049
8050 ret = intel_atomic_setup_commit(state, nonblock);
8051 if (!ret)
8052 ret = intel_atomic_swap_state(state);
8053
8054 if (ret) {
8055 drm_atomic_helper_unprepare_planes(dev, &state->base);
8056 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
8057 return ret;
8058 }
8059
8060 drm_atomic_state_get(&state->base);
8061 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
8062
8063 if (nonblock && state->modeset) {
8064 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
8065 } else if (nonblock) {
8066 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
8067 } else {
8068 if (state->modeset)
8069 flush_workqueue(dev_priv->display.wq.modeset);
8070 intel_atomic_commit_tail(state);
8071 }
8072
8073 return 0;
8074}
8075
8076/**
8077 * intel_plane_destroy - destroy a plane
8078 * @plane: plane to destroy
8079 *
8080 * Common destruction function for all types of planes (primary, cursor,
8081 * sprite).
8082 */
8083void intel_plane_destroy(struct drm_plane *plane)
8084{
8085 drm_plane_cleanup(plane);
8086 kfree(to_intel_plane(plane));
8087}
8088
8089static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
8090{
8091 struct drm_device *dev = encoder->base.dev;
8092 struct intel_encoder *source_encoder;
8093 u32 possible_clones = 0;
8094
8095 for_each_intel_encoder(dev, source_encoder) {
8096 if (encoders_cloneable(encoder, source_encoder))
8097 possible_clones |= drm_encoder_mask(&source_encoder->base);
8098 }
8099
8100 return possible_clones;
8101}
8102
8103static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
8104{
8105 struct drm_device *dev = encoder->base.dev;
8106 struct intel_crtc *crtc;
8107 u32 possible_crtcs = 0;
8108
8109 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
8110 possible_crtcs |= drm_crtc_mask(&crtc->base);
8111
8112 return possible_crtcs;
8113}
8114
8115static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
8116{
8117 if (!IS_MOBILE(dev_priv))
8118 return false;
8119
8120 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
8121 return false;
8122
8123 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
8124 return false;
8125
8126 return true;
8127}
8128
8129static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
8130{
8131 if (DISPLAY_VER(dev_priv) >= 9)
8132 return false;
8133
8134 if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
8135 return false;
8136
8137 if (HAS_PCH_LPT_H(dev_priv) &&
8138 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
8139 return false;
8140
8141 /* DDI E can't be used if DDI A requires 4 lanes */
8142 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
8143 return false;
8144
8145 if (!dev_priv->display.vbt.int_crt_support)
8146 return false;
8147
8148 return true;
8149}
8150
8151bool assert_port_valid(struct drm_i915_private *i915, enum port port)
8152{
8153 return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
8154 "Platform does not support port %c\n", port_name(port));
8155}
8156
8157void intel_setup_outputs(struct drm_i915_private *dev_priv)
8158{
8159 struct intel_display *display = &dev_priv->display;
8160 struct intel_encoder *encoder;
8161 bool dpd_is_edp = false;
8162
8163 intel_pps_unlock_regs_wa(display);
8164
8165 if (!HAS_DISPLAY(dev_priv))
8166 return;
8167
8168 if (HAS_DDI(dev_priv)) {
8169 if (intel_ddi_crt_present(dev_priv))
8170 intel_crt_init(display);
8171
8172 intel_bios_for_each_encoder(display, intel_ddi_init);
8173
8174 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
8175 vlv_dsi_init(dev_priv);
8176 } else if (HAS_PCH_SPLIT(dev_priv)) {
8177 int found;
8178
8179 /*
8180 * intel_edp_init_connector() depends on this completing first,
8181 * to prevent the registration of both eDP and LVDS and the
8182 * incorrect sharing of the PPS.
8183 */
8184 intel_lvds_init(dev_priv);
8185 intel_crt_init(display);
8186
8187 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8188
8189 if (ilk_has_edp_a(dev_priv))
8190 g4x_dp_init(dev_priv, DP_A, PORT_A);
8191
8192 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
8193 /* PCH SDVOB multiplex with HDMIB */
8194 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
8195 if (!found)
8196 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
8197 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
8198 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
8199 }
8200
8201 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
8202 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
8203
8204 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
8205 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
8206
8207 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
8208 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
8209
8210 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
8211 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
8212 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8213 bool has_edp, has_port;
8214
8215 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
8216 intel_crt_init(display);
8217
8218 /*
8219 * The DP_DETECTED bit is the latched state of the DDC
8220 * SDA pin at boot. However since eDP doesn't require DDC
8221 * (no way to plug in a DP->HDMI dongle) the DDC pins for
8222 * eDP ports may have been muxed to an alternate function.
8223 * Thus we can't rely on the DP_DETECTED bit alone to detect
8224 * eDP ports. Consult the VBT as well as DP_DETECTED to
8225 * detect eDP ports.
8226 *
8227 * Sadly the straps seem to be missing sometimes even for HDMI
8228 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
8229 * and VBT for the presence of the port. Additionally we can't
8230 * trust the port type the VBT declares as we've seen at least
8231 * HDMI ports that the VBT claim are DP or eDP.
8232 */
8233 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8234 has_port = intel_bios_is_port_present(display, PORT_B);
8235 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8236 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8237 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8238 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8239
8240 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8241 has_port = intel_bios_is_port_present(display, PORT_C);
8242 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8243 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
8244 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
8245 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
8246
8247 if (IS_CHERRYVIEW(dev_priv)) {
8248 /*
8249 * eDP not supported on port D,
8250 * so no need to worry about it
8251 */
8252 has_port = intel_bios_is_port_present(display, PORT_D);
8253 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
8254 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
8255 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
8256 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
8257 }
8258
8259 vlv_dsi_init(dev_priv);
8260 } else if (IS_PINEVIEW(dev_priv)) {
8261 intel_lvds_init(dev_priv);
8262 intel_crt_init(display);
8263 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
8264 bool found = false;
8265
8266 if (IS_MOBILE(dev_priv))
8267 intel_lvds_init(dev_priv);
8268
8269 intel_crt_init(display);
8270
8271 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8272 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
8273 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
8274 if (!found && IS_G4X(dev_priv)) {
8275 drm_dbg_kms(&dev_priv->drm,
8276 "probing HDMI on SDVOB\n");
8277 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
8278 }
8279
8280 if (!found && IS_G4X(dev_priv))
8281 g4x_dp_init(dev_priv, DP_B, PORT_B);
8282 }
8283
8284 /* Before G4X SDVOC doesn't have its own detect register */
8285
8286 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8287 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
8288 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
8289 }
8290
8291 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
8292
8293 if (IS_G4X(dev_priv)) {
8294 drm_dbg_kms(&dev_priv->drm,
8295 "probing HDMI on SDVOC\n");
8296 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
8297 }
8298 if (IS_G4X(dev_priv))
8299 g4x_dp_init(dev_priv, DP_C, PORT_C);
8300 }
8301
8302 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
8303 g4x_dp_init(dev_priv, DP_D, PORT_D);
8304
8305 if (SUPPORTS_TV(dev_priv))
8306 intel_tv_init(display);
8307 } else if (DISPLAY_VER(dev_priv) == 2) {
8308 if (IS_I85X(dev_priv))
8309 intel_lvds_init(dev_priv);
8310
8311 intel_crt_init(display);
8312 intel_dvo_init(dev_priv);
8313 }
8314
8315 for_each_intel_encoder(&dev_priv->drm, encoder) {
8316 encoder->base.possible_crtcs =
8317 intel_encoder_possible_crtcs(encoder);
8318 encoder->base.possible_clones =
8319 intel_encoder_possible_clones(encoder);
8320 }
8321
8322 intel_init_pch_refclk(dev_priv);
8323
8324 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
8325}
8326
8327static int max_dotclock(struct drm_i915_private *i915)
8328{
8329 int max_dotclock = i915->display.cdclk.max_dotclk_freq;
8330
8331 if (HAS_ULTRAJOINER(i915))
8332 max_dotclock *= 4;
8333 else if (HAS_UNCOMPRESSED_JOINER(i915) || HAS_BIGJOINER(i915))
8334 max_dotclock *= 2;
8335
8336 return max_dotclock;
8337}
8338
8339enum drm_mode_status intel_mode_valid(struct drm_device *dev,
8340 const struct drm_display_mode *mode)
8341{
8342 struct drm_i915_private *dev_priv = to_i915(dev);
8343 int hdisplay_max, htotal_max;
8344 int vdisplay_max, vtotal_max;
8345
8346 /*
8347 * Can't reject DBLSCAN here because Xorg ddxen can add piles
8348 * of DBLSCAN modes to the output's mode list when they detect
8349 * the scaling mode property on the connector. And they don't
8350 * ask the kernel to validate those modes in any way until
8351 * modeset time at which point the client gets a protocol error.
8352 * So in order to not upset those clients we silently ignore the
8353 * DBLSCAN flag on such connectors. For other connectors we will
8354 * reject modes with the DBLSCAN flag in encoder->compute_config().
8355 * And we always reject DBLSCAN modes in connector->mode_valid()
8356 * as we never want such modes on the connector's mode list.
8357 */
8358
8359 if (mode->vscan > 1)
8360 return MODE_NO_VSCAN;
8361
8362 if (mode->flags & DRM_MODE_FLAG_HSKEW)
8363 return MODE_H_ILLEGAL;
8364
8365 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8366 DRM_MODE_FLAG_NCSYNC |
8367 DRM_MODE_FLAG_PCSYNC))
8368 return MODE_HSYNC;
8369
8370 if (mode->flags & (DRM_MODE_FLAG_BCAST |
8371 DRM_MODE_FLAG_PIXMUX |
8372 DRM_MODE_FLAG_CLKDIV2))
8373 return MODE_BAD;
8374
8375 /*
8376 * Reject clearly excessive dotclocks early to
8377 * avoid having to worry about huge integers later.
8378 */
8379 if (mode->clock > max_dotclock(dev_priv))
8380 return MODE_CLOCK_HIGH;
8381
8382 /* Transcoder timing limits */
8383 if (DISPLAY_VER(dev_priv) >= 11) {
8384 hdisplay_max = 16384;
8385 vdisplay_max = 8192;
8386 htotal_max = 16384;
8387 vtotal_max = 8192;
8388 } else if (DISPLAY_VER(dev_priv) >= 9 ||
8389 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8390 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8391 vdisplay_max = 4096;
8392 htotal_max = 8192;
8393 vtotal_max = 8192;
8394 } else if (DISPLAY_VER(dev_priv) >= 3) {
8395 hdisplay_max = 4096;
8396 vdisplay_max = 4096;
8397 htotal_max = 8192;
8398 vtotal_max = 8192;
8399 } else {
8400 hdisplay_max = 2048;
8401 vdisplay_max = 2048;
8402 htotal_max = 4096;
8403 vtotal_max = 4096;
8404 }
8405
8406 if (mode->hdisplay > hdisplay_max ||
8407 mode->hsync_start > htotal_max ||
8408 mode->hsync_end > htotal_max ||
8409 mode->htotal > htotal_max)
8410 return MODE_H_ILLEGAL;
8411
8412 if (mode->vdisplay > vdisplay_max ||
8413 mode->vsync_start > vtotal_max ||
8414 mode->vsync_end > vtotal_max ||
8415 mode->vtotal > vtotal_max)
8416 return MODE_V_ILLEGAL;
8417
8418 return MODE_OK;
8419}
8420
8421enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
8422 const struct drm_display_mode *mode)
8423{
8424 /*
8425 * Additional transcoder timing limits,
8426 * excluding BXT/GLK DSI transcoders.
8427 */
8428 if (DISPLAY_VER(dev_priv) >= 5) {
8429 if (mode->hdisplay < 64 ||
8430 mode->htotal - mode->hdisplay < 32)
8431 return MODE_H_ILLEGAL;
8432
8433 if (mode->vtotal - mode->vdisplay < 5)
8434 return MODE_V_ILLEGAL;
8435 } else {
8436 if (mode->htotal - mode->hdisplay < 32)
8437 return MODE_H_ILLEGAL;
8438
8439 if (mode->vtotal - mode->vdisplay < 3)
8440 return MODE_V_ILLEGAL;
8441 }
8442
8443 /*
8444 * Cantiga+ cannot handle modes with a hsync front porch of 0.
8445 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8446 */
8447 if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
8448 mode->hsync_start == mode->hdisplay)
8449 return MODE_H_ILLEGAL;
8450
8451 return MODE_OK;
8452}
8453
8454enum drm_mode_status
8455intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8456 const struct drm_display_mode *mode,
8457 int num_joined_pipes)
8458{
8459 int plane_width_max, plane_height_max;
8460
8461 /*
8462 * intel_mode_valid() should be
8463 * sufficient on older platforms.
8464 */
8465 if (DISPLAY_VER(dev_priv) < 9)
8466 return MODE_OK;
8467
8468 /*
8469 * Most people will probably want a fullscreen
8470 * plane so let's not advertize modes that are
8471 * too big for that.
8472 */
8473 if (DISPLAY_VER(dev_priv) >= 30) {
8474 plane_width_max = 6144 * num_joined_pipes;
8475 plane_height_max = 4800;
8476 } else if (DISPLAY_VER(dev_priv) >= 11) {
8477 plane_width_max = 5120 * num_joined_pipes;
8478 plane_height_max = 4320;
8479 } else {
8480 plane_width_max = 5120;
8481 plane_height_max = 4096;
8482 }
8483
8484 if (mode->hdisplay > plane_width_max)
8485 return MODE_H_ILLEGAL;
8486
8487 if (mode->vdisplay > plane_height_max)
8488 return MODE_V_ILLEGAL;
8489
8490 return MODE_OK;
8491}
8492
8493static const struct intel_display_funcs skl_display_funcs = {
8494 .get_pipe_config = hsw_get_pipe_config,
8495 .crtc_enable = hsw_crtc_enable,
8496 .crtc_disable = hsw_crtc_disable,
8497 .commit_modeset_enables = skl_commit_modeset_enables,
8498 .get_initial_plane_config = skl_get_initial_plane_config,
8499 .fixup_initial_plane_config = skl_fixup_initial_plane_config,
8500};
8501
8502static const struct intel_display_funcs ddi_display_funcs = {
8503 .get_pipe_config = hsw_get_pipe_config,
8504 .crtc_enable = hsw_crtc_enable,
8505 .crtc_disable = hsw_crtc_disable,
8506 .commit_modeset_enables = intel_commit_modeset_enables,
8507 .get_initial_plane_config = i9xx_get_initial_plane_config,
8508 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8509};
8510
8511static const struct intel_display_funcs pch_split_display_funcs = {
8512 .get_pipe_config = ilk_get_pipe_config,
8513 .crtc_enable = ilk_crtc_enable,
8514 .crtc_disable = ilk_crtc_disable,
8515 .commit_modeset_enables = intel_commit_modeset_enables,
8516 .get_initial_plane_config = i9xx_get_initial_plane_config,
8517 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8518};
8519
8520static const struct intel_display_funcs vlv_display_funcs = {
8521 .get_pipe_config = i9xx_get_pipe_config,
8522 .crtc_enable = valleyview_crtc_enable,
8523 .crtc_disable = i9xx_crtc_disable,
8524 .commit_modeset_enables = intel_commit_modeset_enables,
8525 .get_initial_plane_config = i9xx_get_initial_plane_config,
8526 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8527};
8528
8529static const struct intel_display_funcs i9xx_display_funcs = {
8530 .get_pipe_config = i9xx_get_pipe_config,
8531 .crtc_enable = i9xx_crtc_enable,
8532 .crtc_disable = i9xx_crtc_disable,
8533 .commit_modeset_enables = intel_commit_modeset_enables,
8534 .get_initial_plane_config = i9xx_get_initial_plane_config,
8535 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8536};
8537
8538/**
8539 * intel_init_display_hooks - initialize the display modesetting hooks
8540 * @dev_priv: device private
8541 */
8542void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8543{
8544 if (DISPLAY_VER(dev_priv) >= 9) {
8545 dev_priv->display.funcs.display = &skl_display_funcs;
8546 } else if (HAS_DDI(dev_priv)) {
8547 dev_priv->display.funcs.display = &ddi_display_funcs;
8548 } else if (HAS_PCH_SPLIT(dev_priv)) {
8549 dev_priv->display.funcs.display = &pch_split_display_funcs;
8550 } else if (IS_CHERRYVIEW(dev_priv) ||
8551 IS_VALLEYVIEW(dev_priv)) {
8552 dev_priv->display.funcs.display = &vlv_display_funcs;
8553 } else {
8554 dev_priv->display.funcs.display = &i9xx_display_funcs;
8555 }
8556}
8557
8558int intel_initial_commit(struct drm_device *dev)
8559{
8560 struct drm_atomic_state *state = NULL;
8561 struct drm_modeset_acquire_ctx ctx;
8562 struct intel_crtc *crtc;
8563 int ret = 0;
8564
8565 state = drm_atomic_state_alloc(dev);
8566 if (!state)
8567 return -ENOMEM;
8568
8569 drm_modeset_acquire_init(&ctx, 0);
8570
8571 state->acquire_ctx = &ctx;
8572 to_intel_atomic_state(state)->internal = true;
8573
8574retry:
8575 for_each_intel_crtc(dev, crtc) {
8576 struct intel_crtc_state *crtc_state =
8577 intel_atomic_get_crtc_state(state, crtc);
8578
8579 if (IS_ERR(crtc_state)) {
8580 ret = PTR_ERR(crtc_state);
8581 goto out;
8582 }
8583
8584 if (crtc_state->hw.active) {
8585 struct intel_encoder *encoder;
8586
8587 ret = drm_atomic_add_affected_planes(state, &crtc->base);
8588 if (ret)
8589 goto out;
8590
8591 /*
8592 * FIXME hack to force a LUT update to avoid the
8593 * plane update forcing the pipe gamma on without
8594 * having a proper LUT loaded. Remove once we
8595 * have readout for pipe gamma enable.
8596 */
8597 crtc_state->uapi.color_mgmt_changed = true;
8598
8599 for_each_intel_encoder_mask(dev, encoder,
8600 crtc_state->uapi.encoder_mask) {
8601 if (encoder->initial_fastset_check &&
8602 !encoder->initial_fastset_check(encoder, crtc_state)) {
8603 ret = drm_atomic_add_affected_connectors(state,
8604 &crtc->base);
8605 if (ret)
8606 goto out;
8607 }
8608 }
8609 }
8610 }
8611
8612 ret = drm_atomic_commit(state);
8613
8614out:
8615 if (ret == -EDEADLK) {
8616 drm_atomic_state_clear(state);
8617 drm_modeset_backoff(&ctx);
8618 goto retry;
8619 }
8620
8621 drm_atomic_state_put(state);
8622
8623 drm_modeset_drop_locks(&ctx);
8624 drm_modeset_acquire_fini(&ctx);
8625
8626 return ret;
8627}
8628
8629void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
8630{
8631 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8632 enum transcoder cpu_transcoder = (enum transcoder)pipe;
8633 /* 640x480@60Hz, ~25175 kHz */
8634 struct dpll clock = {
8635 .m1 = 18,
8636 .m2 = 7,
8637 .p1 = 13,
8638 .p2 = 4,
8639 .n = 2,
8640 };
8641 u32 dpll, fp;
8642 int i;
8643
8644 drm_WARN_ON(display->drm,
8645 i9xx_calc_dpll_params(48000, &clock) != 25154);
8646
8647 drm_dbg_kms(display->drm,
8648 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8649 pipe_name(pipe), clock.vco, clock.dot);
8650
8651 fp = i9xx_dpll_compute_fp(&clock);
8652 dpll = DPLL_DVO_2X_MODE |
8653 DPLL_VGA_MODE_DIS |
8654 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8655 PLL_P2_DIVIDE_BY_4 |
8656 PLL_REF_INPUT_DREFCLK |
8657 DPLL_VCO_ENABLE;
8658
8659 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
8660 HACTIVE(640 - 1) | HTOTAL(800 - 1));
8661 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
8662 HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8663 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
8664 HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8665 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
8666 VACTIVE(480 - 1) | VTOTAL(525 - 1));
8667 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
8668 VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8669 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
8670 VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8671 intel_de_write(display, PIPESRC(display, pipe),
8672 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8673
8674 intel_de_write(display, FP0(pipe), fp);
8675 intel_de_write(display, FP1(pipe), fp);
8676
8677 /*
8678 * Apparently we need to have VGA mode enabled prior to changing
8679 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8680 * dividers, even though the register value does change.
8681 */
8682 intel_de_write(display, DPLL(display, pipe),
8683 dpll & ~DPLL_VGA_MODE_DIS);
8684 intel_de_write(display, DPLL(display, pipe), dpll);
8685
8686 /* Wait for the clocks to stabilize. */
8687 intel_de_posting_read(display, DPLL(display, pipe));
8688 udelay(150);
8689
8690 /* The pixel multiplier can only be updated once the
8691 * DPLL is enabled and the clocks are stable.
8692 *
8693 * So write it again.
8694 */
8695 intel_de_write(display, DPLL(display, pipe), dpll);
8696
8697 /* We do this three times for luck */
8698 for (i = 0; i < 3 ; i++) {
8699 intel_de_write(display, DPLL(display, pipe), dpll);
8700 intel_de_posting_read(display, DPLL(display, pipe));
8701 udelay(150); /* wait for warmup */
8702 }
8703
8704 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
8705 intel_de_posting_read(display, TRANSCONF(display, pipe));
8706
8707 intel_wait_for_pipe_scanline_moving(crtc);
8708}
8709
8710void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
8711{
8712 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8713
8714 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
8715 pipe_name(pipe));
8716
8717 drm_WARN_ON(display->drm,
8718 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
8719 drm_WARN_ON(display->drm,
8720 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
8721 drm_WARN_ON(display->drm,
8722 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
8723 drm_WARN_ON(display->drm,
8724 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
8725 drm_WARN_ON(display->drm,
8726 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
8727
8728 intel_de_write(display, TRANSCONF(display, pipe), 0);
8729 intel_de_posting_read(display, TRANSCONF(display, pipe));
8730
8731 intel_wait_for_pipe_scanline_stopped(crtc);
8732
8733 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
8734 intel_de_posting_read(display, DPLL(display, pipe));
8735}
8736
8737void intel_hpd_poll_fini(struct drm_i915_private *i915)
8738{
8739 struct intel_connector *connector;
8740 struct drm_connector_list_iter conn_iter;
8741
8742 /* Kill all the work that may have been queued by hpd. */
8743 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8744 for_each_intel_connector_iter(connector, &conn_iter) {
8745 if (connector->modeset_retry_work.func &&
8746 cancel_work_sync(&connector->modeset_retry_work))
8747 drm_connector_put(&connector->base);
8748 if (connector->hdcp.shim) {
8749 cancel_delayed_work_sync(&connector->hdcp.check_work);
8750 cancel_work_sync(&connector->hdcp.prop_work);
8751 }
8752 }
8753 drm_connector_list_iter_end(&conn_iter);
8754}
8755
8756bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8757{
8758 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8759}