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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <acpi/video.h>
28#include <linux/i2c.h>
29#include <linux/input.h>
30#include <linux/intel-iommu.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/dma-resv.h>
34#include <linux/slab.h>
35
36#include <drm/drm_atomic.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_atomic_uapi.h>
39#include <drm/drm_damage_helper.h>
40#include <drm/drm_dp_helper.h>
41#include <drm/drm_edid.h>
42#include <drm/drm_fourcc.h>
43#include <drm/drm_plane_helper.h>
44#include <drm/drm_probe_helper.h>
45#include <drm/drm_rect.h>
46
47#include "display/intel_audio.h"
48#include "display/intel_crt.h"
49#include "display/intel_ddi.h"
50#include "display/intel_display_debugfs.h"
51#include "display/intel_dp.h"
52#include "display/intel_dp_mst.h"
53#include "display/intel_dpll.h"
54#include "display/intel_dpll_mgr.h"
55#include "display/intel_dsi.h"
56#include "display/intel_dvo.h"
57#include "display/intel_fb.h"
58#include "display/intel_gmbus.h"
59#include "display/intel_hdmi.h"
60#include "display/intel_lvds.h"
61#include "display/intel_sdvo.h"
62#include "display/intel_tv.h"
63#include "display/intel_vdsc.h"
64#include "display/intel_vrr.h"
65
66#include "gem/i915_gem_lmem.h"
67#include "gem/i915_gem_object.h"
68
69#include "gt/intel_rps.h"
70#include "gt/gen8_ppgtt.h"
71
72#include "g4x_dp.h"
73#include "g4x_hdmi.h"
74#include "i915_drv.h"
75#include "intel_acpi.h"
76#include "intel_atomic.h"
77#include "intel_atomic_plane.h"
78#include "intel_bw.h"
79#include "intel_cdclk.h"
80#include "intel_color.h"
81#include "intel_crtc.h"
82#include "intel_de.h"
83#include "intel_display_types.h"
84#include "intel_dmc.h"
85#include "intel_dp_link_training.h"
86#include "intel_fbc.h"
87#include "intel_fdi.h"
88#include "intel_fbdev.h"
89#include "intel_fifo_underrun.h"
90#include "intel_frontbuffer.h"
91#include "intel_hdcp.h"
92#include "intel_hotplug.h"
93#include "intel_overlay.h"
94#include "intel_pipe_crc.h"
95#include "intel_pm.h"
96#include "intel_pps.h"
97#include "intel_psr.h"
98#include "intel_quirks.h"
99#include "intel_sideband.h"
100#include "intel_sprite.h"
101#include "intel_tc.h"
102#include "intel_vga.h"
103#include "i9xx_plane.h"
104#include "skl_scaler.h"
105#include "skl_universal_plane.h"
106
107static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
108 struct intel_crtc_state *pipe_config);
109static void ilk_pch_clock_get(struct intel_crtc *crtc,
110 struct intel_crtc_state *pipe_config);
111
112static int intel_framebuffer_init(struct intel_framebuffer *ifb,
113 struct drm_i915_gem_object *obj,
114 struct drm_mode_fb_cmd2 *mode_cmd);
115static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
116static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
117static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
118 const struct intel_link_m_n *m_n,
119 const struct intel_link_m_n *m2_n2);
120static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
121static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
122static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
123static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
124static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
125static void intel_modeset_setup_hw_state(struct drm_device *dev,
126 struct drm_modeset_acquire_ctx *ctx);
127
128struct i915_dpt {
129 struct i915_address_space vm;
130
131 struct drm_i915_gem_object *obj;
132 struct i915_vma *vma;
133 void __iomem *iomem;
134};
135
136#define i915_is_dpt(vm) ((vm)->is_dpt)
137
138static inline struct i915_dpt *
139i915_vm_to_dpt(struct i915_address_space *vm)
140{
141 BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
142 GEM_BUG_ON(!i915_is_dpt(vm));
143 return container_of(vm, struct i915_dpt, vm);
144}
145
146#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
147
148static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
149{
150 writeq(pte, addr);
151}
152
153static void dpt_insert_page(struct i915_address_space *vm,
154 dma_addr_t addr,
155 u64 offset,
156 enum i915_cache_level level,
157 u32 flags)
158{
159 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
160 gen8_pte_t __iomem *base = dpt->iomem;
161
162 gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
163 vm->pte_encode(addr, level, flags));
164}
165
166static void dpt_insert_entries(struct i915_address_space *vm,
167 struct i915_vma *vma,
168 enum i915_cache_level level,
169 u32 flags)
170{
171 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
172 gen8_pte_t __iomem *base = dpt->iomem;
173 const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
174 struct sgt_iter sgt_iter;
175 dma_addr_t addr;
176 int i;
177
178 /*
179 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
180 * not to allow the user to override access to a read only page.
181 */
182
183 i = vma->node.start / I915_GTT_PAGE_SIZE;
184 for_each_sgt_daddr(addr, sgt_iter, vma->pages)
185 gen8_set_pte(&base[i++], pte_encode | addr);
186}
187
188static void dpt_clear_range(struct i915_address_space *vm,
189 u64 start, u64 length)
190{
191}
192
193static void dpt_bind_vma(struct i915_address_space *vm,
194 struct i915_vm_pt_stash *stash,
195 struct i915_vma *vma,
196 enum i915_cache_level cache_level,
197 u32 flags)
198{
199 struct drm_i915_gem_object *obj = vma->obj;
200 u32 pte_flags;
201
202 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
203 pte_flags = 0;
204 if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
205 pte_flags |= PTE_READ_ONLY;
206 if (i915_gem_object_is_lmem(obj))
207 pte_flags |= PTE_LM;
208
209 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
210
211 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
212
213 /*
214 * Without aliasing PPGTT there's no difference between
215 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
216 * upgrade to both bound if we bind either to avoid double-binding.
217 */
218 atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
219}
220
221static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
222{
223 vm->clear_range(vm, vma->node.start, vma->size);
224}
225
226static void dpt_cleanup(struct i915_address_space *vm)
227{
228 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
229
230 i915_gem_object_put(dpt->obj);
231}
232
233static struct i915_address_space *
234intel_dpt_create(struct intel_framebuffer *fb)
235{
236 struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;
237 struct drm_i915_private *i915 = to_i915(obj->dev);
238 struct drm_i915_gem_object *dpt_obj;
239 struct i915_address_space *vm;
240 struct i915_dpt *dpt;
241 size_t size;
242 int ret;
243
244 if (intel_fb_needs_pot_stride_remap(fb))
245 size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);
246 else
247 size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
248
249 size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
250
251 if (HAS_LMEM(i915))
252 dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
253 else
254 dpt_obj = i915_gem_object_create_stolen(i915, size);
255 if (IS_ERR(dpt_obj))
256 return ERR_CAST(dpt_obj);
257
258 ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
259 if (ret) {
260 i915_gem_object_put(dpt_obj);
261 return ERR_PTR(ret);
262 }
263
264 dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
265 if (!dpt) {
266 i915_gem_object_put(dpt_obj);
267 return ERR_PTR(-ENOMEM);
268 }
269
270 vm = &dpt->vm;
271
272 vm->gt = &i915->gt;
273 vm->i915 = i915;
274 vm->dma = i915->drm.dev;
275 vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
276 vm->is_dpt = true;
277
278 i915_address_space_init(vm, VM_CLASS_DPT);
279
280 vm->insert_page = dpt_insert_page;
281 vm->clear_range = dpt_clear_range;
282 vm->insert_entries = dpt_insert_entries;
283 vm->cleanup = dpt_cleanup;
284
285 vm->vma_ops.bind_vma = dpt_bind_vma;
286 vm->vma_ops.unbind_vma = dpt_unbind_vma;
287 vm->vma_ops.set_pages = ggtt_set_pages;
288 vm->vma_ops.clear_pages = clear_pages;
289
290 vm->pte_encode = gen8_ggtt_pte_encode;
291
292 dpt->obj = dpt_obj;
293
294 return &dpt->vm;
295}
296
297static void intel_dpt_destroy(struct i915_address_space *vm)
298{
299 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
300
301 i915_vm_close(&dpt->vm);
302}
303
304/* returns HPLL frequency in kHz */
305int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
306{
307 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
308
309 /* Obtain SKU information */
310 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
311 CCK_FUSE_HPLL_FREQ_MASK;
312
313 return vco_freq[hpll_freq] * 1000;
314}
315
316int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
317 const char *name, u32 reg, int ref_freq)
318{
319 u32 val;
320 int divider;
321
322 val = vlv_cck_read(dev_priv, reg);
323 divider = val & CCK_FREQUENCY_VALUES;
324
325 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
326 (divider << CCK_FREQUENCY_STATUS_SHIFT),
327 "%s change in progress\n", name);
328
329 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
330}
331
332int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
333 const char *name, u32 reg)
334{
335 int hpll;
336
337 vlv_cck_get(dev_priv);
338
339 if (dev_priv->hpll_freq == 0)
340 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
341
342 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
343
344 vlv_cck_put(dev_priv);
345
346 return hpll;
347}
348
349static void intel_update_czclk(struct drm_i915_private *dev_priv)
350{
351 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
352 return;
353
354 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
355 CCK_CZ_CLOCK_CONTROL);
356
357 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
358 dev_priv->czclk_freq);
359}
360
361/* WA Display #0827: Gen9:all */
362static void
363skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
364{
365 if (enable)
366 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
367 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
368 else
369 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
370 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
371}
372
373/* Wa_2006604312:icl,ehl */
374static void
375icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
376 bool enable)
377{
378 if (enable)
379 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
380 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
381 else
382 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
383 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
384}
385
386static bool
387is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
388{
389 return crtc_state->master_transcoder != INVALID_TRANSCODER;
390}
391
392static bool
393is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
394{
395 return crtc_state->sync_mode_slaves_mask != 0;
396}
397
398bool
399is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
400{
401 return is_trans_port_sync_master(crtc_state) ||
402 is_trans_port_sync_slave(crtc_state);
403}
404
405static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
406 enum pipe pipe)
407{
408 i915_reg_t reg = PIPEDSL(pipe);
409 u32 line1, line2;
410 u32 line_mask;
411
412 if (DISPLAY_VER(dev_priv) == 2)
413 line_mask = DSL_LINEMASK_GEN2;
414 else
415 line_mask = DSL_LINEMASK_GEN3;
416
417 line1 = intel_de_read(dev_priv, reg) & line_mask;
418 msleep(5);
419 line2 = intel_de_read(dev_priv, reg) & line_mask;
420
421 return line1 != line2;
422}
423
424static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
425{
426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
427 enum pipe pipe = crtc->pipe;
428
429 /* Wait for the display line to settle/start moving */
430 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
431 drm_err(&dev_priv->drm,
432 "pipe %c scanline %s wait timed out\n",
433 pipe_name(pipe), onoff(state));
434}
435
436static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
437{
438 wait_for_pipe_scanline_moving(crtc, false);
439}
440
441static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
442{
443 wait_for_pipe_scanline_moving(crtc, true);
444}
445
446static void
447intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
448{
449 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
451
452 if (DISPLAY_VER(dev_priv) >= 4) {
453 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
454 i915_reg_t reg = PIPECONF(cpu_transcoder);
455
456 /* Wait for the Pipe State to go off */
457 if (intel_de_wait_for_clear(dev_priv, reg,
458 I965_PIPECONF_ACTIVE, 100))
459 drm_WARN(&dev_priv->drm, 1,
460 "pipe_off wait timed out\n");
461 } else {
462 intel_wait_for_pipe_scanline_stopped(crtc);
463 }
464}
465
466/* Only for pre-ILK configs */
467void assert_pll(struct drm_i915_private *dev_priv,
468 enum pipe pipe, bool state)
469{
470 u32 val;
471 bool cur_state;
472
473 val = intel_de_read(dev_priv, DPLL(pipe));
474 cur_state = !!(val & DPLL_VCO_ENABLE);
475 I915_STATE_WARN(cur_state != state,
476 "PLL state assertion failure (expected %s, current %s)\n",
477 onoff(state), onoff(cur_state));
478}
479
480/* XXX: the dsi pll is shared between MIPI DSI ports */
481void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
482{
483 u32 val;
484 bool cur_state;
485
486 vlv_cck_get(dev_priv);
487 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
488 vlv_cck_put(dev_priv);
489
490 cur_state = val & DSI_PLL_VCO_EN;
491 I915_STATE_WARN(cur_state != state,
492 "DSI PLL state assertion failure (expected %s, current %s)\n",
493 onoff(state), onoff(cur_state));
494}
495
496static void assert_fdi_tx(struct drm_i915_private *dev_priv,
497 enum pipe pipe, bool state)
498{
499 bool cur_state;
500
501 if (HAS_DDI(dev_priv)) {
502 /*
503 * DDI does not have a specific FDI_TX register.
504 *
505 * FDI is never fed from EDP transcoder
506 * so pipe->transcoder cast is fine here.
507 */
508 enum transcoder cpu_transcoder = (enum transcoder)pipe;
509 u32 val = intel_de_read(dev_priv,
510 TRANS_DDI_FUNC_CTL(cpu_transcoder));
511 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
512 } else {
513 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
514 cur_state = !!(val & FDI_TX_ENABLE);
515 }
516 I915_STATE_WARN(cur_state != state,
517 "FDI TX state assertion failure (expected %s, current %s)\n",
518 onoff(state), onoff(cur_state));
519}
520#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
521#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
522
523static void assert_fdi_rx(struct drm_i915_private *dev_priv,
524 enum pipe pipe, bool state)
525{
526 u32 val;
527 bool cur_state;
528
529 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
530 cur_state = !!(val & FDI_RX_ENABLE);
531 I915_STATE_WARN(cur_state != state,
532 "FDI RX state assertion failure (expected %s, current %s)\n",
533 onoff(state), onoff(cur_state));
534}
535#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
536#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
537
538static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
539 enum pipe pipe)
540{
541 u32 val;
542
543 /* ILK FDI PLL is always enabled */
544 if (IS_IRONLAKE(dev_priv))
545 return;
546
547 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
548 if (HAS_DDI(dev_priv))
549 return;
550
551 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
552 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
553}
554
555void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
556 enum pipe pipe, bool state)
557{
558 u32 val;
559 bool cur_state;
560
561 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
562 cur_state = !!(val & FDI_RX_PLL_ENABLE);
563 I915_STATE_WARN(cur_state != state,
564 "FDI RX PLL assertion failure (expected %s, current %s)\n",
565 onoff(state), onoff(cur_state));
566}
567
568void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
569{
570 i915_reg_t pp_reg;
571 u32 val;
572 enum pipe panel_pipe = INVALID_PIPE;
573 bool locked = true;
574
575 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
576 return;
577
578 if (HAS_PCH_SPLIT(dev_priv)) {
579 u32 port_sel;
580
581 pp_reg = PP_CONTROL(0);
582 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
583
584 switch (port_sel) {
585 case PANEL_PORT_SELECT_LVDS:
586 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
587 break;
588 case PANEL_PORT_SELECT_DPA:
589 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
590 break;
591 case PANEL_PORT_SELECT_DPC:
592 g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
593 break;
594 case PANEL_PORT_SELECT_DPD:
595 g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
596 break;
597 default:
598 MISSING_CASE(port_sel);
599 break;
600 }
601 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
602 /* presumably write lock depends on pipe, not port select */
603 pp_reg = PP_CONTROL(pipe);
604 panel_pipe = pipe;
605 } else {
606 u32 port_sel;
607
608 pp_reg = PP_CONTROL(0);
609 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
610
611 drm_WARN_ON(&dev_priv->drm,
612 port_sel != PANEL_PORT_SELECT_LVDS);
613 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
614 }
615
616 val = intel_de_read(dev_priv, pp_reg);
617 if (!(val & PANEL_POWER_ON) ||
618 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
619 locked = false;
620
621 I915_STATE_WARN(panel_pipe == pipe && locked,
622 "panel assertion failure, pipe %c regs locked\n",
623 pipe_name(pipe));
624}
625
626void assert_pipe(struct drm_i915_private *dev_priv,
627 enum transcoder cpu_transcoder, bool state)
628{
629 bool cur_state;
630 enum intel_display_power_domain power_domain;
631 intel_wakeref_t wakeref;
632
633 /* we keep both pipes enabled on 830 */
634 if (IS_I830(dev_priv))
635 state = true;
636
637 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
638 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
639 if (wakeref) {
640 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
641 cur_state = !!(val & PIPECONF_ENABLE);
642
643 intel_display_power_put(dev_priv, power_domain, wakeref);
644 } else {
645 cur_state = false;
646 }
647
648 I915_STATE_WARN(cur_state != state,
649 "transcoder %s assertion failure (expected %s, current %s)\n",
650 transcoder_name(cpu_transcoder),
651 onoff(state), onoff(cur_state));
652}
653
654static void assert_plane(struct intel_plane *plane, bool state)
655{
656 enum pipe pipe;
657 bool cur_state;
658
659 cur_state = plane->get_hw_state(plane, &pipe);
660
661 I915_STATE_WARN(cur_state != state,
662 "%s assertion failure (expected %s, current %s)\n",
663 plane->base.name, onoff(state), onoff(cur_state));
664}
665
666#define assert_plane_enabled(p) assert_plane(p, true)
667#define assert_plane_disabled(p) assert_plane(p, false)
668
669static void assert_planes_disabled(struct intel_crtc *crtc)
670{
671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
672 struct intel_plane *plane;
673
674 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
675 assert_plane_disabled(plane);
676}
677
678void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
679 enum pipe pipe)
680{
681 u32 val;
682 bool enabled;
683
684 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
685 enabled = !!(val & TRANS_ENABLE);
686 I915_STATE_WARN(enabled,
687 "transcoder assertion failed, should be off on pipe %c but is still active\n",
688 pipe_name(pipe));
689}
690
691static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
692 enum pipe pipe, enum port port,
693 i915_reg_t dp_reg)
694{
695 enum pipe port_pipe;
696 bool state;
697
698 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
699
700 I915_STATE_WARN(state && port_pipe == pipe,
701 "PCH DP %c enabled on transcoder %c, should be disabled\n",
702 port_name(port), pipe_name(pipe));
703
704 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
705 "IBX PCH DP %c still using transcoder B\n",
706 port_name(port));
707}
708
709static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
710 enum pipe pipe, enum port port,
711 i915_reg_t hdmi_reg)
712{
713 enum pipe port_pipe;
714 bool state;
715
716 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
717
718 I915_STATE_WARN(state && port_pipe == pipe,
719 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
720 port_name(port), pipe_name(pipe));
721
722 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
723 "IBX PCH HDMI %c still using transcoder B\n",
724 port_name(port));
725}
726
727static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
728 enum pipe pipe)
729{
730 enum pipe port_pipe;
731
732 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
733 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
734 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
735
736 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
737 port_pipe == pipe,
738 "PCH VGA enabled on transcoder %c, should be disabled\n",
739 pipe_name(pipe));
740
741 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
742 port_pipe == pipe,
743 "PCH LVDS enabled on transcoder %c, should be disabled\n",
744 pipe_name(pipe));
745
746 /* PCH SDVOB multiplex with HDMIB */
747 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
748 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
749 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
750}
751
752void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
753 struct intel_digital_port *dig_port,
754 unsigned int expected_mask)
755{
756 u32 port_mask;
757 i915_reg_t dpll_reg;
758
759 switch (dig_port->base.port) {
760 case PORT_B:
761 port_mask = DPLL_PORTB_READY_MASK;
762 dpll_reg = DPLL(0);
763 break;
764 case PORT_C:
765 port_mask = DPLL_PORTC_READY_MASK;
766 dpll_reg = DPLL(0);
767 expected_mask <<= 4;
768 break;
769 case PORT_D:
770 port_mask = DPLL_PORTD_READY_MASK;
771 dpll_reg = DPIO_PHY_STATUS;
772 break;
773 default:
774 BUG();
775 }
776
777 if (intel_de_wait_for_register(dev_priv, dpll_reg,
778 port_mask, expected_mask, 1000))
779 drm_WARN(&dev_priv->drm, 1,
780 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
781 dig_port->base.base.base.id, dig_port->base.base.name,
782 intel_de_read(dev_priv, dpll_reg) & port_mask,
783 expected_mask);
784}
785
786static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
787{
788 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
790 enum pipe pipe = crtc->pipe;
791 i915_reg_t reg;
792 u32 val, pipeconf_val;
793
794 /* Make sure PCH DPLL is enabled */
795 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
796
797 /* FDI must be feeding us bits for PCH ports */
798 assert_fdi_tx_enabled(dev_priv, pipe);
799 assert_fdi_rx_enabled(dev_priv, pipe);
800
801 if (HAS_PCH_CPT(dev_priv)) {
802 reg = TRANS_CHICKEN2(pipe);
803 val = intel_de_read(dev_priv, reg);
804 /*
805 * Workaround: Set the timing override bit
806 * before enabling the pch transcoder.
807 */
808 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
809 /* Configure frame start delay to match the CPU */
810 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
811 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
812 intel_de_write(dev_priv, reg, val);
813 }
814
815 reg = PCH_TRANSCONF(pipe);
816 val = intel_de_read(dev_priv, reg);
817 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
818
819 if (HAS_PCH_IBX(dev_priv)) {
820 /* Configure frame start delay to match the CPU */
821 val &= ~TRANS_FRAME_START_DELAY_MASK;
822 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
823
824 /*
825 * Make the BPC in transcoder be consistent with
826 * that in pipeconf reg. For HDMI we must use 8bpc
827 * here for both 8bpc and 12bpc.
828 */
829 val &= ~PIPECONF_BPC_MASK;
830 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
831 val |= PIPECONF_8BPC;
832 else
833 val |= pipeconf_val & PIPECONF_BPC_MASK;
834 }
835
836 val &= ~TRANS_INTERLACE_MASK;
837 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
838 if (HAS_PCH_IBX(dev_priv) &&
839 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
840 val |= TRANS_LEGACY_INTERLACED_ILK;
841 else
842 val |= TRANS_INTERLACED;
843 } else {
844 val |= TRANS_PROGRESSIVE;
845 }
846
847 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
848 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
849 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
850 pipe_name(pipe));
851}
852
853static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
854 enum transcoder cpu_transcoder)
855{
856 u32 val, pipeconf_val;
857
858 /* FDI must be feeding us bits for PCH ports */
859 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
860 assert_fdi_rx_enabled(dev_priv, PIPE_A);
861
862 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
863 /* Workaround: set timing override bit. */
864 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
865 /* Configure frame start delay to match the CPU */
866 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
867 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
868 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
869
870 val = TRANS_ENABLE;
871 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
872
873 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
874 PIPECONF_INTERLACED_ILK)
875 val |= TRANS_INTERLACED;
876 else
877 val |= TRANS_PROGRESSIVE;
878
879 intel_de_write(dev_priv, LPT_TRANSCONF, val);
880 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
881 TRANS_STATE_ENABLE, 100))
882 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
883}
884
885static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
886 enum pipe pipe)
887{
888 i915_reg_t reg;
889 u32 val;
890
891 /* FDI relies on the transcoder */
892 assert_fdi_tx_disabled(dev_priv, pipe);
893 assert_fdi_rx_disabled(dev_priv, pipe);
894
895 /* Ports must be off as well */
896 assert_pch_ports_disabled(dev_priv, pipe);
897
898 reg = PCH_TRANSCONF(pipe);
899 val = intel_de_read(dev_priv, reg);
900 val &= ~TRANS_ENABLE;
901 intel_de_write(dev_priv, reg, val);
902 /* wait for PCH transcoder off, transcoder state */
903 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
904 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
905 pipe_name(pipe));
906
907 if (HAS_PCH_CPT(dev_priv)) {
908 /* Workaround: Clear the timing override chicken bit again. */
909 reg = TRANS_CHICKEN2(pipe);
910 val = intel_de_read(dev_priv, reg);
911 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
912 intel_de_write(dev_priv, reg, val);
913 }
914}
915
916void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
917{
918 u32 val;
919
920 val = intel_de_read(dev_priv, LPT_TRANSCONF);
921 val &= ~TRANS_ENABLE;
922 intel_de_write(dev_priv, LPT_TRANSCONF, val);
923 /* wait for PCH transcoder off, transcoder state */
924 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
925 TRANS_STATE_ENABLE, 50))
926 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
927
928 /* Workaround: clear timing override bit. */
929 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
930 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
931 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
932}
933
934enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
935{
936 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
937
938 if (HAS_PCH_LPT(dev_priv))
939 return PIPE_A;
940 else
941 return crtc->pipe;
942}
943
944void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
945{
946 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
948 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
949 enum pipe pipe = crtc->pipe;
950 i915_reg_t reg;
951 u32 val;
952
953 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
954
955 assert_planes_disabled(crtc);
956
957 /*
958 * A pipe without a PLL won't actually be able to drive bits from
959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
960 * need the check.
961 */
962 if (HAS_GMCH(dev_priv)) {
963 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
964 assert_dsi_pll_enabled(dev_priv);
965 else
966 assert_pll_enabled(dev_priv, pipe);
967 } else {
968 if (new_crtc_state->has_pch_encoder) {
969 /* if driving the PCH, we need FDI enabled */
970 assert_fdi_rx_pll_enabled(dev_priv,
971 intel_crtc_pch_transcoder(crtc));
972 assert_fdi_tx_pll_enabled(dev_priv,
973 (enum pipe) cpu_transcoder);
974 }
975 /* FIXME: assert CPU port conditions for SNB+ */
976 }
977
978 /* Wa_22012358565:adlp */
979 if (DISPLAY_VER(dev_priv) == 13)
980 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
981 0, PIPE_ARB_USE_PROG_SLOTS);
982
983 reg = PIPECONF(cpu_transcoder);
984 val = intel_de_read(dev_priv, reg);
985 if (val & PIPECONF_ENABLE) {
986 /* we keep both pipes enabled on 830 */
987 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
988 return;
989 }
990
991 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
992 intel_de_posting_read(dev_priv, reg);
993
994 /*
995 * Until the pipe starts PIPEDSL reads will return a stale value,
996 * which causes an apparent vblank timestamp jump when PIPEDSL
997 * resets to its proper value. That also messes up the frame count
998 * when it's derived from the timestamps. So let's wait for the
999 * pipe to start properly before we call drm_crtc_vblank_on()
1000 */
1001 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1002 intel_wait_for_pipe_scanline_moving(crtc);
1003}
1004
1005void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1006{
1007 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1009 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1010 enum pipe pipe = crtc->pipe;
1011 i915_reg_t reg;
1012 u32 val;
1013
1014 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1015
1016 /*
1017 * Make sure planes won't keep trying to pump pixels to us,
1018 * or we might hang the display.
1019 */
1020 assert_planes_disabled(crtc);
1021
1022 reg = PIPECONF(cpu_transcoder);
1023 val = intel_de_read(dev_priv, reg);
1024 if ((val & PIPECONF_ENABLE) == 0)
1025 return;
1026
1027 /*
1028 * Double wide has implications for planes
1029 * so best keep it disabled when not needed.
1030 */
1031 if (old_crtc_state->double_wide)
1032 val &= ~PIPECONF_DOUBLE_WIDE;
1033
1034 /* Don't disable pipe or pipe PLLs if needed */
1035 if (!IS_I830(dev_priv))
1036 val &= ~PIPECONF_ENABLE;
1037
1038 intel_de_write(dev_priv, reg, val);
1039 if ((val & PIPECONF_ENABLE) == 0)
1040 intel_wait_for_pipe_off(old_crtc_state);
1041}
1042
1043bool
1044intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
1045 u64 modifier)
1046{
1047 return info->is_yuv &&
1048 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
1049}
1050
1051unsigned int
1052intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1053{
1054 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1055 unsigned int cpp = fb->format->cpp[color_plane];
1056
1057 switch (fb->modifier) {
1058 case DRM_FORMAT_MOD_LINEAR:
1059 return intel_tile_size(dev_priv);
1060 case I915_FORMAT_MOD_X_TILED:
1061 if (DISPLAY_VER(dev_priv) == 2)
1062 return 128;
1063 else
1064 return 512;
1065 case I915_FORMAT_MOD_Y_TILED_CCS:
1066 if (is_ccs_plane(fb, color_plane))
1067 return 128;
1068 fallthrough;
1069 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1070 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1071 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1072 if (is_ccs_plane(fb, color_plane))
1073 return 64;
1074 fallthrough;
1075 case I915_FORMAT_MOD_Y_TILED:
1076 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
1077 return 128;
1078 else
1079 return 512;
1080 case I915_FORMAT_MOD_Yf_TILED_CCS:
1081 if (is_ccs_plane(fb, color_plane))
1082 return 128;
1083 fallthrough;
1084 case I915_FORMAT_MOD_Yf_TILED:
1085 switch (cpp) {
1086 case 1:
1087 return 64;
1088 case 2:
1089 case 4:
1090 return 128;
1091 case 8:
1092 case 16:
1093 return 256;
1094 default:
1095 MISSING_CASE(cpp);
1096 return cpp;
1097 }
1098 break;
1099 default:
1100 MISSING_CASE(fb->modifier);
1101 return cpp;
1102 }
1103}
1104
1105unsigned int
1106intel_fb_align_height(const struct drm_framebuffer *fb,
1107 int color_plane, unsigned int height)
1108{
1109 unsigned int tile_height = intel_tile_height(fb, color_plane);
1110
1111 return ALIGN(height, tile_height);
1112}
1113
1114unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1115{
1116 unsigned int size = 0;
1117 int i;
1118
1119 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1120 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
1121
1122 return size;
1123}
1124
1125unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
1126{
1127 unsigned int size = 0;
1128 int i;
1129
1130 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
1131 size += rem_info->plane[i].dst_stride * rem_info->plane[i].height;
1132
1133 return size;
1134}
1135
1136static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1137{
1138 if (DISPLAY_VER(dev_priv) >= 9)
1139 return 256 * 1024;
1140 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1141 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1142 return 128 * 1024;
1143 else if (DISPLAY_VER(dev_priv) >= 4)
1144 return 4 * 1024;
1145 else
1146 return 0;
1147}
1148
1149static bool has_async_flips(struct drm_i915_private *i915)
1150{
1151 return DISPLAY_VER(i915) >= 5;
1152}
1153
1154unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
1155 int color_plane)
1156{
1157 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1158
1159 if (intel_fb_uses_dpt(fb))
1160 return 512 * 4096;
1161
1162 /* AUX_DIST needs only 4K alignment */
1163 if (is_ccs_plane(fb, color_plane))
1164 return 4096;
1165
1166 if (is_semiplanar_uv_plane(fb, color_plane)) {
1167 /*
1168 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
1169 * alignment for linear UV planes on all platforms.
1170 */
1171 if (DISPLAY_VER(dev_priv) >= 12) {
1172 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1173 return intel_linear_alignment(dev_priv);
1174
1175 return intel_tile_row_size(fb, color_plane);
1176 }
1177
1178 return 4096;
1179 }
1180
1181 drm_WARN_ON(&dev_priv->drm, color_plane != 0);
1182
1183 switch (fb->modifier) {
1184 case DRM_FORMAT_MOD_LINEAR:
1185 return intel_linear_alignment(dev_priv);
1186 case I915_FORMAT_MOD_X_TILED:
1187 if (has_async_flips(dev_priv))
1188 return 256 * 1024;
1189 return 0;
1190 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1191 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1192 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1193 return 16 * 1024;
1194 case I915_FORMAT_MOD_Y_TILED_CCS:
1195 case I915_FORMAT_MOD_Yf_TILED_CCS:
1196 case I915_FORMAT_MOD_Y_TILED:
1197 case I915_FORMAT_MOD_Yf_TILED:
1198 return 1 * 1024 * 1024;
1199 default:
1200 MISSING_CASE(fb->modifier);
1201 return 0;
1202 }
1203}
1204
1205static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1206{
1207 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1208 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1209
1210 return DISPLAY_VER(dev_priv) < 4 ||
1211 (plane->has_fbc &&
1212 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
1213}
1214
1215static struct i915_vma *
1216intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
1217 const struct i915_ggtt_view *view,
1218 bool uses_fence,
1219 unsigned long *out_flags,
1220 struct i915_address_space *vm)
1221{
1222 struct drm_device *dev = fb->dev;
1223 struct drm_i915_private *dev_priv = to_i915(dev);
1224 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1225 struct i915_vma *vma;
1226 u32 alignment;
1227 int ret;
1228
1229 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
1230 return ERR_PTR(-EINVAL);
1231
1232 alignment = 4096 * 512;
1233
1234 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1235
1236 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1237 if (ret) {
1238 vma = ERR_PTR(ret);
1239 goto err;
1240 }
1241
1242 vma = i915_vma_instance(obj, vm, view);
1243 if (IS_ERR(vma))
1244 goto err;
1245
1246 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
1247 ret = i915_vma_unbind(vma);
1248 if (ret) {
1249 vma = ERR_PTR(ret);
1250 goto err;
1251 }
1252 }
1253
1254 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
1255 if (ret) {
1256 vma = ERR_PTR(ret);
1257 goto err;
1258 }
1259
1260 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
1261
1262 i915_gem_object_flush_if_display(obj);
1263
1264 i915_vma_get(vma);
1265err:
1266 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1267
1268 return vma;
1269}
1270
1271struct i915_vma *
1272intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1273 bool phys_cursor,
1274 const struct i915_ggtt_view *view,
1275 bool uses_fence,
1276 unsigned long *out_flags)
1277{
1278 struct drm_device *dev = fb->dev;
1279 struct drm_i915_private *dev_priv = to_i915(dev);
1280 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1281 intel_wakeref_t wakeref;
1282 struct i915_gem_ww_ctx ww;
1283 struct i915_vma *vma;
1284 unsigned int pinctl;
1285 u32 alignment;
1286 int ret;
1287
1288 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
1289 return ERR_PTR(-EINVAL);
1290
1291 if (phys_cursor)
1292 alignment = intel_cursor_alignment(dev_priv);
1293 else
1294 alignment = intel_surf_alignment(fb, 0);
1295 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
1296 return ERR_PTR(-EINVAL);
1297
1298 /* Note that the w/a also requires 64 PTE of padding following the
1299 * bo. We currently fill all unused PTE with the shadow page and so
1300 * we should always have valid PTE following the scanout preventing
1301 * the VT-d warning.
1302 */
1303 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
1304 alignment = 256 * 1024;
1305
1306 /*
1307 * Global gtt pte registers are special registers which actually forward
1308 * writes to a chunk of system memory. Which means that there is no risk
1309 * that the register values disappear as soon as we call
1310 * intel_runtime_pm_put(), so it is correct to wrap only the
1311 * pin/unpin/fence and not more.
1312 */
1313 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1314
1315 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1316
1317 /*
1318 * Valleyview is definitely limited to scanning out the first
1319 * 512MiB. Lets presume this behaviour was inherited from the
1320 * g4x display engine and that all earlier gen are similarly
1321 * limited. Testing suggests that it is a little more
1322 * complicated than this. For example, Cherryview appears quite
1323 * happy to scanout from anywhere within its global aperture.
1324 */
1325 pinctl = 0;
1326 if (HAS_GMCH(dev_priv))
1327 pinctl |= PIN_MAPPABLE;
1328
1329 i915_gem_ww_ctx_init(&ww, true);
1330retry:
1331 ret = i915_gem_object_lock(obj, &ww);
1332 if (!ret && phys_cursor)
1333 ret = i915_gem_object_attach_phys(obj, alignment);
1334 if (!ret)
1335 ret = i915_gem_object_pin_pages(obj);
1336 if (ret)
1337 goto err;
1338
1339 if (!ret) {
1340 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
1341 view, pinctl);
1342 if (IS_ERR(vma)) {
1343 ret = PTR_ERR(vma);
1344 goto err_unpin;
1345 }
1346 }
1347
1348 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
1349 /*
1350 * Install a fence for tiled scan-out. Pre-i965 always needs a
1351 * fence, whereas 965+ only requires a fence if using
1352 * framebuffer compression. For simplicity, we always, when
1353 * possible, install a fence as the cost is not that onerous.
1354 *
1355 * If we fail to fence the tiled scanout, then either the
1356 * modeset will reject the change (which is highly unlikely as
1357 * the affected systems, all but one, do not have unmappable
1358 * space) or we will not be able to enable full powersaving
1359 * techniques (also likely not to apply due to various limits
1360 * FBC and the like impose on the size of the buffer, which
1361 * presumably we violated anyway with this unmappable buffer).
1362 * Anyway, it is presumably better to stumble onwards with
1363 * something and try to run the system in a "less than optimal"
1364 * mode that matches the user configuration.
1365 */
1366 ret = i915_vma_pin_fence(vma);
1367 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
1368 i915_vma_unpin(vma);
1369 goto err_unpin;
1370 }
1371 ret = 0;
1372
1373 if (vma->fence)
1374 *out_flags |= PLANE_HAS_FENCE;
1375 }
1376
1377 i915_vma_get(vma);
1378
1379err_unpin:
1380 i915_gem_object_unpin_pages(obj);
1381err:
1382 if (ret == -EDEADLK) {
1383 ret = i915_gem_ww_ctx_backoff(&ww);
1384 if (!ret)
1385 goto retry;
1386 }
1387 i915_gem_ww_ctx_fini(&ww);
1388 if (ret)
1389 vma = ERR_PTR(ret);
1390
1391 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1392 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1393 return vma;
1394}
1395
1396void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
1397{
1398 if (flags & PLANE_HAS_FENCE)
1399 i915_vma_unpin_fence(vma);
1400 i915_vma_unpin(vma);
1401 i915_vma_put(vma);
1402}
1403
1404/*
1405 * Convert the x/y offsets into a linear offset.
1406 * Only valid with 0/180 degree rotation, which is fine since linear
1407 * offset is only used with linear buffers on pre-hsw and tiled buffers
1408 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1409 */
1410u32 intel_fb_xy_to_linear(int x, int y,
1411 const struct intel_plane_state *state,
1412 int color_plane)
1413{
1414 const struct drm_framebuffer *fb = state->hw.fb;
1415 unsigned int cpp = fb->format->cpp[color_plane];
1416 unsigned int pitch = state->view.color_plane[color_plane].stride;
1417
1418 return y * pitch + x * cpp;
1419}
1420
1421/*
1422 * Add the x/y offsets derived from fb->offsets[] to the user
1423 * specified plane src x/y offsets. The resulting x/y offsets
1424 * specify the start of scanout from the beginning of the gtt mapping.
1425 */
1426void intel_add_fb_offsets(int *x, int *y,
1427 const struct intel_plane_state *state,
1428 int color_plane)
1429
1430{
1431 *x += state->view.color_plane[color_plane].x;
1432 *y += state->view.color_plane[color_plane].y;
1433}
1434
1435static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
1436{
1437 switch (fb_modifier) {
1438 case I915_FORMAT_MOD_X_TILED:
1439 return I915_TILING_X;
1440 case I915_FORMAT_MOD_Y_TILED:
1441 case I915_FORMAT_MOD_Y_TILED_CCS:
1442 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1443 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1444 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1445 return I915_TILING_Y;
1446 default:
1447 return I915_TILING_NONE;
1448 }
1449}
1450
1451/*
1452 * From the Sky Lake PRM:
1453 * "The Color Control Surface (CCS) contains the compression status of
1454 * the cache-line pairs. The compression state of the cache-line pair
1455 * is specified by 2 bits in the CCS. Each CCS cache-line represents
1456 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1457 * cache-line-pairs. CCS is always Y tiled."
1458 *
1459 * Since cache line pairs refers to horizontally adjacent cache lines,
1460 * each cache line in the CCS corresponds to an area of 32x16 cache
1461 * lines on the main surface. Since each pixel is 4 bytes, this gives
1462 * us a ratio of one byte in the CCS for each 8x16 pixels in the
1463 * main surface.
1464 */
1465static const struct drm_format_info skl_ccs_formats[] = {
1466 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1467 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1468 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1469 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1470 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1471 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1472 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1473 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1474};
1475
1476/*
1477 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1478 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1479 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1480 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1481 * the main surface.
1482 */
1483static const struct drm_format_info gen12_ccs_formats[] = {
1484 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1485 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1486 .hsub = 1, .vsub = 1, },
1487 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1488 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1489 .hsub = 1, .vsub = 1, },
1490 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1491 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1492 .hsub = 1, .vsub = 1, .has_alpha = true },
1493 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1494 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1495 .hsub = 1, .vsub = 1, .has_alpha = true },
1496 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
1497 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1498 .hsub = 2, .vsub = 1, .is_yuv = true },
1499 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
1500 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1501 .hsub = 2, .vsub = 1, .is_yuv = true },
1502 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
1503 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1504 .hsub = 2, .vsub = 1, .is_yuv = true },
1505 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
1506 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1507 .hsub = 2, .vsub = 1, .is_yuv = true },
1508 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
1509 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1510 .hsub = 1, .vsub = 1, .is_yuv = true },
1511 { .format = DRM_FORMAT_NV12, .num_planes = 4,
1512 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
1513 .hsub = 2, .vsub = 2, .is_yuv = true },
1514 { .format = DRM_FORMAT_P010, .num_planes = 4,
1515 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1516 .hsub = 2, .vsub = 2, .is_yuv = true },
1517 { .format = DRM_FORMAT_P012, .num_planes = 4,
1518 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1519 .hsub = 2, .vsub = 2, .is_yuv = true },
1520 { .format = DRM_FORMAT_P016, .num_planes = 4,
1521 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1522 .hsub = 2, .vsub = 2, .is_yuv = true },
1523};
1524
1525/*
1526 * Same as gen12_ccs_formats[] above, but with additional surface used
1527 * to pass Clear Color information in plane 2 with 64 bits of data.
1528 */
1529static const struct drm_format_info gen12_ccs_cc_formats[] = {
1530 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
1531 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1532 .hsub = 1, .vsub = 1, },
1533 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
1534 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1535 .hsub = 1, .vsub = 1, },
1536 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
1537 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1538 .hsub = 1, .vsub = 1, .has_alpha = true },
1539 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
1540 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1541 .hsub = 1, .vsub = 1, .has_alpha = true },
1542};
1543
1544static const struct drm_format_info *
1545lookup_format_info(const struct drm_format_info formats[],
1546 int num_formats, u32 format)
1547{
1548 int i;
1549
1550 for (i = 0; i < num_formats; i++) {
1551 if (formats[i].format == format)
1552 return &formats[i];
1553 }
1554
1555 return NULL;
1556}
1557
1558static const struct drm_format_info *
1559intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
1560{
1561 switch (cmd->modifier[0]) {
1562 case I915_FORMAT_MOD_Y_TILED_CCS:
1563 case I915_FORMAT_MOD_Yf_TILED_CCS:
1564 return lookup_format_info(skl_ccs_formats,
1565 ARRAY_SIZE(skl_ccs_formats),
1566 cmd->pixel_format);
1567 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1568 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1569 return lookup_format_info(gen12_ccs_formats,
1570 ARRAY_SIZE(gen12_ccs_formats),
1571 cmd->pixel_format);
1572 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1573 return lookup_format_info(gen12_ccs_cc_formats,
1574 ARRAY_SIZE(gen12_ccs_cc_formats),
1575 cmd->pixel_format);
1576 default:
1577 return NULL;
1578 }
1579}
1580
1581static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
1582{
1583 return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
1584 512) * 64;
1585}
1586
1587u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
1588 u32 pixel_format, u64 modifier)
1589{
1590 struct intel_crtc *crtc;
1591 struct intel_plane *plane;
1592
1593 if (!HAS_DISPLAY(dev_priv))
1594 return 0;
1595
1596 /*
1597 * We assume the primary plane for pipe A has
1598 * the highest stride limits of them all,
1599 * if in case pipe A is disabled, use the first pipe from pipe_mask.
1600 */
1601 crtc = intel_get_first_crtc(dev_priv);
1602 if (!crtc)
1603 return 0;
1604
1605 plane = to_intel_plane(crtc->base.primary);
1606
1607 return plane->max_stride(plane, pixel_format, modifier,
1608 DRM_MODE_ROTATE_0);
1609}
1610
1611static
1612u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1613 u32 pixel_format, u64 modifier)
1614{
1615 /*
1616 * Arbitrary limit for gen4+ chosen to match the
1617 * render engine max stride.
1618 *
1619 * The new CCS hash mode makes remapping impossible
1620 */
1621 if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
1622 intel_modifier_uses_dpt(dev_priv, modifier))
1623 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1624 else if (DISPLAY_VER(dev_priv) >= 7)
1625 return 256 * 1024;
1626 else
1627 return 128 * 1024;
1628}
1629
1630static u32
1631intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1632{
1633 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1634 u32 tile_width;
1635
1636 if (is_surface_linear(fb, color_plane)) {
1637 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1638 fb->format->format,
1639 fb->modifier);
1640
1641 /*
1642 * To make remapping with linear generally feasible
1643 * we need the stride to be page aligned.
1644 */
1645 if (fb->pitches[color_plane] > max_stride &&
1646 !is_ccs_modifier(fb->modifier))
1647 return intel_tile_size(dev_priv);
1648 else
1649 return 64;
1650 }
1651
1652 tile_width = intel_tile_width_bytes(fb, color_plane);
1653 if (is_ccs_modifier(fb->modifier)) {
1654 /*
1655 * Display WA #0531: skl,bxt,kbl,glk
1656 *
1657 * Render decompression and plane width > 3840
1658 * combined with horizontal panning requires the
1659 * plane stride to be a multiple of 4. We'll just
1660 * require the entire fb to accommodate that to avoid
1661 * potential runtime errors at plane configuration time.
1662 */
1663 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1664 color_plane == 0 && fb->width > 3840)
1665 tile_width *= 4;
1666 /*
1667 * The main surface pitch must be padded to a multiple of four
1668 * tile widths.
1669 */
1670 else if (DISPLAY_VER(dev_priv) >= 12)
1671 tile_width *= 4;
1672 }
1673 return tile_width;
1674}
1675
1676static struct i915_vma *
1677initial_plane_vma(struct drm_i915_private *i915,
1678 struct intel_initial_plane_config *plane_config)
1679{
1680 struct drm_i915_gem_object *obj;
1681 struct i915_vma *vma;
1682 u32 base, size;
1683
1684 if (plane_config->size == 0)
1685 return NULL;
1686
1687 base = round_down(plane_config->base,
1688 I915_GTT_MIN_ALIGNMENT);
1689 size = round_up(plane_config->base + plane_config->size,
1690 I915_GTT_MIN_ALIGNMENT);
1691 size -= base;
1692
1693 /*
1694 * If the FB is too big, just don't use it since fbdev is not very
1695 * important and we should probably use that space with FBC or other
1696 * features.
1697 */
1698 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
1699 size * 2 > i915->stolen_usable_size)
1700 return NULL;
1701
1702 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
1703 if (IS_ERR(obj))
1704 return NULL;
1705
1706 /*
1707 * Mark it WT ahead of time to avoid changing the
1708 * cache_level during fbdev initialization. The
1709 * unbind there would get stuck waiting for rcu.
1710 */
1711 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
1712 I915_CACHE_WT : I915_CACHE_NONE);
1713
1714 switch (plane_config->tiling) {
1715 case I915_TILING_NONE:
1716 break;
1717 case I915_TILING_X:
1718 case I915_TILING_Y:
1719 obj->tiling_and_stride =
1720 plane_config->fb->base.pitches[0] |
1721 plane_config->tiling;
1722 break;
1723 default:
1724 MISSING_CASE(plane_config->tiling);
1725 goto err_obj;
1726 }
1727
1728 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1729 if (IS_ERR(vma))
1730 goto err_obj;
1731
1732 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
1733 goto err_obj;
1734
1735 if (i915_gem_object_is_tiled(obj) &&
1736 !i915_vma_is_map_and_fenceable(vma))
1737 goto err_obj;
1738
1739 return vma;
1740
1741err_obj:
1742 i915_gem_object_put(obj);
1743 return NULL;
1744}
1745
1746static bool
1747intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
1748 struct intel_initial_plane_config *plane_config)
1749{
1750 struct drm_device *dev = crtc->base.dev;
1751 struct drm_i915_private *dev_priv = to_i915(dev);
1752 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
1753 struct drm_framebuffer *fb = &plane_config->fb->base;
1754 struct i915_vma *vma;
1755
1756 switch (fb->modifier) {
1757 case DRM_FORMAT_MOD_LINEAR:
1758 case I915_FORMAT_MOD_X_TILED:
1759 case I915_FORMAT_MOD_Y_TILED:
1760 break;
1761 default:
1762 drm_dbg(&dev_priv->drm,
1763 "Unsupported modifier for initial FB: 0x%llx\n",
1764 fb->modifier);
1765 return false;
1766 }
1767
1768 vma = initial_plane_vma(dev_priv, plane_config);
1769 if (!vma)
1770 return false;
1771
1772 mode_cmd.pixel_format = fb->format->format;
1773 mode_cmd.width = fb->width;
1774 mode_cmd.height = fb->height;
1775 mode_cmd.pitches[0] = fb->pitches[0];
1776 mode_cmd.modifier[0] = fb->modifier;
1777 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
1778
1779 if (intel_framebuffer_init(to_intel_framebuffer(fb),
1780 vma->obj, &mode_cmd)) {
1781 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
1782 goto err_vma;
1783 }
1784
1785 plane_config->vma = vma;
1786 return true;
1787
1788err_vma:
1789 i915_vma_put(vma);
1790 return false;
1791}
1792
1793static void
1794intel_set_plane_visible(struct intel_crtc_state *crtc_state,
1795 struct intel_plane_state *plane_state,
1796 bool visible)
1797{
1798 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1799
1800 plane_state->uapi.visible = visible;
1801
1802 if (visible)
1803 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
1804 else
1805 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
1806}
1807
1808static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
1809{
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct drm_plane *plane;
1812
1813 /*
1814 * Active_planes aliases if multiple "primary" or cursor planes
1815 * have been used on the same (or wrong) pipe. plane_mask uses
1816 * unique ids, hence we can use that to reconstruct active_planes.
1817 */
1818 crtc_state->enabled_planes = 0;
1819 crtc_state->active_planes = 0;
1820
1821 drm_for_each_plane_mask(plane, &dev_priv->drm,
1822 crtc_state->uapi.plane_mask) {
1823 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
1824 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
1825 }
1826}
1827
1828static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
1829 struct intel_plane *plane)
1830{
1831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832 struct intel_crtc_state *crtc_state =
1833 to_intel_crtc_state(crtc->base.state);
1834 struct intel_plane_state *plane_state =
1835 to_intel_plane_state(plane->base.state);
1836
1837 drm_dbg_kms(&dev_priv->drm,
1838 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
1839 plane->base.base.id, plane->base.name,
1840 crtc->base.base.id, crtc->base.name);
1841
1842 intel_set_plane_visible(crtc_state, plane_state, false);
1843 fixup_plane_bitmasks(crtc_state);
1844 crtc_state->data_rate[plane->id] = 0;
1845 crtc_state->min_cdclk[plane->id] = 0;
1846
1847 if (plane->id == PLANE_PRIMARY)
1848 hsw_disable_ips(crtc_state);
1849
1850 /*
1851 * Vblank time updates from the shadow to live plane control register
1852 * are blocked if the memory self-refresh mode is active at that
1853 * moment. So to make sure the plane gets truly disabled, disable
1854 * first the self-refresh mode. The self-refresh enable bit in turn
1855 * will be checked/applied by the HW only at the next frame start
1856 * event which is after the vblank start event, so we need to have a
1857 * wait-for-vblank between disabling the plane and the pipe.
1858 */
1859 if (HAS_GMCH(dev_priv) &&
1860 intel_set_memory_cxsr(dev_priv, false))
1861 intel_wait_for_vblank(dev_priv, crtc->pipe);
1862
1863 /*
1864 * Gen2 reports pipe underruns whenever all planes are disabled.
1865 * So disable underrun reporting before all the planes get disabled.
1866 */
1867 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
1868 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
1869
1870 intel_disable_plane(plane, crtc_state);
1871 intel_wait_for_vblank(dev_priv, crtc->pipe);
1872}
1873
1874static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
1875{
1876 struct drm_i915_private *i915 = vm->i915;
1877 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
1878 intel_wakeref_t wakeref;
1879 struct i915_vma *vma;
1880 void __iomem *iomem;
1881
1882 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1883 atomic_inc(&i915->gpu_error.pending_fb_pin);
1884
1885 vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
1886 HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
1887 if (IS_ERR(vma))
1888 goto err;
1889
1890 iomem = i915_vma_pin_iomap(vma);
1891 i915_vma_unpin(vma);
1892 if (IS_ERR(iomem)) {
1893 vma = iomem;
1894 goto err;
1895 }
1896
1897 dpt->vma = vma;
1898 dpt->iomem = iomem;
1899
1900 i915_vma_get(vma);
1901
1902err:
1903 atomic_dec(&i915->gpu_error.pending_fb_pin);
1904 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1905
1906 return vma;
1907}
1908
1909static void intel_dpt_unpin(struct i915_address_space *vm)
1910{
1911 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
1912
1913 i915_vma_unpin_iomap(dpt->vma);
1914 i915_vma_put(dpt->vma);
1915}
1916
1917static void
1918intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
1919 struct intel_initial_plane_config *plane_config)
1920{
1921 struct drm_device *dev = intel_crtc->base.dev;
1922 struct drm_i915_private *dev_priv = to_i915(dev);
1923 struct drm_crtc *c;
1924 struct drm_plane *primary = intel_crtc->base.primary;
1925 struct drm_plane_state *plane_state = primary->state;
1926 struct intel_plane *intel_plane = to_intel_plane(primary);
1927 struct intel_plane_state *intel_state =
1928 to_intel_plane_state(plane_state);
1929 struct intel_crtc_state *crtc_state =
1930 to_intel_crtc_state(intel_crtc->base.state);
1931 struct drm_framebuffer *fb;
1932 struct i915_vma *vma;
1933
1934 /*
1935 * TODO:
1936 * Disable planes if get_initial_plane_config() failed.
1937 * Make sure things work if the surface base is not page aligned.
1938 */
1939 if (!plane_config->fb)
1940 return;
1941
1942 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
1943 fb = &plane_config->fb->base;
1944 vma = plane_config->vma;
1945 goto valid_fb;
1946 }
1947
1948 /*
1949 * Failed to alloc the obj, check to see if we should share
1950 * an fb with another CRTC instead
1951 */
1952 for_each_crtc(dev, c) {
1953 struct intel_plane_state *state;
1954
1955 if (c == &intel_crtc->base)
1956 continue;
1957
1958 if (!to_intel_crtc_state(c->state)->uapi.active)
1959 continue;
1960
1961 state = to_intel_plane_state(c->primary->state);
1962 if (!state->ggtt_vma)
1963 continue;
1964
1965 if (intel_plane_ggtt_offset(state) == plane_config->base) {
1966 fb = state->hw.fb;
1967 vma = state->ggtt_vma;
1968 goto valid_fb;
1969 }
1970 }
1971
1972 /*
1973 * We've failed to reconstruct the BIOS FB. Current display state
1974 * indicates that the primary plane is visible, but has a NULL FB,
1975 * which will lead to problems later if we don't fix it up. The
1976 * simplest solution is to just disable the primary plane now and
1977 * pretend the BIOS never had it enabled.
1978 */
1979 intel_plane_disable_noatomic(intel_crtc, intel_plane);
1980 if (crtc_state->bigjoiner) {
1981 struct intel_crtc *slave =
1982 crtc_state->bigjoiner_linked_crtc;
1983 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
1984 }
1985
1986 return;
1987
1988valid_fb:
1989 plane_state->rotation = plane_config->rotation;
1990 intel_fb_fill_view(to_intel_framebuffer(fb), plane_state->rotation,
1991 &intel_state->view);
1992
1993 __i915_vma_pin(vma);
1994 intel_state->ggtt_vma = i915_vma_get(vma);
1995 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
1996 if (vma->fence)
1997 intel_state->flags |= PLANE_HAS_FENCE;
1998
1999 plane_state->src_x = 0;
2000 plane_state->src_y = 0;
2001 plane_state->src_w = fb->width << 16;
2002 plane_state->src_h = fb->height << 16;
2003
2004 plane_state->crtc_x = 0;
2005 plane_state->crtc_y = 0;
2006 plane_state->crtc_w = fb->width;
2007 plane_state->crtc_h = fb->height;
2008
2009 if (plane_config->tiling)
2010 dev_priv->preserve_bios_swizzle = true;
2011
2012 plane_state->fb = fb;
2013 drm_framebuffer_get(fb);
2014
2015 plane_state->crtc = &intel_crtc->base;
2016 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state,
2017 intel_crtc);
2018
2019 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
2020
2021 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2022 &to_intel_frontbuffer(fb)->bits);
2023}
2024
2025unsigned int
2026intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
2027{
2028 int x = 0, y = 0;
2029
2030 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
2031 plane_state->view.color_plane[0].offset, 0);
2032
2033 return y;
2034}
2035
2036static int
2037__intel_display_resume(struct drm_device *dev,
2038 struct drm_atomic_state *state,
2039 struct drm_modeset_acquire_ctx *ctx)
2040{
2041 struct drm_crtc_state *crtc_state;
2042 struct drm_crtc *crtc;
2043 int i, ret;
2044
2045 intel_modeset_setup_hw_state(dev, ctx);
2046 intel_vga_redisable(to_i915(dev));
2047
2048 if (!state)
2049 return 0;
2050
2051 /*
2052 * We've duplicated the state, pointers to the old state are invalid.
2053 *
2054 * Don't attempt to use the old state until we commit the duplicated state.
2055 */
2056 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
2057 /*
2058 * Force recalculation even if we restore
2059 * current state. With fast modeset this may not result
2060 * in a modeset when the state is compatible.
2061 */
2062 crtc_state->mode_changed = true;
2063 }
2064
2065 /* ignore any reset values/BIOS leftovers in the WM registers */
2066 if (!HAS_GMCH(to_i915(dev)))
2067 to_intel_atomic_state(state)->skip_intermediate_wm = true;
2068
2069 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
2070
2071 drm_WARN_ON(dev, ret == -EDEADLK);
2072 return ret;
2073}
2074
2075static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
2076{
2077 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
2078 intel_has_gpu_reset(&dev_priv->gt));
2079}
2080
2081void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
2082{
2083 struct drm_device *dev = &dev_priv->drm;
2084 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2085 struct drm_atomic_state *state;
2086 int ret;
2087
2088 if (!HAS_DISPLAY(dev_priv))
2089 return;
2090
2091 /* reset doesn't touch the display */
2092 if (!dev_priv->params.force_reset_modeset_test &&
2093 !gpu_reset_clobbers_display(dev_priv))
2094 return;
2095
2096 /* We have a modeset vs reset deadlock, defensively unbreak it. */
2097 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2098 smp_mb__after_atomic();
2099 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
2100
2101 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
2102 drm_dbg_kms(&dev_priv->drm,
2103 "Modeset potentially stuck, unbreaking through wedging\n");
2104 intel_gt_set_wedged(&dev_priv->gt);
2105 }
2106
2107 /*
2108 * Need mode_config.mutex so that we don't
2109 * trample ongoing ->detect() and whatnot.
2110 */
2111 mutex_lock(&dev->mode_config.mutex);
2112 drm_modeset_acquire_init(ctx, 0);
2113 while (1) {
2114 ret = drm_modeset_lock_all_ctx(dev, ctx);
2115 if (ret != -EDEADLK)
2116 break;
2117
2118 drm_modeset_backoff(ctx);
2119 }
2120 /*
2121 * Disabling the crtcs gracefully seems nicer. Also the
2122 * g33 docs say we should at least disable all the planes.
2123 */
2124 state = drm_atomic_helper_duplicate_state(dev, ctx);
2125 if (IS_ERR(state)) {
2126 ret = PTR_ERR(state);
2127 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
2128 ret);
2129 return;
2130 }
2131
2132 ret = drm_atomic_helper_disable_all(dev, ctx);
2133 if (ret) {
2134 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2135 ret);
2136 drm_atomic_state_put(state);
2137 return;
2138 }
2139
2140 dev_priv->modeset_restore_state = state;
2141 state->acquire_ctx = ctx;
2142}
2143
2144void intel_display_finish_reset(struct drm_i915_private *dev_priv)
2145{
2146 struct drm_device *dev = &dev_priv->drm;
2147 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2148 struct drm_atomic_state *state;
2149 int ret;
2150
2151 if (!HAS_DISPLAY(dev_priv))
2152 return;
2153
2154 /* reset doesn't touch the display */
2155 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
2156 return;
2157
2158 state = fetch_and_zero(&dev_priv->modeset_restore_state);
2159 if (!state)
2160 goto unlock;
2161
2162 /* reset doesn't touch the display */
2163 if (!gpu_reset_clobbers_display(dev_priv)) {
2164 /* for testing only restore the display */
2165 ret = __intel_display_resume(dev, state, ctx);
2166 if (ret)
2167 drm_err(&dev_priv->drm,
2168 "Restoring old state failed with %i\n", ret);
2169 } else {
2170 /*
2171 * The display has been reset as well,
2172 * so need a full re-initialization.
2173 */
2174 intel_pps_unlock_regs_wa(dev_priv);
2175 intel_modeset_init_hw(dev_priv);
2176 intel_init_clock_gating(dev_priv);
2177 intel_hpd_init(dev_priv);
2178
2179 ret = __intel_display_resume(dev, state, ctx);
2180 if (ret)
2181 drm_err(&dev_priv->drm,
2182 "Restoring old state failed with %i\n", ret);
2183
2184 intel_hpd_poll_disable(dev_priv);
2185 }
2186
2187 drm_atomic_state_put(state);
2188unlock:
2189 drm_modeset_drop_locks(ctx);
2190 drm_modeset_acquire_fini(ctx);
2191 mutex_unlock(&dev->mode_config.mutex);
2192
2193 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2194}
2195
2196static void icl_set_pipe_chicken(struct intel_crtc *crtc)
2197{
2198 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2199 enum pipe pipe = crtc->pipe;
2200 u32 tmp;
2201
2202 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
2203
2204 /*
2205 * Display WA #1153: icl
2206 * enable hardware to bypass the alpha math
2207 * and rounding for per-pixel values 00 and 0xff
2208 */
2209 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
2210 /*
2211 * Display WA # 1605353570: icl
2212 * Set the pixel rounding bit to 1 for allowing
2213 * passthrough of Frame buffer pixels unmodified
2214 * across pipe
2215 */
2216 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
2217
2218 /*
2219 * "The underrun recovery mechanism should be disabled
2220 * when the following is enabled for this pipe:
2221 * WiDi
2222 * Downscaling (this includes YUV420 fullblend)
2223 * COG
2224 * DSC
2225 * PSR2"
2226 *
2227 * FIXME: enable whenever possible...
2228 */
2229 if (IS_ALDERLAKE_P(dev_priv))
2230 tmp |= UNDERRUN_RECOVERY_DISABLE;
2231
2232 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
2233}
2234
2235bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
2236{
2237 struct drm_crtc *crtc;
2238 bool cleanup_done;
2239
2240 drm_for_each_crtc(crtc, &dev_priv->drm) {
2241 struct drm_crtc_commit *commit;
2242 spin_lock(&crtc->commit_lock);
2243 commit = list_first_entry_or_null(&crtc->commit_list,
2244 struct drm_crtc_commit, commit_entry);
2245 cleanup_done = commit ?
2246 try_wait_for_completion(&commit->cleanup_done) : true;
2247 spin_unlock(&crtc->commit_lock);
2248
2249 if (cleanup_done)
2250 continue;
2251
2252 drm_crtc_wait_one_vblank(crtc);
2253
2254 return true;
2255 }
2256
2257 return false;
2258}
2259
2260void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
2261{
2262 u32 temp;
2263
2264 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
2265
2266 mutex_lock(&dev_priv->sb_lock);
2267
2268 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2269 temp |= SBI_SSCCTL_DISABLE;
2270 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2271
2272 mutex_unlock(&dev_priv->sb_lock);
2273}
2274
2275/* Program iCLKIP clock to the desired frequency */
2276static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
2277{
2278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2279 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2280 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
2281 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2282 u32 temp;
2283
2284 lpt_disable_iclkip(dev_priv);
2285
2286 /* The iCLK virtual clock root frequency is in MHz,
2287 * but the adjusted_mode->crtc_clock in in KHz. To get the
2288 * divisors, it is necessary to divide one by another, so we
2289 * convert the virtual clock precision to KHz here for higher
2290 * precision.
2291 */
2292 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
2293 u32 iclk_virtual_root_freq = 172800 * 1000;
2294 u32 iclk_pi_range = 64;
2295 u32 desired_divisor;
2296
2297 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2298 clock << auxdiv);
2299 divsel = (desired_divisor / iclk_pi_range) - 2;
2300 phaseinc = desired_divisor % iclk_pi_range;
2301
2302 /*
2303 * Near 20MHz is a corner case which is
2304 * out of range for the 7-bit divisor
2305 */
2306 if (divsel <= 0x7f)
2307 break;
2308 }
2309
2310 /* This should not happen with any sane values */
2311 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2312 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2313 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
2314 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2315
2316 drm_dbg_kms(&dev_priv->drm,
2317 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2318 clock, auxdiv, divsel, phasedir, phaseinc);
2319
2320 mutex_lock(&dev_priv->sb_lock);
2321
2322 /* Program SSCDIVINTPHASE6 */
2323 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2324 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2325 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2326 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2327 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2328 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2329 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2330 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2331
2332 /* Program SSCAUXDIV */
2333 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2334 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2335 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2336 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2337
2338 /* Enable modulator and associated divider */
2339 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2340 temp &= ~SBI_SSCCTL_DISABLE;
2341 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2342
2343 mutex_unlock(&dev_priv->sb_lock);
2344
2345 /* Wait for initialization time */
2346 udelay(24);
2347
2348 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2349}
2350
2351int lpt_get_iclkip(struct drm_i915_private *dev_priv)
2352{
2353 u32 divsel, phaseinc, auxdiv;
2354 u32 iclk_virtual_root_freq = 172800 * 1000;
2355 u32 iclk_pi_range = 64;
2356 u32 desired_divisor;
2357 u32 temp;
2358
2359 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
2360 return 0;
2361
2362 mutex_lock(&dev_priv->sb_lock);
2363
2364 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2365 if (temp & SBI_SSCCTL_DISABLE) {
2366 mutex_unlock(&dev_priv->sb_lock);
2367 return 0;
2368 }
2369
2370 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2371 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
2372 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
2373 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
2374 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
2375
2376 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2377 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
2378 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
2379
2380 mutex_unlock(&dev_priv->sb_lock);
2381
2382 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
2383
2384 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2385 desired_divisor << auxdiv);
2386}
2387
2388static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
2389 enum pipe pch_transcoder)
2390{
2391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2393 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2394
2395 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
2396 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
2397 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
2398 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
2399 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
2400 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
2401
2402 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
2403 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2404 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
2405 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
2406 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
2407 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
2408 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2409 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
2410}
2411
2412static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
2413{
2414 u32 temp;
2415
2416 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
2417 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
2418 return;
2419
2420 drm_WARN_ON(&dev_priv->drm,
2421 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
2422 FDI_RX_ENABLE);
2423 drm_WARN_ON(&dev_priv->drm,
2424 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
2425 FDI_RX_ENABLE);
2426
2427 temp &= ~FDI_BC_BIFURCATION_SELECT;
2428 if (enable)
2429 temp |= FDI_BC_BIFURCATION_SELECT;
2430
2431 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
2432 enable ? "en" : "dis");
2433 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
2434 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
2435}
2436
2437static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
2438{
2439 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2440 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2441
2442 switch (crtc->pipe) {
2443 case PIPE_A:
2444 break;
2445 case PIPE_B:
2446 if (crtc_state->fdi_lanes > 2)
2447 cpt_set_fdi_bc_bifurcation(dev_priv, false);
2448 else
2449 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2450
2451 break;
2452 case PIPE_C:
2453 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2454
2455 break;
2456 default:
2457 BUG();
2458 }
2459}
2460
2461/*
2462 * Finds the encoder associated with the given CRTC. This can only be
2463 * used when we know that the CRTC isn't feeding multiple encoders!
2464 */
2465struct intel_encoder *
2466intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
2467 const struct intel_crtc_state *crtc_state)
2468{
2469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2470 const struct drm_connector_state *connector_state;
2471 const struct drm_connector *connector;
2472 struct intel_encoder *encoder = NULL;
2473 int num_encoders = 0;
2474 int i;
2475
2476 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
2477 if (connector_state->crtc != &crtc->base)
2478 continue;
2479
2480 encoder = to_intel_encoder(connector_state->best_encoder);
2481 num_encoders++;
2482 }
2483
2484 drm_WARN(encoder->base.dev, num_encoders != 1,
2485 "%d encoders for pipe %c\n",
2486 num_encoders, pipe_name(crtc->pipe));
2487
2488 return encoder;
2489}
2490
2491/*
2492 * Enable PCH resources required for PCH ports:
2493 * - PCH PLLs
2494 * - FDI training & RX/TX
2495 * - update transcoder timings
2496 * - DP transcoding bits
2497 * - transcoder
2498 */
2499static void ilk_pch_enable(const struct intel_atomic_state *state,
2500 const struct intel_crtc_state *crtc_state)
2501{
2502 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2503 struct drm_device *dev = crtc->base.dev;
2504 struct drm_i915_private *dev_priv = to_i915(dev);
2505 enum pipe pipe = crtc->pipe;
2506 u32 temp;
2507
2508 assert_pch_transcoder_disabled(dev_priv, pipe);
2509
2510 if (IS_IVYBRIDGE(dev_priv))
2511 ivb_update_fdi_bc_bifurcation(crtc_state);
2512
2513 /* Write the TU size bits before fdi link training, so that error
2514 * detection works. */
2515 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
2516 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2517
2518 /* For PCH output, training FDI link */
2519 dev_priv->display.fdi_link_train(crtc, crtc_state);
2520
2521 /* We need to program the right clock selection before writing the pixel
2522 * mutliplier into the DPLL. */
2523 if (HAS_PCH_CPT(dev_priv)) {
2524 u32 sel;
2525
2526 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
2527 temp |= TRANS_DPLL_ENABLE(pipe);
2528 sel = TRANS_DPLLB_SEL(pipe);
2529 if (crtc_state->shared_dpll ==
2530 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
2531 temp |= sel;
2532 else
2533 temp &= ~sel;
2534 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
2535 }
2536
2537 /* XXX: pch pll's can be enabled any time before we enable the PCH
2538 * transcoder, and we actually should do this to not upset any PCH
2539 * transcoder that already use the clock when we share it.
2540 *
2541 * Note that enable_shared_dpll tries to do the right thing, but
2542 * get_shared_dpll unconditionally resets the pll - we need that to have
2543 * the right LVDS enable sequence. */
2544 intel_enable_shared_dpll(crtc_state);
2545
2546 /* set transcoder timing, panel must allow it */
2547 assert_panel_unlocked(dev_priv, pipe);
2548 ilk_pch_transcoder_set_timings(crtc_state, pipe);
2549
2550 intel_fdi_normal_train(crtc);
2551
2552 /* For PCH DP, enable TRANS_DP_CTL */
2553 if (HAS_PCH_CPT(dev_priv) &&
2554 intel_crtc_has_dp_encoder(crtc_state)) {
2555 const struct drm_display_mode *adjusted_mode =
2556 &crtc_state->hw.adjusted_mode;
2557 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2558 i915_reg_t reg = TRANS_DP_CTL(pipe);
2559 enum port port;
2560
2561 temp = intel_de_read(dev_priv, reg);
2562 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2563 TRANS_DP_SYNC_MASK |
2564 TRANS_DP_BPC_MASK);
2565 temp |= TRANS_DP_OUTPUT_ENABLE;
2566 temp |= bpc << 9; /* same format but at 11:9 */
2567
2568 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2569 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2570 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2571 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2572
2573 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
2574 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
2575 temp |= TRANS_DP_PORT_SEL(port);
2576
2577 intel_de_write(dev_priv, reg, temp);
2578 }
2579
2580 ilk_enable_pch_transcoder(crtc_state);
2581}
2582
2583void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
2584{
2585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2587 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2588
2589 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
2590
2591 lpt_program_iclkip(crtc_state);
2592
2593 /* Set transcoder timing. */
2594 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
2595
2596 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
2597}
2598
2599static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
2600 enum pipe pipe)
2601{
2602 i915_reg_t dslreg = PIPEDSL(pipe);
2603 u32 temp;
2604
2605 temp = intel_de_read(dev_priv, dslreg);
2606 udelay(500);
2607 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
2608 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
2609 drm_err(&dev_priv->drm,
2610 "mode set failed: pipe %c stuck\n",
2611 pipe_name(pipe));
2612 }
2613}
2614
2615static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
2616{
2617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2618 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2619 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
2620 enum pipe pipe = crtc->pipe;
2621 int width = drm_rect_width(dst);
2622 int height = drm_rect_height(dst);
2623 int x = dst->x1;
2624 int y = dst->y1;
2625
2626 if (!crtc_state->pch_pfit.enabled)
2627 return;
2628
2629 /* Force use of hard-coded filter coefficients
2630 * as some pre-programmed values are broken,
2631 * e.g. x201.
2632 */
2633 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
2634 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2635 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
2636 else
2637 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2638 PF_FILTER_MED_3x3);
2639 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
2640 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
2641}
2642
2643void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
2644{
2645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2646 struct drm_device *dev = crtc->base.dev;
2647 struct drm_i915_private *dev_priv = to_i915(dev);
2648
2649 if (!crtc_state->ips_enabled)
2650 return;
2651
2652 /*
2653 * We can only enable IPS after we enable a plane and wait for a vblank
2654 * This function is called from post_plane_update, which is run after
2655 * a vblank wait.
2656 */
2657 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
2658
2659 if (IS_BROADWELL(dev_priv)) {
2660 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
2661 IPS_ENABLE | IPS_PCODE_CONTROL));
2662 /* Quoting Art Runyan: "its not safe to expect any particular
2663 * value in IPS_CTL bit 31 after enabling IPS through the
2664 * mailbox." Moreover, the mailbox may return a bogus state,
2665 * so we need to just enable it and continue on.
2666 */
2667 } else {
2668 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
2669 /* The bit only becomes 1 in the next vblank, so this wait here
2670 * is essentially intel_wait_for_vblank. If we don't have this
2671 * and don't wait for vblanks until the end of crtc_enable, then
2672 * the HW state readout code will complain that the expected
2673 * IPS_CTL value is not the one we read. */
2674 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
2675 drm_err(&dev_priv->drm,
2676 "Timed out waiting for IPS enable\n");
2677 }
2678}
2679
2680void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
2681{
2682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2683 struct drm_device *dev = crtc->base.dev;
2684 struct drm_i915_private *dev_priv = to_i915(dev);
2685
2686 if (!crtc_state->ips_enabled)
2687 return;
2688
2689 if (IS_BROADWELL(dev_priv)) {
2690 drm_WARN_ON(dev,
2691 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
2692 /*
2693 * Wait for PCODE to finish disabling IPS. The BSpec specified
2694 * 42ms timeout value leads to occasional timeouts so use 100ms
2695 * instead.
2696 */
2697 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
2698 drm_err(&dev_priv->drm,
2699 "Timed out waiting for IPS disable\n");
2700 } else {
2701 intel_de_write(dev_priv, IPS_CTL, 0);
2702 intel_de_posting_read(dev_priv, IPS_CTL);
2703 }
2704
2705 /* We need to wait for a vblank before we can disable the plane. */
2706 intel_wait_for_vblank(dev_priv, crtc->pipe);
2707}
2708
2709static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
2710{
2711 if (intel_crtc->overlay)
2712 (void) intel_overlay_switch_off(intel_crtc->overlay);
2713
2714 /* Let userspace switch the overlay on again. In most cases userspace
2715 * has to recompute where to put it anyway.
2716 */
2717}
2718
2719static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
2720 const struct intel_crtc_state *new_crtc_state)
2721{
2722 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2724
2725 if (!old_crtc_state->ips_enabled)
2726 return false;
2727
2728 if (intel_crtc_needs_modeset(new_crtc_state))
2729 return true;
2730
2731 /*
2732 * Workaround : Do not read or write the pipe palette/gamma data while
2733 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2734 *
2735 * Disable IPS before we program the LUT.
2736 */
2737 if (IS_HASWELL(dev_priv) &&
2738 (new_crtc_state->uapi.color_mgmt_changed ||
2739 new_crtc_state->update_pipe) &&
2740 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2741 return true;
2742
2743 return !new_crtc_state->ips_enabled;
2744}
2745
2746static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
2747 const struct intel_crtc_state *new_crtc_state)
2748{
2749 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2751
2752 if (!new_crtc_state->ips_enabled)
2753 return false;
2754
2755 if (intel_crtc_needs_modeset(new_crtc_state))
2756 return true;
2757
2758 /*
2759 * Workaround : Do not read or write the pipe palette/gamma data while
2760 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2761 *
2762 * Re-enable IPS after the LUT has been programmed.
2763 */
2764 if (IS_HASWELL(dev_priv) &&
2765 (new_crtc_state->uapi.color_mgmt_changed ||
2766 new_crtc_state->update_pipe) &&
2767 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2768 return true;
2769
2770 /*
2771 * We can't read out IPS on broadwell, assume the worst and
2772 * forcibly enable IPS on the first fastset.
2773 */
2774 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
2775 return true;
2776
2777 return !old_crtc_state->ips_enabled;
2778}
2779
2780static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
2781{
2782 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2783
2784 if (!crtc_state->nv12_planes)
2785 return false;
2786
2787 /* WA Display #0827: Gen9:all */
2788 if (DISPLAY_VER(dev_priv) == 9)
2789 return true;
2790
2791 return false;
2792}
2793
2794static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
2795{
2796 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2797
2798 /* Wa_2006604312:icl,ehl */
2799 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
2800 return true;
2801
2802 return false;
2803}
2804
2805static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
2806 const struct intel_crtc_state *new_crtc_state)
2807{
2808 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
2809 new_crtc_state->active_planes;
2810}
2811
2812static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
2813 const struct intel_crtc_state *new_crtc_state)
2814{
2815 return old_crtc_state->active_planes &&
2816 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
2817}
2818
2819static void intel_post_plane_update(struct intel_atomic_state *state,
2820 struct intel_crtc *crtc)
2821{
2822 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2823 const struct intel_crtc_state *old_crtc_state =
2824 intel_atomic_get_old_crtc_state(state, crtc);
2825 const struct intel_crtc_state *new_crtc_state =
2826 intel_atomic_get_new_crtc_state(state, crtc);
2827 enum pipe pipe = crtc->pipe;
2828
2829 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
2830
2831 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
2832 intel_update_watermarks(crtc);
2833
2834 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
2835 hsw_enable_ips(new_crtc_state);
2836
2837 intel_fbc_post_update(state, crtc);
2838
2839 if (needs_nv12_wa(old_crtc_state) &&
2840 !needs_nv12_wa(new_crtc_state))
2841 skl_wa_827(dev_priv, pipe, false);
2842
2843 if (needs_scalerclk_wa(old_crtc_state) &&
2844 !needs_scalerclk_wa(new_crtc_state))
2845 icl_wa_scalerclkgating(dev_priv, pipe, false);
2846}
2847
2848static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
2849 struct intel_crtc *crtc)
2850{
2851 const struct intel_crtc_state *crtc_state =
2852 intel_atomic_get_new_crtc_state(state, crtc);
2853 u8 update_planes = crtc_state->update_planes;
2854 const struct intel_plane_state *plane_state;
2855 struct intel_plane *plane;
2856 int i;
2857
2858 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2859 if (plane->enable_flip_done &&
2860 plane->pipe == crtc->pipe &&
2861 update_planes & BIT(plane->id))
2862 plane->enable_flip_done(plane);
2863 }
2864}
2865
2866static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
2867 struct intel_crtc *crtc)
2868{
2869 const struct intel_crtc_state *crtc_state =
2870 intel_atomic_get_new_crtc_state(state, crtc);
2871 u8 update_planes = crtc_state->update_planes;
2872 const struct intel_plane_state *plane_state;
2873 struct intel_plane *plane;
2874 int i;
2875
2876 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2877 if (plane->disable_flip_done &&
2878 plane->pipe == crtc->pipe &&
2879 update_planes & BIT(plane->id))
2880 plane->disable_flip_done(plane);
2881 }
2882}
2883
2884static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
2885 struct intel_crtc *crtc)
2886{
2887 struct drm_i915_private *i915 = to_i915(state->base.dev);
2888 const struct intel_crtc_state *old_crtc_state =
2889 intel_atomic_get_old_crtc_state(state, crtc);
2890 const struct intel_crtc_state *new_crtc_state =
2891 intel_atomic_get_new_crtc_state(state, crtc);
2892 u8 update_planes = new_crtc_state->update_planes;
2893 const struct intel_plane_state *old_plane_state;
2894 struct intel_plane *plane;
2895 bool need_vbl_wait = false;
2896 int i;
2897
2898 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
2899 if (plane->need_async_flip_disable_wa &&
2900 plane->pipe == crtc->pipe &&
2901 update_planes & BIT(plane->id)) {
2902 /*
2903 * Apart from the async flip bit we want to
2904 * preserve the old state for the plane.
2905 */
2906 plane->async_flip(plane, old_crtc_state,
2907 old_plane_state, false);
2908 need_vbl_wait = true;
2909 }
2910 }
2911
2912 if (need_vbl_wait)
2913 intel_wait_for_vblank(i915, crtc->pipe);
2914}
2915
2916static void intel_pre_plane_update(struct intel_atomic_state *state,
2917 struct intel_crtc *crtc)
2918{
2919 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2920 const struct intel_crtc_state *old_crtc_state =
2921 intel_atomic_get_old_crtc_state(state, crtc);
2922 const struct intel_crtc_state *new_crtc_state =
2923 intel_atomic_get_new_crtc_state(state, crtc);
2924 enum pipe pipe = crtc->pipe;
2925
2926 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
2927 hsw_disable_ips(old_crtc_state);
2928
2929 if (intel_fbc_pre_update(state, crtc))
2930 intel_wait_for_vblank(dev_priv, pipe);
2931
2932 /* Display WA 827 */
2933 if (!needs_nv12_wa(old_crtc_state) &&
2934 needs_nv12_wa(new_crtc_state))
2935 skl_wa_827(dev_priv, pipe, true);
2936
2937 /* Wa_2006604312:icl,ehl */
2938 if (!needs_scalerclk_wa(old_crtc_state) &&
2939 needs_scalerclk_wa(new_crtc_state))
2940 icl_wa_scalerclkgating(dev_priv, pipe, true);
2941
2942 /*
2943 * Vblank time updates from the shadow to live plane control register
2944 * are blocked if the memory self-refresh mode is active at that
2945 * moment. So to make sure the plane gets truly disabled, disable
2946 * first the self-refresh mode. The self-refresh enable bit in turn
2947 * will be checked/applied by the HW only at the next frame start
2948 * event which is after the vblank start event, so we need to have a
2949 * wait-for-vblank between disabling the plane and the pipe.
2950 */
2951 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
2952 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
2953 intel_wait_for_vblank(dev_priv, pipe);
2954
2955 /*
2956 * IVB workaround: must disable low power watermarks for at least
2957 * one frame before enabling scaling. LP watermarks can be re-enabled
2958 * when scaling is disabled.
2959 *
2960 * WaCxSRDisabledForSpriteScaling:ivb
2961 */
2962 if (old_crtc_state->hw.active &&
2963 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
2964 intel_wait_for_vblank(dev_priv, pipe);
2965
2966 /*
2967 * If we're doing a modeset we don't need to do any
2968 * pre-vblank watermark programming here.
2969 */
2970 if (!intel_crtc_needs_modeset(new_crtc_state)) {
2971 /*
2972 * For platforms that support atomic watermarks, program the
2973 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
2974 * will be the intermediate values that are safe for both pre- and
2975 * post- vblank; when vblank happens, the 'active' values will be set
2976 * to the final 'target' values and we'll do this again to get the
2977 * optimal watermarks. For gen9+ platforms, the values we program here
2978 * will be the final target values which will get automatically latched
2979 * at vblank time; no further programming will be necessary.
2980 *
2981 * If a platform hasn't been transitioned to atomic watermarks yet,
2982 * we'll continue to update watermarks the old way, if flags tell
2983 * us to.
2984 */
2985 if (dev_priv->display.initial_watermarks)
2986 dev_priv->display.initial_watermarks(state, crtc);
2987 else if (new_crtc_state->update_wm_pre)
2988 intel_update_watermarks(crtc);
2989 }
2990
2991 /*
2992 * Gen2 reports pipe underruns whenever all planes are disabled.
2993 * So disable underrun reporting before all the planes get disabled.
2994 *
2995 * We do this after .initial_watermarks() so that we have a
2996 * chance of catching underruns with the intermediate watermarks
2997 * vs. the old plane configuration.
2998 */
2999 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
3000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3001
3002 /*
3003 * WA for platforms where async address update enable bit
3004 * is double buffered and only latched at start of vblank.
3005 */
3006 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
3007 intel_crtc_async_flip_disable_wa(state, crtc);
3008}
3009
3010static void intel_crtc_disable_planes(struct intel_atomic_state *state,
3011 struct intel_crtc *crtc)
3012{
3013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3014 const struct intel_crtc_state *new_crtc_state =
3015 intel_atomic_get_new_crtc_state(state, crtc);
3016 unsigned int update_mask = new_crtc_state->update_planes;
3017 const struct intel_plane_state *old_plane_state;
3018 struct intel_plane *plane;
3019 unsigned fb_bits = 0;
3020 int i;
3021
3022 intel_crtc_dpms_overlay_disable(crtc);
3023
3024 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
3025 if (crtc->pipe != plane->pipe ||
3026 !(update_mask & BIT(plane->id)))
3027 continue;
3028
3029 intel_disable_plane(plane, new_crtc_state);
3030
3031 if (old_plane_state->uapi.visible)
3032 fb_bits |= plane->frontbuffer_bit;
3033 }
3034
3035 intel_frontbuffer_flip(dev_priv, fb_bits);
3036}
3037
3038/*
3039 * intel_connector_primary_encoder - get the primary encoder for a connector
3040 * @connector: connector for which to return the encoder
3041 *
3042 * Returns the primary encoder for a connector. There is a 1:1 mapping from
3043 * all connectors to their encoder, except for DP-MST connectors which have
3044 * both a virtual and a primary encoder. These DP-MST primary encoders can be
3045 * pointed to by as many DP-MST connectors as there are pipes.
3046 */
3047static struct intel_encoder *
3048intel_connector_primary_encoder(struct intel_connector *connector)
3049{
3050 struct intel_encoder *encoder;
3051
3052 if (connector->mst_port)
3053 return &dp_to_dig_port(connector->mst_port)->base;
3054
3055 encoder = intel_attached_encoder(connector);
3056 drm_WARN_ON(connector->base.dev, !encoder);
3057
3058 return encoder;
3059}
3060
3061static void intel_encoders_update_prepare(struct intel_atomic_state *state)
3062{
3063 struct drm_connector_state *new_conn_state;
3064 struct drm_connector *connector;
3065 int i;
3066
3067 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3068 i) {
3069 struct intel_connector *intel_connector;
3070 struct intel_encoder *encoder;
3071 struct intel_crtc *crtc;
3072
3073 if (!intel_connector_needs_modeset(state, connector))
3074 continue;
3075
3076 intel_connector = to_intel_connector(connector);
3077 encoder = intel_connector_primary_encoder(intel_connector);
3078 if (!encoder->update_prepare)
3079 continue;
3080
3081 crtc = new_conn_state->crtc ?
3082 to_intel_crtc(new_conn_state->crtc) : NULL;
3083 encoder->update_prepare(state, encoder, crtc);
3084 }
3085}
3086
3087static void intel_encoders_update_complete(struct intel_atomic_state *state)
3088{
3089 struct drm_connector_state *new_conn_state;
3090 struct drm_connector *connector;
3091 int i;
3092
3093 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3094 i) {
3095 struct intel_connector *intel_connector;
3096 struct intel_encoder *encoder;
3097 struct intel_crtc *crtc;
3098
3099 if (!intel_connector_needs_modeset(state, connector))
3100 continue;
3101
3102 intel_connector = to_intel_connector(connector);
3103 encoder = intel_connector_primary_encoder(intel_connector);
3104 if (!encoder->update_complete)
3105 continue;
3106
3107 crtc = new_conn_state->crtc ?
3108 to_intel_crtc(new_conn_state->crtc) : NULL;
3109 encoder->update_complete(state, encoder, crtc);
3110 }
3111}
3112
3113static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
3114 struct intel_crtc *crtc)
3115{
3116 const struct intel_crtc_state *crtc_state =
3117 intel_atomic_get_new_crtc_state(state, crtc);
3118 const struct drm_connector_state *conn_state;
3119 struct drm_connector *conn;
3120 int i;
3121
3122 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3123 struct intel_encoder *encoder =
3124 to_intel_encoder(conn_state->best_encoder);
3125
3126 if (conn_state->crtc != &crtc->base)
3127 continue;
3128
3129 if (encoder->pre_pll_enable)
3130 encoder->pre_pll_enable(state, encoder,
3131 crtc_state, conn_state);
3132 }
3133}
3134
3135static void intel_encoders_pre_enable(struct intel_atomic_state *state,
3136 struct intel_crtc *crtc)
3137{
3138 const struct intel_crtc_state *crtc_state =
3139 intel_atomic_get_new_crtc_state(state, crtc);
3140 const struct drm_connector_state *conn_state;
3141 struct drm_connector *conn;
3142 int i;
3143
3144 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3145 struct intel_encoder *encoder =
3146 to_intel_encoder(conn_state->best_encoder);
3147
3148 if (conn_state->crtc != &crtc->base)
3149 continue;
3150
3151 if (encoder->pre_enable)
3152 encoder->pre_enable(state, encoder,
3153 crtc_state, conn_state);
3154 }
3155}
3156
3157static void intel_encoders_enable(struct intel_atomic_state *state,
3158 struct intel_crtc *crtc)
3159{
3160 const struct intel_crtc_state *crtc_state =
3161 intel_atomic_get_new_crtc_state(state, crtc);
3162 const struct drm_connector_state *conn_state;
3163 struct drm_connector *conn;
3164 int i;
3165
3166 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3167 struct intel_encoder *encoder =
3168 to_intel_encoder(conn_state->best_encoder);
3169
3170 if (conn_state->crtc != &crtc->base)
3171 continue;
3172
3173 if (encoder->enable)
3174 encoder->enable(state, encoder,
3175 crtc_state, conn_state);
3176 intel_opregion_notify_encoder(encoder, true);
3177 }
3178}
3179
3180static void intel_encoders_disable(struct intel_atomic_state *state,
3181 struct intel_crtc *crtc)
3182{
3183 const struct intel_crtc_state *old_crtc_state =
3184 intel_atomic_get_old_crtc_state(state, crtc);
3185 const struct drm_connector_state *old_conn_state;
3186 struct drm_connector *conn;
3187 int i;
3188
3189 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3190 struct intel_encoder *encoder =
3191 to_intel_encoder(old_conn_state->best_encoder);
3192
3193 if (old_conn_state->crtc != &crtc->base)
3194 continue;
3195
3196 intel_opregion_notify_encoder(encoder, false);
3197 if (encoder->disable)
3198 encoder->disable(state, encoder,
3199 old_crtc_state, old_conn_state);
3200 }
3201}
3202
3203static void intel_encoders_post_disable(struct intel_atomic_state *state,
3204 struct intel_crtc *crtc)
3205{
3206 const struct intel_crtc_state *old_crtc_state =
3207 intel_atomic_get_old_crtc_state(state, crtc);
3208 const struct drm_connector_state *old_conn_state;
3209 struct drm_connector *conn;
3210 int i;
3211
3212 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3213 struct intel_encoder *encoder =
3214 to_intel_encoder(old_conn_state->best_encoder);
3215
3216 if (old_conn_state->crtc != &crtc->base)
3217 continue;
3218
3219 if (encoder->post_disable)
3220 encoder->post_disable(state, encoder,
3221 old_crtc_state, old_conn_state);
3222 }
3223}
3224
3225static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
3226 struct intel_crtc *crtc)
3227{
3228 const struct intel_crtc_state *old_crtc_state =
3229 intel_atomic_get_old_crtc_state(state, crtc);
3230 const struct drm_connector_state *old_conn_state;
3231 struct drm_connector *conn;
3232 int i;
3233
3234 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3235 struct intel_encoder *encoder =
3236 to_intel_encoder(old_conn_state->best_encoder);
3237
3238 if (old_conn_state->crtc != &crtc->base)
3239 continue;
3240
3241 if (encoder->post_pll_disable)
3242 encoder->post_pll_disable(state, encoder,
3243 old_crtc_state, old_conn_state);
3244 }
3245}
3246
3247static void intel_encoders_update_pipe(struct intel_atomic_state *state,
3248 struct intel_crtc *crtc)
3249{
3250 const struct intel_crtc_state *crtc_state =
3251 intel_atomic_get_new_crtc_state(state, crtc);
3252 const struct drm_connector_state *conn_state;
3253 struct drm_connector *conn;
3254 int i;
3255
3256 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3257 struct intel_encoder *encoder =
3258 to_intel_encoder(conn_state->best_encoder);
3259
3260 if (conn_state->crtc != &crtc->base)
3261 continue;
3262
3263 if (encoder->update_pipe)
3264 encoder->update_pipe(state, encoder,
3265 crtc_state, conn_state);
3266 }
3267}
3268
3269static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
3270{
3271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3272 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3273
3274 plane->disable_plane(plane, crtc_state);
3275}
3276
3277static void ilk_crtc_enable(struct intel_atomic_state *state,
3278 struct intel_crtc *crtc)
3279{
3280 const struct intel_crtc_state *new_crtc_state =
3281 intel_atomic_get_new_crtc_state(state, crtc);
3282 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3283 enum pipe pipe = crtc->pipe;
3284
3285 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3286 return;
3287
3288 /*
3289 * Sometimes spurious CPU pipe underruns happen during FDI
3290 * training, at least with VGA+HDMI cloning. Suppress them.
3291 *
3292 * On ILK we get an occasional spurious CPU pipe underruns
3293 * between eDP port A enable and vdd enable. Also PCH port
3294 * enable seems to result in the occasional CPU pipe underrun.
3295 *
3296 * Spurious PCH underruns also occur during PCH enabling.
3297 */
3298 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3299 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3300
3301 if (new_crtc_state->has_pch_encoder)
3302 intel_prepare_shared_dpll(new_crtc_state);
3303
3304 if (intel_crtc_has_dp_encoder(new_crtc_state))
3305 intel_dp_set_m_n(new_crtc_state, M1_N1);
3306
3307 intel_set_transcoder_timings(new_crtc_state);
3308 intel_set_pipe_src_size(new_crtc_state);
3309
3310 if (new_crtc_state->has_pch_encoder)
3311 intel_cpu_transcoder_set_m_n(new_crtc_state,
3312 &new_crtc_state->fdi_m_n, NULL);
3313
3314 ilk_set_pipeconf(new_crtc_state);
3315
3316 crtc->active = true;
3317
3318 intel_encoders_pre_enable(state, crtc);
3319
3320 if (new_crtc_state->has_pch_encoder) {
3321 /* Note: FDI PLL enabling _must_ be done before we enable the
3322 * cpu pipes, hence this is separate from all the other fdi/pch
3323 * enabling. */
3324 ilk_fdi_pll_enable(new_crtc_state);
3325 } else {
3326 assert_fdi_tx_disabled(dev_priv, pipe);
3327 assert_fdi_rx_disabled(dev_priv, pipe);
3328 }
3329
3330 ilk_pfit_enable(new_crtc_state);
3331
3332 /*
3333 * On ILK+ LUT must be loaded before the pipe is running but with
3334 * clocks enabled
3335 */
3336 intel_color_load_luts(new_crtc_state);
3337 intel_color_commit(new_crtc_state);
3338 /* update DSPCNTR to configure gamma for pipe bottom color */
3339 intel_disable_primary_plane(new_crtc_state);
3340
3341 if (dev_priv->display.initial_watermarks)
3342 dev_priv->display.initial_watermarks(state, crtc);
3343 intel_enable_pipe(new_crtc_state);
3344
3345 if (new_crtc_state->has_pch_encoder)
3346 ilk_pch_enable(state, new_crtc_state);
3347
3348 intel_crtc_vblank_on(new_crtc_state);
3349
3350 intel_encoders_enable(state, crtc);
3351
3352 if (HAS_PCH_CPT(dev_priv))
3353 cpt_verify_modeset(dev_priv, pipe);
3354
3355 /*
3356 * Must wait for vblank to avoid spurious PCH FIFO underruns.
3357 * And a second vblank wait is needed at least on ILK with
3358 * some interlaced HDMI modes. Let's do the double wait always
3359 * in case there are more corner cases we don't know about.
3360 */
3361 if (new_crtc_state->has_pch_encoder) {
3362 intel_wait_for_vblank(dev_priv, pipe);
3363 intel_wait_for_vblank(dev_priv, pipe);
3364 }
3365 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3366 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3367}
3368
3369/* IPS only exists on ULT machines and is tied to pipe A. */
3370static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3371{
3372 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
3373}
3374
3375static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
3376 enum pipe pipe, bool apply)
3377{
3378 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
3379 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
3380
3381 if (apply)
3382 val |= mask;
3383 else
3384 val &= ~mask;
3385
3386 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
3387}
3388
3389static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
3390{
3391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3392 enum pipe pipe = crtc->pipe;
3393 u32 val;
3394
3395 val = MBUS_DBOX_A_CREDIT(2);
3396
3397 if (DISPLAY_VER(dev_priv) >= 12) {
3398 val |= MBUS_DBOX_BW_CREDIT(2);
3399 val |= MBUS_DBOX_B_CREDIT(12);
3400 } else {
3401 val |= MBUS_DBOX_BW_CREDIT(1);
3402 val |= MBUS_DBOX_B_CREDIT(8);
3403 }
3404
3405 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
3406}
3407
3408static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
3409{
3410 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3412
3413 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
3414 HSW_LINETIME(crtc_state->linetime) |
3415 HSW_IPS_LINETIME(crtc_state->ips_linetime));
3416}
3417
3418static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
3419{
3420 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3421 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3422 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
3423 u32 val;
3424
3425 val = intel_de_read(dev_priv, reg);
3426 val &= ~HSW_FRAME_START_DELAY_MASK;
3427 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
3428 intel_de_write(dev_priv, reg, val);
3429}
3430
3431static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
3432 const struct intel_crtc_state *crtc_state)
3433{
3434 struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
3435 struct drm_i915_private *dev_priv = to_i915(master->base.dev);
3436 struct intel_crtc_state *master_crtc_state;
3437 struct drm_connector_state *conn_state;
3438 struct drm_connector *conn;
3439 struct intel_encoder *encoder = NULL;
3440 int i;
3441
3442 if (crtc_state->bigjoiner_slave)
3443 master = crtc_state->bigjoiner_linked_crtc;
3444
3445 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
3446
3447 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3448 if (conn_state->crtc != &master->base)
3449 continue;
3450
3451 encoder = to_intel_encoder(conn_state->best_encoder);
3452 break;
3453 }
3454
3455 if (!crtc_state->bigjoiner_slave) {
3456 /* need to enable VDSC, which we skipped in pre-enable */
3457 intel_dsc_enable(encoder, crtc_state);
3458 } else {
3459 /*
3460 * Enable sequence steps 1-7 on bigjoiner master
3461 */
3462 intel_encoders_pre_pll_enable(state, master);
3463 intel_enable_shared_dpll(master_crtc_state);
3464 intel_encoders_pre_enable(state, master);
3465
3466 /* and DSC on slave */
3467 intel_dsc_enable(NULL, crtc_state);
3468 }
3469
3470 if (DISPLAY_VER(dev_priv) >= 13)
3471 intel_uncompressed_joiner_enable(crtc_state);
3472}
3473
3474static void hsw_crtc_enable(struct intel_atomic_state *state,
3475 struct intel_crtc *crtc)
3476{
3477 const struct intel_crtc_state *new_crtc_state =
3478 intel_atomic_get_new_crtc_state(state, crtc);
3479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3480 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
3481 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3482 bool psl_clkgate_wa;
3483
3484 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3485 return;
3486
3487 if (!new_crtc_state->bigjoiner) {
3488 intel_encoders_pre_pll_enable(state, crtc);
3489
3490 if (new_crtc_state->shared_dpll)
3491 intel_enable_shared_dpll(new_crtc_state);
3492
3493 intel_encoders_pre_enable(state, crtc);
3494 } else {
3495 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
3496 }
3497
3498 intel_set_pipe_src_size(new_crtc_state);
3499 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
3500 bdw_set_pipemisc(new_crtc_state);
3501
3502 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
3503 intel_set_transcoder_timings(new_crtc_state);
3504
3505 if (cpu_transcoder != TRANSCODER_EDP)
3506 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
3507 new_crtc_state->pixel_multiplier - 1);
3508
3509 if (new_crtc_state->has_pch_encoder)
3510 intel_cpu_transcoder_set_m_n(new_crtc_state,
3511 &new_crtc_state->fdi_m_n, NULL);
3512
3513 hsw_set_frame_start_delay(new_crtc_state);
3514 }
3515
3516 if (!transcoder_is_dsi(cpu_transcoder))
3517 hsw_set_pipeconf(new_crtc_state);
3518
3519 crtc->active = true;
3520
3521 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
3522 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
3523 new_crtc_state->pch_pfit.enabled;
3524 if (psl_clkgate_wa)
3525 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
3526
3527 if (DISPLAY_VER(dev_priv) >= 9)
3528 skl_pfit_enable(new_crtc_state);
3529 else
3530 ilk_pfit_enable(new_crtc_state);
3531
3532 /*
3533 * On ILK+ LUT must be loaded before the pipe is running but with
3534 * clocks enabled
3535 */
3536 intel_color_load_luts(new_crtc_state);
3537 intel_color_commit(new_crtc_state);
3538 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
3539 if (DISPLAY_VER(dev_priv) < 9)
3540 intel_disable_primary_plane(new_crtc_state);
3541
3542 hsw_set_linetime_wm(new_crtc_state);
3543
3544 if (DISPLAY_VER(dev_priv) >= 11)
3545 icl_set_pipe_chicken(crtc);
3546
3547 if (dev_priv->display.initial_watermarks)
3548 dev_priv->display.initial_watermarks(state, crtc);
3549
3550 if (DISPLAY_VER(dev_priv) >= 11)
3551 icl_pipe_mbus_enable(crtc);
3552
3553 if (new_crtc_state->bigjoiner_slave)
3554 intel_crtc_vblank_on(new_crtc_state);
3555
3556 intel_encoders_enable(state, crtc);
3557
3558 if (psl_clkgate_wa) {
3559 intel_wait_for_vblank(dev_priv, pipe);
3560 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
3561 }
3562
3563 /* If we change the relative order between pipe/planes enabling, we need
3564 * to change the workaround. */
3565 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
3566 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
3567 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3568 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3569 }
3570}
3571
3572void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
3573{
3574 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3576 enum pipe pipe = crtc->pipe;
3577
3578 /* To avoid upsetting the power well on haswell only disable the pfit if
3579 * it's in use. The hw state code will make sure we get this right. */
3580 if (!old_crtc_state->pch_pfit.enabled)
3581 return;
3582
3583 intel_de_write(dev_priv, PF_CTL(pipe), 0);
3584 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
3585 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
3586}
3587
3588static void ilk_crtc_disable(struct intel_atomic_state *state,
3589 struct intel_crtc *crtc)
3590{
3591 const struct intel_crtc_state *old_crtc_state =
3592 intel_atomic_get_old_crtc_state(state, crtc);
3593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3594 enum pipe pipe = crtc->pipe;
3595
3596 /*
3597 * Sometimes spurious CPU pipe underruns happen when the
3598 * pipe is already disabled, but FDI RX/TX is still enabled.
3599 * Happens at least with VGA+HDMI cloning. Suppress them.
3600 */
3601 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3602 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3603
3604 intel_encoders_disable(state, crtc);
3605
3606 intel_crtc_vblank_off(old_crtc_state);
3607
3608 intel_disable_pipe(old_crtc_state);
3609
3610 ilk_pfit_disable(old_crtc_state);
3611
3612 if (old_crtc_state->has_pch_encoder)
3613 ilk_fdi_disable(crtc);
3614
3615 intel_encoders_post_disable(state, crtc);
3616
3617 if (old_crtc_state->has_pch_encoder) {
3618 ilk_disable_pch_transcoder(dev_priv, pipe);
3619
3620 if (HAS_PCH_CPT(dev_priv)) {
3621 i915_reg_t reg;
3622 u32 temp;
3623
3624 /* disable TRANS_DP_CTL */
3625 reg = TRANS_DP_CTL(pipe);
3626 temp = intel_de_read(dev_priv, reg);
3627 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3628 TRANS_DP_PORT_SEL_MASK);
3629 temp |= TRANS_DP_PORT_SEL_NONE;
3630 intel_de_write(dev_priv, reg, temp);
3631
3632 /* disable DPLL_SEL */
3633 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
3634 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3635 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
3636 }
3637
3638 ilk_fdi_pll_disable(crtc);
3639 }
3640
3641 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3642 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3643}
3644
3645static void hsw_crtc_disable(struct intel_atomic_state *state,
3646 struct intel_crtc *crtc)
3647{
3648 /*
3649 * FIXME collapse everything to one hook.
3650 * Need care with mst->ddi interactions.
3651 */
3652 intel_encoders_disable(state, crtc);
3653 intel_encoders_post_disable(state, crtc);
3654}
3655
3656static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
3657{
3658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3660
3661 if (!crtc_state->gmch_pfit.control)
3662 return;
3663
3664 /*
3665 * The panel fitter should only be adjusted whilst the pipe is disabled,
3666 * according to register description and PRM.
3667 */
3668 drm_WARN_ON(&dev_priv->drm,
3669 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
3670 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
3671
3672 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
3673 crtc_state->gmch_pfit.pgm_ratios);
3674 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
3675
3676 /* Border color in case we don't scale up to the full screen. Black by
3677 * default, change to something else for debugging. */
3678 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
3679}
3680
3681bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
3682{
3683 if (phy == PHY_NONE)
3684 return false;
3685 else if (IS_ALDERLAKE_S(dev_priv))
3686 return phy <= PHY_E;
3687 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
3688 return phy <= PHY_D;
3689 else if (IS_JSL_EHL(dev_priv))
3690 return phy <= PHY_C;
3691 else if (DISPLAY_VER(dev_priv) >= 11)
3692 return phy <= PHY_B;
3693 else
3694 return false;
3695}
3696
3697bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
3698{
3699 if (IS_ALDERLAKE_P(dev_priv))
3700 return phy >= PHY_F && phy <= PHY_I;
3701 else if (IS_TIGERLAKE(dev_priv))
3702 return phy >= PHY_D && phy <= PHY_I;
3703 else if (IS_ICELAKE(dev_priv))
3704 return phy >= PHY_C && phy <= PHY_F;
3705 else
3706 return false;
3707}
3708
3709enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
3710{
3711 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
3712 return PHY_D + port - PORT_D_XELPD;
3713 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
3714 return PHY_F + port - PORT_TC1;
3715 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
3716 return PHY_B + port - PORT_TC1;
3717 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
3718 return PHY_C + port - PORT_TC1;
3719 else if (IS_JSL_EHL(i915) && port == PORT_D)
3720 return PHY_A;
3721
3722 return PHY_A + port - PORT_A;
3723}
3724
3725enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
3726{
3727 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
3728 return TC_PORT_NONE;
3729
3730 if (DISPLAY_VER(dev_priv) >= 12)
3731 return TC_PORT_1 + port - PORT_TC1;
3732 else
3733 return TC_PORT_1 + port - PORT_C;
3734}
3735
3736enum intel_display_power_domain intel_port_to_power_domain(enum port port)
3737{
3738 switch (port) {
3739 case PORT_A:
3740 return POWER_DOMAIN_PORT_DDI_A_LANES;
3741 case PORT_B:
3742 return POWER_DOMAIN_PORT_DDI_B_LANES;
3743 case PORT_C:
3744 return POWER_DOMAIN_PORT_DDI_C_LANES;
3745 case PORT_D:
3746 return POWER_DOMAIN_PORT_DDI_D_LANES;
3747 case PORT_E:
3748 return POWER_DOMAIN_PORT_DDI_E_LANES;
3749 case PORT_F:
3750 return POWER_DOMAIN_PORT_DDI_F_LANES;
3751 case PORT_G:
3752 return POWER_DOMAIN_PORT_DDI_G_LANES;
3753 case PORT_H:
3754 return POWER_DOMAIN_PORT_DDI_H_LANES;
3755 case PORT_I:
3756 return POWER_DOMAIN_PORT_DDI_I_LANES;
3757 default:
3758 MISSING_CASE(port);
3759 return POWER_DOMAIN_PORT_OTHER;
3760 }
3761}
3762
3763enum intel_display_power_domain
3764intel_aux_power_domain(struct intel_digital_port *dig_port)
3765{
3766 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3767 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
3768
3769 if (intel_phy_is_tc(dev_priv, phy) &&
3770 dig_port->tc_mode == TC_PORT_TBT_ALT) {
3771 switch (dig_port->aux_ch) {
3772 case AUX_CH_C:
3773 return POWER_DOMAIN_AUX_C_TBT;
3774 case AUX_CH_D:
3775 return POWER_DOMAIN_AUX_D_TBT;
3776 case AUX_CH_E:
3777 return POWER_DOMAIN_AUX_E_TBT;
3778 case AUX_CH_F:
3779 return POWER_DOMAIN_AUX_F_TBT;
3780 case AUX_CH_G:
3781 return POWER_DOMAIN_AUX_G_TBT;
3782 case AUX_CH_H:
3783 return POWER_DOMAIN_AUX_H_TBT;
3784 case AUX_CH_I:
3785 return POWER_DOMAIN_AUX_I_TBT;
3786 default:
3787 MISSING_CASE(dig_port->aux_ch);
3788 return POWER_DOMAIN_AUX_C_TBT;
3789 }
3790 }
3791
3792 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
3793}
3794
3795/*
3796 * Converts aux_ch to power_domain without caring about TBT ports for that use
3797 * intel_aux_power_domain()
3798 */
3799enum intel_display_power_domain
3800intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
3801{
3802 switch (aux_ch) {
3803 case AUX_CH_A:
3804 return POWER_DOMAIN_AUX_A;
3805 case AUX_CH_B:
3806 return POWER_DOMAIN_AUX_B;
3807 case AUX_CH_C:
3808 return POWER_DOMAIN_AUX_C;
3809 case AUX_CH_D:
3810 return POWER_DOMAIN_AUX_D;
3811 case AUX_CH_E:
3812 return POWER_DOMAIN_AUX_E;
3813 case AUX_CH_F:
3814 return POWER_DOMAIN_AUX_F;
3815 case AUX_CH_G:
3816 return POWER_DOMAIN_AUX_G;
3817 case AUX_CH_H:
3818 return POWER_DOMAIN_AUX_H;
3819 case AUX_CH_I:
3820 return POWER_DOMAIN_AUX_I;
3821 default:
3822 MISSING_CASE(aux_ch);
3823 return POWER_DOMAIN_AUX_A;
3824 }
3825}
3826
3827static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3828{
3829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3831 struct drm_encoder *encoder;
3832 enum pipe pipe = crtc->pipe;
3833 u64 mask;
3834 enum transcoder transcoder = crtc_state->cpu_transcoder;
3835
3836 if (!crtc_state->hw.active)
3837 return 0;
3838
3839 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
3840 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
3841 if (crtc_state->pch_pfit.enabled ||
3842 crtc_state->pch_pfit.force_thru)
3843 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
3844
3845 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
3846 crtc_state->uapi.encoder_mask) {
3847 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3848
3849 mask |= BIT_ULL(intel_encoder->power_domain);
3850 }
3851
3852 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
3853 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
3854
3855 if (crtc_state->shared_dpll)
3856 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
3857
3858 if (crtc_state->dsc.compression_enable)
3859 mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
3860
3861 return mask;
3862}
3863
3864static u64
3865modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3866{
3867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3868 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3869 enum intel_display_power_domain domain;
3870 u64 domains, new_domains, old_domains;
3871
3872 domains = get_crtc_power_domains(crtc_state);
3873
3874 new_domains = domains & ~crtc->enabled_power_domains.mask;
3875 old_domains = crtc->enabled_power_domains.mask & ~domains;
3876
3877 for_each_power_domain(domain, new_domains)
3878 intel_display_power_get_in_set(dev_priv,
3879 &crtc->enabled_power_domains,
3880 domain);
3881
3882 return old_domains;
3883}
3884
3885static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
3886 u64 domains)
3887{
3888 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
3889 &crtc->enabled_power_domains,
3890 domains);
3891}
3892
3893static void valleyview_crtc_enable(struct intel_atomic_state *state,
3894 struct intel_crtc *crtc)
3895{
3896 const struct intel_crtc_state *new_crtc_state =
3897 intel_atomic_get_new_crtc_state(state, crtc);
3898 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3899 enum pipe pipe = crtc->pipe;
3900
3901 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3902 return;
3903
3904 if (intel_crtc_has_dp_encoder(new_crtc_state))
3905 intel_dp_set_m_n(new_crtc_state, M1_N1);
3906
3907 intel_set_transcoder_timings(new_crtc_state);
3908 intel_set_pipe_src_size(new_crtc_state);
3909
3910 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3911 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
3912 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
3913 }
3914
3915 i9xx_set_pipeconf(new_crtc_state);
3916
3917 crtc->active = true;
3918
3919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3920
3921 intel_encoders_pre_pll_enable(state, crtc);
3922
3923 if (IS_CHERRYVIEW(dev_priv)) {
3924 chv_prepare_pll(crtc, new_crtc_state);
3925 chv_enable_pll(crtc, new_crtc_state);
3926 } else {
3927 vlv_prepare_pll(crtc, new_crtc_state);
3928 vlv_enable_pll(crtc, new_crtc_state);
3929 }
3930
3931 intel_encoders_pre_enable(state, crtc);
3932
3933 i9xx_pfit_enable(new_crtc_state);
3934
3935 intel_color_load_luts(new_crtc_state);
3936 intel_color_commit(new_crtc_state);
3937 /* update DSPCNTR to configure gamma for pipe bottom color */
3938 intel_disable_primary_plane(new_crtc_state);
3939
3940 dev_priv->display.initial_watermarks(state, crtc);
3941 intel_enable_pipe(new_crtc_state);
3942
3943 intel_crtc_vblank_on(new_crtc_state);
3944
3945 intel_encoders_enable(state, crtc);
3946}
3947
3948static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
3949{
3950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3951 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3952
3953 intel_de_write(dev_priv, FP0(crtc->pipe),
3954 crtc_state->dpll_hw_state.fp0);
3955 intel_de_write(dev_priv, FP1(crtc->pipe),
3956 crtc_state->dpll_hw_state.fp1);
3957}
3958
3959static void i9xx_crtc_enable(struct intel_atomic_state *state,
3960 struct intel_crtc *crtc)
3961{
3962 const struct intel_crtc_state *new_crtc_state =
3963 intel_atomic_get_new_crtc_state(state, crtc);
3964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3965 enum pipe pipe = crtc->pipe;
3966
3967 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3968 return;
3969
3970 i9xx_set_pll_dividers(new_crtc_state);
3971
3972 if (intel_crtc_has_dp_encoder(new_crtc_state))
3973 intel_dp_set_m_n(new_crtc_state, M1_N1);
3974
3975 intel_set_transcoder_timings(new_crtc_state);
3976 intel_set_pipe_src_size(new_crtc_state);
3977
3978 i9xx_set_pipeconf(new_crtc_state);
3979
3980 crtc->active = true;
3981
3982 if (DISPLAY_VER(dev_priv) != 2)
3983 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3984
3985 intel_encoders_pre_enable(state, crtc);
3986
3987 i9xx_enable_pll(crtc, new_crtc_state);
3988
3989 i9xx_pfit_enable(new_crtc_state);
3990
3991 intel_color_load_luts(new_crtc_state);
3992 intel_color_commit(new_crtc_state);
3993 /* update DSPCNTR to configure gamma for pipe bottom color */
3994 intel_disable_primary_plane(new_crtc_state);
3995
3996 if (dev_priv->display.initial_watermarks)
3997 dev_priv->display.initial_watermarks(state, crtc);
3998 else
3999 intel_update_watermarks(crtc);
4000 intel_enable_pipe(new_crtc_state);
4001
4002 intel_crtc_vblank_on(new_crtc_state);
4003
4004 intel_encoders_enable(state, crtc);
4005
4006 /* prevents spurious underruns */
4007 if (DISPLAY_VER(dev_priv) == 2)
4008 intel_wait_for_vblank(dev_priv, pipe);
4009}
4010
4011static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
4012{
4013 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4015
4016 if (!old_crtc_state->gmch_pfit.control)
4017 return;
4018
4019 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
4020
4021 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
4022 intel_de_read(dev_priv, PFIT_CONTROL));
4023 intel_de_write(dev_priv, PFIT_CONTROL, 0);
4024}
4025
4026static void i9xx_crtc_disable(struct intel_atomic_state *state,
4027 struct intel_crtc *crtc)
4028{
4029 struct intel_crtc_state *old_crtc_state =
4030 intel_atomic_get_old_crtc_state(state, crtc);
4031 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4032 enum pipe pipe = crtc->pipe;
4033
4034 /*
4035 * On gen2 planes are double buffered but the pipe isn't, so we must
4036 * wait for planes to fully turn off before disabling the pipe.
4037 */
4038 if (DISPLAY_VER(dev_priv) == 2)
4039 intel_wait_for_vblank(dev_priv, pipe);
4040
4041 intel_encoders_disable(state, crtc);
4042
4043 intel_crtc_vblank_off(old_crtc_state);
4044
4045 intel_disable_pipe(old_crtc_state);
4046
4047 i9xx_pfit_disable(old_crtc_state);
4048
4049 intel_encoders_post_disable(state, crtc);
4050
4051 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
4052 if (IS_CHERRYVIEW(dev_priv))
4053 chv_disable_pll(dev_priv, pipe);
4054 else if (IS_VALLEYVIEW(dev_priv))
4055 vlv_disable_pll(dev_priv, pipe);
4056 else
4057 i9xx_disable_pll(old_crtc_state);
4058 }
4059
4060 intel_encoders_post_pll_disable(state, crtc);
4061
4062 if (DISPLAY_VER(dev_priv) != 2)
4063 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4064
4065 if (!dev_priv->display.initial_watermarks)
4066 intel_update_watermarks(crtc);
4067
4068 /* clock the pipe down to 640x480@60 to potentially save power */
4069 if (IS_I830(dev_priv))
4070 i830_enable_pipe(dev_priv, pipe);
4071}
4072
4073static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
4074 struct drm_modeset_acquire_ctx *ctx)
4075{
4076 struct intel_encoder *encoder;
4077 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4078 struct intel_bw_state *bw_state =
4079 to_intel_bw_state(dev_priv->bw_obj.state);
4080 struct intel_cdclk_state *cdclk_state =
4081 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
4082 struct intel_dbuf_state *dbuf_state =
4083 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
4084 struct intel_crtc_state *crtc_state =
4085 to_intel_crtc_state(crtc->base.state);
4086 struct intel_plane *plane;
4087 struct drm_atomic_state *state;
4088 struct intel_crtc_state *temp_crtc_state;
4089 enum pipe pipe = crtc->pipe;
4090 int ret;
4091
4092 if (!crtc_state->hw.active)
4093 return;
4094
4095 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
4096 const struct intel_plane_state *plane_state =
4097 to_intel_plane_state(plane->base.state);
4098
4099 if (plane_state->uapi.visible)
4100 intel_plane_disable_noatomic(crtc, plane);
4101 }
4102
4103 state = drm_atomic_state_alloc(&dev_priv->drm);
4104 if (!state) {
4105 drm_dbg_kms(&dev_priv->drm,
4106 "failed to disable [CRTC:%d:%s], out of memory",
4107 crtc->base.base.id, crtc->base.name);
4108 return;
4109 }
4110
4111 state->acquire_ctx = ctx;
4112
4113 /* Everything's already locked, -EDEADLK can't happen. */
4114 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
4115 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
4116
4117 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
4118
4119 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
4120
4121 drm_atomic_state_put(state);
4122
4123 drm_dbg_kms(&dev_priv->drm,
4124 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
4125 crtc->base.base.id, crtc->base.name);
4126
4127 crtc->active = false;
4128 crtc->base.enabled = false;
4129
4130 drm_WARN_ON(&dev_priv->drm,
4131 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
4132 crtc_state->uapi.active = false;
4133 crtc_state->uapi.connector_mask = 0;
4134 crtc_state->uapi.encoder_mask = 0;
4135 intel_crtc_free_hw_state(crtc_state);
4136 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
4137
4138 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
4139 encoder->base.crtc = NULL;
4140
4141 intel_fbc_disable(crtc);
4142 intel_update_watermarks(crtc);
4143 intel_disable_shared_dpll(crtc_state);
4144
4145 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
4146
4147 dev_priv->active_pipes &= ~BIT(pipe);
4148 cdclk_state->min_cdclk[pipe] = 0;
4149 cdclk_state->min_voltage_level[pipe] = 0;
4150 cdclk_state->active_pipes &= ~BIT(pipe);
4151
4152 dbuf_state->active_pipes &= ~BIT(pipe);
4153
4154 bw_state->data_rate[pipe] = 0;
4155 bw_state->num_active_planes[pipe] = 0;
4156}
4157
4158/*
4159 * turn all crtc's off, but do not adjust state
4160 * This has to be paired with a call to intel_modeset_setup_hw_state.
4161 */
4162int intel_display_suspend(struct drm_device *dev)
4163{
4164 struct drm_i915_private *dev_priv = to_i915(dev);
4165 struct drm_atomic_state *state;
4166 int ret;
4167
4168 if (!HAS_DISPLAY(dev_priv))
4169 return 0;
4170
4171 state = drm_atomic_helper_suspend(dev);
4172 ret = PTR_ERR_OR_ZERO(state);
4173 if (ret)
4174 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4175 ret);
4176 else
4177 dev_priv->modeset_restore_state = state;
4178 return ret;
4179}
4180
4181void intel_encoder_destroy(struct drm_encoder *encoder)
4182{
4183 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4184
4185 drm_encoder_cleanup(encoder);
4186 kfree(intel_encoder);
4187}
4188
4189/* Cross check the actual hw state with our own modeset state tracking (and it's
4190 * internal consistency). */
4191static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
4192 struct drm_connector_state *conn_state)
4193{
4194 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4195 struct drm_i915_private *i915 = to_i915(connector->base.dev);
4196
4197 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
4198 connector->base.base.id, connector->base.name);
4199
4200 if (connector->get_hw_state(connector)) {
4201 struct intel_encoder *encoder = intel_attached_encoder(connector);
4202
4203 I915_STATE_WARN(!crtc_state,
4204 "connector enabled without attached crtc\n");
4205
4206 if (!crtc_state)
4207 return;
4208
4209 I915_STATE_WARN(!crtc_state->hw.active,
4210 "connector is active, but attached crtc isn't\n");
4211
4212 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
4213 return;
4214
4215 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
4216 "atomic encoder doesn't match attached encoder\n");
4217
4218 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
4219 "attached encoder crtc differs from connector crtc\n");
4220 } else {
4221 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
4222 "attached crtc is active, but connector isn't\n");
4223 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
4224 "best encoder set without crtc!\n");
4225 }
4226}
4227
4228bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
4229{
4230 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4232
4233 /* IPS only exists on ULT machines and is tied to pipe A. */
4234 if (!hsw_crtc_supports_ips(crtc))
4235 return false;
4236
4237 if (!dev_priv->params.enable_ips)
4238 return false;
4239
4240 if (crtc_state->pipe_bpp > 24)
4241 return false;
4242
4243 /*
4244 * We compare against max which means we must take
4245 * the increased cdclk requirement into account when
4246 * calculating the new cdclk.
4247 *
4248 * Should measure whether using a lower cdclk w/o IPS
4249 */
4250 if (IS_BROADWELL(dev_priv) &&
4251 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
4252 return false;
4253
4254 return true;
4255}
4256
4257static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
4258{
4259 struct drm_i915_private *dev_priv =
4260 to_i915(crtc_state->uapi.crtc->dev);
4261 struct intel_atomic_state *state =
4262 to_intel_atomic_state(crtc_state->uapi.state);
4263
4264 crtc_state->ips_enabled = false;
4265
4266 if (!hsw_crtc_state_ips_capable(crtc_state))
4267 return 0;
4268
4269 /*
4270 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4271 * enabled and disabled dynamically based on package C states,
4272 * user space can't make reliable use of the CRCs, so let's just
4273 * completely disable it.
4274 */
4275 if (crtc_state->crc_enabled)
4276 return 0;
4277
4278 /* IPS should be fine as long as at least one plane is enabled. */
4279 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
4280 return 0;
4281
4282 if (IS_BROADWELL(dev_priv)) {
4283 const struct intel_cdclk_state *cdclk_state;
4284
4285 cdclk_state = intel_atomic_get_cdclk_state(state);
4286 if (IS_ERR(cdclk_state))
4287 return PTR_ERR(cdclk_state);
4288
4289 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
4290 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
4291 return 0;
4292 }
4293
4294 crtc_state->ips_enabled = true;
4295
4296 return 0;
4297}
4298
4299static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
4300{
4301 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4302
4303 /* GDG double wide on either pipe, otherwise pipe A only */
4304 return DISPLAY_VER(dev_priv) < 4 &&
4305 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
4306}
4307
4308static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
4309{
4310 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
4311 struct drm_rect src;
4312
4313 /*
4314 * We only use IF-ID interlacing. If we ever use
4315 * PF-ID we'll need to adjust the pixel_rate here.
4316 */
4317
4318 if (!crtc_state->pch_pfit.enabled)
4319 return pixel_rate;
4320
4321 drm_rect_init(&src, 0, 0,
4322 crtc_state->pipe_src_w << 16,
4323 crtc_state->pipe_src_h << 16);
4324
4325 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
4326 pixel_rate);
4327}
4328
4329static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
4330 const struct drm_display_mode *timings)
4331{
4332 mode->hdisplay = timings->crtc_hdisplay;
4333 mode->htotal = timings->crtc_htotal;
4334 mode->hsync_start = timings->crtc_hsync_start;
4335 mode->hsync_end = timings->crtc_hsync_end;
4336
4337 mode->vdisplay = timings->crtc_vdisplay;
4338 mode->vtotal = timings->crtc_vtotal;
4339 mode->vsync_start = timings->crtc_vsync_start;
4340 mode->vsync_end = timings->crtc_vsync_end;
4341
4342 mode->flags = timings->flags;
4343 mode->type = DRM_MODE_TYPE_DRIVER;
4344
4345 mode->clock = timings->crtc_clock;
4346
4347 drm_mode_set_name(mode);
4348}
4349
4350static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
4351{
4352 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4353
4354 if (HAS_GMCH(dev_priv))
4355 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
4356 crtc_state->pixel_rate =
4357 crtc_state->hw.pipe_mode.crtc_clock;
4358 else
4359 crtc_state->pixel_rate =
4360 ilk_pipe_pixel_rate(crtc_state);
4361}
4362
4363static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
4364{
4365 struct drm_display_mode *mode = &crtc_state->hw.mode;
4366 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4367 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4368
4369 drm_mode_copy(pipe_mode, adjusted_mode);
4370
4371 if (crtc_state->bigjoiner) {
4372 /*
4373 * transcoder is programmed to the full mode,
4374 * but pipe timings are half of the transcoder mode
4375 */
4376 pipe_mode->crtc_hdisplay /= 2;
4377 pipe_mode->crtc_hblank_start /= 2;
4378 pipe_mode->crtc_hblank_end /= 2;
4379 pipe_mode->crtc_hsync_start /= 2;
4380 pipe_mode->crtc_hsync_end /= 2;
4381 pipe_mode->crtc_htotal /= 2;
4382 pipe_mode->crtc_clock /= 2;
4383 }
4384
4385 if (crtc_state->splitter.enable) {
4386 int n = crtc_state->splitter.link_count;
4387 int overlap = crtc_state->splitter.pixel_overlap;
4388
4389 /*
4390 * eDP MSO uses segment timings from EDID for transcoder
4391 * timings, but full mode for everything else.
4392 *
4393 * h_full = (h_segment - pixel_overlap) * link_count
4394 */
4395 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4396 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4397 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4398 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4399 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4400 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4401 pipe_mode->crtc_clock *= n;
4402
4403 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4404 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
4405 } else {
4406 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4407 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
4408 }
4409
4410 intel_crtc_compute_pixel_rate(crtc_state);
4411
4412 drm_mode_copy(mode, adjusted_mode);
4413 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
4414 mode->vdisplay = crtc_state->pipe_src_h;
4415}
4416
4417static void intel_encoder_get_config(struct intel_encoder *encoder,
4418 struct intel_crtc_state *crtc_state)
4419{
4420 encoder->get_config(encoder, crtc_state);
4421
4422 intel_crtc_readout_derived_state(crtc_state);
4423}
4424
4425static int intel_crtc_compute_config(struct intel_crtc *crtc,
4426 struct intel_crtc_state *pipe_config)
4427{
4428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4429 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
4430 int clock_limit = dev_priv->max_dotclk_freq;
4431
4432 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
4433
4434 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
4435 if (pipe_config->bigjoiner) {
4436 pipe_mode->crtc_clock /= 2;
4437 pipe_mode->crtc_hdisplay /= 2;
4438 pipe_mode->crtc_hblank_start /= 2;
4439 pipe_mode->crtc_hblank_end /= 2;
4440 pipe_mode->crtc_hsync_start /= 2;
4441 pipe_mode->crtc_hsync_end /= 2;
4442 pipe_mode->crtc_htotal /= 2;
4443 pipe_config->pipe_src_w /= 2;
4444 }
4445
4446 if (pipe_config->splitter.enable) {
4447 int n = pipe_config->splitter.link_count;
4448 int overlap = pipe_config->splitter.pixel_overlap;
4449
4450 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4451 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4452 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4453 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4454 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4455 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4456 pipe_mode->crtc_clock *= n;
4457 }
4458
4459 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4460
4461 if (DISPLAY_VER(dev_priv) < 4) {
4462 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
4463
4464 /*
4465 * Enable double wide mode when the dot clock
4466 * is > 90% of the (display) core speed.
4467 */
4468 if (intel_crtc_supports_double_wide(crtc) &&
4469 pipe_mode->crtc_clock > clock_limit) {
4470 clock_limit = dev_priv->max_dotclk_freq;
4471 pipe_config->double_wide = true;
4472 }
4473 }
4474
4475 if (pipe_mode->crtc_clock > clock_limit) {
4476 drm_dbg_kms(&dev_priv->drm,
4477 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
4478 pipe_mode->crtc_clock, clock_limit,
4479 yesno(pipe_config->double_wide));
4480 return -EINVAL;
4481 }
4482
4483 /*
4484 * Pipe horizontal size must be even in:
4485 * - DVO ganged mode
4486 * - LVDS dual channel mode
4487 * - Double wide pipe
4488 */
4489 if (pipe_config->pipe_src_w & 1) {
4490 if (pipe_config->double_wide) {
4491 drm_dbg_kms(&dev_priv->drm,
4492 "Odd pipe source width not supported with double wide pipe\n");
4493 return -EINVAL;
4494 }
4495
4496 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4497 intel_is_dual_link_lvds(dev_priv)) {
4498 drm_dbg_kms(&dev_priv->drm,
4499 "Odd pipe source width not supported with dual link LVDS\n");
4500 return -EINVAL;
4501 }
4502 }
4503
4504 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4505 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4506 */
4507 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
4508 pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
4509 return -EINVAL;
4510
4511 intel_crtc_compute_pixel_rate(pipe_config);
4512
4513 if (pipe_config->has_pch_encoder)
4514 return ilk_fdi_compute_config(crtc, pipe_config);
4515
4516 return 0;
4517}
4518
4519static void
4520intel_reduce_m_n_ratio(u32 *num, u32 *den)
4521{
4522 while (*num > DATA_LINK_M_N_MASK ||
4523 *den > DATA_LINK_M_N_MASK) {
4524 *num >>= 1;
4525 *den >>= 1;
4526 }
4527}
4528
4529static void compute_m_n(unsigned int m, unsigned int n,
4530 u32 *ret_m, u32 *ret_n,
4531 bool constant_n)
4532{
4533 /*
4534 * Several DP dongles in particular seem to be fussy about
4535 * too large link M/N values. Give N value as 0x8000 that
4536 * should be acceptable by specific devices. 0x8000 is the
4537 * specified fixed N value for asynchronous clock mode,
4538 * which the devices expect also in synchronous clock mode.
4539 */
4540 if (constant_n)
4541 *ret_n = DP_LINK_CONSTANT_N_VALUE;
4542 else
4543 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4544
4545 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
4546 intel_reduce_m_n_ratio(ret_m, ret_n);
4547}
4548
4549void
4550intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
4551 int pixel_clock, int link_clock,
4552 struct intel_link_m_n *m_n,
4553 bool constant_n, bool fec_enable)
4554{
4555 u32 data_clock = bits_per_pixel * pixel_clock;
4556
4557 if (fec_enable)
4558 data_clock = intel_dp_mode_to_fec_clock(data_clock);
4559
4560 m_n->tu = 64;
4561 compute_m_n(data_clock,
4562 link_clock * nlanes * 8,
4563 &m_n->gmch_m, &m_n->gmch_n,
4564 constant_n);
4565
4566 compute_m_n(pixel_clock, link_clock,
4567 &m_n->link_m, &m_n->link_n,
4568 constant_n);
4569}
4570
4571static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
4572{
4573 /*
4574 * There may be no VBT; and if the BIOS enabled SSC we can
4575 * just keep using it to avoid unnecessary flicker. Whereas if the
4576 * BIOS isn't using it, don't assume it will work even if the VBT
4577 * indicates as much.
4578 */
4579 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
4580 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
4581 PCH_DREF_CONTROL) &
4582 DREF_SSC1_ENABLE;
4583
4584 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
4585 drm_dbg_kms(&dev_priv->drm,
4586 "SSC %s by BIOS, overriding VBT which says %s\n",
4587 enableddisabled(bios_lvds_use_ssc),
4588 enableddisabled(dev_priv->vbt.lvds_use_ssc));
4589 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
4590 }
4591 }
4592}
4593
4594static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4595 const struct intel_link_m_n *m_n)
4596{
4597 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4599 enum pipe pipe = crtc->pipe;
4600
4601 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
4602 TU_SIZE(m_n->tu) | m_n->gmch_m);
4603 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4604 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4605 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4606}
4607
4608static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
4609 enum transcoder transcoder)
4610{
4611 if (IS_HASWELL(dev_priv))
4612 return transcoder == TRANSCODER_EDP;
4613
4614 /*
4615 * Strictly speaking some registers are available before
4616 * gen7, but we only support DRRS on gen7+
4617 */
4618 return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
4619}
4620
4621static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4622 const struct intel_link_m_n *m_n,
4623 const struct intel_link_m_n *m2_n2)
4624{
4625 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4627 enum pipe pipe = crtc->pipe;
4628 enum transcoder transcoder = crtc_state->cpu_transcoder;
4629
4630 if (DISPLAY_VER(dev_priv) >= 5) {
4631 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
4632 TU_SIZE(m_n->tu) | m_n->gmch_m);
4633 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
4634 m_n->gmch_n);
4635 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
4636 m_n->link_m);
4637 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
4638 m_n->link_n);
4639 /*
4640 * M2_N2 registers are set only if DRRS is supported
4641 * (to make sure the registers are not unnecessarily accessed).
4642 */
4643 if (m2_n2 && crtc_state->has_drrs &&
4644 transcoder_has_m2_n2(dev_priv, transcoder)) {
4645 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
4646 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
4647 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
4648 m2_n2->gmch_n);
4649 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
4650 m2_n2->link_m);
4651 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
4652 m2_n2->link_n);
4653 }
4654 } else {
4655 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
4656 TU_SIZE(m_n->tu) | m_n->gmch_m);
4657 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4658 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
4659 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
4660 }
4661}
4662
4663void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
4664{
4665 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
4666 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4667
4668 if (m_n == M1_N1) {
4669 dp_m_n = &crtc_state->dp_m_n;
4670 dp_m2_n2 = &crtc_state->dp_m2_n2;
4671 } else if (m_n == M2_N2) {
4672
4673 /*
4674 * M2_N2 registers are not supported. Hence m2_n2 divider value
4675 * needs to be programmed into M1_N1.
4676 */
4677 dp_m_n = &crtc_state->dp_m2_n2;
4678 } else {
4679 drm_err(&i915->drm, "Unsupported divider value\n");
4680 return;
4681 }
4682
4683 if (crtc_state->has_pch_encoder)
4684 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
4685 else
4686 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
4687}
4688
4689static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
4690{
4691 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4692 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4693 enum pipe pipe = crtc->pipe;
4694 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4695 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4696 u32 crtc_vtotal, crtc_vblank_end;
4697 int vsyncshift = 0;
4698
4699 /* We need to be careful not to changed the adjusted mode, for otherwise
4700 * the hw state checker will get angry at the mismatch. */
4701 crtc_vtotal = adjusted_mode->crtc_vtotal;
4702 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4703
4704 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4705 /* the chip adds 2 halflines automatically */
4706 crtc_vtotal -= 1;
4707 crtc_vblank_end -= 1;
4708
4709 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4710 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
4711 else
4712 vsyncshift = adjusted_mode->crtc_hsync_start -
4713 adjusted_mode->crtc_htotal / 2;
4714 if (vsyncshift < 0)
4715 vsyncshift += adjusted_mode->crtc_htotal;
4716 }
4717
4718 if (DISPLAY_VER(dev_priv) > 3)
4719 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
4720 vsyncshift);
4721
4722 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
4723 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
4724 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
4725 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
4726 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
4727 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
4728
4729 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
4730 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
4731 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
4732 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
4733 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
4734 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
4735
4736 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4737 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4738 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4739 * bits. */
4740 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
4741 (pipe == PIPE_B || pipe == PIPE_C))
4742 intel_de_write(dev_priv, VTOTAL(pipe),
4743 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
4744
4745}
4746
4747static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
4748{
4749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4751 enum pipe pipe = crtc->pipe;
4752
4753 /* pipesrc controls the size that is scaled from, which should
4754 * always be the user's requested size.
4755 */
4756 intel_de_write(dev_priv, PIPESRC(pipe),
4757 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
4758}
4759
4760static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
4761{
4762 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4763 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4764
4765 if (DISPLAY_VER(dev_priv) == 2)
4766 return false;
4767
4768 if (DISPLAY_VER(dev_priv) >= 9 ||
4769 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4770 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
4771 else
4772 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
4773}
4774
4775static void intel_get_transcoder_timings(struct intel_crtc *crtc,
4776 struct intel_crtc_state *pipe_config)
4777{
4778 struct drm_device *dev = crtc->base.dev;
4779 struct drm_i915_private *dev_priv = to_i915(dev);
4780 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4781 u32 tmp;
4782
4783 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
4784 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4785 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4786
4787 if (!transcoder_is_dsi(cpu_transcoder)) {
4788 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
4789 pipe_config->hw.adjusted_mode.crtc_hblank_start =
4790 (tmp & 0xffff) + 1;
4791 pipe_config->hw.adjusted_mode.crtc_hblank_end =
4792 ((tmp >> 16) & 0xffff) + 1;
4793 }
4794 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
4795 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4796 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4797
4798 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
4799 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4800 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4801
4802 if (!transcoder_is_dsi(cpu_transcoder)) {
4803 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
4804 pipe_config->hw.adjusted_mode.crtc_vblank_start =
4805 (tmp & 0xffff) + 1;
4806 pipe_config->hw.adjusted_mode.crtc_vblank_end =
4807 ((tmp >> 16) & 0xffff) + 1;
4808 }
4809 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
4810 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4811 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4812
4813 if (intel_pipe_is_interlaced(pipe_config)) {
4814 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4815 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
4816 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
4817 }
4818}
4819
4820static void intel_get_pipe_src_size(struct intel_crtc *crtc,
4821 struct intel_crtc_state *pipe_config)
4822{
4823 struct drm_device *dev = crtc->base.dev;
4824 struct drm_i915_private *dev_priv = to_i915(dev);
4825 u32 tmp;
4826
4827 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
4828 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4829 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4830}
4831
4832static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
4833{
4834 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4836 u32 pipeconf;
4837
4838 pipeconf = 0;
4839
4840 /* we keep both pipes enabled on 830 */
4841 if (IS_I830(dev_priv))
4842 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
4843
4844 if (crtc_state->double_wide)
4845 pipeconf |= PIPECONF_DOUBLE_WIDE;
4846
4847 /* only g4x and later have fancy bpc/dither controls */
4848 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4849 IS_CHERRYVIEW(dev_priv)) {
4850 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4851 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
4852 pipeconf |= PIPECONF_DITHER_EN |
4853 PIPECONF_DITHER_TYPE_SP;
4854
4855 switch (crtc_state->pipe_bpp) {
4856 case 18:
4857 pipeconf |= PIPECONF_6BPC;
4858 break;
4859 case 24:
4860 pipeconf |= PIPECONF_8BPC;
4861 break;
4862 case 30:
4863 pipeconf |= PIPECONF_10BPC;
4864 break;
4865 default:
4866 /* Case prevented by intel_choose_pipe_bpp_dither. */
4867 BUG();
4868 }
4869 }
4870
4871 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
4872 if (DISPLAY_VER(dev_priv) < 4 ||
4873 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4874 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4875 else
4876 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
4877 } else {
4878 pipeconf |= PIPECONF_PROGRESSIVE;
4879 }
4880
4881 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
4882 crtc_state->limited_color_range)
4883 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4884
4885 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
4886
4887 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
4888
4889 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
4890 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
4891}
4892
4893static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
4894{
4895 if (IS_I830(dev_priv))
4896 return false;
4897
4898 return DISPLAY_VER(dev_priv) >= 4 ||
4899 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
4900}
4901
4902static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
4903{
4904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4906 u32 tmp;
4907
4908 if (!i9xx_has_pfit(dev_priv))
4909 return;
4910
4911 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
4912 if (!(tmp & PFIT_ENABLE))
4913 return;
4914
4915 /* Check whether the pfit is attached to our pipe. */
4916 if (DISPLAY_VER(dev_priv) < 4) {
4917 if (crtc->pipe != PIPE_B)
4918 return;
4919 } else {
4920 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4921 return;
4922 }
4923
4924 crtc_state->gmch_pfit.control = tmp;
4925 crtc_state->gmch_pfit.pgm_ratios =
4926 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
4927}
4928
4929static void vlv_crtc_clock_get(struct intel_crtc *crtc,
4930 struct intel_crtc_state *pipe_config)
4931{
4932 struct drm_device *dev = crtc->base.dev;
4933 struct drm_i915_private *dev_priv = to_i915(dev);
4934 enum pipe pipe = crtc->pipe;
4935 struct dpll clock;
4936 u32 mdiv;
4937 int refclk = 100000;
4938
4939 /* In case of DSI, DPLL will not be used */
4940 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4941 return;
4942
4943 vlv_dpio_get(dev_priv);
4944 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
4945 vlv_dpio_put(dev_priv);
4946
4947 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
4948 clock.m2 = mdiv & DPIO_M2DIV_MASK;
4949 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
4950 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
4951 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
4952
4953 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
4954}
4955
4956static void chv_crtc_clock_get(struct intel_crtc *crtc,
4957 struct intel_crtc_state *pipe_config)
4958{
4959 struct drm_device *dev = crtc->base.dev;
4960 struct drm_i915_private *dev_priv = to_i915(dev);
4961 enum pipe pipe = crtc->pipe;
4962 enum dpio_channel port = vlv_pipe_to_channel(pipe);
4963 struct dpll clock;
4964 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
4965 int refclk = 100000;
4966
4967 /* In case of DSI, DPLL will not be used */
4968 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4969 return;
4970
4971 vlv_dpio_get(dev_priv);
4972 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
4973 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
4974 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
4975 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
4976 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
4977 vlv_dpio_put(dev_priv);
4978
4979 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
4980 clock.m2 = (pll_dw0 & 0xff) << 22;
4981 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
4982 clock.m2 |= pll_dw2 & 0x3fffff;
4983 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
4984 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
4985 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
4986
4987 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
4988}
4989
4990static enum intel_output_format
4991bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
4992{
4993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4994 u32 tmp;
4995
4996 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
4997
4998 if (tmp & PIPEMISC_YUV420_ENABLE) {
4999 /* We support 4:2:0 in full blend mode only */
5000 drm_WARN_ON(&dev_priv->drm,
5001 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
5002
5003 return INTEL_OUTPUT_FORMAT_YCBCR420;
5004 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
5005 return INTEL_OUTPUT_FORMAT_YCBCR444;
5006 } else {
5007 return INTEL_OUTPUT_FORMAT_RGB;
5008 }
5009}
5010
5011static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
5012{
5013 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5014 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5016 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
5017 u32 tmp;
5018
5019 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
5020
5021 if (tmp & DISPPLANE_GAMMA_ENABLE)
5022 crtc_state->gamma_enable = true;
5023
5024 if (!HAS_GMCH(dev_priv) &&
5025 tmp & DISPPLANE_PIPE_CSC_ENABLE)
5026 crtc_state->csc_enable = true;
5027}
5028
5029static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5030 struct intel_crtc_state *pipe_config)
5031{
5032 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5033 enum intel_display_power_domain power_domain;
5034 intel_wakeref_t wakeref;
5035 u32 tmp;
5036 bool ret;
5037
5038 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
5039 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
5040 if (!wakeref)
5041 return false;
5042
5043 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
5044 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5045 pipe_config->shared_dpll = NULL;
5046
5047 ret = false;
5048
5049 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
5050 if (!(tmp & PIPECONF_ENABLE))
5051 goto out;
5052
5053 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5054 IS_CHERRYVIEW(dev_priv)) {
5055 switch (tmp & PIPECONF_BPC_MASK) {
5056 case PIPECONF_6BPC:
5057 pipe_config->pipe_bpp = 18;
5058 break;
5059 case PIPECONF_8BPC:
5060 pipe_config->pipe_bpp = 24;
5061 break;
5062 case PIPECONF_10BPC:
5063 pipe_config->pipe_bpp = 30;
5064 break;
5065 default:
5066 break;
5067 }
5068 }
5069
5070 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5071 (tmp & PIPECONF_COLOR_RANGE_SELECT))
5072 pipe_config->limited_color_range = true;
5073
5074 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
5075 PIPECONF_GAMMA_MODE_SHIFT;
5076
5077 if (IS_CHERRYVIEW(dev_priv))
5078 pipe_config->cgm_mode = intel_de_read(dev_priv,
5079 CGM_PIPE_MODE(crtc->pipe));
5080
5081 i9xx_get_pipe_color_config(pipe_config);
5082 intel_color_get_config(pipe_config);
5083
5084 if (DISPLAY_VER(dev_priv) < 4)
5085 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5086
5087 intel_get_transcoder_timings(crtc, pipe_config);
5088 intel_get_pipe_src_size(crtc, pipe_config);
5089
5090 i9xx_get_pfit_config(pipe_config);
5091
5092 if (DISPLAY_VER(dev_priv) >= 4) {
5093 /* No way to read it out on pipes B and C */
5094 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
5095 tmp = dev_priv->chv_dpll_md[crtc->pipe];
5096 else
5097 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
5098 pipe_config->pixel_multiplier =
5099 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5100 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5101 pipe_config->dpll_hw_state.dpll_md = tmp;
5102 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
5103 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
5104 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
5105 pipe_config->pixel_multiplier =
5106 ((tmp & SDVO_MULTIPLIER_MASK)
5107 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5108 } else {
5109 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5110 * port and will be fixed up in the encoder->get_config
5111 * function. */
5112 pipe_config->pixel_multiplier = 1;
5113 }
5114 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
5115 DPLL(crtc->pipe));
5116 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
5117 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
5118 FP0(crtc->pipe));
5119 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
5120 FP1(crtc->pipe));
5121 } else {
5122 /* Mask out read-only status bits. */
5123 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5124 DPLL_PORTC_READY_MASK |
5125 DPLL_PORTB_READY_MASK);
5126 }
5127
5128 if (IS_CHERRYVIEW(dev_priv))
5129 chv_crtc_clock_get(crtc, pipe_config);
5130 else if (IS_VALLEYVIEW(dev_priv))
5131 vlv_crtc_clock_get(crtc, pipe_config);
5132 else
5133 i9xx_crtc_clock_get(crtc, pipe_config);
5134
5135 /*
5136 * Normally the dotclock is filled in by the encoder .get_config()
5137 * but in case the pipe is enabled w/o any ports we need a sane
5138 * default.
5139 */
5140 pipe_config->hw.adjusted_mode.crtc_clock =
5141 pipe_config->port_clock / pipe_config->pixel_multiplier;
5142
5143 ret = true;
5144
5145out:
5146 intel_display_power_put(dev_priv, power_domain, wakeref);
5147
5148 return ret;
5149}
5150
5151static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
5152{
5153 struct intel_encoder *encoder;
5154 int i;
5155 u32 val, final;
5156 bool has_lvds = false;
5157 bool has_cpu_edp = false;
5158 bool has_panel = false;
5159 bool has_ck505 = false;
5160 bool can_ssc = false;
5161 bool using_ssc_source = false;
5162
5163 /* We need to take the global config into account */
5164 for_each_intel_encoder(&dev_priv->drm, encoder) {
5165 switch (encoder->type) {
5166 case INTEL_OUTPUT_LVDS:
5167 has_panel = true;
5168 has_lvds = true;
5169 break;
5170 case INTEL_OUTPUT_EDP:
5171 has_panel = true;
5172 if (encoder->port == PORT_A)
5173 has_cpu_edp = true;
5174 break;
5175 default:
5176 break;
5177 }
5178 }
5179
5180 if (HAS_PCH_IBX(dev_priv)) {
5181 has_ck505 = dev_priv->vbt.display_clock_mode;
5182 can_ssc = has_ck505;
5183 } else {
5184 has_ck505 = false;
5185 can_ssc = true;
5186 }
5187
5188 /* Check if any DPLLs are using the SSC source */
5189 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
5190 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
5191
5192 if (!(temp & DPLL_VCO_ENABLE))
5193 continue;
5194
5195 if ((temp & PLL_REF_INPUT_MASK) ==
5196 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5197 using_ssc_source = true;
5198 break;
5199 }
5200 }
5201
5202 drm_dbg_kms(&dev_priv->drm,
5203 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
5204 has_panel, has_lvds, has_ck505, using_ssc_source);
5205
5206 /* Ironlake: try to setup display ref clock before DPLL
5207 * enabling. This is only under driver's control after
5208 * PCH B stepping, previous chipset stepping should be
5209 * ignoring this setting.
5210 */
5211 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
5212
5213 /* As we must carefully and slowly disable/enable each source in turn,
5214 * compute the final state we want first and check if we need to
5215 * make any changes at all.
5216 */
5217 final = val;
5218 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5219 if (has_ck505)
5220 final |= DREF_NONSPREAD_CK505_ENABLE;
5221 else
5222 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5223
5224 final &= ~DREF_SSC_SOURCE_MASK;
5225 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5226 final &= ~DREF_SSC1_ENABLE;
5227
5228 if (has_panel) {
5229 final |= DREF_SSC_SOURCE_ENABLE;
5230
5231 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5232 final |= DREF_SSC1_ENABLE;
5233
5234 if (has_cpu_edp) {
5235 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5236 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5237 else
5238 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5239 } else
5240 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5241 } else if (using_ssc_source) {
5242 final |= DREF_SSC_SOURCE_ENABLE;
5243 final |= DREF_SSC1_ENABLE;
5244 }
5245
5246 if (final == val)
5247 return;
5248
5249 /* Always enable nonspread source */
5250 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5251
5252 if (has_ck505)
5253 val |= DREF_NONSPREAD_CK505_ENABLE;
5254 else
5255 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5256
5257 if (has_panel) {
5258 val &= ~DREF_SSC_SOURCE_MASK;
5259 val |= DREF_SSC_SOURCE_ENABLE;
5260
5261 /* SSC must be turned on before enabling the CPU output */
5262 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5263 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
5264 val |= DREF_SSC1_ENABLE;
5265 } else
5266 val &= ~DREF_SSC1_ENABLE;
5267
5268 /* Get SSC going before enabling the outputs */
5269 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5270 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5271 udelay(200);
5272
5273 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5274
5275 /* Enable CPU source on CPU attached eDP */
5276 if (has_cpu_edp) {
5277 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5278 drm_dbg_kms(&dev_priv->drm,
5279 "Using SSC on eDP\n");
5280 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5281 } else
5282 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5283 } else
5284 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5285
5286 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5287 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5288 udelay(200);
5289 } else {
5290 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
5291
5292 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5293
5294 /* Turn off CPU output */
5295 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5296
5297 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5298 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5299 udelay(200);
5300
5301 if (!using_ssc_source) {
5302 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
5303
5304 /* Turn off the SSC source */
5305 val &= ~DREF_SSC_SOURCE_MASK;
5306 val |= DREF_SSC_SOURCE_DISABLE;
5307
5308 /* Turn off SSC1 */
5309 val &= ~DREF_SSC1_ENABLE;
5310
5311 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5312 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5313 udelay(200);
5314 }
5315 }
5316
5317 BUG_ON(val != final);
5318}
5319
5320static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5321{
5322 u32 tmp;
5323
5324 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5325 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5326 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5327
5328 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5329 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5330 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
5331
5332 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5333 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5334 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5335
5336 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5337 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5338 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
5339}
5340
5341/* WaMPhyProgramming:hsw */
5342static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5343{
5344 u32 tmp;
5345
5346 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5347 tmp &= ~(0xFF << 24);
5348 tmp |= (0x12 << 24);
5349 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5350
5351 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5352 tmp |= (1 << 11);
5353 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5354
5355 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5356 tmp |= (1 << 11);
5357 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5358
5359 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5360 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5361 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5362
5363 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5364 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5365 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5366
5367 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5368 tmp &= ~(7 << 13);
5369 tmp |= (5 << 13);
5370 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5371
5372 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5373 tmp &= ~(7 << 13);
5374 tmp |= (5 << 13);
5375 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5376
5377 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5378 tmp &= ~0xFF;
5379 tmp |= 0x1C;
5380 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5381
5382 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5383 tmp &= ~0xFF;
5384 tmp |= 0x1C;
5385 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5386
5387 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5388 tmp &= ~(0xFF << 16);
5389 tmp |= (0x1C << 16);
5390 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5391
5392 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5393 tmp &= ~(0xFF << 16);
5394 tmp |= (0x1C << 16);
5395 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5396
5397 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5398 tmp |= (1 << 27);
5399 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5400
5401 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5402 tmp |= (1 << 27);
5403 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5404
5405 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5406 tmp &= ~(0xF << 28);
5407 tmp |= (4 << 28);
5408 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5409
5410 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5411 tmp &= ~(0xF << 28);
5412 tmp |= (4 << 28);
5413 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5414}
5415
5416/* Implements 3 different sequences from BSpec chapter "Display iCLK
5417 * Programming" based on the parameters passed:
5418 * - Sequence to enable CLKOUT_DP
5419 * - Sequence to enable CLKOUT_DP without spread
5420 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5421 */
5422static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
5423 bool with_spread, bool with_fdi)
5424{
5425 u32 reg, tmp;
5426
5427 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
5428 "FDI requires downspread\n"))
5429 with_spread = true;
5430 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
5431 with_fdi, "LP PCH doesn't have FDI\n"))
5432 with_fdi = false;
5433
5434 mutex_lock(&dev_priv->sb_lock);
5435
5436 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5437 tmp &= ~SBI_SSCCTL_DISABLE;
5438 tmp |= SBI_SSCCTL_PATHALT;
5439 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5440
5441 udelay(24);
5442
5443 if (with_spread) {
5444 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5445 tmp &= ~SBI_SSCCTL_PATHALT;
5446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5447
5448 if (with_fdi) {
5449 lpt_reset_fdi_mphy(dev_priv);
5450 lpt_program_fdi_mphy(dev_priv);
5451 }
5452 }
5453
5454 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5455 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5456 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5457 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5458
5459 mutex_unlock(&dev_priv->sb_lock);
5460}
5461
5462/* Sequence to disable CLKOUT_DP */
5463void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
5464{
5465 u32 reg, tmp;
5466
5467 mutex_lock(&dev_priv->sb_lock);
5468
5469 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5470 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5471 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5472 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5473
5474 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5475 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5476 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5477 tmp |= SBI_SSCCTL_PATHALT;
5478 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5479 udelay(32);
5480 }
5481 tmp |= SBI_SSCCTL_DISABLE;
5482 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5483 }
5484
5485 mutex_unlock(&dev_priv->sb_lock);
5486}
5487
5488#define BEND_IDX(steps) ((50 + (steps)) / 5)
5489
5490static const u16 sscdivintphase[] = {
5491 [BEND_IDX( 50)] = 0x3B23,
5492 [BEND_IDX( 45)] = 0x3B23,
5493 [BEND_IDX( 40)] = 0x3C23,
5494 [BEND_IDX( 35)] = 0x3C23,
5495 [BEND_IDX( 30)] = 0x3D23,
5496 [BEND_IDX( 25)] = 0x3D23,
5497 [BEND_IDX( 20)] = 0x3E23,
5498 [BEND_IDX( 15)] = 0x3E23,
5499 [BEND_IDX( 10)] = 0x3F23,
5500 [BEND_IDX( 5)] = 0x3F23,
5501 [BEND_IDX( 0)] = 0x0025,
5502 [BEND_IDX( -5)] = 0x0025,
5503 [BEND_IDX(-10)] = 0x0125,
5504 [BEND_IDX(-15)] = 0x0125,
5505 [BEND_IDX(-20)] = 0x0225,
5506 [BEND_IDX(-25)] = 0x0225,
5507 [BEND_IDX(-30)] = 0x0325,
5508 [BEND_IDX(-35)] = 0x0325,
5509 [BEND_IDX(-40)] = 0x0425,
5510 [BEND_IDX(-45)] = 0x0425,
5511 [BEND_IDX(-50)] = 0x0525,
5512};
5513
5514/*
5515 * Bend CLKOUT_DP
5516 * steps -50 to 50 inclusive, in steps of 5
5517 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
5518 * change in clock period = -(steps / 10) * 5.787 ps
5519 */
5520static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
5521{
5522 u32 tmp;
5523 int idx = BEND_IDX(steps);
5524
5525 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
5526 return;
5527
5528 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
5529 return;
5530
5531 mutex_lock(&dev_priv->sb_lock);
5532
5533 if (steps % 10 != 0)
5534 tmp = 0xAAAAAAAB;
5535 else
5536 tmp = 0x00000000;
5537 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
5538
5539 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
5540 tmp &= 0xffff0000;
5541 tmp |= sscdivintphase[idx];
5542 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
5543
5544 mutex_unlock(&dev_priv->sb_lock);
5545}
5546
5547#undef BEND_IDX
5548
5549static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
5550{
5551 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5552 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
5553
5554 if ((ctl & SPLL_PLL_ENABLE) == 0)
5555 return false;
5556
5557 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
5558 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5559 return true;
5560
5561 if (IS_BROADWELL(dev_priv) &&
5562 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
5563 return true;
5564
5565 return false;
5566}
5567
5568static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
5569 enum intel_dpll_id id)
5570{
5571 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5572 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
5573
5574 if ((ctl & WRPLL_PLL_ENABLE) == 0)
5575 return false;
5576
5577 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
5578 return true;
5579
5580 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
5581 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
5582 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5583 return true;
5584
5585 return false;
5586}
5587
5588static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
5589{
5590 struct intel_encoder *encoder;
5591 bool has_fdi = false;
5592
5593 for_each_intel_encoder(&dev_priv->drm, encoder) {
5594 switch (encoder->type) {
5595 case INTEL_OUTPUT_ANALOG:
5596 has_fdi = true;
5597 break;
5598 default:
5599 break;
5600 }
5601 }
5602
5603 /*
5604 * The BIOS may have decided to use the PCH SSC
5605 * reference so we must not disable it until the
5606 * relevant PLLs have stopped relying on it. We'll
5607 * just leave the PCH SSC reference enabled in case
5608 * any active PLL is using it. It will get disabled
5609 * after runtime suspend if we don't have FDI.
5610 *
5611 * TODO: Move the whole reference clock handling
5612 * to the modeset sequence proper so that we can
5613 * actually enable/disable/reconfigure these things
5614 * safely. To do that we need to introduce a real
5615 * clock hierarchy. That would also allow us to do
5616 * clock bending finally.
5617 */
5618 dev_priv->pch_ssc_use = 0;
5619
5620 if (spll_uses_pch_ssc(dev_priv)) {
5621 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
5622 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
5623 }
5624
5625 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
5626 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
5627 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
5628 }
5629
5630 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
5631 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
5632 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
5633 }
5634
5635 if (dev_priv->pch_ssc_use)
5636 return;
5637
5638 if (has_fdi) {
5639 lpt_bend_clkout_dp(dev_priv, 0);
5640 lpt_enable_clkout_dp(dev_priv, true, true);
5641 } else {
5642 lpt_disable_clkout_dp(dev_priv);
5643 }
5644}
5645
5646/*
5647 * Initialize reference clocks when the driver loads
5648 */
5649void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
5650{
5651 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
5652 ilk_init_pch_refclk(dev_priv);
5653 else if (HAS_PCH_LPT(dev_priv))
5654 lpt_init_pch_refclk(dev_priv);
5655}
5656
5657static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
5658{
5659 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5660 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5661 enum pipe pipe = crtc->pipe;
5662 u32 val;
5663
5664 val = 0;
5665
5666 switch (crtc_state->pipe_bpp) {
5667 case 18:
5668 val |= PIPECONF_6BPC;
5669 break;
5670 case 24:
5671 val |= PIPECONF_8BPC;
5672 break;
5673 case 30:
5674 val |= PIPECONF_10BPC;
5675 break;
5676 case 36:
5677 val |= PIPECONF_12BPC;
5678 break;
5679 default:
5680 /* Case prevented by intel_choose_pipe_bpp_dither. */
5681 BUG();
5682 }
5683
5684 if (crtc_state->dither)
5685 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5686
5687 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5688 val |= PIPECONF_INTERLACED_ILK;
5689 else
5690 val |= PIPECONF_PROGRESSIVE;
5691
5692 /*
5693 * This would end up with an odd purple hue over
5694 * the entire display. Make sure we don't do it.
5695 */
5696 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
5697 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
5698
5699 if (crtc_state->limited_color_range &&
5700 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
5701 val |= PIPECONF_COLOR_RANGE_SELECT;
5702
5703 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5704 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
5705
5706 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
5707
5708 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
5709
5710 intel_de_write(dev_priv, PIPECONF(pipe), val);
5711 intel_de_posting_read(dev_priv, PIPECONF(pipe));
5712}
5713
5714static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
5715{
5716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5718 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5719 u32 val = 0;
5720
5721 if (IS_HASWELL(dev_priv) && crtc_state->dither)
5722 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5723
5724 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5725 val |= PIPECONF_INTERLACED_ILK;
5726 else
5727 val |= PIPECONF_PROGRESSIVE;
5728
5729 if (IS_HASWELL(dev_priv) &&
5730 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5731 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
5732
5733 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
5734 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
5735}
5736
5737static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
5738{
5739 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5740 const struct intel_crtc_scaler_state *scaler_state =
5741 &crtc_state->scaler_state;
5742
5743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5744 u32 val = 0;
5745 int i;
5746
5747 switch (crtc_state->pipe_bpp) {
5748 case 18:
5749 val |= PIPEMISC_6_BPC;
5750 break;
5751 case 24:
5752 val |= PIPEMISC_8_BPC;
5753 break;
5754 case 30:
5755 val |= PIPEMISC_10_BPC;
5756 break;
5757 case 36:
5758 /* Port output 12BPC defined for ADLP+ */
5759 if (DISPLAY_VER(dev_priv) > 12)
5760 val |= PIPEMISC_12_BPC_ADLP;
5761 break;
5762 default:
5763 MISSING_CASE(crtc_state->pipe_bpp);
5764 break;
5765 }
5766
5767 if (crtc_state->dither)
5768 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5769
5770 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
5771 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
5772 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
5773
5774 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5775 val |= PIPEMISC_YUV420_ENABLE |
5776 PIPEMISC_YUV420_MODE_FULL_BLEND;
5777
5778 if (DISPLAY_VER(dev_priv) >= 11 &&
5779 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
5780 BIT(PLANE_CURSOR))) == 0)
5781 val |= PIPEMISC_HDR_MODE_PRECISION;
5782
5783 if (DISPLAY_VER(dev_priv) >= 12)
5784 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
5785
5786 if (IS_ALDERLAKE_P(dev_priv)) {
5787 bool scaler_in_use = false;
5788
5789 for (i = 0; i < crtc->num_scalers; i++) {
5790 if (!scaler_state->scalers[i].in_use)
5791 continue;
5792
5793 scaler_in_use = true;
5794 break;
5795 }
5796
5797 intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
5798 PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
5799 scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
5800 PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
5801 }
5802
5803 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
5804}
5805
5806int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
5807{
5808 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5809 u32 tmp;
5810
5811 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
5812
5813 switch (tmp & PIPEMISC_BPC_MASK) {
5814 case PIPEMISC_6_BPC:
5815 return 18;
5816 case PIPEMISC_8_BPC:
5817 return 24;
5818 case PIPEMISC_10_BPC:
5819 return 30;
5820 /*
5821 * PORT OUTPUT 12 BPC defined for ADLP+.
5822 *
5823 * TODO:
5824 * For previous platforms with DSI interface, bits 5:7
5825 * are used for storing pipe_bpp irrespective of dithering.
5826 * Since the value of 12 BPC is not defined for these bits
5827 * on older platforms, need to find a workaround for 12 BPC
5828 * MIPI DSI HW readout.
5829 */
5830 case PIPEMISC_12_BPC_ADLP:
5831 if (DISPLAY_VER(dev_priv) > 12)
5832 return 36;
5833 fallthrough;
5834 default:
5835 MISSING_CASE(tmp);
5836 return 0;
5837 }
5838}
5839
5840int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
5841{
5842 /*
5843 * Account for spread spectrum to avoid
5844 * oversubscribing the link. Max center spread
5845 * is 2.5%; use 5% for safety's sake.
5846 */
5847 u32 bps = target_clock * bpp * 21 / 20;
5848 return DIV_ROUND_UP(bps, link_bw * 8);
5849}
5850
5851static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5852 struct intel_link_m_n *m_n)
5853{
5854 struct drm_device *dev = crtc->base.dev;
5855 struct drm_i915_private *dev_priv = to_i915(dev);
5856 enum pipe pipe = crtc->pipe;
5857
5858 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
5859 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
5860 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5861 & ~TU_SIZE_MASK;
5862 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
5863 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5864 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5865}
5866
5867static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5868 enum transcoder transcoder,
5869 struct intel_link_m_n *m_n,
5870 struct intel_link_m_n *m2_n2)
5871{
5872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5873 enum pipe pipe = crtc->pipe;
5874
5875 if (DISPLAY_VER(dev_priv) >= 5) {
5876 m_n->link_m = intel_de_read(dev_priv,
5877 PIPE_LINK_M1(transcoder));
5878 m_n->link_n = intel_de_read(dev_priv,
5879 PIPE_LINK_N1(transcoder));
5880 m_n->gmch_m = intel_de_read(dev_priv,
5881 PIPE_DATA_M1(transcoder))
5882 & ~TU_SIZE_MASK;
5883 m_n->gmch_n = intel_de_read(dev_priv,
5884 PIPE_DATA_N1(transcoder));
5885 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
5886 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5887
5888 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
5889 m2_n2->link_m = intel_de_read(dev_priv,
5890 PIPE_LINK_M2(transcoder));
5891 m2_n2->link_n = intel_de_read(dev_priv,
5892 PIPE_LINK_N2(transcoder));
5893 m2_n2->gmch_m = intel_de_read(dev_priv,
5894 PIPE_DATA_M2(transcoder))
5895 & ~TU_SIZE_MASK;
5896 m2_n2->gmch_n = intel_de_read(dev_priv,
5897 PIPE_DATA_N2(transcoder));
5898 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
5899 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5900 }
5901 } else {
5902 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
5903 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
5904 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5905 & ~TU_SIZE_MASK;
5906 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
5907 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5908 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5909 }
5910}
5911
5912void intel_dp_get_m_n(struct intel_crtc *crtc,
5913 struct intel_crtc_state *pipe_config)
5914{
5915 if (pipe_config->has_pch_encoder)
5916 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5917 else
5918 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5919 &pipe_config->dp_m_n,
5920 &pipe_config->dp_m2_n2);
5921}
5922
5923static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
5924 struct intel_crtc_state *pipe_config)
5925{
5926 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5927 &pipe_config->fdi_m_n, NULL);
5928}
5929
5930static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
5931 u32 pos, u32 size)
5932{
5933 drm_rect_init(&crtc_state->pch_pfit.dst,
5934 pos >> 16, pos & 0xffff,
5935 size >> 16, size & 0xffff);
5936}
5937
5938static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
5939{
5940 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5941 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5942 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
5943 int id = -1;
5944 int i;
5945
5946 /* find scaler attached to this pipe */
5947 for (i = 0; i < crtc->num_scalers; i++) {
5948 u32 ctl, pos, size;
5949
5950 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
5951 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
5952 continue;
5953
5954 id = i;
5955 crtc_state->pch_pfit.enabled = true;
5956
5957 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
5958 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
5959
5960 ilk_get_pfit_pos_size(crtc_state, pos, size);
5961
5962 scaler_state->scalers[i].in_use = true;
5963 break;
5964 }
5965
5966 scaler_state->scaler_id = id;
5967 if (id >= 0)
5968 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
5969 else
5970 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
5971}
5972
5973static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
5974{
5975 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5976 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5977 u32 ctl, pos, size;
5978
5979 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
5980 if ((ctl & PF_ENABLE) == 0)
5981 return;
5982
5983 crtc_state->pch_pfit.enabled = true;
5984
5985 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
5986 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
5987
5988 ilk_get_pfit_pos_size(crtc_state, pos, size);
5989
5990 /*
5991 * We currently do not free assignements of panel fitters on
5992 * ivb/hsw (since we don't use the higher upscaling modes which
5993 * differentiates them) so just WARN about this case for now.
5994 */
5995 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
5996 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
5997}
5998
5999static bool ilk_get_pipe_config(struct intel_crtc *crtc,
6000 struct intel_crtc_state *pipe_config)
6001{
6002 struct drm_device *dev = crtc->base.dev;
6003 struct drm_i915_private *dev_priv = to_i915(dev);
6004 enum intel_display_power_domain power_domain;
6005 intel_wakeref_t wakeref;
6006 u32 tmp;
6007 bool ret;
6008
6009 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
6010 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
6011 if (!wakeref)
6012 return false;
6013
6014 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6015 pipe_config->shared_dpll = NULL;
6016
6017 ret = false;
6018 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
6019 if (!(tmp & PIPECONF_ENABLE))
6020 goto out;
6021
6022 switch (tmp & PIPECONF_BPC_MASK) {
6023 case PIPECONF_6BPC:
6024 pipe_config->pipe_bpp = 18;
6025 break;
6026 case PIPECONF_8BPC:
6027 pipe_config->pipe_bpp = 24;
6028 break;
6029 case PIPECONF_10BPC:
6030 pipe_config->pipe_bpp = 30;
6031 break;
6032 case PIPECONF_12BPC:
6033 pipe_config->pipe_bpp = 36;
6034 break;
6035 default:
6036 break;
6037 }
6038
6039 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
6040 pipe_config->limited_color_range = true;
6041
6042 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
6043 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
6044 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
6045 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6046 break;
6047 default:
6048 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6049 break;
6050 }
6051
6052 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
6053 PIPECONF_GAMMA_MODE_SHIFT;
6054
6055 pipe_config->csc_mode = intel_de_read(dev_priv,
6056 PIPE_CSC_MODE(crtc->pipe));
6057
6058 i9xx_get_pipe_color_config(pipe_config);
6059 intel_color_get_config(pipe_config);
6060
6061 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6062 struct intel_shared_dpll *pll;
6063 enum intel_dpll_id pll_id;
6064 bool pll_active;
6065
6066 pipe_config->has_pch_encoder = true;
6067
6068 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
6069 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6070 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6071
6072 ilk_get_fdi_m_n_config(crtc, pipe_config);
6073
6074 if (HAS_PCH_IBX(dev_priv)) {
6075 /*
6076 * The pipe->pch transcoder and pch transcoder->pll
6077 * mapping is fixed.
6078 */
6079 pll_id = (enum intel_dpll_id) crtc->pipe;
6080 } else {
6081 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
6082 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6083 pll_id = DPLL_ID_PCH_PLL_B;
6084 else
6085 pll_id= DPLL_ID_PCH_PLL_A;
6086 }
6087
6088 pipe_config->shared_dpll =
6089 intel_get_shared_dpll_by_id(dev_priv, pll_id);
6090 pll = pipe_config->shared_dpll;
6091
6092 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
6093 &pipe_config->dpll_hw_state);
6094 drm_WARN_ON(dev, !pll_active);
6095
6096 tmp = pipe_config->dpll_hw_state.dpll;
6097 pipe_config->pixel_multiplier =
6098 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6099 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6100
6101 ilk_pch_clock_get(crtc, pipe_config);
6102 } else {
6103 pipe_config->pixel_multiplier = 1;
6104 }
6105
6106 intel_get_transcoder_timings(crtc, pipe_config);
6107 intel_get_pipe_src_size(crtc, pipe_config);
6108
6109 ilk_get_pfit_config(pipe_config);
6110
6111 ret = true;
6112
6113out:
6114 intel_display_power_put(dev_priv, power_domain, wakeref);
6115
6116 return ret;
6117}
6118
6119static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
6120 struct intel_crtc_state *pipe_config,
6121 struct intel_display_power_domain_set *power_domain_set)
6122{
6123 struct drm_device *dev = crtc->base.dev;
6124 struct drm_i915_private *dev_priv = to_i915(dev);
6125 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
6126 unsigned long enabled_panel_transcoders = 0;
6127 enum transcoder panel_transcoder;
6128 u32 tmp;
6129
6130 if (DISPLAY_VER(dev_priv) >= 11)
6131 panel_transcoder_mask |=
6132 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
6133
6134 /*
6135 * The pipe->transcoder mapping is fixed with the exception of the eDP
6136 * and DSI transcoders handled below.
6137 */
6138 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6139
6140 /*
6141 * XXX: Do intel_display_power_get_if_enabled before reading this (for
6142 * consistency and less surprising code; it's in always on power).
6143 */
6144 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
6145 panel_transcoder_mask) {
6146 bool force_thru = false;
6147 enum pipe trans_pipe;
6148
6149 tmp = intel_de_read(dev_priv,
6150 TRANS_DDI_FUNC_CTL(panel_transcoder));
6151 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6152 continue;
6153
6154 /*
6155 * Log all enabled ones, only use the first one.
6156 *
6157 * FIXME: This won't work for two separate DSI displays.
6158 */
6159 enabled_panel_transcoders |= BIT(panel_transcoder);
6160 if (enabled_panel_transcoders != BIT(panel_transcoder))
6161 continue;
6162
6163 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6164 default:
6165 drm_WARN(dev, 1,
6166 "unknown pipe linked to transcoder %s\n",
6167 transcoder_name(panel_transcoder));
6168 fallthrough;
6169 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6170 force_thru = true;
6171 fallthrough;
6172 case TRANS_DDI_EDP_INPUT_A_ON:
6173 trans_pipe = PIPE_A;
6174 break;
6175 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6176 trans_pipe = PIPE_B;
6177 break;
6178 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6179 trans_pipe = PIPE_C;
6180 break;
6181 case TRANS_DDI_EDP_INPUT_D_ONOFF:
6182 trans_pipe = PIPE_D;
6183 break;
6184 }
6185
6186 if (trans_pipe == crtc->pipe) {
6187 pipe_config->cpu_transcoder = panel_transcoder;
6188 pipe_config->pch_pfit.force_thru = force_thru;
6189 }
6190 }
6191
6192 /*
6193 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
6194 */
6195 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
6196 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
6197
6198 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6199 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6200 return false;
6201
6202 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
6203
6204 return tmp & PIPECONF_ENABLE;
6205}
6206
6207static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
6208 struct intel_crtc_state *pipe_config,
6209 struct intel_display_power_domain_set *power_domain_set)
6210{
6211 struct drm_device *dev = crtc->base.dev;
6212 struct drm_i915_private *dev_priv = to_i915(dev);
6213 enum transcoder cpu_transcoder;
6214 enum port port;
6215 u32 tmp;
6216
6217 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
6218 if (port == PORT_A)
6219 cpu_transcoder = TRANSCODER_DSI_A;
6220 else
6221 cpu_transcoder = TRANSCODER_DSI_C;
6222
6223 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6224 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6225 continue;
6226
6227 /*
6228 * The PLL needs to be enabled with a valid divider
6229 * configuration, otherwise accessing DSI registers will hang
6230 * the machine. See BSpec North Display Engine
6231 * registers/MIPI[BXT]. We can break out here early, since we
6232 * need the same DSI PLL to be enabled for both DSI ports.
6233 */
6234 if (!bxt_dsi_pll_is_enabled(dev_priv))
6235 break;
6236
6237 /* XXX: this works for video mode only */
6238 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
6239 if (!(tmp & DPI_ENABLE))
6240 continue;
6241
6242 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
6243 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
6244 continue;
6245
6246 pipe_config->cpu_transcoder = cpu_transcoder;
6247 break;
6248 }
6249
6250 return transcoder_is_dsi(pipe_config->cpu_transcoder);
6251}
6252
6253static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
6254 struct intel_crtc_state *pipe_config)
6255{
6256 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6257 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6258 enum port port;
6259 u32 tmp;
6260
6261 if (transcoder_is_dsi(cpu_transcoder)) {
6262 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
6263 PORT_A : PORT_B;
6264 } else {
6265 tmp = intel_de_read(dev_priv,
6266 TRANS_DDI_FUNC_CTL(cpu_transcoder));
6267 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6268 return;
6269 if (DISPLAY_VER(dev_priv) >= 12)
6270 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6271 else
6272 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6273 }
6274
6275 /*
6276 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6277 * DDI E. So just check whether this pipe is wired to DDI E and whether
6278 * the PCH transcoder is on.
6279 */
6280 if (DISPLAY_VER(dev_priv) < 9 &&
6281 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
6282 pipe_config->has_pch_encoder = true;
6283
6284 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
6285 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6286 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6287
6288 ilk_get_fdi_m_n_config(crtc, pipe_config);
6289 }
6290}
6291
6292static bool hsw_get_pipe_config(struct intel_crtc *crtc,
6293 struct intel_crtc_state *pipe_config)
6294{
6295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6296 struct intel_display_power_domain_set power_domain_set = { };
6297 bool active;
6298 u32 tmp;
6299
6300 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6301 POWER_DOMAIN_PIPE(crtc->pipe)))
6302 return false;
6303
6304 pipe_config->shared_dpll = NULL;
6305
6306 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
6307
6308 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
6309 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
6310 drm_WARN_ON(&dev_priv->drm, active);
6311 active = true;
6312 }
6313
6314 intel_dsc_get_config(pipe_config);
6315 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
6316 intel_uncompressed_joiner_get_config(pipe_config);
6317
6318 if (!active) {
6319 /* bigjoiner slave doesn't enable transcoder */
6320 if (!pipe_config->bigjoiner_slave)
6321 goto out;
6322
6323 active = true;
6324 pipe_config->pixel_multiplier = 1;
6325
6326 /* we cannot read out most state, so don't bother.. */
6327 pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
6328 } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
6329 DISPLAY_VER(dev_priv) >= 11) {
6330 hsw_get_ddi_port_state(crtc, pipe_config);
6331 intel_get_transcoder_timings(crtc, pipe_config);
6332 }
6333
6334 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
6335 intel_vrr_get_config(crtc, pipe_config);
6336
6337 intel_get_pipe_src_size(crtc, pipe_config);
6338
6339 if (IS_HASWELL(dev_priv)) {
6340 u32 tmp = intel_de_read(dev_priv,
6341 PIPECONF(pipe_config->cpu_transcoder));
6342
6343 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
6344 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6345 else
6346 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6347 } else {
6348 pipe_config->output_format =
6349 bdw_get_pipemisc_output_format(crtc);
6350 }
6351
6352 pipe_config->gamma_mode = intel_de_read(dev_priv,
6353 GAMMA_MODE(crtc->pipe));
6354
6355 pipe_config->csc_mode = intel_de_read(dev_priv,
6356 PIPE_CSC_MODE(crtc->pipe));
6357
6358 if (DISPLAY_VER(dev_priv) >= 9) {
6359 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
6360
6361 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
6362 pipe_config->gamma_enable = true;
6363
6364 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
6365 pipe_config->csc_enable = true;
6366 } else {
6367 i9xx_get_pipe_color_config(pipe_config);
6368 }
6369
6370 intel_color_get_config(pipe_config);
6371
6372 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
6373 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
6374 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6375 pipe_config->ips_linetime =
6376 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
6377
6378 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6379 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
6380 if (DISPLAY_VER(dev_priv) >= 9)
6381 skl_get_pfit_config(pipe_config);
6382 else
6383 ilk_get_pfit_config(pipe_config);
6384 }
6385
6386 if (hsw_crtc_supports_ips(crtc)) {
6387 if (IS_HASWELL(dev_priv))
6388 pipe_config->ips_enabled = intel_de_read(dev_priv,
6389 IPS_CTL) & IPS_ENABLE;
6390 else {
6391 /*
6392 * We cannot readout IPS state on broadwell, set to
6393 * true so we can set it to a defined state on first
6394 * commit.
6395 */
6396 pipe_config->ips_enabled = true;
6397 }
6398 }
6399
6400 if (pipe_config->bigjoiner_slave) {
6401 /* Cannot be read out as a slave, set to 0. */
6402 pipe_config->pixel_multiplier = 0;
6403 } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
6404 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
6405 pipe_config->pixel_multiplier =
6406 intel_de_read(dev_priv,
6407 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
6408 } else {
6409 pipe_config->pixel_multiplier = 1;
6410 }
6411
6412out:
6413 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
6414
6415 return active;
6416}
6417
6418static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
6419{
6420 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6421 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6422
6423 if (!i915->display.get_pipe_config(crtc, crtc_state))
6424 return false;
6425
6426 crtc_state->hw.active = true;
6427
6428 intel_crtc_readout_derived_state(crtc_state);
6429
6430 return true;
6431}
6432
6433/* VESA 640x480x72Hz mode to set on the pipe */
6434static const struct drm_display_mode load_detect_mode = {
6435 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6436 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6437};
6438
6439struct drm_framebuffer *
6440intel_framebuffer_create(struct drm_i915_gem_object *obj,
6441 struct drm_mode_fb_cmd2 *mode_cmd)
6442{
6443 struct intel_framebuffer *intel_fb;
6444 int ret;
6445
6446 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6447 if (!intel_fb)
6448 return ERR_PTR(-ENOMEM);
6449
6450 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
6451 if (ret)
6452 goto err;
6453
6454 return &intel_fb->base;
6455
6456err:
6457 kfree(intel_fb);
6458 return ERR_PTR(ret);
6459}
6460
6461static int intel_modeset_disable_planes(struct drm_atomic_state *state,
6462 struct drm_crtc *crtc)
6463{
6464 struct drm_plane *plane;
6465 struct drm_plane_state *plane_state;
6466 int ret, i;
6467
6468 ret = drm_atomic_add_affected_planes(state, crtc);
6469 if (ret)
6470 return ret;
6471
6472 for_each_new_plane_in_state(state, plane, plane_state, i) {
6473 if (plane_state->crtc != crtc)
6474 continue;
6475
6476 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
6477 if (ret)
6478 return ret;
6479
6480 drm_atomic_set_fb_for_plane(plane_state, NULL);
6481 }
6482
6483 return 0;
6484}
6485
6486int intel_get_load_detect_pipe(struct drm_connector *connector,
6487 struct intel_load_detect_pipe *old,
6488 struct drm_modeset_acquire_ctx *ctx)
6489{
6490 struct intel_crtc *intel_crtc;
6491 struct intel_encoder *intel_encoder =
6492 intel_attached_encoder(to_intel_connector(connector));
6493 struct drm_crtc *possible_crtc;
6494 struct drm_encoder *encoder = &intel_encoder->base;
6495 struct drm_crtc *crtc = NULL;
6496 struct drm_device *dev = encoder->dev;
6497 struct drm_i915_private *dev_priv = to_i915(dev);
6498 struct drm_mode_config *config = &dev->mode_config;
6499 struct drm_atomic_state *state = NULL, *restore_state = NULL;
6500 struct drm_connector_state *connector_state;
6501 struct intel_crtc_state *crtc_state;
6502 int ret, i = -1;
6503
6504 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6505 connector->base.id, connector->name,
6506 encoder->base.id, encoder->name);
6507
6508 old->restore_state = NULL;
6509
6510 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
6511
6512 /*
6513 * Algorithm gets a little messy:
6514 *
6515 * - if the connector already has an assigned crtc, use it (but make
6516 * sure it's on first)
6517 *
6518 * - try to find the first unused crtc that can drive this connector,
6519 * and use that if we find one
6520 */
6521
6522 /* See if we already have a CRTC for this connector */
6523 if (connector->state->crtc) {
6524 crtc = connector->state->crtc;
6525
6526 ret = drm_modeset_lock(&crtc->mutex, ctx);
6527 if (ret)
6528 goto fail;
6529
6530 /* Make sure the crtc and connector are running */
6531 goto found;
6532 }
6533
6534 /* Find an unused one (if possible) */
6535 for_each_crtc(dev, possible_crtc) {
6536 i++;
6537 if (!(encoder->possible_crtcs & (1 << i)))
6538 continue;
6539
6540 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
6541 if (ret)
6542 goto fail;
6543
6544 if (possible_crtc->state->enable) {
6545 drm_modeset_unlock(&possible_crtc->mutex);
6546 continue;
6547 }
6548
6549 crtc = possible_crtc;
6550 break;
6551 }
6552
6553 /*
6554 * If we didn't find an unused CRTC, don't use any.
6555 */
6556 if (!crtc) {
6557 drm_dbg_kms(&dev_priv->drm,
6558 "no pipe available for load-detect\n");
6559 ret = -ENODEV;
6560 goto fail;
6561 }
6562
6563found:
6564 intel_crtc = to_intel_crtc(crtc);
6565
6566 state = drm_atomic_state_alloc(dev);
6567 restore_state = drm_atomic_state_alloc(dev);
6568 if (!state || !restore_state) {
6569 ret = -ENOMEM;
6570 goto fail;
6571 }
6572
6573 state->acquire_ctx = ctx;
6574 restore_state->acquire_ctx = ctx;
6575
6576 connector_state = drm_atomic_get_connector_state(state, connector);
6577 if (IS_ERR(connector_state)) {
6578 ret = PTR_ERR(connector_state);
6579 goto fail;
6580 }
6581
6582 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
6583 if (ret)
6584 goto fail;
6585
6586 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6587 if (IS_ERR(crtc_state)) {
6588 ret = PTR_ERR(crtc_state);
6589 goto fail;
6590 }
6591
6592 crtc_state->uapi.active = true;
6593
6594 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
6595 &load_detect_mode);
6596 if (ret)
6597 goto fail;
6598
6599 ret = intel_modeset_disable_planes(state, crtc);
6600 if (ret)
6601 goto fail;
6602
6603 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
6604 if (!ret)
6605 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
6606 if (!ret)
6607 ret = drm_atomic_add_affected_planes(restore_state, crtc);
6608 if (ret) {
6609 drm_dbg_kms(&dev_priv->drm,
6610 "Failed to create a copy of old state to restore: %i\n",
6611 ret);
6612 goto fail;
6613 }
6614
6615 ret = drm_atomic_commit(state);
6616 if (ret) {
6617 drm_dbg_kms(&dev_priv->drm,
6618 "failed to set mode on load-detect pipe\n");
6619 goto fail;
6620 }
6621
6622 old->restore_state = restore_state;
6623 drm_atomic_state_put(state);
6624
6625 /* let the connector get through one full cycle before testing */
6626 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
6627 return true;
6628
6629fail:
6630 if (state) {
6631 drm_atomic_state_put(state);
6632 state = NULL;
6633 }
6634 if (restore_state) {
6635 drm_atomic_state_put(restore_state);
6636 restore_state = NULL;
6637 }
6638
6639 if (ret == -EDEADLK)
6640 return ret;
6641
6642 return false;
6643}
6644
6645void intel_release_load_detect_pipe(struct drm_connector *connector,
6646 struct intel_load_detect_pipe *old,
6647 struct drm_modeset_acquire_ctx *ctx)
6648{
6649 struct intel_encoder *intel_encoder =
6650 intel_attached_encoder(to_intel_connector(connector));
6651 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
6652 struct drm_encoder *encoder = &intel_encoder->base;
6653 struct drm_atomic_state *state = old->restore_state;
6654 int ret;
6655
6656 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6657 connector->base.id, connector->name,
6658 encoder->base.id, encoder->name);
6659
6660 if (!state)
6661 return;
6662
6663 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
6664 if (ret)
6665 drm_dbg_kms(&i915->drm,
6666 "Couldn't release load detect pipe: %i\n", ret);
6667 drm_atomic_state_put(state);
6668}
6669
6670static int i9xx_pll_refclk(struct drm_device *dev,
6671 const struct intel_crtc_state *pipe_config)
6672{
6673 struct drm_i915_private *dev_priv = to_i915(dev);
6674 u32 dpll = pipe_config->dpll_hw_state.dpll;
6675
6676 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
6677 return dev_priv->vbt.lvds_ssc_freq;
6678 else if (HAS_PCH_SPLIT(dev_priv))
6679 return 120000;
6680 else if (DISPLAY_VER(dev_priv) != 2)
6681 return 96000;
6682 else
6683 return 48000;
6684}
6685
6686/* Returns the clock of the currently programmed mode of the given pipe. */
6687static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6688 struct intel_crtc_state *pipe_config)
6689{
6690 struct drm_device *dev = crtc->base.dev;
6691 struct drm_i915_private *dev_priv = to_i915(dev);
6692 enum pipe pipe = crtc->pipe;
6693 u32 dpll = pipe_config->dpll_hw_state.dpll;
6694 u32 fp;
6695 struct dpll clock;
6696 int port_clock;
6697 int refclk = i9xx_pll_refclk(dev, pipe_config);
6698
6699 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6700 fp = pipe_config->dpll_hw_state.fp0;
6701 else
6702 fp = pipe_config->dpll_hw_state.fp1;
6703
6704 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6705 if (IS_PINEVIEW(dev_priv)) {
6706 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6707 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6708 } else {
6709 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6710 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6711 }
6712
6713 if (DISPLAY_VER(dev_priv) != 2) {
6714 if (IS_PINEVIEW(dev_priv))
6715 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6716 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6717 else
6718 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6719 DPLL_FPA01_P1_POST_DIV_SHIFT);
6720
6721 switch (dpll & DPLL_MODE_MASK) {
6722 case DPLLB_MODE_DAC_SERIAL:
6723 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6724 5 : 10;
6725 break;
6726 case DPLLB_MODE_LVDS:
6727 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6728 7 : 14;
6729 break;
6730 default:
6731 drm_dbg_kms(&dev_priv->drm,
6732 "Unknown DPLL mode %08x in programmed "
6733 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6734 return;
6735 }
6736
6737 if (IS_PINEVIEW(dev_priv))
6738 port_clock = pnv_calc_dpll_params(refclk, &clock);
6739 else
6740 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6741 } else {
6742 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
6743 LVDS);
6744 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
6745
6746 if (is_lvds) {
6747 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6748 DPLL_FPA01_P1_POST_DIV_SHIFT);
6749
6750 if (lvds & LVDS_CLKB_POWER_UP)
6751 clock.p2 = 7;
6752 else
6753 clock.p2 = 14;
6754 } else {
6755 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6756 clock.p1 = 2;
6757 else {
6758 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6759 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6760 }
6761 if (dpll & PLL_P2_DIVIDE_BY_4)
6762 clock.p2 = 4;
6763 else
6764 clock.p2 = 2;
6765 }
6766
6767 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6768 }
6769
6770 /*
6771 * This value includes pixel_multiplier. We will use
6772 * port_clock to compute adjusted_mode.crtc_clock in the
6773 * encoder's get_config() function.
6774 */
6775 pipe_config->port_clock = port_clock;
6776}
6777
6778int intel_dotclock_calculate(int link_freq,
6779 const struct intel_link_m_n *m_n)
6780{
6781 /*
6782 * The calculation for the data clock is:
6783 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
6784 * But we want to avoid losing precison if possible, so:
6785 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
6786 *
6787 * and the link clock is simpler:
6788 * link_clock = (m * link_clock) / n
6789 */
6790
6791 if (!m_n->link_n)
6792 return 0;
6793
6794 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
6795}
6796
6797static void ilk_pch_clock_get(struct intel_crtc *crtc,
6798 struct intel_crtc_state *pipe_config)
6799{
6800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6801
6802 /* read out port_clock from the DPLL */
6803 i9xx_crtc_clock_get(crtc, pipe_config);
6804
6805 /*
6806 * In case there is an active pipe without active ports,
6807 * we may need some idea for the dotclock anyway.
6808 * Calculate one based on the FDI configuration.
6809 */
6810 pipe_config->hw.adjusted_mode.crtc_clock =
6811 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
6812 &pipe_config->fdi_m_n);
6813}
6814
6815/* Returns the currently programmed mode of the given encoder. */
6816struct drm_display_mode *
6817intel_encoder_current_mode(struct intel_encoder *encoder)
6818{
6819 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6820 struct intel_crtc_state *crtc_state;
6821 struct drm_display_mode *mode;
6822 struct intel_crtc *crtc;
6823 enum pipe pipe;
6824
6825 if (!encoder->get_hw_state(encoder, &pipe))
6826 return NULL;
6827
6828 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6829
6830 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6831 if (!mode)
6832 return NULL;
6833
6834 crtc_state = intel_crtc_state_alloc(crtc);
6835 if (!crtc_state) {
6836 kfree(mode);
6837 return NULL;
6838 }
6839
6840 if (!intel_crtc_get_pipe_config(crtc_state)) {
6841 kfree(crtc_state);
6842 kfree(mode);
6843 return NULL;
6844 }
6845
6846 intel_encoder_get_config(encoder, crtc_state);
6847
6848 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
6849
6850 kfree(crtc_state);
6851
6852 return mode;
6853}
6854
6855/**
6856 * intel_wm_need_update - Check whether watermarks need updating
6857 * @cur: current plane state
6858 * @new: new plane state
6859 *
6860 * Check current plane state versus the new one to determine whether
6861 * watermarks need to be recalculated.
6862 *
6863 * Returns true or false.
6864 */
6865static bool intel_wm_need_update(const struct intel_plane_state *cur,
6866 struct intel_plane_state *new)
6867{
6868 /* Update watermarks on tiling or size changes. */
6869 if (new->uapi.visible != cur->uapi.visible)
6870 return true;
6871
6872 if (!cur->hw.fb || !new->hw.fb)
6873 return false;
6874
6875 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
6876 cur->hw.rotation != new->hw.rotation ||
6877 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
6878 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
6879 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
6880 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
6881 return true;
6882
6883 return false;
6884}
6885
6886static bool needs_scaling(const struct intel_plane_state *state)
6887{
6888 int src_w = drm_rect_width(&state->uapi.src) >> 16;
6889 int src_h = drm_rect_height(&state->uapi.src) >> 16;
6890 int dst_w = drm_rect_width(&state->uapi.dst);
6891 int dst_h = drm_rect_height(&state->uapi.dst);
6892
6893 return (src_w != dst_w || src_h != dst_h);
6894}
6895
6896int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
6897 struct intel_crtc_state *crtc_state,
6898 const struct intel_plane_state *old_plane_state,
6899 struct intel_plane_state *plane_state)
6900{
6901 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6902 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
6903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6904 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6905 bool was_crtc_enabled = old_crtc_state->hw.active;
6906 bool is_crtc_enabled = crtc_state->hw.active;
6907 bool turn_off, turn_on, visible, was_visible;
6908 int ret;
6909
6910 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
6911 ret = skl_update_scaler_plane(crtc_state, plane_state);
6912 if (ret)
6913 return ret;
6914 }
6915
6916 was_visible = old_plane_state->uapi.visible;
6917 visible = plane_state->uapi.visible;
6918
6919 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
6920 was_visible = false;
6921
6922 /*
6923 * Visibility is calculated as if the crtc was on, but
6924 * after scaler setup everything depends on it being off
6925 * when the crtc isn't active.
6926 *
6927 * FIXME this is wrong for watermarks. Watermarks should also
6928 * be computed as if the pipe would be active. Perhaps move
6929 * per-plane wm computation to the .check_plane() hook, and
6930 * only combine the results from all planes in the current place?
6931 */
6932 if (!is_crtc_enabled) {
6933 intel_plane_set_invisible(crtc_state, plane_state);
6934 visible = false;
6935 }
6936
6937 if (!was_visible && !visible)
6938 return 0;
6939
6940 turn_off = was_visible && (!visible || mode_changed);
6941 turn_on = visible && (!was_visible || mode_changed);
6942
6943 drm_dbg_atomic(&dev_priv->drm,
6944 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
6945 crtc->base.base.id, crtc->base.name,
6946 plane->base.base.id, plane->base.name,
6947 was_visible, visible,
6948 turn_off, turn_on, mode_changed);
6949
6950 if (turn_on) {
6951 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6952 crtc_state->update_wm_pre = true;
6953
6954 /* must disable cxsr around plane enable/disable */
6955 if (plane->id != PLANE_CURSOR)
6956 crtc_state->disable_cxsr = true;
6957 } else if (turn_off) {
6958 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6959 crtc_state->update_wm_post = true;
6960
6961 /* must disable cxsr around plane enable/disable */
6962 if (plane->id != PLANE_CURSOR)
6963 crtc_state->disable_cxsr = true;
6964 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
6965 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
6966 /* FIXME bollocks */
6967 crtc_state->update_wm_pre = true;
6968 crtc_state->update_wm_post = true;
6969 }
6970 }
6971
6972 if (visible || was_visible)
6973 crtc_state->fb_bits |= plane->frontbuffer_bit;
6974
6975 /*
6976 * ILK/SNB DVSACNTR/Sprite Enable
6977 * IVB SPR_CTL/Sprite Enable
6978 * "When in Self Refresh Big FIFO mode, a write to enable the
6979 * plane will be internally buffered and delayed while Big FIFO
6980 * mode is exiting."
6981 *
6982 * Which means that enabling the sprite can take an extra frame
6983 * when we start in big FIFO mode (LP1+). Thus we need to drop
6984 * down to LP0 and wait for vblank in order to make sure the
6985 * sprite gets enabled on the next vblank after the register write.
6986 * Doing otherwise would risk enabling the sprite one frame after
6987 * we've already signalled flip completion. We can resume LP1+
6988 * once the sprite has been enabled.
6989 *
6990 *
6991 * WaCxSRDisabledForSpriteScaling:ivb
6992 * IVB SPR_SCALE/Scaling Enable
6993 * "Low Power watermarks must be disabled for at least one
6994 * frame before enabling sprite scaling, and kept disabled
6995 * until sprite scaling is disabled."
6996 *
6997 * ILK/SNB DVSASCALE/Scaling Enable
6998 * "When in Self Refresh Big FIFO mode, scaling enable will be
6999 * masked off while Big FIFO mode is exiting."
7000 *
7001 * Despite the w/a only being listed for IVB we assume that
7002 * the ILK/SNB note has similar ramifications, hence we apply
7003 * the w/a on all three platforms.
7004 *
7005 * With experimental results seems this is needed also for primary
7006 * plane, not only sprite plane.
7007 */
7008 if (plane->id != PLANE_CURSOR &&
7009 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
7010 IS_IVYBRIDGE(dev_priv)) &&
7011 (turn_on || (!needs_scaling(old_plane_state) &&
7012 needs_scaling(plane_state))))
7013 crtc_state->disable_lp_wm = true;
7014
7015 return 0;
7016}
7017
7018static bool encoders_cloneable(const struct intel_encoder *a,
7019 const struct intel_encoder *b)
7020{
7021 /* masks could be asymmetric, so check both ways */
7022 return a == b || (a->cloneable & (1 << b->type) &&
7023 b->cloneable & (1 << a->type));
7024}
7025
7026static bool check_single_encoder_cloning(struct intel_atomic_state *state,
7027 struct intel_crtc *crtc,
7028 struct intel_encoder *encoder)
7029{
7030 struct intel_encoder *source_encoder;
7031 struct drm_connector *connector;
7032 struct drm_connector_state *connector_state;
7033 int i;
7034
7035 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
7036 if (connector_state->crtc != &crtc->base)
7037 continue;
7038
7039 source_encoder =
7040 to_intel_encoder(connector_state->best_encoder);
7041 if (!encoders_cloneable(encoder, source_encoder))
7042 return false;
7043 }
7044
7045 return true;
7046}
7047
7048static int icl_add_linked_planes(struct intel_atomic_state *state)
7049{
7050 struct intel_plane *plane, *linked;
7051 struct intel_plane_state *plane_state, *linked_plane_state;
7052 int i;
7053
7054 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7055 linked = plane_state->planar_linked_plane;
7056
7057 if (!linked)
7058 continue;
7059
7060 linked_plane_state = intel_atomic_get_plane_state(state, linked);
7061 if (IS_ERR(linked_plane_state))
7062 return PTR_ERR(linked_plane_state);
7063
7064 drm_WARN_ON(state->base.dev,
7065 linked_plane_state->planar_linked_plane != plane);
7066 drm_WARN_ON(state->base.dev,
7067 linked_plane_state->planar_slave == plane_state->planar_slave);
7068 }
7069
7070 return 0;
7071}
7072
7073static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
7074{
7075 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7076 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7077 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
7078 struct intel_plane *plane, *linked;
7079 struct intel_plane_state *plane_state;
7080 int i;
7081
7082 if (DISPLAY_VER(dev_priv) < 11)
7083 return 0;
7084
7085 /*
7086 * Destroy all old plane links and make the slave plane invisible
7087 * in the crtc_state->active_planes mask.
7088 */
7089 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7090 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
7091 continue;
7092
7093 plane_state->planar_linked_plane = NULL;
7094 if (plane_state->planar_slave && !plane_state->uapi.visible) {
7095 crtc_state->enabled_planes &= ~BIT(plane->id);
7096 crtc_state->active_planes &= ~BIT(plane->id);
7097 crtc_state->update_planes |= BIT(plane->id);
7098 }
7099
7100 plane_state->planar_slave = false;
7101 }
7102
7103 if (!crtc_state->nv12_planes)
7104 return 0;
7105
7106 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7107 struct intel_plane_state *linked_state = NULL;
7108
7109 if (plane->pipe != crtc->pipe ||
7110 !(crtc_state->nv12_planes & BIT(plane->id)))
7111 continue;
7112
7113 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
7114 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
7115 continue;
7116
7117 if (crtc_state->active_planes & BIT(linked->id))
7118 continue;
7119
7120 linked_state = intel_atomic_get_plane_state(state, linked);
7121 if (IS_ERR(linked_state))
7122 return PTR_ERR(linked_state);
7123
7124 break;
7125 }
7126
7127 if (!linked_state) {
7128 drm_dbg_kms(&dev_priv->drm,
7129 "Need %d free Y planes for planar YUV\n",
7130 hweight8(crtc_state->nv12_planes));
7131
7132 return -EINVAL;
7133 }
7134
7135 plane_state->planar_linked_plane = linked;
7136
7137 linked_state->planar_slave = true;
7138 linked_state->planar_linked_plane = plane;
7139 crtc_state->enabled_planes |= BIT(linked->id);
7140 crtc_state->active_planes |= BIT(linked->id);
7141 crtc_state->update_planes |= BIT(linked->id);
7142 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
7143 linked->base.name, plane->base.name);
7144
7145 /* Copy parameters to slave plane */
7146 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
7147 linked_state->color_ctl = plane_state->color_ctl;
7148 linked_state->view = plane_state->view;
7149
7150 intel_plane_copy_hw_state(linked_state, plane_state);
7151 linked_state->uapi.src = plane_state->uapi.src;
7152 linked_state->uapi.dst = plane_state->uapi.dst;
7153
7154 if (icl_is_hdr_plane(dev_priv, plane->id)) {
7155 if (linked->id == PLANE_SPRITE5)
7156 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
7157 else if (linked->id == PLANE_SPRITE4)
7158 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
7159 else if (linked->id == PLANE_SPRITE3)
7160 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
7161 else if (linked->id == PLANE_SPRITE2)
7162 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
7163 else
7164 MISSING_CASE(linked->id);
7165 }
7166 }
7167
7168 return 0;
7169}
7170
7171static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
7172{
7173 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7174 struct intel_atomic_state *state =
7175 to_intel_atomic_state(new_crtc_state->uapi.state);
7176 const struct intel_crtc_state *old_crtc_state =
7177 intel_atomic_get_old_crtc_state(state, crtc);
7178
7179 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
7180}
7181
7182static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
7183{
7184 const struct drm_display_mode *pipe_mode =
7185 &crtc_state->hw.pipe_mode;
7186 int linetime_wm;
7187
7188 if (!crtc_state->hw.enable)
7189 return 0;
7190
7191 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7192 pipe_mode->crtc_clock);
7193
7194 return min(linetime_wm, 0x1ff);
7195}
7196
7197static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
7198 const struct intel_cdclk_state *cdclk_state)
7199{
7200 const struct drm_display_mode *pipe_mode =
7201 &crtc_state->hw.pipe_mode;
7202 int linetime_wm;
7203
7204 if (!crtc_state->hw.enable)
7205 return 0;
7206
7207 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7208 cdclk_state->logical.cdclk);
7209
7210 return min(linetime_wm, 0x1ff);
7211}
7212
7213static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
7214{
7215 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7216 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7217 const struct drm_display_mode *pipe_mode =
7218 &crtc_state->hw.pipe_mode;
7219 int linetime_wm;
7220
7221 if (!crtc_state->hw.enable)
7222 return 0;
7223
7224 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
7225 crtc_state->pixel_rate);
7226
7227 /* Display WA #1135: BXT:ALL GLK:ALL */
7228 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
7229 dev_priv->ipc_enabled)
7230 linetime_wm /= 2;
7231
7232 return min(linetime_wm, 0x1ff);
7233}
7234
7235static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
7236 struct intel_crtc *crtc)
7237{
7238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7239 struct intel_crtc_state *crtc_state =
7240 intel_atomic_get_new_crtc_state(state, crtc);
7241 const struct intel_cdclk_state *cdclk_state;
7242
7243 if (DISPLAY_VER(dev_priv) >= 9)
7244 crtc_state->linetime = skl_linetime_wm(crtc_state);
7245 else
7246 crtc_state->linetime = hsw_linetime_wm(crtc_state);
7247
7248 if (!hsw_crtc_supports_ips(crtc))
7249 return 0;
7250
7251 cdclk_state = intel_atomic_get_cdclk_state(state);
7252 if (IS_ERR(cdclk_state))
7253 return PTR_ERR(cdclk_state);
7254
7255 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
7256 cdclk_state);
7257
7258 return 0;
7259}
7260
7261static int intel_crtc_atomic_check(struct intel_atomic_state *state,
7262 struct intel_crtc *crtc)
7263{
7264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7265 struct intel_crtc_state *crtc_state =
7266 intel_atomic_get_new_crtc_state(state, crtc);
7267 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
7268 int ret;
7269
7270 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
7271 mode_changed && !crtc_state->hw.active)
7272 crtc_state->update_wm_post = true;
7273
7274 if (mode_changed && crtc_state->hw.enable &&
7275 dev_priv->display.crtc_compute_clock &&
7276 !crtc_state->bigjoiner_slave &&
7277 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
7278 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
7279 if (ret)
7280 return ret;
7281 }
7282
7283 /*
7284 * May need to update pipe gamma enable bits
7285 * when C8 planes are getting enabled/disabled.
7286 */
7287 if (c8_planes_changed(crtc_state))
7288 crtc_state->uapi.color_mgmt_changed = true;
7289
7290 if (mode_changed || crtc_state->update_pipe ||
7291 crtc_state->uapi.color_mgmt_changed) {
7292 ret = intel_color_check(crtc_state);
7293 if (ret)
7294 return ret;
7295 }
7296
7297 if (dev_priv->display.compute_pipe_wm) {
7298 ret = dev_priv->display.compute_pipe_wm(crtc_state);
7299 if (ret) {
7300 drm_dbg_kms(&dev_priv->drm,
7301 "Target pipe watermarks are invalid\n");
7302 return ret;
7303 }
7304 }
7305
7306 if (dev_priv->display.compute_intermediate_wm) {
7307 if (drm_WARN_ON(&dev_priv->drm,
7308 !dev_priv->display.compute_pipe_wm))
7309 return 0;
7310
7311 /*
7312 * Calculate 'intermediate' watermarks that satisfy both the
7313 * old state and the new state. We can program these
7314 * immediately.
7315 */
7316 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
7317 if (ret) {
7318 drm_dbg_kms(&dev_priv->drm,
7319 "No valid intermediate pipe watermarks are possible\n");
7320 return ret;
7321 }
7322 }
7323
7324 if (DISPLAY_VER(dev_priv) >= 9) {
7325 if (mode_changed || crtc_state->update_pipe) {
7326 ret = skl_update_scaler_crtc(crtc_state);
7327 if (ret)
7328 return ret;
7329 }
7330
7331 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
7332 if (ret)
7333 return ret;
7334 }
7335
7336 if (HAS_IPS(dev_priv)) {
7337 ret = hsw_compute_ips_config(crtc_state);
7338 if (ret)
7339 return ret;
7340 }
7341
7342 if (DISPLAY_VER(dev_priv) >= 9 ||
7343 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7344 ret = hsw_compute_linetime_wm(state, crtc);
7345 if (ret)
7346 return ret;
7347
7348 }
7349
7350 if (!mode_changed) {
7351 ret = intel_psr2_sel_fetch_update(state, crtc);
7352 if (ret)
7353 return ret;
7354 }
7355
7356 return 0;
7357}
7358
7359static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
7360{
7361 struct intel_connector *connector;
7362 struct drm_connector_list_iter conn_iter;
7363
7364 drm_connector_list_iter_begin(dev, &conn_iter);
7365 for_each_intel_connector_iter(connector, &conn_iter) {
7366 struct drm_connector_state *conn_state = connector->base.state;
7367 struct intel_encoder *encoder =
7368 to_intel_encoder(connector->base.encoder);
7369
7370 if (conn_state->crtc)
7371 drm_connector_put(&connector->base);
7372
7373 if (encoder) {
7374 struct intel_crtc *crtc =
7375 to_intel_crtc(encoder->base.crtc);
7376 const struct intel_crtc_state *crtc_state =
7377 to_intel_crtc_state(crtc->base.state);
7378
7379 conn_state->best_encoder = &encoder->base;
7380 conn_state->crtc = &crtc->base;
7381 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
7382
7383 drm_connector_get(&connector->base);
7384 } else {
7385 conn_state->best_encoder = NULL;
7386 conn_state->crtc = NULL;
7387 }
7388 }
7389 drm_connector_list_iter_end(&conn_iter);
7390}
7391
7392static int
7393compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
7394 struct intel_crtc_state *pipe_config)
7395{
7396 struct drm_connector *connector = conn_state->connector;
7397 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7398 const struct drm_display_info *info = &connector->display_info;
7399 int bpp;
7400
7401 switch (conn_state->max_bpc) {
7402 case 6 ... 7:
7403 bpp = 6 * 3;
7404 break;
7405 case 8 ... 9:
7406 bpp = 8 * 3;
7407 break;
7408 case 10 ... 11:
7409 bpp = 10 * 3;
7410 break;
7411 case 12 ... 16:
7412 bpp = 12 * 3;
7413 break;
7414 default:
7415 MISSING_CASE(conn_state->max_bpc);
7416 return -EINVAL;
7417 }
7418
7419 if (bpp < pipe_config->pipe_bpp) {
7420 drm_dbg_kms(&i915->drm,
7421 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
7422 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
7423 connector->base.id, connector->name,
7424 bpp, 3 * info->bpc,
7425 3 * conn_state->max_requested_bpc,
7426 pipe_config->pipe_bpp);
7427
7428 pipe_config->pipe_bpp = bpp;
7429 }
7430
7431 return 0;
7432}
7433
7434static int
7435compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7436 struct intel_crtc_state *pipe_config)
7437{
7438 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7439 struct drm_atomic_state *state = pipe_config->uapi.state;
7440 struct drm_connector *connector;
7441 struct drm_connector_state *connector_state;
7442 int bpp, i;
7443
7444 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7445 IS_CHERRYVIEW(dev_priv)))
7446 bpp = 10*3;
7447 else if (DISPLAY_VER(dev_priv) >= 5)
7448 bpp = 12*3;
7449 else
7450 bpp = 8*3;
7451
7452 pipe_config->pipe_bpp = bpp;
7453
7454 /* Clamp display bpp to connector max bpp */
7455 for_each_new_connector_in_state(state, connector, connector_state, i) {
7456 int ret;
7457
7458 if (connector_state->crtc != &crtc->base)
7459 continue;
7460
7461 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
7462 if (ret)
7463 return ret;
7464 }
7465
7466 return 0;
7467}
7468
7469static void intel_dump_crtc_timings(struct drm_i915_private *i915,
7470 const struct drm_display_mode *mode)
7471{
7472 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
7473 "type: 0x%x flags: 0x%x\n",
7474 mode->crtc_clock,
7475 mode->crtc_hdisplay, mode->crtc_hsync_start,
7476 mode->crtc_hsync_end, mode->crtc_htotal,
7477 mode->crtc_vdisplay, mode->crtc_vsync_start,
7478 mode->crtc_vsync_end, mode->crtc_vtotal,
7479 mode->type, mode->flags);
7480}
7481
7482static void
7483intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
7484 const char *id, unsigned int lane_count,
7485 const struct intel_link_m_n *m_n)
7486{
7487 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7488
7489 drm_dbg_kms(&i915->drm,
7490 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7491 id, lane_count,
7492 m_n->gmch_m, m_n->gmch_n,
7493 m_n->link_m, m_n->link_n, m_n->tu);
7494}
7495
7496static void
7497intel_dump_infoframe(struct drm_i915_private *dev_priv,
7498 const union hdmi_infoframe *frame)
7499{
7500 if (!drm_debug_enabled(DRM_UT_KMS))
7501 return;
7502
7503 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
7504}
7505
7506static void
7507intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
7508 const struct drm_dp_vsc_sdp *vsc)
7509{
7510 if (!drm_debug_enabled(DRM_UT_KMS))
7511 return;
7512
7513 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
7514}
7515
7516#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
7517
7518static const char * const output_type_str[] = {
7519 OUTPUT_TYPE(UNUSED),
7520 OUTPUT_TYPE(ANALOG),
7521 OUTPUT_TYPE(DVO),
7522 OUTPUT_TYPE(SDVO),
7523 OUTPUT_TYPE(LVDS),
7524 OUTPUT_TYPE(TVOUT),
7525 OUTPUT_TYPE(HDMI),
7526 OUTPUT_TYPE(DP),
7527 OUTPUT_TYPE(EDP),
7528 OUTPUT_TYPE(DSI),
7529 OUTPUT_TYPE(DDI),
7530 OUTPUT_TYPE(DP_MST),
7531};
7532
7533#undef OUTPUT_TYPE
7534
7535static void snprintf_output_types(char *buf, size_t len,
7536 unsigned int output_types)
7537{
7538 char *str = buf;
7539 int i;
7540
7541 str[0] = '\0';
7542
7543 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
7544 int r;
7545
7546 if ((output_types & BIT(i)) == 0)
7547 continue;
7548
7549 r = snprintf(str, len, "%s%s",
7550 str != buf ? "," : "", output_type_str[i]);
7551 if (r >= len)
7552 break;
7553 str += r;
7554 len -= r;
7555
7556 output_types &= ~BIT(i);
7557 }
7558
7559 WARN_ON_ONCE(output_types != 0);
7560}
7561
7562static const char * const output_format_str[] = {
7563 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
7564 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
7565 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
7566};
7567
7568static const char *output_formats(enum intel_output_format format)
7569{
7570 if (format >= ARRAY_SIZE(output_format_str))
7571 return "invalid";
7572 return output_format_str[format];
7573}
7574
7575static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
7576{
7577 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
7578 struct drm_i915_private *i915 = to_i915(plane->base.dev);
7579 const struct drm_framebuffer *fb = plane_state->hw.fb;
7580
7581 if (!fb) {
7582 drm_dbg_kms(&i915->drm,
7583 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
7584 plane->base.base.id, plane->base.name,
7585 yesno(plane_state->uapi.visible));
7586 return;
7587 }
7588
7589 drm_dbg_kms(&i915->drm,
7590 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
7591 plane->base.base.id, plane->base.name,
7592 fb->base.id, fb->width, fb->height, &fb->format->format,
7593 fb->modifier, yesno(plane_state->uapi.visible));
7594 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
7595 plane_state->hw.rotation, plane_state->scaler_id);
7596 if (plane_state->uapi.visible)
7597 drm_dbg_kms(&i915->drm,
7598 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
7599 DRM_RECT_FP_ARG(&plane_state->uapi.src),
7600 DRM_RECT_ARG(&plane_state->uapi.dst));
7601}
7602
7603static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
7604 struct intel_atomic_state *state,
7605 const char *context)
7606{
7607 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
7608 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7609 const struct intel_plane_state *plane_state;
7610 struct intel_plane *plane;
7611 char buf[64];
7612 int i;
7613
7614 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
7615 crtc->base.base.id, crtc->base.name,
7616 yesno(pipe_config->hw.enable), context);
7617
7618 if (!pipe_config->hw.enable)
7619 goto dump_planes;
7620
7621 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
7622 drm_dbg_kms(&dev_priv->drm,
7623 "active: %s, output_types: %s (0x%x), output format: %s\n",
7624 yesno(pipe_config->hw.active),
7625 buf, pipe_config->output_types,
7626 output_formats(pipe_config->output_format));
7627
7628 drm_dbg_kms(&dev_priv->drm,
7629 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
7630 transcoder_name(pipe_config->cpu_transcoder),
7631 pipe_config->pipe_bpp, pipe_config->dither);
7632
7633 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
7634 transcoder_name(pipe_config->mst_master_transcoder));
7635
7636 drm_dbg_kms(&dev_priv->drm,
7637 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
7638 transcoder_name(pipe_config->master_transcoder),
7639 pipe_config->sync_mode_slaves_mask);
7640
7641 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
7642 pipe_config->bigjoiner_slave ? "slave" :
7643 pipe_config->bigjoiner ? "master" : "no");
7644
7645 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
7646 enableddisabled(pipe_config->splitter.enable),
7647 pipe_config->splitter.link_count,
7648 pipe_config->splitter.pixel_overlap);
7649
7650 if (pipe_config->has_pch_encoder)
7651 intel_dump_m_n_config(pipe_config, "fdi",
7652 pipe_config->fdi_lanes,
7653 &pipe_config->fdi_m_n);
7654
7655 if (intel_crtc_has_dp_encoder(pipe_config)) {
7656 intel_dump_m_n_config(pipe_config, "dp m_n",
7657 pipe_config->lane_count, &pipe_config->dp_m_n);
7658 if (pipe_config->has_drrs)
7659 intel_dump_m_n_config(pipe_config, "dp m2_n2",
7660 pipe_config->lane_count,
7661 &pipe_config->dp_m2_n2);
7662 }
7663
7664 drm_dbg_kms(&dev_priv->drm,
7665 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
7666 pipe_config->has_audio, pipe_config->has_infoframe,
7667 pipe_config->infoframes.enable);
7668
7669 if (pipe_config->infoframes.enable &
7670 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
7671 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
7672 pipe_config->infoframes.gcp);
7673 if (pipe_config->infoframes.enable &
7674 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
7675 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
7676 if (pipe_config->infoframes.enable &
7677 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
7678 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
7679 if (pipe_config->infoframes.enable &
7680 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
7681 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
7682 if (pipe_config->infoframes.enable &
7683 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
7684 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7685 if (pipe_config->infoframes.enable &
7686 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
7687 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7688 if (pipe_config->infoframes.enable &
7689 intel_hdmi_infoframe_enable(DP_SDP_VSC))
7690 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
7691
7692 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
7693 yesno(pipe_config->vrr.enable),
7694 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
7695 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
7696 pipe_config->vrr.flipline,
7697 intel_vrr_vmin_vblank_start(pipe_config),
7698 intel_vrr_vmax_vblank_start(pipe_config));
7699
7700 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
7701 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
7702 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
7703 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
7704 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
7705 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
7706 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
7707 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
7708 drm_dbg_kms(&dev_priv->drm,
7709 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
7710 pipe_config->port_clock,
7711 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
7712 pipe_config->pixel_rate);
7713
7714 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
7715 pipe_config->linetime, pipe_config->ips_linetime);
7716
7717 if (DISPLAY_VER(dev_priv) >= 9)
7718 drm_dbg_kms(&dev_priv->drm,
7719 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
7720 crtc->num_scalers,
7721 pipe_config->scaler_state.scaler_users,
7722 pipe_config->scaler_state.scaler_id);
7723
7724 if (HAS_GMCH(dev_priv))
7725 drm_dbg_kms(&dev_priv->drm,
7726 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7727 pipe_config->gmch_pfit.control,
7728 pipe_config->gmch_pfit.pgm_ratios,
7729 pipe_config->gmch_pfit.lvds_border_bits);
7730 else
7731 drm_dbg_kms(&dev_priv->drm,
7732 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
7733 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
7734 enableddisabled(pipe_config->pch_pfit.enabled),
7735 yesno(pipe_config->pch_pfit.force_thru));
7736
7737 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
7738 pipe_config->ips_enabled, pipe_config->double_wide);
7739
7740 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
7741
7742 if (IS_CHERRYVIEW(dev_priv))
7743 drm_dbg_kms(&dev_priv->drm,
7744 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7745 pipe_config->cgm_mode, pipe_config->gamma_mode,
7746 pipe_config->gamma_enable, pipe_config->csc_enable);
7747 else
7748 drm_dbg_kms(&dev_priv->drm,
7749 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7750 pipe_config->csc_mode, pipe_config->gamma_mode,
7751 pipe_config->gamma_enable, pipe_config->csc_enable);
7752
7753 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
7754 pipe_config->hw.degamma_lut ?
7755 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
7756 pipe_config->hw.gamma_lut ?
7757 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
7758
7759dump_planes:
7760 if (!state)
7761 return;
7762
7763 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7764 if (plane->pipe == crtc->pipe)
7765 intel_dump_plane_state(plane_state);
7766 }
7767}
7768
7769static bool check_digital_port_conflicts(struct intel_atomic_state *state)
7770{
7771 struct drm_device *dev = state->base.dev;
7772 struct drm_connector *connector;
7773 struct drm_connector_list_iter conn_iter;
7774 unsigned int used_ports = 0;
7775 unsigned int used_mst_ports = 0;
7776 bool ret = true;
7777
7778 /*
7779 * We're going to peek into connector->state,
7780 * hence connection_mutex must be held.
7781 */
7782 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
7783
7784 /*
7785 * Walk the connector list instead of the encoder
7786 * list to detect the problem on ddi platforms
7787 * where there's just one encoder per digital port.
7788 */
7789 drm_connector_list_iter_begin(dev, &conn_iter);
7790 drm_for_each_connector_iter(connector, &conn_iter) {
7791 struct drm_connector_state *connector_state;
7792 struct intel_encoder *encoder;
7793
7794 connector_state =
7795 drm_atomic_get_new_connector_state(&state->base,
7796 connector);
7797 if (!connector_state)
7798 connector_state = connector->state;
7799
7800 if (!connector_state->best_encoder)
7801 continue;
7802
7803 encoder = to_intel_encoder(connector_state->best_encoder);
7804
7805 drm_WARN_ON(dev, !connector_state->crtc);
7806
7807 switch (encoder->type) {
7808 case INTEL_OUTPUT_DDI:
7809 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
7810 break;
7811 fallthrough;
7812 case INTEL_OUTPUT_DP:
7813 case INTEL_OUTPUT_HDMI:
7814 case INTEL_OUTPUT_EDP:
7815 /* the same port mustn't appear more than once */
7816 if (used_ports & BIT(encoder->port))
7817 ret = false;
7818
7819 used_ports |= BIT(encoder->port);
7820 break;
7821 case INTEL_OUTPUT_DP_MST:
7822 used_mst_ports |=
7823 1 << encoder->port;
7824 break;
7825 default:
7826 break;
7827 }
7828 }
7829 drm_connector_list_iter_end(&conn_iter);
7830
7831 /* can't mix MST and SST/HDMI on the same port */
7832 if (used_ports & used_mst_ports)
7833 return false;
7834
7835 return ret;
7836}
7837
7838static void
7839intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
7840 struct intel_crtc_state *crtc_state)
7841{
7842 const struct intel_crtc_state *from_crtc_state = crtc_state;
7843
7844 if (crtc_state->bigjoiner_slave) {
7845 from_crtc_state = intel_atomic_get_new_crtc_state(state,
7846 crtc_state->bigjoiner_linked_crtc);
7847
7848 /* No need to copy state if the master state is unchanged */
7849 if (!from_crtc_state)
7850 return;
7851 }
7852
7853 intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
7854}
7855
7856static void
7857intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
7858 struct intel_crtc_state *crtc_state)
7859{
7860 crtc_state->hw.enable = crtc_state->uapi.enable;
7861 crtc_state->hw.active = crtc_state->uapi.active;
7862 crtc_state->hw.mode = crtc_state->uapi.mode;
7863 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
7864 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
7865
7866 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
7867}
7868
7869static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
7870{
7871 if (crtc_state->bigjoiner_slave)
7872 return;
7873
7874 crtc_state->uapi.enable = crtc_state->hw.enable;
7875 crtc_state->uapi.active = crtc_state->hw.active;
7876 drm_WARN_ON(crtc_state->uapi.crtc->dev,
7877 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
7878
7879 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
7880 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
7881
7882 /* copy color blobs to uapi */
7883 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
7884 crtc_state->hw.degamma_lut);
7885 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
7886 crtc_state->hw.gamma_lut);
7887 drm_property_replace_blob(&crtc_state->uapi.ctm,
7888 crtc_state->hw.ctm);
7889}
7890
7891static int
7892copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
7893 const struct intel_crtc_state *from_crtc_state)
7894{
7895 struct intel_crtc_state *saved_state;
7896 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7897
7898 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
7899 if (!saved_state)
7900 return -ENOMEM;
7901
7902 saved_state->uapi = crtc_state->uapi;
7903 saved_state->scaler_state = crtc_state->scaler_state;
7904 saved_state->shared_dpll = crtc_state->shared_dpll;
7905 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7906 saved_state->crc_enabled = crtc_state->crc_enabled;
7907
7908 intel_crtc_free_hw_state(crtc_state);
7909 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7910 kfree(saved_state);
7911
7912 /* Re-init hw state */
7913 memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
7914 crtc_state->hw.enable = from_crtc_state->hw.enable;
7915 crtc_state->hw.active = from_crtc_state->hw.active;
7916 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
7917 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
7918
7919 /* Some fixups */
7920 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
7921 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
7922 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
7923 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
7924 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
7925 crtc_state->bigjoiner_slave = true;
7926 crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
7927 crtc_state->has_audio = false;
7928
7929 return 0;
7930}
7931
7932static int
7933intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
7934 struct intel_crtc_state *crtc_state)
7935{
7936 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7937 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7938 struct intel_crtc_state *saved_state;
7939
7940 saved_state = intel_crtc_state_alloc(crtc);
7941 if (!saved_state)
7942 return -ENOMEM;
7943
7944 /* free the old crtc_state->hw members */
7945 intel_crtc_free_hw_state(crtc_state);
7946
7947 /* FIXME: before the switch to atomic started, a new pipe_config was
7948 * kzalloc'd. Code that depends on any field being zero should be
7949 * fixed, so that the crtc_state can be safely duplicated. For now,
7950 * only fields that are know to not cause problems are preserved. */
7951
7952 saved_state->uapi = crtc_state->uapi;
7953 saved_state->scaler_state = crtc_state->scaler_state;
7954 saved_state->shared_dpll = crtc_state->shared_dpll;
7955 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7956 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
7957 sizeof(saved_state->icl_port_dplls));
7958 saved_state->crc_enabled = crtc_state->crc_enabled;
7959 if (IS_G4X(dev_priv) ||
7960 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7961 saved_state->wm = crtc_state->wm;
7962
7963 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7964 kfree(saved_state);
7965
7966 intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
7967
7968 return 0;
7969}
7970
7971static int
7972intel_modeset_pipe_config(struct intel_atomic_state *state,
7973 struct intel_crtc_state *pipe_config)
7974{
7975 struct drm_crtc *crtc = pipe_config->uapi.crtc;
7976 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7977 struct drm_connector *connector;
7978 struct drm_connector_state *connector_state;
7979 int base_bpp, ret, i;
7980 bool retry = true;
7981
7982 pipe_config->cpu_transcoder =
7983 (enum transcoder) to_intel_crtc(crtc)->pipe;
7984
7985 /*
7986 * Sanitize sync polarity flags based on requested ones. If neither
7987 * positive or negative polarity is requested, treat this as meaning
7988 * negative polarity.
7989 */
7990 if (!(pipe_config->hw.adjusted_mode.flags &
7991 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
7992 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
7993
7994 if (!(pipe_config->hw.adjusted_mode.flags &
7995 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
7996 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
7997
7998 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7999 pipe_config);
8000 if (ret)
8001 return ret;
8002
8003 base_bpp = pipe_config->pipe_bpp;
8004
8005 /*
8006 * Determine the real pipe dimensions. Note that stereo modes can
8007 * increase the actual pipe size due to the frame doubling and
8008 * insertion of additional space for blanks between the frame. This
8009 * is stored in the crtc timings. We use the requested mode to do this
8010 * computation to clearly distinguish it from the adjusted mode, which
8011 * can be changed by the connectors in the below retry loop.
8012 */
8013 drm_mode_get_hv_timing(&pipe_config->hw.mode,
8014 &pipe_config->pipe_src_w,
8015 &pipe_config->pipe_src_h);
8016
8017 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8018 struct intel_encoder *encoder =
8019 to_intel_encoder(connector_state->best_encoder);
8020
8021 if (connector_state->crtc != crtc)
8022 continue;
8023
8024 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
8025 drm_dbg_kms(&i915->drm,
8026 "rejecting invalid cloning configuration\n");
8027 return -EINVAL;
8028 }
8029
8030 /*
8031 * Determine output_types before calling the .compute_config()
8032 * hooks so that the hooks can use this information safely.
8033 */
8034 if (encoder->compute_output_type)
8035 pipe_config->output_types |=
8036 BIT(encoder->compute_output_type(encoder, pipe_config,
8037 connector_state));
8038 else
8039 pipe_config->output_types |= BIT(encoder->type);
8040 }
8041
8042encoder_retry:
8043 /* Ensure the port clock defaults are reset when retrying. */
8044 pipe_config->port_clock = 0;
8045 pipe_config->pixel_multiplier = 1;
8046
8047 /* Fill in default crtc timings, allow encoders to overwrite them. */
8048 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
8049 CRTC_STEREO_DOUBLE);
8050
8051 /* Pass our mode to the connectors and the CRTC to give them a chance to
8052 * adjust it according to limitations or connector properties, and also
8053 * a chance to reject the mode entirely.
8054 */
8055 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8056 struct intel_encoder *encoder =
8057 to_intel_encoder(connector_state->best_encoder);
8058
8059 if (connector_state->crtc != crtc)
8060 continue;
8061
8062 ret = encoder->compute_config(encoder, pipe_config,
8063 connector_state);
8064 if (ret < 0) {
8065 if (ret != -EDEADLK)
8066 drm_dbg_kms(&i915->drm,
8067 "Encoder config failure: %d\n",
8068 ret);
8069 return ret;
8070 }
8071 }
8072
8073 /* Set default port clock if not overwritten by the encoder. Needs to be
8074 * done afterwards in case the encoder adjusts the mode. */
8075 if (!pipe_config->port_clock)
8076 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
8077 * pipe_config->pixel_multiplier;
8078
8079 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8080 if (ret == -EDEADLK)
8081 return ret;
8082 if (ret < 0) {
8083 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
8084 return ret;
8085 }
8086
8087 if (ret == I915_DISPLAY_CONFIG_RETRY) {
8088 if (drm_WARN(&i915->drm, !retry,
8089 "loop in pipe configuration computation\n"))
8090 return -EINVAL;
8091
8092 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
8093 retry = false;
8094 goto encoder_retry;
8095 }
8096
8097 /* Dithering seems to not pass-through bits correctly when it should, so
8098 * only enable it on 6bpc panels and when its not a compliance
8099 * test requesting 6bpc video pattern.
8100 */
8101 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
8102 !pipe_config->dither_force_disable;
8103 drm_dbg_kms(&i915->drm,
8104 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
8105 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8106
8107 return 0;
8108}
8109
8110static int
8111intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
8112{
8113 struct intel_atomic_state *state =
8114 to_intel_atomic_state(crtc_state->uapi.state);
8115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8116 struct drm_connector_state *conn_state;
8117 struct drm_connector *connector;
8118 int i;
8119
8120 for_each_new_connector_in_state(&state->base, connector,
8121 conn_state, i) {
8122 struct intel_encoder *encoder =
8123 to_intel_encoder(conn_state->best_encoder);
8124 int ret;
8125
8126 if (conn_state->crtc != &crtc->base ||
8127 !encoder->compute_config_late)
8128 continue;
8129
8130 ret = encoder->compute_config_late(encoder, crtc_state,
8131 conn_state);
8132 if (ret)
8133 return ret;
8134 }
8135
8136 return 0;
8137}
8138
8139bool intel_fuzzy_clock_check(int clock1, int clock2)
8140{
8141 int diff;
8142
8143 if (clock1 == clock2)
8144 return true;
8145
8146 if (!clock1 || !clock2)
8147 return false;
8148
8149 diff = abs(clock1 - clock2);
8150
8151 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8152 return true;
8153
8154 return false;
8155}
8156
8157static bool
8158intel_compare_m_n(unsigned int m, unsigned int n,
8159 unsigned int m2, unsigned int n2,
8160 bool exact)
8161{
8162 if (m == m2 && n == n2)
8163 return true;
8164
8165 if (exact || !m || !n || !m2 || !n2)
8166 return false;
8167
8168 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
8169
8170 if (n > n2) {
8171 while (n > n2) {
8172 m2 <<= 1;
8173 n2 <<= 1;
8174 }
8175 } else if (n < n2) {
8176 while (n < n2) {
8177 m <<= 1;
8178 n <<= 1;
8179 }
8180 }
8181
8182 if (n != n2)
8183 return false;
8184
8185 return intel_fuzzy_clock_check(m, m2);
8186}
8187
8188static bool
8189intel_compare_link_m_n(const struct intel_link_m_n *m_n,
8190 const struct intel_link_m_n *m2_n2,
8191 bool exact)
8192{
8193 return m_n->tu == m2_n2->tu &&
8194 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
8195 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
8196 intel_compare_m_n(m_n->link_m, m_n->link_n,
8197 m2_n2->link_m, m2_n2->link_n, exact);
8198}
8199
8200static bool
8201intel_compare_infoframe(const union hdmi_infoframe *a,
8202 const union hdmi_infoframe *b)
8203{
8204 return memcmp(a, b, sizeof(*a)) == 0;
8205}
8206
8207static bool
8208intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
8209 const struct drm_dp_vsc_sdp *b)
8210{
8211 return memcmp(a, b, sizeof(*a)) == 0;
8212}
8213
8214static void
8215pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
8216 bool fastset, const char *name,
8217 const union hdmi_infoframe *a,
8218 const union hdmi_infoframe *b)
8219{
8220 if (fastset) {
8221 if (!drm_debug_enabled(DRM_UT_KMS))
8222 return;
8223
8224 drm_dbg_kms(&dev_priv->drm,
8225 "fastset mismatch in %s infoframe\n", name);
8226 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8227 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
8228 drm_dbg_kms(&dev_priv->drm, "found:\n");
8229 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
8230 } else {
8231 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
8232 drm_err(&dev_priv->drm, "expected:\n");
8233 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
8234 drm_err(&dev_priv->drm, "found:\n");
8235 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
8236 }
8237}
8238
8239static void
8240pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
8241 bool fastset, const char *name,
8242 const struct drm_dp_vsc_sdp *a,
8243 const struct drm_dp_vsc_sdp *b)
8244{
8245 if (fastset) {
8246 if (!drm_debug_enabled(DRM_UT_KMS))
8247 return;
8248
8249 drm_dbg_kms(&dev_priv->drm,
8250 "fastset mismatch in %s dp sdp\n", name);
8251 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8252 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
8253 drm_dbg_kms(&dev_priv->drm, "found:\n");
8254 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
8255 } else {
8256 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
8257 drm_err(&dev_priv->drm, "expected:\n");
8258 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
8259 drm_err(&dev_priv->drm, "found:\n");
8260 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
8261 }
8262}
8263
8264static void __printf(4, 5)
8265pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
8266 const char *name, const char *format, ...)
8267{
8268 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
8269 struct va_format vaf;
8270 va_list args;
8271
8272 va_start(args, format);
8273 vaf.fmt = format;
8274 vaf.va = &args;
8275
8276 if (fastset)
8277 drm_dbg_kms(&i915->drm,
8278 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
8279 crtc->base.base.id, crtc->base.name, name, &vaf);
8280 else
8281 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
8282 crtc->base.base.id, crtc->base.name, name, &vaf);
8283
8284 va_end(args);
8285}
8286
8287static bool fastboot_enabled(struct drm_i915_private *dev_priv)
8288{
8289 if (dev_priv->params.fastboot != -1)
8290 return dev_priv->params.fastboot;
8291
8292 /* Enable fastboot by default on Skylake and newer */
8293 if (DISPLAY_VER(dev_priv) >= 9)
8294 return true;
8295
8296 /* Enable fastboot by default on VLV and CHV */
8297 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8298 return true;
8299
8300 /* Disabled by default on all others */
8301 return false;
8302}
8303
8304static bool
8305intel_pipe_config_compare(const struct intel_crtc_state *current_config,
8306 const struct intel_crtc_state *pipe_config,
8307 bool fastset)
8308{
8309 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
8310 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
8311 bool ret = true;
8312 u32 bp_gamma = 0;
8313 bool fixup_inherited = fastset &&
8314 current_config->inherited && !pipe_config->inherited;
8315
8316 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
8317 drm_dbg_kms(&dev_priv->drm,
8318 "initial modeset and fastboot not set\n");
8319 ret = false;
8320 }
8321
8322#define PIPE_CONF_CHECK_X(name) do { \
8323 if (current_config->name != pipe_config->name) { \
8324 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8325 "(expected 0x%08x, found 0x%08x)", \
8326 current_config->name, \
8327 pipe_config->name); \
8328 ret = false; \
8329 } \
8330} while (0)
8331
8332#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
8333 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
8334 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8335 "(expected 0x%08x, found 0x%08x)", \
8336 current_config->name & (mask), \
8337 pipe_config->name & (mask)); \
8338 ret = false; \
8339 } \
8340} while (0)
8341
8342#define PIPE_CONF_CHECK_I(name) do { \
8343 if (current_config->name != pipe_config->name) { \
8344 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8345 "(expected %i, found %i)", \
8346 current_config->name, \
8347 pipe_config->name); \
8348 ret = false; \
8349 } \
8350} while (0)
8351
8352#define PIPE_CONF_CHECK_BOOL(name) do { \
8353 if (current_config->name != pipe_config->name) { \
8354 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8355 "(expected %s, found %s)", \
8356 yesno(current_config->name), \
8357 yesno(pipe_config->name)); \
8358 ret = false; \
8359 } \
8360} while (0)
8361
8362/*
8363 * Checks state where we only read out the enabling, but not the entire
8364 * state itself (like full infoframes or ELD for audio). These states
8365 * require a full modeset on bootup to fix up.
8366 */
8367#define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
8368 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
8369 PIPE_CONF_CHECK_BOOL(name); \
8370 } else { \
8371 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8372 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
8373 yesno(current_config->name), \
8374 yesno(pipe_config->name)); \
8375 ret = false; \
8376 } \
8377} while (0)
8378
8379#define PIPE_CONF_CHECK_P(name) do { \
8380 if (current_config->name != pipe_config->name) { \
8381 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8382 "(expected %p, found %p)", \
8383 current_config->name, \
8384 pipe_config->name); \
8385 ret = false; \
8386 } \
8387} while (0)
8388
8389#define PIPE_CONF_CHECK_M_N(name) do { \
8390 if (!intel_compare_link_m_n(¤t_config->name, \
8391 &pipe_config->name,\
8392 !fastset)) { \
8393 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8394 "(expected tu %i gmch %i/%i link %i/%i, " \
8395 "found tu %i, gmch %i/%i link %i/%i)", \
8396 current_config->name.tu, \
8397 current_config->name.gmch_m, \
8398 current_config->name.gmch_n, \
8399 current_config->name.link_m, \
8400 current_config->name.link_n, \
8401 pipe_config->name.tu, \
8402 pipe_config->name.gmch_m, \
8403 pipe_config->name.gmch_n, \
8404 pipe_config->name.link_m, \
8405 pipe_config->name.link_n); \
8406 ret = false; \
8407 } \
8408} while (0)
8409
8410/* This is required for BDW+ where there is only one set of registers for
8411 * switching between high and low RR.
8412 * This macro can be used whenever a comparison has to be made between one
8413 * hw state and multiple sw state variables.
8414 */
8415#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
8416 if (!intel_compare_link_m_n(¤t_config->name, \
8417 &pipe_config->name, !fastset) && \
8418 !intel_compare_link_m_n(¤t_config->alt_name, \
8419 &pipe_config->name, !fastset)) { \
8420 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8421 "(expected tu %i gmch %i/%i link %i/%i, " \
8422 "or tu %i gmch %i/%i link %i/%i, " \
8423 "found tu %i, gmch %i/%i link %i/%i)", \
8424 current_config->name.tu, \
8425 current_config->name.gmch_m, \
8426 current_config->name.gmch_n, \
8427 current_config->name.link_m, \
8428 current_config->name.link_n, \
8429 current_config->alt_name.tu, \
8430 current_config->alt_name.gmch_m, \
8431 current_config->alt_name.gmch_n, \
8432 current_config->alt_name.link_m, \
8433 current_config->alt_name.link_n, \
8434 pipe_config->name.tu, \
8435 pipe_config->name.gmch_m, \
8436 pipe_config->name.gmch_n, \
8437 pipe_config->name.link_m, \
8438 pipe_config->name.link_n); \
8439 ret = false; \
8440 } \
8441} while (0)
8442
8443#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
8444 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8445 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8446 "(%x) (expected %i, found %i)", \
8447 (mask), \
8448 current_config->name & (mask), \
8449 pipe_config->name & (mask)); \
8450 ret = false; \
8451 } \
8452} while (0)
8453
8454#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
8455 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8456 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8457 "(expected %i, found %i)", \
8458 current_config->name, \
8459 pipe_config->name); \
8460 ret = false; \
8461 } \
8462} while (0)
8463
8464#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
8465 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
8466 &pipe_config->infoframes.name)) { \
8467 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
8468 ¤t_config->infoframes.name, \
8469 &pipe_config->infoframes.name); \
8470 ret = false; \
8471 } \
8472} while (0)
8473
8474#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
8475 if (!current_config->has_psr && !pipe_config->has_psr && \
8476 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
8477 &pipe_config->infoframes.name)) { \
8478 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
8479 ¤t_config->infoframes.name, \
8480 &pipe_config->infoframes.name); \
8481 ret = false; \
8482 } \
8483} while (0)
8484
8485#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
8486 if (current_config->name1 != pipe_config->name1) { \
8487 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
8488 "(expected %i, found %i, won't compare lut values)", \
8489 current_config->name1, \
8490 pipe_config->name1); \
8491 ret = false;\
8492 } else { \
8493 if (!intel_color_lut_equal(current_config->name2, \
8494 pipe_config->name2, pipe_config->name1, \
8495 bit_precision)) { \
8496 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
8497 "hw_state doesn't match sw_state"); \
8498 ret = false; \
8499 } \
8500 } \
8501} while (0)
8502
8503#define PIPE_CONF_QUIRK(quirk) \
8504 ((current_config->quirks | pipe_config->quirks) & (quirk))
8505
8506 PIPE_CONF_CHECK_I(cpu_transcoder);
8507
8508 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
8509 PIPE_CONF_CHECK_I(fdi_lanes);
8510 PIPE_CONF_CHECK_M_N(fdi_m_n);
8511
8512 PIPE_CONF_CHECK_I(lane_count);
8513 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
8514
8515 if (DISPLAY_VER(dev_priv) < 8) {
8516 PIPE_CONF_CHECK_M_N(dp_m_n);
8517
8518 if (current_config->has_drrs)
8519 PIPE_CONF_CHECK_M_N(dp_m2_n2);
8520 } else
8521 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
8522
8523 PIPE_CONF_CHECK_X(output_types);
8524
8525 /* FIXME do the readout properly and get rid of this quirk */
8526 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8527 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
8528 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
8529 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
8530 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
8531 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
8532 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
8533
8534 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
8535 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
8536 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
8537 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
8538 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
8539 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
8540
8541 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
8542 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
8543 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
8544 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
8545 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
8546 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
8547
8548 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
8549 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
8550 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
8551 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
8552 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
8553 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
8554
8555 PIPE_CONF_CHECK_I(pixel_multiplier);
8556
8557 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8558 DRM_MODE_FLAG_INTERLACE);
8559
8560 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8561 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8562 DRM_MODE_FLAG_PHSYNC);
8563 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8564 DRM_MODE_FLAG_NHSYNC);
8565 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8566 DRM_MODE_FLAG_PVSYNC);
8567 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8568 DRM_MODE_FLAG_NVSYNC);
8569 }
8570 }
8571
8572 PIPE_CONF_CHECK_I(output_format);
8573 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
8574 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
8575 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8576 PIPE_CONF_CHECK_BOOL(limited_color_range);
8577
8578 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
8579 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
8580 PIPE_CONF_CHECK_BOOL(has_infoframe);
8581 /* FIXME do the readout properly and get rid of this quirk */
8582 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8583 PIPE_CONF_CHECK_BOOL(fec_enable);
8584
8585 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
8586
8587 PIPE_CONF_CHECK_X(gmch_pfit.control);
8588 /* pfit ratios are autocomputed by the hw on gen4+ */
8589 if (DISPLAY_VER(dev_priv) < 4)
8590 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
8591 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
8592
8593 /*
8594 * Changing the EDP transcoder input mux
8595 * (A_ONOFF vs. A_ON) requires a full modeset.
8596 */
8597 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
8598
8599 if (!fastset) {
8600 PIPE_CONF_CHECK_I(pipe_src_w);
8601 PIPE_CONF_CHECK_I(pipe_src_h);
8602
8603 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
8604 if (current_config->pch_pfit.enabled) {
8605 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
8606 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
8607 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
8608 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
8609 }
8610
8611 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
8612 /* FIXME do the readout properly and get rid of this quirk */
8613 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8614 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
8615
8616 PIPE_CONF_CHECK_X(gamma_mode);
8617 if (IS_CHERRYVIEW(dev_priv))
8618 PIPE_CONF_CHECK_X(cgm_mode);
8619 else
8620 PIPE_CONF_CHECK_X(csc_mode);
8621 PIPE_CONF_CHECK_BOOL(gamma_enable);
8622 PIPE_CONF_CHECK_BOOL(csc_enable);
8623
8624 PIPE_CONF_CHECK_I(linetime);
8625 PIPE_CONF_CHECK_I(ips_linetime);
8626
8627 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
8628 if (bp_gamma)
8629 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
8630
8631 PIPE_CONF_CHECK_BOOL(has_psr);
8632 PIPE_CONF_CHECK_BOOL(has_psr2);
8633 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
8634 PIPE_CONF_CHECK_I(dc3co_exitline);
8635 }
8636
8637 PIPE_CONF_CHECK_BOOL(double_wide);
8638
8639 PIPE_CONF_CHECK_P(shared_dpll);
8640
8641 /* FIXME do the readout properly and get rid of this quirk */
8642 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8643 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8644 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8645 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8646 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8647 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
8648 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
8649 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
8650 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
8651 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
8652 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
8653 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
8654 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
8655 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
8656 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
8657 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
8658 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
8659 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
8660 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
8661 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
8662 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
8663 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
8664 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
8665 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
8666 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
8667 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
8668 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
8669 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
8670 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
8671 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
8672 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
8673 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
8674
8675 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
8676 PIPE_CONF_CHECK_X(dsi_pll.div);
8677
8678 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
8679 PIPE_CONF_CHECK_I(pipe_bpp);
8680
8681 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
8682 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
8683 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8684
8685 PIPE_CONF_CHECK_I(min_voltage_level);
8686 }
8687
8688 if (fastset && (current_config->has_psr || pipe_config->has_psr))
8689 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
8690 ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
8691 else
8692 PIPE_CONF_CHECK_X(infoframes.enable);
8693
8694 PIPE_CONF_CHECK_X(infoframes.gcp);
8695 PIPE_CONF_CHECK_INFOFRAME(avi);
8696 PIPE_CONF_CHECK_INFOFRAME(spd);
8697 PIPE_CONF_CHECK_INFOFRAME(hdmi);
8698 PIPE_CONF_CHECK_INFOFRAME(drm);
8699 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
8700
8701 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
8702 PIPE_CONF_CHECK_I(master_transcoder);
8703 PIPE_CONF_CHECK_BOOL(bigjoiner);
8704 PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
8705 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
8706
8707 PIPE_CONF_CHECK_I(dsc.compression_enable);
8708 PIPE_CONF_CHECK_I(dsc.dsc_split);
8709 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
8710
8711 PIPE_CONF_CHECK_BOOL(splitter.enable);
8712 PIPE_CONF_CHECK_I(splitter.link_count);
8713 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
8714
8715 PIPE_CONF_CHECK_I(mst_master_transcoder);
8716
8717 PIPE_CONF_CHECK_BOOL(vrr.enable);
8718 PIPE_CONF_CHECK_I(vrr.vmin);
8719 PIPE_CONF_CHECK_I(vrr.vmax);
8720 PIPE_CONF_CHECK_I(vrr.flipline);
8721 PIPE_CONF_CHECK_I(vrr.pipeline_full);
8722 PIPE_CONF_CHECK_I(vrr.guardband);
8723
8724#undef PIPE_CONF_CHECK_X
8725#undef PIPE_CONF_CHECK_I
8726#undef PIPE_CONF_CHECK_BOOL
8727#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
8728#undef PIPE_CONF_CHECK_P
8729#undef PIPE_CONF_CHECK_FLAGS
8730#undef PIPE_CONF_CHECK_CLOCK_FUZZY
8731#undef PIPE_CONF_CHECK_COLOR_LUT
8732#undef PIPE_CONF_QUIRK
8733
8734 return ret;
8735}
8736
8737static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
8738 const struct intel_crtc_state *pipe_config)
8739{
8740 if (pipe_config->has_pch_encoder) {
8741 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
8742 &pipe_config->fdi_m_n);
8743 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
8744
8745 /*
8746 * FDI already provided one idea for the dotclock.
8747 * Yell if the encoder disagrees.
8748 */
8749 drm_WARN(&dev_priv->drm,
8750 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
8751 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8752 fdi_dotclock, dotclock);
8753 }
8754}
8755
8756static void verify_wm_state(struct intel_crtc *crtc,
8757 struct intel_crtc_state *new_crtc_state)
8758{
8759 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8760 struct skl_hw_state {
8761 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
8762 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
8763 struct skl_pipe_wm wm;
8764 } *hw;
8765 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
8766 int level, max_level = ilk_wm_max_level(dev_priv);
8767 struct intel_plane *plane;
8768 u8 hw_enabled_slices;
8769
8770 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
8771 return;
8772
8773 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
8774 if (!hw)
8775 return;
8776
8777 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
8778
8779 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
8780
8781 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
8782
8783 if (DISPLAY_VER(dev_priv) >= 11 &&
8784 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
8785 drm_err(&dev_priv->drm,
8786 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
8787 dev_priv->dbuf.enabled_slices,
8788 hw_enabled_slices);
8789
8790 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
8791 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
8792 const struct skl_wm_level *hw_wm_level, *sw_wm_level;
8793
8794 /* Watermarks */
8795 for (level = 0; level <= max_level; level++) {
8796 hw_wm_level = &hw->wm.planes[plane->id].wm[level];
8797 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
8798
8799 if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
8800 continue;
8801
8802 drm_err(&dev_priv->drm,
8803 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8804 plane->base.base.id, plane->base.name, level,
8805 sw_wm_level->enable,
8806 sw_wm_level->blocks,
8807 sw_wm_level->lines,
8808 hw_wm_level->enable,
8809 hw_wm_level->blocks,
8810 hw_wm_level->lines);
8811 }
8812
8813 hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
8814 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
8815
8816 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8817 drm_err(&dev_priv->drm,
8818 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8819 plane->base.base.id, plane->base.name,
8820 sw_wm_level->enable,
8821 sw_wm_level->blocks,
8822 sw_wm_level->lines,
8823 hw_wm_level->enable,
8824 hw_wm_level->blocks,
8825 hw_wm_level->lines);
8826 }
8827
8828 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
8829 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
8830
8831 if (HAS_HW_SAGV_WM(dev_priv) &&
8832 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8833 drm_err(&dev_priv->drm,
8834 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8835 plane->base.base.id, plane->base.name,
8836 sw_wm_level->enable,
8837 sw_wm_level->blocks,
8838 sw_wm_level->lines,
8839 hw_wm_level->enable,
8840 hw_wm_level->blocks,
8841 hw_wm_level->lines);
8842 }
8843
8844 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
8845 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
8846
8847 if (HAS_HW_SAGV_WM(dev_priv) &&
8848 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8849 drm_err(&dev_priv->drm,
8850 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8851 plane->base.base.id, plane->base.name,
8852 sw_wm_level->enable,
8853 sw_wm_level->blocks,
8854 sw_wm_level->lines,
8855 hw_wm_level->enable,
8856 hw_wm_level->blocks,
8857 hw_wm_level->lines);
8858 }
8859
8860 /* DDB */
8861 hw_ddb_entry = &hw->ddb_y[plane->id];
8862 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
8863
8864 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
8865 drm_err(&dev_priv->drm,
8866 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
8867 plane->base.base.id, plane->base.name,
8868 sw_ddb_entry->start, sw_ddb_entry->end,
8869 hw_ddb_entry->start, hw_ddb_entry->end);
8870 }
8871 }
8872
8873 kfree(hw);
8874}
8875
8876static void
8877verify_connector_state(struct intel_atomic_state *state,
8878 struct intel_crtc *crtc)
8879{
8880 struct drm_connector *connector;
8881 struct drm_connector_state *new_conn_state;
8882 int i;
8883
8884 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
8885 struct drm_encoder *encoder = connector->encoder;
8886 struct intel_crtc_state *crtc_state = NULL;
8887
8888 if (new_conn_state->crtc != &crtc->base)
8889 continue;
8890
8891 if (crtc)
8892 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
8893
8894 intel_connector_verify_state(crtc_state, new_conn_state);
8895
8896 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
8897 "connector's atomic encoder doesn't match legacy encoder\n");
8898 }
8899}
8900
8901static void
8902verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
8903{
8904 struct intel_encoder *encoder;
8905 struct drm_connector *connector;
8906 struct drm_connector_state *old_conn_state, *new_conn_state;
8907 int i;
8908
8909 for_each_intel_encoder(&dev_priv->drm, encoder) {
8910 bool enabled = false, found = false;
8911 enum pipe pipe;
8912
8913 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
8914 encoder->base.base.id,
8915 encoder->base.name);
8916
8917 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
8918 new_conn_state, i) {
8919 if (old_conn_state->best_encoder == &encoder->base)
8920 found = true;
8921
8922 if (new_conn_state->best_encoder != &encoder->base)
8923 continue;
8924 found = enabled = true;
8925
8926 I915_STATE_WARN(new_conn_state->crtc !=
8927 encoder->base.crtc,
8928 "connector's crtc doesn't match encoder crtc\n");
8929 }
8930
8931 if (!found)
8932 continue;
8933
8934 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8935 "encoder's enabled state mismatch "
8936 "(expected %i, found %i)\n",
8937 !!encoder->base.crtc, enabled);
8938
8939 if (!encoder->base.crtc) {
8940 bool active;
8941
8942 active = encoder->get_hw_state(encoder, &pipe);
8943 I915_STATE_WARN(active,
8944 "encoder detached but still enabled on pipe %c.\n",
8945 pipe_name(pipe));
8946 }
8947 }
8948}
8949
8950static void
8951verify_crtc_state(struct intel_crtc *crtc,
8952 struct intel_crtc_state *old_crtc_state,
8953 struct intel_crtc_state *new_crtc_state)
8954{
8955 struct drm_device *dev = crtc->base.dev;
8956 struct drm_i915_private *dev_priv = to_i915(dev);
8957 struct intel_encoder *encoder;
8958 struct intel_crtc_state *pipe_config = old_crtc_state;
8959 struct drm_atomic_state *state = old_crtc_state->uapi.state;
8960 struct intel_crtc *master = crtc;
8961
8962 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
8963 intel_crtc_free_hw_state(old_crtc_state);
8964 intel_crtc_state_reset(old_crtc_state, crtc);
8965 old_crtc_state->uapi.state = state;
8966
8967 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
8968 crtc->base.name);
8969
8970 pipe_config->hw.enable = new_crtc_state->hw.enable;
8971
8972 intel_crtc_get_pipe_config(pipe_config);
8973
8974 /* we keep both pipes enabled on 830 */
8975 if (IS_I830(dev_priv) && pipe_config->hw.active)
8976 pipe_config->hw.active = new_crtc_state->hw.active;
8977
8978 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
8979 "crtc active state doesn't match with hw state "
8980 "(expected %i, found %i)\n",
8981 new_crtc_state->hw.active, pipe_config->hw.active);
8982
8983 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
8984 "transitional active state does not match atomic hw state "
8985 "(expected %i, found %i)\n",
8986 new_crtc_state->hw.active, crtc->active);
8987
8988 if (new_crtc_state->bigjoiner_slave)
8989 master = new_crtc_state->bigjoiner_linked_crtc;
8990
8991 for_each_encoder_on_crtc(dev, &master->base, encoder) {
8992 enum pipe pipe;
8993 bool active;
8994
8995 active = encoder->get_hw_state(encoder, &pipe);
8996 I915_STATE_WARN(active != new_crtc_state->hw.active,
8997 "[ENCODER:%i] active %i with crtc active %i\n",
8998 encoder->base.base.id, active,
8999 new_crtc_state->hw.active);
9000
9001 I915_STATE_WARN(active && master->pipe != pipe,
9002 "Encoder connected to wrong pipe %c\n",
9003 pipe_name(pipe));
9004
9005 if (active)
9006 intel_encoder_get_config(encoder, pipe_config);
9007 }
9008
9009 if (!new_crtc_state->hw.active)
9010 return;
9011
9012 intel_pipe_config_sanity_check(dev_priv, pipe_config);
9013
9014 if (!intel_pipe_config_compare(new_crtc_state,
9015 pipe_config, false)) {
9016 I915_STATE_WARN(1, "pipe state doesn't match!\n");
9017 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
9018 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
9019 }
9020}
9021
9022static void
9023intel_verify_planes(struct intel_atomic_state *state)
9024{
9025 struct intel_plane *plane;
9026 const struct intel_plane_state *plane_state;
9027 int i;
9028
9029 for_each_new_intel_plane_in_state(state, plane,
9030 plane_state, i)
9031 assert_plane(plane, plane_state->planar_slave ||
9032 plane_state->uapi.visible);
9033}
9034
9035static void
9036verify_single_dpll_state(struct drm_i915_private *dev_priv,
9037 struct intel_shared_dpll *pll,
9038 struct intel_crtc *crtc,
9039 struct intel_crtc_state *new_crtc_state)
9040{
9041 struct intel_dpll_hw_state dpll_hw_state;
9042 u8 pipe_mask;
9043 bool active;
9044
9045 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9046
9047 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
9048
9049 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
9050
9051 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
9052 I915_STATE_WARN(!pll->on && pll->active_mask,
9053 "pll in active use but not on in sw tracking\n");
9054 I915_STATE_WARN(pll->on && !pll->active_mask,
9055 "pll is on but not used by any active pipe\n");
9056 I915_STATE_WARN(pll->on != active,
9057 "pll on state mismatch (expected %i, found %i)\n",
9058 pll->on, active);
9059 }
9060
9061 if (!crtc) {
9062 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
9063 "more active pll users than references: 0x%x vs 0x%x\n",
9064 pll->active_mask, pll->state.pipe_mask);
9065
9066 return;
9067 }
9068
9069 pipe_mask = BIT(crtc->pipe);
9070
9071 if (new_crtc_state->hw.active)
9072 I915_STATE_WARN(!(pll->active_mask & pipe_mask),
9073 "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
9074 pipe_name(crtc->pipe), pll->active_mask);
9075 else
9076 I915_STATE_WARN(pll->active_mask & pipe_mask,
9077 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
9078 pipe_name(crtc->pipe), pll->active_mask);
9079
9080 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
9081 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
9082 pipe_mask, pll->state.pipe_mask);
9083
9084 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
9085 &dpll_hw_state,
9086 sizeof(dpll_hw_state)),
9087 "pll hw state mismatch\n");
9088}
9089
9090static void
9091verify_shared_dpll_state(struct intel_crtc *crtc,
9092 struct intel_crtc_state *old_crtc_state,
9093 struct intel_crtc_state *new_crtc_state)
9094{
9095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9096
9097 if (new_crtc_state->shared_dpll)
9098 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
9099
9100 if (old_crtc_state->shared_dpll &&
9101 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
9102 u8 pipe_mask = BIT(crtc->pipe);
9103 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
9104
9105 I915_STATE_WARN(pll->active_mask & pipe_mask,
9106 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
9107 pipe_name(crtc->pipe), pll->active_mask);
9108 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
9109 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
9110 pipe_name(crtc->pipe), pll->state.pipe_mask);
9111 }
9112}
9113
9114static void
9115intel_modeset_verify_crtc(struct intel_crtc *crtc,
9116 struct intel_atomic_state *state,
9117 struct intel_crtc_state *old_crtc_state,
9118 struct intel_crtc_state *new_crtc_state)
9119{
9120 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
9121 return;
9122
9123 verify_wm_state(crtc, new_crtc_state);
9124 verify_connector_state(state, crtc);
9125 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
9126 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
9127}
9128
9129static void
9130verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
9131{
9132 int i;
9133
9134 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
9135 verify_single_dpll_state(dev_priv,
9136 &dev_priv->dpll.shared_dplls[i],
9137 NULL, NULL);
9138}
9139
9140static void
9141intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
9142 struct intel_atomic_state *state)
9143{
9144 verify_encoder_state(dev_priv, state);
9145 verify_connector_state(state, NULL);
9146 verify_disabled_dpll_state(dev_priv);
9147}
9148
9149int intel_modeset_all_pipes(struct intel_atomic_state *state)
9150{
9151 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9152 struct intel_crtc *crtc;
9153
9154 /*
9155 * Add all pipes to the state, and force
9156 * a modeset on all the active ones.
9157 */
9158 for_each_intel_crtc(&dev_priv->drm, crtc) {
9159 struct intel_crtc_state *crtc_state;
9160 int ret;
9161
9162 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9163 if (IS_ERR(crtc_state))
9164 return PTR_ERR(crtc_state);
9165
9166 if (!crtc_state->hw.active ||
9167 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
9168 continue;
9169
9170 crtc_state->uapi.mode_changed = true;
9171
9172 ret = drm_atomic_add_affected_connectors(&state->base,
9173 &crtc->base);
9174 if (ret)
9175 return ret;
9176
9177 ret = intel_atomic_add_affected_planes(state, crtc);
9178 if (ret)
9179 return ret;
9180
9181 crtc_state->update_planes |= crtc_state->active_planes;
9182 }
9183
9184 return 0;
9185}
9186
9187static void
9188intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
9189{
9190 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9192 struct drm_display_mode adjusted_mode =
9193 crtc_state->hw.adjusted_mode;
9194
9195 if (crtc_state->vrr.enable) {
9196 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
9197 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
9198 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
9199 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
9200 }
9201
9202 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
9203
9204 crtc->mode_flags = crtc_state->mode_flags;
9205
9206 /*
9207 * The scanline counter increments at the leading edge of hsync.
9208 *
9209 * On most platforms it starts counting from vtotal-1 on the
9210 * first active line. That means the scanline counter value is
9211 * always one less than what we would expect. Ie. just after
9212 * start of vblank, which also occurs at start of hsync (on the
9213 * last active line), the scanline counter will read vblank_start-1.
9214 *
9215 * On gen2 the scanline counter starts counting from 1 instead
9216 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
9217 * to keep the value positive), instead of adding one.
9218 *
9219 * On HSW+ the behaviour of the scanline counter depends on the output
9220 * type. For DP ports it behaves like most other platforms, but on HDMI
9221 * there's an extra 1 line difference. So we need to add two instead of
9222 * one to the value.
9223 *
9224 * On VLV/CHV DSI the scanline counter would appear to increment
9225 * approx. 1/3 of a scanline before start of vblank. Unfortunately
9226 * that means we can't tell whether we're in vblank or not while
9227 * we're on that particular line. We must still set scanline_offset
9228 * to 1 so that the vblank timestamps come out correct when we query
9229 * the scanline counter from within the vblank interrupt handler.
9230 * However if queried just before the start of vblank we'll get an
9231 * answer that's slightly in the future.
9232 */
9233 if (DISPLAY_VER(dev_priv) == 2) {
9234 int vtotal;
9235
9236 vtotal = adjusted_mode.crtc_vtotal;
9237 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9238 vtotal /= 2;
9239
9240 crtc->scanline_offset = vtotal - 1;
9241 } else if (HAS_DDI(dev_priv) &&
9242 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
9243 crtc->scanline_offset = 2;
9244 } else {
9245 crtc->scanline_offset = 1;
9246 }
9247}
9248
9249static void intel_modeset_clear_plls(struct intel_atomic_state *state)
9250{
9251 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9252 struct intel_crtc_state *new_crtc_state;
9253 struct intel_crtc *crtc;
9254 int i;
9255
9256 if (!dev_priv->display.crtc_compute_clock)
9257 return;
9258
9259 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9260 if (!intel_crtc_needs_modeset(new_crtc_state))
9261 continue;
9262
9263 intel_release_shared_dplls(state, crtc);
9264 }
9265}
9266
9267/*
9268 * This implements the workaround described in the "notes" section of the mode
9269 * set sequence documentation. When going from no pipes or single pipe to
9270 * multiple pipes, and planes are enabled after the pipe, we need to wait at
9271 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
9272 */
9273static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
9274{
9275 struct intel_crtc_state *crtc_state;
9276 struct intel_crtc *crtc;
9277 struct intel_crtc_state *first_crtc_state = NULL;
9278 struct intel_crtc_state *other_crtc_state = NULL;
9279 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
9280 int i;
9281
9282 /* look at all crtc's that are going to be enabled in during modeset */
9283 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9284 if (!crtc_state->hw.active ||
9285 !intel_crtc_needs_modeset(crtc_state))
9286 continue;
9287
9288 if (first_crtc_state) {
9289 other_crtc_state = crtc_state;
9290 break;
9291 } else {
9292 first_crtc_state = crtc_state;
9293 first_pipe = crtc->pipe;
9294 }
9295 }
9296
9297 /* No workaround needed? */
9298 if (!first_crtc_state)
9299 return 0;
9300
9301 /* w/a possibly needed, check how many crtc's are already enabled. */
9302 for_each_intel_crtc(state->base.dev, crtc) {
9303 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9304 if (IS_ERR(crtc_state))
9305 return PTR_ERR(crtc_state);
9306
9307 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
9308
9309 if (!crtc_state->hw.active ||
9310 intel_crtc_needs_modeset(crtc_state))
9311 continue;
9312
9313 /* 2 or more enabled crtcs means no need for w/a */
9314 if (enabled_pipe != INVALID_PIPE)
9315 return 0;
9316
9317 enabled_pipe = crtc->pipe;
9318 }
9319
9320 if (enabled_pipe != INVALID_PIPE)
9321 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
9322 else if (other_crtc_state)
9323 other_crtc_state->hsw_workaround_pipe = first_pipe;
9324
9325 return 0;
9326}
9327
9328u8 intel_calc_active_pipes(struct intel_atomic_state *state,
9329 u8 active_pipes)
9330{
9331 const struct intel_crtc_state *crtc_state;
9332 struct intel_crtc *crtc;
9333 int i;
9334
9335 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9336 if (crtc_state->hw.active)
9337 active_pipes |= BIT(crtc->pipe);
9338 else
9339 active_pipes &= ~BIT(crtc->pipe);
9340 }
9341
9342 return active_pipes;
9343}
9344
9345static int intel_modeset_checks(struct intel_atomic_state *state)
9346{
9347 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9348
9349 state->modeset = true;
9350
9351 if (IS_HASWELL(dev_priv))
9352 return hsw_mode_set_planes_workaround(state);
9353
9354 return 0;
9355}
9356
9357/*
9358 * Handle calculation of various watermark data at the end of the atomic check
9359 * phase. The code here should be run after the per-crtc and per-plane 'check'
9360 * handlers to ensure that all derived state has been updated.
9361 */
9362static int calc_watermark_data(struct intel_atomic_state *state)
9363{
9364 struct drm_device *dev = state->base.dev;
9365 struct drm_i915_private *dev_priv = to_i915(dev);
9366
9367 /* Is there platform-specific watermark information to calculate? */
9368 if (dev_priv->display.compute_global_watermarks)
9369 return dev_priv->display.compute_global_watermarks(state);
9370
9371 return 0;
9372}
9373
9374static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
9375 struct intel_crtc_state *new_crtc_state)
9376{
9377 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
9378 return;
9379
9380 new_crtc_state->uapi.mode_changed = false;
9381 new_crtc_state->update_pipe = true;
9382}
9383
9384static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
9385 struct intel_crtc_state *new_crtc_state)
9386{
9387 /*
9388 * If we're not doing the full modeset we want to
9389 * keep the current M/N values as they may be
9390 * sufficiently different to the computed values
9391 * to cause problems.
9392 *
9393 * FIXME: should really copy more fuzzy state here
9394 */
9395 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
9396 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
9397 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
9398 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
9399}
9400
9401static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
9402 struct intel_crtc *crtc,
9403 u8 plane_ids_mask)
9404{
9405 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9406 struct intel_plane *plane;
9407
9408 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
9409 struct intel_plane_state *plane_state;
9410
9411 if ((plane_ids_mask & BIT(plane->id)) == 0)
9412 continue;
9413
9414 plane_state = intel_atomic_get_plane_state(state, plane);
9415 if (IS_ERR(plane_state))
9416 return PTR_ERR(plane_state);
9417 }
9418
9419 return 0;
9420}
9421
9422int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
9423 struct intel_crtc *crtc)
9424{
9425 const struct intel_crtc_state *old_crtc_state =
9426 intel_atomic_get_old_crtc_state(state, crtc);
9427 const struct intel_crtc_state *new_crtc_state =
9428 intel_atomic_get_new_crtc_state(state, crtc);
9429
9430 return intel_crtc_add_planes_to_state(state, crtc,
9431 old_crtc_state->enabled_planes |
9432 new_crtc_state->enabled_planes);
9433}
9434
9435static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
9436{
9437 /* See {hsw,vlv,ivb}_plane_ratio() */
9438 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
9439 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9440 IS_IVYBRIDGE(dev_priv);
9441}
9442
9443static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
9444 struct intel_crtc *crtc,
9445 struct intel_crtc *other)
9446{
9447 const struct intel_plane_state *plane_state;
9448 struct intel_plane *plane;
9449 u8 plane_ids = 0;
9450 int i;
9451
9452 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9453 if (plane->pipe == crtc->pipe)
9454 plane_ids |= BIT(plane->id);
9455 }
9456
9457 return intel_crtc_add_planes_to_state(state, other, plane_ids);
9458}
9459
9460static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
9461{
9462 const struct intel_crtc_state *crtc_state;
9463 struct intel_crtc *crtc;
9464 int i;
9465
9466 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9467 int ret;
9468
9469 if (!crtc_state->bigjoiner)
9470 continue;
9471
9472 ret = intel_crtc_add_bigjoiner_planes(state, crtc,
9473 crtc_state->bigjoiner_linked_crtc);
9474 if (ret)
9475 return ret;
9476 }
9477
9478 return 0;
9479}
9480
9481static int intel_atomic_check_planes(struct intel_atomic_state *state)
9482{
9483 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9484 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9485 struct intel_plane_state *plane_state;
9486 struct intel_plane *plane;
9487 struct intel_crtc *crtc;
9488 int i, ret;
9489
9490 ret = icl_add_linked_planes(state);
9491 if (ret)
9492 return ret;
9493
9494 ret = intel_bigjoiner_add_affected_planes(state);
9495 if (ret)
9496 return ret;
9497
9498 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9499 ret = intel_plane_atomic_check(state, plane);
9500 if (ret) {
9501 drm_dbg_atomic(&dev_priv->drm,
9502 "[PLANE:%d:%s] atomic driver check failed\n",
9503 plane->base.base.id, plane->base.name);
9504 return ret;
9505 }
9506 }
9507
9508 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9509 new_crtc_state, i) {
9510 u8 old_active_planes, new_active_planes;
9511
9512 ret = icl_check_nv12_planes(new_crtc_state);
9513 if (ret)
9514 return ret;
9515
9516 /*
9517 * On some platforms the number of active planes affects
9518 * the planes' minimum cdclk calculation. Add such planes
9519 * to the state before we compute the minimum cdclk.
9520 */
9521 if (!active_planes_affects_min_cdclk(dev_priv))
9522 continue;
9523
9524 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9525 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9526
9527 if (hweight8(old_active_planes) == hweight8(new_active_planes))
9528 continue;
9529
9530 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
9531 if (ret)
9532 return ret;
9533 }
9534
9535 return 0;
9536}
9537
9538static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
9539 bool *need_cdclk_calc)
9540{
9541 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9542 const struct intel_cdclk_state *old_cdclk_state;
9543 const struct intel_cdclk_state *new_cdclk_state;
9544 struct intel_plane_state *plane_state;
9545 struct intel_bw_state *new_bw_state;
9546 struct intel_plane *plane;
9547 int min_cdclk = 0;
9548 enum pipe pipe;
9549 int ret;
9550 int i;
9551 /*
9552 * active_planes bitmask has been updated, and potentially
9553 * affected planes are part of the state. We can now
9554 * compute the minimum cdclk for each plane.
9555 */
9556 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9557 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
9558 if (ret)
9559 return ret;
9560 }
9561
9562 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
9563 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
9564
9565 if (new_cdclk_state &&
9566 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
9567 *need_cdclk_calc = true;
9568
9569 ret = dev_priv->display.bw_calc_min_cdclk(state);
9570 if (ret)
9571 return ret;
9572
9573 new_bw_state = intel_atomic_get_new_bw_state(state);
9574
9575 if (!new_cdclk_state || !new_bw_state)
9576 return 0;
9577
9578 for_each_pipe(dev_priv, pipe) {
9579 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
9580
9581 /*
9582 * Currently do this change only if we need to increase
9583 */
9584 if (new_bw_state->min_cdclk > min_cdclk)
9585 *need_cdclk_calc = true;
9586 }
9587
9588 return 0;
9589}
9590
9591static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
9592{
9593 struct intel_crtc_state *crtc_state;
9594 struct intel_crtc *crtc;
9595 int i;
9596
9597 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9598 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
9599 int ret;
9600
9601 ret = intel_crtc_atomic_check(state, crtc);
9602 if (ret) {
9603 drm_dbg_atomic(&i915->drm,
9604 "[CRTC:%d:%s] atomic driver check failed\n",
9605 crtc->base.base.id, crtc->base.name);
9606 return ret;
9607 }
9608 }
9609
9610 return 0;
9611}
9612
9613static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
9614 u8 transcoders)
9615{
9616 const struct intel_crtc_state *new_crtc_state;
9617 struct intel_crtc *crtc;
9618 int i;
9619
9620 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9621 if (new_crtc_state->hw.enable &&
9622 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
9623 intel_crtc_needs_modeset(new_crtc_state))
9624 return true;
9625 }
9626
9627 return false;
9628}
9629
9630static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
9631 struct intel_crtc *crtc,
9632 struct intel_crtc_state *old_crtc_state,
9633 struct intel_crtc_state *new_crtc_state)
9634{
9635 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
9636 struct intel_crtc *slave, *master;
9637
9638 /* slave being enabled, is master is still claiming this crtc? */
9639 if (old_crtc_state->bigjoiner_slave) {
9640 slave = crtc;
9641 master = old_crtc_state->bigjoiner_linked_crtc;
9642 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
9643 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state))
9644 goto claimed;
9645 }
9646
9647 if (!new_crtc_state->bigjoiner)
9648 return 0;
9649
9650 slave = intel_dsc_get_bigjoiner_secondary(crtc);
9651 if (!slave) {
9652 DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
9653 "CRTC + 1 to be used, doesn't exist\n",
9654 crtc->base.base.id, crtc->base.name);
9655 return -EINVAL;
9656 }
9657
9658 new_crtc_state->bigjoiner_linked_crtc = slave;
9659 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
9660 master = crtc;
9661 if (IS_ERR(slave_crtc_state))
9662 return PTR_ERR(slave_crtc_state);
9663
9664 /* master being enabled, slave was already configured? */
9665 if (slave_crtc_state->uapi.enable)
9666 goto claimed;
9667
9668 DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
9669 slave->base.base.id, slave->base.name);
9670
9671 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
9672
9673claimed:
9674 DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
9675 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
9676 slave->base.base.id, slave->base.name,
9677 master->base.base.id, master->base.name);
9678 return -EINVAL;
9679}
9680
9681static void kill_bigjoiner_slave(struct intel_atomic_state *state,
9682 struct intel_crtc_state *master_crtc_state)
9683{
9684 struct intel_crtc_state *slave_crtc_state =
9685 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);
9686
9687 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
9688 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
9689 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
9690 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
9691}
9692
9693/**
9694 * DOC: asynchronous flip implementation
9695 *
9696 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
9697 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
9698 * Correspondingly, support is currently added for primary plane only.
9699 *
9700 * Async flip can only change the plane surface address, so anything else
9701 * changing is rejected from the intel_atomic_check_async() function.
9702 * Once this check is cleared, flip done interrupt is enabled using
9703 * the intel_crtc_enable_flip_done() function.
9704 *
9705 * As soon as the surface address register is written, flip done interrupt is
9706 * generated and the requested events are sent to the usersapce in the interrupt
9707 * handler itself. The timestamp and sequence sent during the flip done event
9708 * correspond to the last vblank and have no relation to the actual time when
9709 * the flip done event was sent.
9710 */
9711static int intel_atomic_check_async(struct intel_atomic_state *state)
9712{
9713 struct drm_i915_private *i915 = to_i915(state->base.dev);
9714 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9715 const struct intel_plane_state *new_plane_state, *old_plane_state;
9716 struct intel_crtc *crtc;
9717 struct intel_plane *plane;
9718 int i;
9719
9720 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9721 new_crtc_state, i) {
9722 if (intel_crtc_needs_modeset(new_crtc_state)) {
9723 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
9724 return -EINVAL;
9725 }
9726
9727 if (!new_crtc_state->hw.active) {
9728 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
9729 return -EINVAL;
9730 }
9731 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
9732 drm_dbg_kms(&i915->drm,
9733 "Active planes cannot be changed during async flip\n");
9734 return -EINVAL;
9735 }
9736 }
9737
9738 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
9739 new_plane_state, i) {
9740 /*
9741 * TODO: Async flip is only supported through the page flip IOCTL
9742 * as of now. So support currently added for primary plane only.
9743 * Support for other planes on platforms on which supports
9744 * this(vlv/chv and icl+) should be added when async flip is
9745 * enabled in the atomic IOCTL path.
9746 */
9747 if (!plane->async_flip)
9748 return -EINVAL;
9749
9750 /*
9751 * FIXME: This check is kept generic for all platforms.
9752 * Need to verify this for all gen9 and gen10 platforms to enable
9753 * this selectively if required.
9754 */
9755 switch (new_plane_state->hw.fb->modifier) {
9756 case I915_FORMAT_MOD_X_TILED:
9757 case I915_FORMAT_MOD_Y_TILED:
9758 case I915_FORMAT_MOD_Yf_TILED:
9759 break;
9760 default:
9761 drm_dbg_kms(&i915->drm,
9762 "Linear memory/CCS does not support async flips\n");
9763 return -EINVAL;
9764 }
9765
9766 if (old_plane_state->view.color_plane[0].stride !=
9767 new_plane_state->view.color_plane[0].stride) {
9768 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
9769 return -EINVAL;
9770 }
9771
9772 if (old_plane_state->hw.fb->modifier !=
9773 new_plane_state->hw.fb->modifier) {
9774 drm_dbg_kms(&i915->drm,
9775 "Framebuffer modifiers cannot be changed in async flip\n");
9776 return -EINVAL;
9777 }
9778
9779 if (old_plane_state->hw.fb->format !=
9780 new_plane_state->hw.fb->format) {
9781 drm_dbg_kms(&i915->drm,
9782 "Framebuffer format cannot be changed in async flip\n");
9783 return -EINVAL;
9784 }
9785
9786 if (old_plane_state->hw.rotation !=
9787 new_plane_state->hw.rotation) {
9788 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
9789 return -EINVAL;
9790 }
9791
9792 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
9793 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
9794 drm_dbg_kms(&i915->drm,
9795 "Plane size/co-ordinates cannot be changed in async flip\n");
9796 return -EINVAL;
9797 }
9798
9799 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
9800 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
9801 return -EINVAL;
9802 }
9803
9804 if (old_plane_state->hw.pixel_blend_mode !=
9805 new_plane_state->hw.pixel_blend_mode) {
9806 drm_dbg_kms(&i915->drm,
9807 "Pixel blend mode cannot be changed in async flip\n");
9808 return -EINVAL;
9809 }
9810
9811 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
9812 drm_dbg_kms(&i915->drm,
9813 "Color encoding cannot be changed in async flip\n");
9814 return -EINVAL;
9815 }
9816
9817 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
9818 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
9819 return -EINVAL;
9820 }
9821 }
9822
9823 return 0;
9824}
9825
9826static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
9827{
9828 struct intel_crtc_state *crtc_state;
9829 struct intel_crtc *crtc;
9830 int i;
9831
9832 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9833 struct intel_crtc_state *linked_crtc_state;
9834 struct intel_crtc *linked_crtc;
9835 int ret;
9836
9837 if (!crtc_state->bigjoiner)
9838 continue;
9839
9840 linked_crtc = crtc_state->bigjoiner_linked_crtc;
9841 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);
9842 if (IS_ERR(linked_crtc_state))
9843 return PTR_ERR(linked_crtc_state);
9844
9845 if (!intel_crtc_needs_modeset(crtc_state))
9846 continue;
9847
9848 linked_crtc_state->uapi.mode_changed = true;
9849
9850 ret = drm_atomic_add_affected_connectors(&state->base,
9851 &linked_crtc->base);
9852 if (ret)
9853 return ret;
9854
9855 ret = intel_atomic_add_affected_planes(state, linked_crtc);
9856 if (ret)
9857 return ret;
9858 }
9859
9860 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9861 /* Kill old bigjoiner link, we may re-establish afterwards */
9862 if (intel_crtc_needs_modeset(crtc_state) &&
9863 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
9864 kill_bigjoiner_slave(state, crtc_state);
9865 }
9866
9867 return 0;
9868}
9869
9870/**
9871 * intel_atomic_check - validate state object
9872 * @dev: drm device
9873 * @_state: state to validate
9874 */
9875static int intel_atomic_check(struct drm_device *dev,
9876 struct drm_atomic_state *_state)
9877{
9878 struct drm_i915_private *dev_priv = to_i915(dev);
9879 struct intel_atomic_state *state = to_intel_atomic_state(_state);
9880 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9881 struct intel_crtc *crtc;
9882 int ret, i;
9883 bool any_ms = false;
9884
9885 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9886 new_crtc_state, i) {
9887 if (new_crtc_state->inherited != old_crtc_state->inherited)
9888 new_crtc_state->uapi.mode_changed = true;
9889 }
9890
9891 intel_vrr_check_modeset(state);
9892
9893 ret = drm_atomic_helper_check_modeset(dev, &state->base);
9894 if (ret)
9895 goto fail;
9896
9897 ret = intel_bigjoiner_add_affected_crtcs(state);
9898 if (ret)
9899 goto fail;
9900
9901 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9902 new_crtc_state, i) {
9903 if (!intel_crtc_needs_modeset(new_crtc_state)) {
9904 /* Light copy */
9905 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
9906
9907 continue;
9908 }
9909
9910 if (!new_crtc_state->uapi.enable) {
9911 if (!new_crtc_state->bigjoiner_slave) {
9912 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
9913 any_ms = true;
9914 }
9915 continue;
9916 }
9917
9918 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
9919 if (ret)
9920 goto fail;
9921
9922 ret = intel_modeset_pipe_config(state, new_crtc_state);
9923 if (ret)
9924 goto fail;
9925
9926 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
9927 new_crtc_state);
9928 if (ret)
9929 goto fail;
9930 }
9931
9932 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9933 new_crtc_state, i) {
9934 if (!intel_crtc_needs_modeset(new_crtc_state))
9935 continue;
9936
9937 ret = intel_modeset_pipe_config_late(new_crtc_state);
9938 if (ret)
9939 goto fail;
9940
9941 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
9942 }
9943
9944 /**
9945 * Check if fastset is allowed by external dependencies like other
9946 * pipes and transcoders.
9947 *
9948 * Right now it only forces a fullmodeset when the MST master
9949 * transcoder did not changed but the pipe of the master transcoder
9950 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
9951 * in case of port synced crtcs, if one of the synced crtcs
9952 * needs a full modeset, all other synced crtcs should be
9953 * forced a full modeset.
9954 */
9955 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9956 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
9957 continue;
9958
9959 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
9960 enum transcoder master = new_crtc_state->mst_master_transcoder;
9961
9962 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
9963 new_crtc_state->uapi.mode_changed = true;
9964 new_crtc_state->update_pipe = false;
9965 }
9966 }
9967
9968 if (is_trans_port_sync_mode(new_crtc_state)) {
9969 u8 trans = new_crtc_state->sync_mode_slaves_mask;
9970
9971 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
9972 trans |= BIT(new_crtc_state->master_transcoder);
9973
9974 if (intel_cpu_transcoders_need_modeset(state, trans)) {
9975 new_crtc_state->uapi.mode_changed = true;
9976 new_crtc_state->update_pipe = false;
9977 }
9978 }
9979
9980 if (new_crtc_state->bigjoiner) {
9981 struct intel_crtc_state *linked_crtc_state =
9982 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);
9983
9984 if (intel_crtc_needs_modeset(linked_crtc_state)) {
9985 new_crtc_state->uapi.mode_changed = true;
9986 new_crtc_state->update_pipe = false;
9987 }
9988 }
9989 }
9990
9991 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9992 new_crtc_state, i) {
9993 if (intel_crtc_needs_modeset(new_crtc_state)) {
9994 any_ms = true;
9995 continue;
9996 }
9997
9998 if (!new_crtc_state->update_pipe)
9999 continue;
10000
10001 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
10002 }
10003
10004 if (any_ms && !check_digital_port_conflicts(state)) {
10005 drm_dbg_kms(&dev_priv->drm,
10006 "rejecting conflicting digital port configuration\n");
10007 ret = -EINVAL;
10008 goto fail;
10009 }
10010
10011 ret = drm_dp_mst_atomic_check(&state->base);
10012 if (ret)
10013 goto fail;
10014
10015 ret = intel_atomic_check_planes(state);
10016 if (ret)
10017 goto fail;
10018
10019 intel_fbc_choose_crtc(dev_priv, state);
10020 ret = calc_watermark_data(state);
10021 if (ret)
10022 goto fail;
10023
10024 ret = intel_bw_atomic_check(state);
10025 if (ret)
10026 goto fail;
10027
10028 ret = intel_atomic_check_cdclk(state, &any_ms);
10029 if (ret)
10030 goto fail;
10031
10032 if (intel_any_crtc_needs_modeset(state))
10033 any_ms = true;
10034
10035 if (any_ms) {
10036 ret = intel_modeset_checks(state);
10037 if (ret)
10038 goto fail;
10039
10040 ret = intel_modeset_calc_cdclk(state);
10041 if (ret)
10042 return ret;
10043
10044 intel_modeset_clear_plls(state);
10045 }
10046
10047 ret = intel_atomic_check_crtcs(state);
10048 if (ret)
10049 goto fail;
10050
10051 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10052 new_crtc_state, i) {
10053 if (new_crtc_state->uapi.async_flip) {
10054 ret = intel_atomic_check_async(state);
10055 if (ret)
10056 goto fail;
10057 }
10058
10059 if (!intel_crtc_needs_modeset(new_crtc_state) &&
10060 !new_crtc_state->update_pipe)
10061 continue;
10062
10063 intel_dump_pipe_config(new_crtc_state, state,
10064 intel_crtc_needs_modeset(new_crtc_state) ?
10065 "[modeset]" : "[fastset]");
10066 }
10067
10068 return 0;
10069
10070 fail:
10071 if (ret == -EDEADLK)
10072 return ret;
10073
10074 /*
10075 * FIXME would probably be nice to know which crtc specifically
10076 * caused the failure, in cases where we can pinpoint it.
10077 */
10078 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10079 new_crtc_state, i)
10080 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
10081
10082 return ret;
10083}
10084
10085static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
10086{
10087 struct intel_crtc_state *crtc_state;
10088 struct intel_crtc *crtc;
10089 int i, ret;
10090
10091 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
10092 if (ret < 0)
10093 return ret;
10094
10095 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10096 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
10097
10098 if (mode_changed || crtc_state->update_pipe ||
10099 crtc_state->uapi.color_mgmt_changed) {
10100 intel_dsb_prepare(crtc_state);
10101 }
10102 }
10103
10104 return 0;
10105}
10106
10107void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
10108 struct intel_crtc_state *crtc_state)
10109{
10110 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10111
10112 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
10113 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10114
10115 if (crtc_state->has_pch_encoder) {
10116 enum pipe pch_transcoder =
10117 intel_crtc_pch_transcoder(crtc);
10118
10119 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
10120 }
10121}
10122
10123static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
10124 const struct intel_crtc_state *new_crtc_state)
10125{
10126 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
10127 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10128
10129 /*
10130 * Update pipe size and adjust fitter if needed: the reason for this is
10131 * that in compute_mode_changes we check the native mode (not the pfit
10132 * mode) to see if we can flip rather than do a full mode set. In the
10133 * fastboot case, we'll flip, but if we don't update the pipesrc and
10134 * pfit state, we'll end up with a big fb scanned out into the wrong
10135 * sized surface.
10136 */
10137 intel_set_pipe_src_size(new_crtc_state);
10138
10139 /* on skylake this is done by detaching scalers */
10140 if (DISPLAY_VER(dev_priv) >= 9) {
10141 if (new_crtc_state->pch_pfit.enabled)
10142 skl_pfit_enable(new_crtc_state);
10143 } else if (HAS_PCH_SPLIT(dev_priv)) {
10144 if (new_crtc_state->pch_pfit.enabled)
10145 ilk_pfit_enable(new_crtc_state);
10146 else if (old_crtc_state->pch_pfit.enabled)
10147 ilk_pfit_disable(old_crtc_state);
10148 }
10149
10150 /*
10151 * The register is supposedly single buffered so perhaps
10152 * not 100% correct to do this here. But SKL+ calculate
10153 * this based on the adjust pixel rate so pfit changes do
10154 * affect it and so it must be updated for fastsets.
10155 * HSW/BDW only really need this here for fastboot, after
10156 * that the value should not change without a full modeset.
10157 */
10158 if (DISPLAY_VER(dev_priv) >= 9 ||
10159 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
10160 hsw_set_linetime_wm(new_crtc_state);
10161
10162 if (DISPLAY_VER(dev_priv) >= 11)
10163 icl_set_pipe_chicken(crtc);
10164}
10165
10166static void commit_pipe_pre_planes(struct intel_atomic_state *state,
10167 struct intel_crtc *crtc)
10168{
10169 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10170 const struct intel_crtc_state *old_crtc_state =
10171 intel_atomic_get_old_crtc_state(state, crtc);
10172 const struct intel_crtc_state *new_crtc_state =
10173 intel_atomic_get_new_crtc_state(state, crtc);
10174 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10175
10176 /*
10177 * During modesets pipe configuration was programmed as the
10178 * CRTC was enabled.
10179 */
10180 if (!modeset) {
10181 if (new_crtc_state->uapi.color_mgmt_changed ||
10182 new_crtc_state->update_pipe)
10183 intel_color_commit(new_crtc_state);
10184
10185 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
10186 bdw_set_pipemisc(new_crtc_state);
10187
10188 if (new_crtc_state->update_pipe)
10189 intel_pipe_fastset(old_crtc_state, new_crtc_state);
10190
10191 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
10192 }
10193
10194 if (dev_priv->display.atomic_update_watermarks)
10195 dev_priv->display.atomic_update_watermarks(state, crtc);
10196}
10197
10198static void commit_pipe_post_planes(struct intel_atomic_state *state,
10199 struct intel_crtc *crtc)
10200{
10201 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10202 const struct intel_crtc_state *new_crtc_state =
10203 intel_atomic_get_new_crtc_state(state, crtc);
10204
10205 /*
10206 * Disable the scaler(s) after the plane(s) so that we don't
10207 * get a catastrophic underrun even if the two operations
10208 * end up happening in two different frames.
10209 */
10210 if (DISPLAY_VER(dev_priv) >= 9 &&
10211 !intel_crtc_needs_modeset(new_crtc_state))
10212 skl_detach_scalers(new_crtc_state);
10213}
10214
10215static void intel_enable_crtc(struct intel_atomic_state *state,
10216 struct intel_crtc *crtc)
10217{
10218 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10219 const struct intel_crtc_state *new_crtc_state =
10220 intel_atomic_get_new_crtc_state(state, crtc);
10221
10222 if (!intel_crtc_needs_modeset(new_crtc_state))
10223 return;
10224
10225 intel_crtc_update_active_timings(new_crtc_state);
10226
10227 dev_priv->display.crtc_enable(state, crtc);
10228
10229 if (new_crtc_state->bigjoiner_slave)
10230 return;
10231
10232 /* vblanks work again, re-enable pipe CRC. */
10233 intel_crtc_enable_pipe_crc(crtc);
10234}
10235
10236static void intel_update_crtc(struct intel_atomic_state *state,
10237 struct intel_crtc *crtc)
10238{
10239 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10240 const struct intel_crtc_state *old_crtc_state =
10241 intel_atomic_get_old_crtc_state(state, crtc);
10242 struct intel_crtc_state *new_crtc_state =
10243 intel_atomic_get_new_crtc_state(state, crtc);
10244 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10245
10246 if (!modeset) {
10247 if (new_crtc_state->preload_luts &&
10248 (new_crtc_state->uapi.color_mgmt_changed ||
10249 new_crtc_state->update_pipe))
10250 intel_color_load_luts(new_crtc_state);
10251
10252 intel_pre_plane_update(state, crtc);
10253
10254 if (new_crtc_state->update_pipe)
10255 intel_encoders_update_pipe(state, crtc);
10256 }
10257
10258 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
10259 intel_fbc_disable(crtc);
10260 else
10261 intel_fbc_enable(state, crtc);
10262
10263 /* Perform vblank evasion around commit operation */
10264 intel_pipe_update_start(new_crtc_state);
10265
10266 commit_pipe_pre_planes(state, crtc);
10267
10268 if (DISPLAY_VER(dev_priv) >= 9)
10269 skl_update_planes_on_crtc(state, crtc);
10270 else
10271 i9xx_update_planes_on_crtc(state, crtc);
10272
10273 commit_pipe_post_planes(state, crtc);
10274
10275 intel_pipe_update_end(new_crtc_state);
10276
10277 /*
10278 * We usually enable FIFO underrun interrupts as part of the
10279 * CRTC enable sequence during modesets. But when we inherit a
10280 * valid pipe configuration from the BIOS we need to take care
10281 * of enabling them on the CRTC's first fastset.
10282 */
10283 if (new_crtc_state->update_pipe && !modeset &&
10284 old_crtc_state->inherited)
10285 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
10286}
10287
10288static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
10289 struct intel_crtc_state *old_crtc_state,
10290 struct intel_crtc_state *new_crtc_state,
10291 struct intel_crtc *crtc)
10292{
10293 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10294
10295 drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
10296
10297 intel_crtc_disable_planes(state, crtc);
10298
10299 /*
10300 * We still need special handling for disabling bigjoiner master
10301 * and slaves since for slave we do not have encoder or plls
10302 * so we dont need to disable those.
10303 */
10304 if (old_crtc_state->bigjoiner) {
10305 intel_crtc_disable_planes(state,
10306 old_crtc_state->bigjoiner_linked_crtc);
10307 old_crtc_state->bigjoiner_linked_crtc->active = false;
10308 }
10309
10310 /*
10311 * We need to disable pipe CRC before disabling the pipe,
10312 * or we race against vblank off.
10313 */
10314 intel_crtc_disable_pipe_crc(crtc);
10315
10316 dev_priv->display.crtc_disable(state, crtc);
10317 crtc->active = false;
10318 intel_fbc_disable(crtc);
10319 intel_disable_shared_dpll(old_crtc_state);
10320
10321 /* FIXME unify this for all platforms */
10322 if (!new_crtc_state->hw.active &&
10323 !HAS_GMCH(dev_priv) &&
10324 dev_priv->display.initial_watermarks)
10325 dev_priv->display.initial_watermarks(state, crtc);
10326}
10327
10328static void intel_commit_modeset_disables(struct intel_atomic_state *state)
10329{
10330 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10331 struct intel_crtc *crtc;
10332 u32 handled = 0;
10333 int i;
10334
10335 /* Only disable port sync and MST slaves */
10336 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10337 new_crtc_state, i) {
10338 if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
10339 continue;
10340
10341 if (!old_crtc_state->hw.active)
10342 continue;
10343
10344 /* In case of Transcoder port Sync master slave CRTCs can be
10345 * assigned in any order and we need to make sure that
10346 * slave CRTCs are disabled first and then master CRTC since
10347 * Slave vblanks are masked till Master Vblanks.
10348 */
10349 if (!is_trans_port_sync_slave(old_crtc_state) &&
10350 !intel_dp_mst_is_slave_trans(old_crtc_state))
10351 continue;
10352
10353 intel_pre_plane_update(state, crtc);
10354 intel_old_crtc_state_disables(state, old_crtc_state,
10355 new_crtc_state, crtc);
10356 handled |= BIT(crtc->pipe);
10357 }
10358
10359 /* Disable everything else left on */
10360 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10361 new_crtc_state, i) {
10362 if (!intel_crtc_needs_modeset(new_crtc_state) ||
10363 (handled & BIT(crtc->pipe)) ||
10364 old_crtc_state->bigjoiner_slave)
10365 continue;
10366
10367 intel_pre_plane_update(state, crtc);
10368 if (old_crtc_state->bigjoiner) {
10369 struct intel_crtc *slave =
10370 old_crtc_state->bigjoiner_linked_crtc;
10371
10372 intel_pre_plane_update(state, slave);
10373 }
10374
10375 if (old_crtc_state->hw.active)
10376 intel_old_crtc_state_disables(state, old_crtc_state,
10377 new_crtc_state, crtc);
10378 }
10379}
10380
10381static void intel_commit_modeset_enables(struct intel_atomic_state *state)
10382{
10383 struct intel_crtc_state *new_crtc_state;
10384 struct intel_crtc *crtc;
10385 int i;
10386
10387 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10388 if (!new_crtc_state->hw.active)
10389 continue;
10390
10391 intel_enable_crtc(state, crtc);
10392 intel_update_crtc(state, crtc);
10393 }
10394}
10395
10396static void skl_commit_modeset_enables(struct intel_atomic_state *state)
10397{
10398 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10399 struct intel_crtc *crtc;
10400 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10401 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
10402 u8 update_pipes = 0, modeset_pipes = 0;
10403 int i;
10404
10405 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10406 enum pipe pipe = crtc->pipe;
10407
10408 if (!new_crtc_state->hw.active)
10409 continue;
10410
10411 /* ignore allocations for crtc's that have been turned off. */
10412 if (!intel_crtc_needs_modeset(new_crtc_state)) {
10413 entries[pipe] = old_crtc_state->wm.skl.ddb;
10414 update_pipes |= BIT(pipe);
10415 } else {
10416 modeset_pipes |= BIT(pipe);
10417 }
10418 }
10419
10420 /*
10421 * Whenever the number of active pipes changes, we need to make sure we
10422 * update the pipes in the right order so that their ddb allocations
10423 * never overlap with each other between CRTC updates. Otherwise we'll
10424 * cause pipe underruns and other bad stuff.
10425 *
10426 * So first lets enable all pipes that do not need a fullmodeset as
10427 * those don't have any external dependency.
10428 */
10429 while (update_pipes) {
10430 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10431 new_crtc_state, i) {
10432 enum pipe pipe = crtc->pipe;
10433
10434 if ((update_pipes & BIT(pipe)) == 0)
10435 continue;
10436
10437 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10438 entries, I915_MAX_PIPES, pipe))
10439 continue;
10440
10441 entries[pipe] = new_crtc_state->wm.skl.ddb;
10442 update_pipes &= ~BIT(pipe);
10443
10444 intel_update_crtc(state, crtc);
10445
10446 /*
10447 * If this is an already active pipe, it's DDB changed,
10448 * and this isn't the last pipe that needs updating
10449 * then we need to wait for a vblank to pass for the
10450 * new ddb allocation to take effect.
10451 */
10452 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
10453 &old_crtc_state->wm.skl.ddb) &&
10454 (update_pipes | modeset_pipes))
10455 intel_wait_for_vblank(dev_priv, pipe);
10456 }
10457 }
10458
10459 update_pipes = modeset_pipes;
10460
10461 /*
10462 * Enable all pipes that needs a modeset and do not depends on other
10463 * pipes
10464 */
10465 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10466 enum pipe pipe = crtc->pipe;
10467
10468 if ((modeset_pipes & BIT(pipe)) == 0)
10469 continue;
10470
10471 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
10472 is_trans_port_sync_master(new_crtc_state) ||
10473 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
10474 continue;
10475
10476 modeset_pipes &= ~BIT(pipe);
10477
10478 intel_enable_crtc(state, crtc);
10479 }
10480
10481 /*
10482 * Then we enable all remaining pipes that depend on other
10483 * pipes: MST slaves and port sync masters, big joiner master
10484 */
10485 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10486 enum pipe pipe = crtc->pipe;
10487
10488 if ((modeset_pipes & BIT(pipe)) == 0)
10489 continue;
10490
10491 modeset_pipes &= ~BIT(pipe);
10492
10493 intel_enable_crtc(state, crtc);
10494 }
10495
10496 /*
10497 * Finally we do the plane updates/etc. for all pipes that got enabled.
10498 */
10499 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10500 enum pipe pipe = crtc->pipe;
10501
10502 if ((update_pipes & BIT(pipe)) == 0)
10503 continue;
10504
10505 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10506 entries, I915_MAX_PIPES, pipe));
10507
10508 entries[pipe] = new_crtc_state->wm.skl.ddb;
10509 update_pipes &= ~BIT(pipe);
10510
10511 intel_update_crtc(state, crtc);
10512 }
10513
10514 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
10515 drm_WARN_ON(&dev_priv->drm, update_pipes);
10516}
10517
10518static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
10519{
10520 struct intel_atomic_state *state, *next;
10521 struct llist_node *freed;
10522
10523 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
10524 llist_for_each_entry_safe(state, next, freed, freed)
10525 drm_atomic_state_put(&state->base);
10526}
10527
10528static void intel_atomic_helper_free_state_worker(struct work_struct *work)
10529{
10530 struct drm_i915_private *dev_priv =
10531 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
10532
10533 intel_atomic_helper_free_state(dev_priv);
10534}
10535
10536static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
10537{
10538 struct wait_queue_entry wait_fence, wait_reset;
10539 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
10540
10541 init_wait_entry(&wait_fence, 0);
10542 init_wait_entry(&wait_reset, 0);
10543 for (;;) {
10544 prepare_to_wait(&intel_state->commit_ready.wait,
10545 &wait_fence, TASK_UNINTERRUPTIBLE);
10546 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10547 I915_RESET_MODESET),
10548 &wait_reset, TASK_UNINTERRUPTIBLE);
10549
10550
10551 if (i915_sw_fence_done(&intel_state->commit_ready) ||
10552 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
10553 break;
10554
10555 schedule();
10556 }
10557 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
10558 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10559 I915_RESET_MODESET),
10560 &wait_reset);
10561}
10562
10563static void intel_cleanup_dsbs(struct intel_atomic_state *state)
10564{
10565 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10566 struct intel_crtc *crtc;
10567 int i;
10568
10569 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10570 new_crtc_state, i)
10571 intel_dsb_cleanup(old_crtc_state);
10572}
10573
10574static void intel_atomic_cleanup_work(struct work_struct *work)
10575{
10576 struct intel_atomic_state *state =
10577 container_of(work, struct intel_atomic_state, base.commit_work);
10578 struct drm_i915_private *i915 = to_i915(state->base.dev);
10579
10580 intel_cleanup_dsbs(state);
10581 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
10582 drm_atomic_helper_commit_cleanup_done(&state->base);
10583 drm_atomic_state_put(&state->base);
10584
10585 intel_atomic_helper_free_state(i915);
10586}
10587
10588static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
10589{
10590 struct drm_i915_private *i915 = to_i915(state->base.dev);
10591 struct intel_plane *plane;
10592 struct intel_plane_state *plane_state;
10593 int i;
10594
10595 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10596 struct drm_framebuffer *fb = plane_state->hw.fb;
10597 int ret;
10598
10599 if (!fb ||
10600 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
10601 continue;
10602
10603 /*
10604 * The layout of the fast clear color value expected by HW
10605 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
10606 * - 4 x 4 bytes per-channel value
10607 * (in surface type specific float/int format provided by the fb user)
10608 * - 8 bytes native color value used by the display
10609 * (converted/written by GPU during a fast clear operation using the
10610 * above per-channel values)
10611 *
10612 * The commit's FB prepare hook already ensured that FB obj is pinned and the
10613 * caller made sure that the object is synced wrt. the related color clear value
10614 * GPU write on it.
10615 */
10616 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
10617 fb->offsets[2] + 16,
10618 &plane_state->ccval,
10619 sizeof(plane_state->ccval));
10620 /* The above could only fail if the FB obj has an unexpected backing store type. */
10621 drm_WARN_ON(&i915->drm, ret);
10622 }
10623}
10624
10625static void intel_atomic_commit_tail(struct intel_atomic_state *state)
10626{
10627 struct drm_device *dev = state->base.dev;
10628 struct drm_i915_private *dev_priv = to_i915(dev);
10629 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10630 struct intel_crtc *crtc;
10631 u64 put_domains[I915_MAX_PIPES] = {};
10632 intel_wakeref_t wakeref = 0;
10633 int i;
10634
10635 intel_atomic_commit_fence_wait(state);
10636
10637 drm_atomic_helper_wait_for_dependencies(&state->base);
10638
10639 if (state->modeset)
10640 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
10641
10642 intel_atomic_prepare_plane_clear_colors(state);
10643
10644 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10645 new_crtc_state, i) {
10646 if (intel_crtc_needs_modeset(new_crtc_state) ||
10647 new_crtc_state->update_pipe) {
10648
10649 put_domains[crtc->pipe] =
10650 modeset_get_crtc_power_domains(new_crtc_state);
10651 }
10652 }
10653
10654 intel_commit_modeset_disables(state);
10655
10656 /* FIXME: Eventually get rid of our crtc->config pointer */
10657 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10658 crtc->config = new_crtc_state;
10659
10660 if (state->modeset) {
10661 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
10662
10663 intel_set_cdclk_pre_plane_update(state);
10664
10665 intel_modeset_verify_disabled(dev_priv, state);
10666 }
10667
10668 intel_sagv_pre_plane_update(state);
10669
10670 /* Complete the events for pipes that have now been disabled */
10671 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10672 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10673
10674 /* Complete events for now disable pipes here. */
10675 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
10676 spin_lock_irq(&dev->event_lock);
10677 drm_crtc_send_vblank_event(&crtc->base,
10678 new_crtc_state->uapi.event);
10679 spin_unlock_irq(&dev->event_lock);
10680
10681 new_crtc_state->uapi.event = NULL;
10682 }
10683 }
10684
10685 if (state->modeset)
10686 intel_encoders_update_prepare(state);
10687
10688 intel_dbuf_pre_plane_update(state);
10689
10690 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10691 if (new_crtc_state->uapi.async_flip)
10692 intel_crtc_enable_flip_done(state, crtc);
10693 }
10694
10695 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10696 dev_priv->display.commit_modeset_enables(state);
10697
10698 if (state->modeset) {
10699 intel_encoders_update_complete(state);
10700
10701 intel_set_cdclk_post_plane_update(state);
10702 }
10703
10704 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
10705 * already, but still need the state for the delayed optimization. To
10706 * fix this:
10707 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
10708 * - schedule that vblank worker _before_ calling hw_done
10709 * - at the start of commit_tail, cancel it _synchrously
10710 * - switch over to the vblank wait helper in the core after that since
10711 * we don't need out special handling any more.
10712 */
10713 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
10714
10715 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10716 if (new_crtc_state->uapi.async_flip)
10717 intel_crtc_disable_flip_done(state, crtc);
10718
10719 if (new_crtc_state->hw.active &&
10720 !intel_crtc_needs_modeset(new_crtc_state) &&
10721 !new_crtc_state->preload_luts &&
10722 (new_crtc_state->uapi.color_mgmt_changed ||
10723 new_crtc_state->update_pipe))
10724 intel_color_load_luts(new_crtc_state);
10725 }
10726
10727 /*
10728 * Now that the vblank has passed, we can go ahead and program the
10729 * optimal watermarks on platforms that need two-step watermark
10730 * programming.
10731 *
10732 * TODO: Move this (and other cleanup) to an async worker eventually.
10733 */
10734 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10735 new_crtc_state, i) {
10736 /*
10737 * Gen2 reports pipe underruns whenever all planes are disabled.
10738 * So re-enable underrun reporting after some planes get enabled.
10739 *
10740 * We do this before .optimize_watermarks() so that we have a
10741 * chance of catching underruns with the intermediate watermarks
10742 * vs. the new plane configuration.
10743 */
10744 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
10745 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10746
10747 if (dev_priv->display.optimize_watermarks)
10748 dev_priv->display.optimize_watermarks(state, crtc);
10749 }
10750
10751 intel_dbuf_post_plane_update(state);
10752
10753 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10754 intel_post_plane_update(state, crtc);
10755
10756 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
10757
10758 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
10759
10760 /*
10761 * DSB cleanup is done in cleanup_work aligning with framebuffer
10762 * cleanup. So copy and reset the dsb structure to sync with
10763 * commit_done and later do dsb cleanup in cleanup_work.
10764 */
10765 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
10766 }
10767
10768 /* Underruns don't always raise interrupts, so check manually */
10769 intel_check_cpu_fifo_underruns(dev_priv);
10770 intel_check_pch_fifo_underruns(dev_priv);
10771
10772 if (state->modeset)
10773 intel_verify_planes(state);
10774
10775 intel_sagv_post_plane_update(state);
10776
10777 drm_atomic_helper_commit_hw_done(&state->base);
10778
10779 if (state->modeset) {
10780 /* As one of the primary mmio accessors, KMS has a high
10781 * likelihood of triggering bugs in unclaimed access. After we
10782 * finish modesetting, see if an error has been flagged, and if
10783 * so enable debugging for the next modeset - and hope we catch
10784 * the culprit.
10785 */
10786 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
10787 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
10788 }
10789 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10790
10791 /*
10792 * Defer the cleanup of the old state to a separate worker to not
10793 * impede the current task (userspace for blocking modesets) that
10794 * are executed inline. For out-of-line asynchronous modesets/flips,
10795 * deferring to a new worker seems overkill, but we would place a
10796 * schedule point (cond_resched()) here anyway to keep latencies
10797 * down.
10798 */
10799 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
10800 queue_work(system_highpri_wq, &state->base.commit_work);
10801}
10802
10803static void intel_atomic_commit_work(struct work_struct *work)
10804{
10805 struct intel_atomic_state *state =
10806 container_of(work, struct intel_atomic_state, base.commit_work);
10807
10808 intel_atomic_commit_tail(state);
10809}
10810
10811static int __i915_sw_fence_call
10812intel_atomic_commit_ready(struct i915_sw_fence *fence,
10813 enum i915_sw_fence_notify notify)
10814{
10815 struct intel_atomic_state *state =
10816 container_of(fence, struct intel_atomic_state, commit_ready);
10817
10818 switch (notify) {
10819 case FENCE_COMPLETE:
10820 /* we do blocking waits in the worker, nothing to do here */
10821 break;
10822 case FENCE_FREE:
10823 {
10824 struct intel_atomic_helper *helper =
10825 &to_i915(state->base.dev)->atomic_helper;
10826
10827 if (llist_add(&state->freed, &helper->free_list))
10828 schedule_work(&helper->free_work);
10829 break;
10830 }
10831 }
10832
10833 return NOTIFY_DONE;
10834}
10835
10836static void intel_atomic_track_fbs(struct intel_atomic_state *state)
10837{
10838 struct intel_plane_state *old_plane_state, *new_plane_state;
10839 struct intel_plane *plane;
10840 int i;
10841
10842 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
10843 new_plane_state, i)
10844 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
10845 to_intel_frontbuffer(new_plane_state->hw.fb),
10846 plane->frontbuffer_bit);
10847}
10848
10849static int intel_atomic_commit(struct drm_device *dev,
10850 struct drm_atomic_state *_state,
10851 bool nonblock)
10852{
10853 struct intel_atomic_state *state = to_intel_atomic_state(_state);
10854 struct drm_i915_private *dev_priv = to_i915(dev);
10855 int ret = 0;
10856
10857 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
10858
10859 drm_atomic_state_get(&state->base);
10860 i915_sw_fence_init(&state->commit_ready,
10861 intel_atomic_commit_ready);
10862
10863 /*
10864 * The intel_legacy_cursor_update() fast path takes care
10865 * of avoiding the vblank waits for simple cursor
10866 * movement and flips. For cursor on/off and size changes,
10867 * we want to perform the vblank waits so that watermark
10868 * updates happen during the correct frames. Gen9+ have
10869 * double buffered watermarks and so shouldn't need this.
10870 *
10871 * Unset state->legacy_cursor_update before the call to
10872 * drm_atomic_helper_setup_commit() because otherwise
10873 * drm_atomic_helper_wait_for_flip_done() is a noop and
10874 * we get FIFO underruns because we didn't wait
10875 * for vblank.
10876 *
10877 * FIXME doing watermarks and fb cleanup from a vblank worker
10878 * (assuming we had any) would solve these problems.
10879 */
10880 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
10881 struct intel_crtc_state *new_crtc_state;
10882 struct intel_crtc *crtc;
10883 int i;
10884
10885 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10886 if (new_crtc_state->wm.need_postvbl_update ||
10887 new_crtc_state->update_wm_post)
10888 state->base.legacy_cursor_update = false;
10889 }
10890
10891 ret = intel_atomic_prepare_commit(state);
10892 if (ret) {
10893 drm_dbg_atomic(&dev_priv->drm,
10894 "Preparing state failed with %i\n", ret);
10895 i915_sw_fence_commit(&state->commit_ready);
10896 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10897 return ret;
10898 }
10899
10900 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
10901 if (!ret)
10902 ret = drm_atomic_helper_swap_state(&state->base, true);
10903 if (!ret)
10904 intel_atomic_swap_global_state(state);
10905
10906 if (ret) {
10907 struct intel_crtc_state *new_crtc_state;
10908 struct intel_crtc *crtc;
10909 int i;
10910
10911 i915_sw_fence_commit(&state->commit_ready);
10912
10913 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10914 intel_dsb_cleanup(new_crtc_state);
10915
10916 drm_atomic_helper_cleanup_planes(dev, &state->base);
10917 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10918 return ret;
10919 }
10920 intel_shared_dpll_swap_state(state);
10921 intel_atomic_track_fbs(state);
10922
10923 drm_atomic_state_get(&state->base);
10924 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
10925
10926 i915_sw_fence_commit(&state->commit_ready);
10927 if (nonblock && state->modeset) {
10928 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
10929 } else if (nonblock) {
10930 queue_work(dev_priv->flip_wq, &state->base.commit_work);
10931 } else {
10932 if (state->modeset)
10933 flush_workqueue(dev_priv->modeset_wq);
10934 intel_atomic_commit_tail(state);
10935 }
10936
10937 return 0;
10938}
10939
10940struct wait_rps_boost {
10941 struct wait_queue_entry wait;
10942
10943 struct drm_crtc *crtc;
10944 struct i915_request *request;
10945};
10946
10947static int do_rps_boost(struct wait_queue_entry *_wait,
10948 unsigned mode, int sync, void *key)
10949{
10950 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
10951 struct i915_request *rq = wait->request;
10952
10953 /*
10954 * If we missed the vblank, but the request is already running it
10955 * is reasonable to assume that it will complete before the next
10956 * vblank without our intervention, so leave RPS alone.
10957 */
10958 if (!i915_request_started(rq))
10959 intel_rps_boost(rq);
10960 i915_request_put(rq);
10961
10962 drm_crtc_vblank_put(wait->crtc);
10963
10964 list_del(&wait->wait.entry);
10965 kfree(wait);
10966 return 1;
10967}
10968
10969static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
10970 struct dma_fence *fence)
10971{
10972 struct wait_rps_boost *wait;
10973
10974 if (!dma_fence_is_i915(fence))
10975 return;
10976
10977 if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
10978 return;
10979
10980 if (drm_crtc_vblank_get(crtc))
10981 return;
10982
10983 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
10984 if (!wait) {
10985 drm_crtc_vblank_put(crtc);
10986 return;
10987 }
10988
10989 wait->request = to_request(dma_fence_get(fence));
10990 wait->crtc = crtc;
10991
10992 wait->wait.func = do_rps_boost;
10993 wait->wait.flags = 0;
10994
10995 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
10996}
10997
10998int intel_plane_pin_fb(struct intel_plane_state *plane_state)
10999{
11000 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11001 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11002 struct drm_framebuffer *fb = plane_state->hw.fb;
11003 struct i915_vma *vma;
11004 bool phys_cursor =
11005 plane->id == PLANE_CURSOR &&
11006 INTEL_INFO(dev_priv)->display.cursor_needs_physical;
11007
11008 if (!intel_fb_uses_dpt(fb)) {
11009 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
11010 &plane_state->view.gtt,
11011 intel_plane_uses_fence(plane_state),
11012 &plane_state->flags);
11013 if (IS_ERR(vma))
11014 return PTR_ERR(vma);
11015
11016 plane_state->ggtt_vma = vma;
11017 } else {
11018 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11019
11020 vma = intel_dpt_pin(intel_fb->dpt_vm);
11021 if (IS_ERR(vma))
11022 return PTR_ERR(vma);
11023
11024 plane_state->ggtt_vma = vma;
11025
11026 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
11027 &plane_state->flags, intel_fb->dpt_vm);
11028 if (IS_ERR(vma)) {
11029 intel_dpt_unpin(intel_fb->dpt_vm);
11030 plane_state->ggtt_vma = NULL;
11031 return PTR_ERR(vma);
11032 }
11033
11034 plane_state->dpt_vma = vma;
11035
11036 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
11037 }
11038
11039 return 0;
11040}
11041
11042void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
11043{
11044 struct drm_framebuffer *fb = old_plane_state->hw.fb;
11045 struct i915_vma *vma;
11046
11047 if (!intel_fb_uses_dpt(fb)) {
11048 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
11049 if (vma)
11050 intel_unpin_fb_vma(vma, old_plane_state->flags);
11051 } else {
11052 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11053
11054 vma = fetch_and_zero(&old_plane_state->dpt_vma);
11055 if (vma)
11056 intel_unpin_fb_vma(vma, old_plane_state->flags);
11057
11058 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
11059 if (vma)
11060 intel_dpt_unpin(intel_fb->dpt_vm);
11061 }
11062}
11063
11064/**
11065 * intel_prepare_plane_fb - Prepare fb for usage on plane
11066 * @_plane: drm plane to prepare for
11067 * @_new_plane_state: the plane state being prepared
11068 *
11069 * Prepares a framebuffer for usage on a display plane. Generally this
11070 * involves pinning the underlying object and updating the frontbuffer tracking
11071 * bits. Some older platforms need special physical address handling for
11072 * cursor planes.
11073 *
11074 * Returns 0 on success, negative error code on failure.
11075 */
11076int
11077intel_prepare_plane_fb(struct drm_plane *_plane,
11078 struct drm_plane_state *_new_plane_state)
11079{
11080 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
11081 struct intel_plane *plane = to_intel_plane(_plane);
11082 struct intel_plane_state *new_plane_state =
11083 to_intel_plane_state(_new_plane_state);
11084 struct intel_atomic_state *state =
11085 to_intel_atomic_state(new_plane_state->uapi.state);
11086 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11087 const struct intel_plane_state *old_plane_state =
11088 intel_atomic_get_old_plane_state(state, plane);
11089 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
11090 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
11091 int ret;
11092
11093 if (old_obj) {
11094 const struct intel_crtc_state *crtc_state =
11095 intel_atomic_get_new_crtc_state(state,
11096 to_intel_crtc(old_plane_state->hw.crtc));
11097
11098 /* Big Hammer, we also need to ensure that any pending
11099 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
11100 * current scanout is retired before unpinning the old
11101 * framebuffer. Note that we rely on userspace rendering
11102 * into the buffer attached to the pipe they are waiting
11103 * on. If not, userspace generates a GPU hang with IPEHR
11104 * point to the MI_WAIT_FOR_EVENT.
11105 *
11106 * This should only fail upon a hung GPU, in which case we
11107 * can safely continue.
11108 */
11109 if (intel_crtc_needs_modeset(crtc_state)) {
11110 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11111 old_obj->base.resv, NULL,
11112 false, 0,
11113 GFP_KERNEL);
11114 if (ret < 0)
11115 return ret;
11116 }
11117 }
11118
11119 if (new_plane_state->uapi.fence) { /* explicit fencing */
11120 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
11121 &attr);
11122 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
11123 new_plane_state->uapi.fence,
11124 i915_fence_timeout(dev_priv),
11125 GFP_KERNEL);
11126 if (ret < 0)
11127 return ret;
11128 }
11129
11130 if (!obj)
11131 return 0;
11132
11133
11134 ret = intel_plane_pin_fb(new_plane_state);
11135 if (ret)
11136 return ret;
11137
11138 i915_gem_object_wait_priority(obj, 0, &attr);
11139 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
11140
11141 if (!new_plane_state->uapi.fence) { /* implicit fencing */
11142 struct dma_fence *fence;
11143
11144 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11145 obj->base.resv, NULL,
11146 false,
11147 i915_fence_timeout(dev_priv),
11148 GFP_KERNEL);
11149 if (ret < 0)
11150 goto unpin_fb;
11151
11152 fence = dma_resv_get_excl_unlocked(obj->base.resv);
11153 if (fence) {
11154 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11155 fence);
11156 dma_fence_put(fence);
11157 }
11158 } else {
11159 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11160 new_plane_state->uapi.fence);
11161 }
11162
11163 /*
11164 * We declare pageflips to be interactive and so merit a small bias
11165 * towards upclocking to deliver the frame on time. By only changing
11166 * the RPS thresholds to sample more regularly and aim for higher
11167 * clocks we can hopefully deliver low power workloads (like kodi)
11168 * that are not quite steady state without resorting to forcing
11169 * maximum clocks following a vblank miss (see do_rps_boost()).
11170 */
11171 if (!state->rps_interactive) {
11172 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
11173 state->rps_interactive = true;
11174 }
11175
11176 return 0;
11177
11178unpin_fb:
11179 intel_plane_unpin_fb(new_plane_state);
11180
11181 return ret;
11182}
11183
11184/**
11185 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11186 * @plane: drm plane to clean up for
11187 * @_old_plane_state: the state from the previous modeset
11188 *
11189 * Cleans up a framebuffer that has just been removed from a plane.
11190 */
11191void
11192intel_cleanup_plane_fb(struct drm_plane *plane,
11193 struct drm_plane_state *_old_plane_state)
11194{
11195 struct intel_plane_state *old_plane_state =
11196 to_intel_plane_state(_old_plane_state);
11197 struct intel_atomic_state *state =
11198 to_intel_atomic_state(old_plane_state->uapi.state);
11199 struct drm_i915_private *dev_priv = to_i915(plane->dev);
11200 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
11201
11202 if (!obj)
11203 return;
11204
11205 if (state->rps_interactive) {
11206 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
11207 state->rps_interactive = false;
11208 }
11209
11210 /* Should only be called after a successful intel_prepare_plane_fb()! */
11211 intel_plane_unpin_fb(old_plane_state);
11212}
11213
11214/**
11215 * intel_plane_destroy - destroy a plane
11216 * @plane: plane to destroy
11217 *
11218 * Common destruction function for all types of planes (primary, cursor,
11219 * sprite).
11220 */
11221void intel_plane_destroy(struct drm_plane *plane)
11222{
11223 drm_plane_cleanup(plane);
11224 kfree(to_intel_plane(plane));
11225}
11226
11227static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
11228{
11229 struct intel_plane *plane;
11230
11231 for_each_intel_plane(&dev_priv->drm, plane) {
11232 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11233 plane->pipe);
11234
11235 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
11236 }
11237}
11238
11239
11240int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
11241 struct drm_file *file)
11242{
11243 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11244 struct drm_crtc *drmmode_crtc;
11245 struct intel_crtc *crtc;
11246
11247 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
11248 if (!drmmode_crtc)
11249 return -ENOENT;
11250
11251 crtc = to_intel_crtc(drmmode_crtc);
11252 pipe_from_crtc_id->pipe = crtc->pipe;
11253
11254 return 0;
11255}
11256
11257static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
11258{
11259 struct drm_device *dev = encoder->base.dev;
11260 struct intel_encoder *source_encoder;
11261 u32 possible_clones = 0;
11262
11263 for_each_intel_encoder(dev, source_encoder) {
11264 if (encoders_cloneable(encoder, source_encoder))
11265 possible_clones |= drm_encoder_mask(&source_encoder->base);
11266 }
11267
11268 return possible_clones;
11269}
11270
11271static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
11272{
11273 struct drm_device *dev = encoder->base.dev;
11274 struct intel_crtc *crtc;
11275 u32 possible_crtcs = 0;
11276
11277 for_each_intel_crtc(dev, crtc) {
11278 if (encoder->pipe_mask & BIT(crtc->pipe))
11279 possible_crtcs |= drm_crtc_mask(&crtc->base);
11280 }
11281
11282 return possible_crtcs;
11283}
11284
11285static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
11286{
11287 if (!IS_MOBILE(dev_priv))
11288 return false;
11289
11290 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
11291 return false;
11292
11293 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
11294 return false;
11295
11296 return true;
11297}
11298
11299static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
11300{
11301 if (DISPLAY_VER(dev_priv) >= 9)
11302 return false;
11303
11304 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
11305 return false;
11306
11307 if (HAS_PCH_LPT_H(dev_priv) &&
11308 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
11309 return false;
11310
11311 /* DDI E can't be used if DDI A requires 4 lanes */
11312 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
11313 return false;
11314
11315 if (!dev_priv->vbt.int_crt_support)
11316 return false;
11317
11318 return true;
11319}
11320
11321static void intel_setup_outputs(struct drm_i915_private *dev_priv)
11322{
11323 struct intel_encoder *encoder;
11324 bool dpd_is_edp = false;
11325
11326 intel_pps_unlock_regs_wa(dev_priv);
11327
11328 if (!HAS_DISPLAY(dev_priv))
11329 return;
11330
11331 if (IS_ALDERLAKE_P(dev_priv)) {
11332 intel_ddi_init(dev_priv, PORT_A);
11333 intel_ddi_init(dev_priv, PORT_B);
11334 intel_ddi_init(dev_priv, PORT_TC1);
11335 intel_ddi_init(dev_priv, PORT_TC2);
11336 intel_ddi_init(dev_priv, PORT_TC3);
11337 intel_ddi_init(dev_priv, PORT_TC4);
11338 } else if (IS_ALDERLAKE_S(dev_priv)) {
11339 intel_ddi_init(dev_priv, PORT_A);
11340 intel_ddi_init(dev_priv, PORT_TC1);
11341 intel_ddi_init(dev_priv, PORT_TC2);
11342 intel_ddi_init(dev_priv, PORT_TC3);
11343 intel_ddi_init(dev_priv, PORT_TC4);
11344 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
11345 intel_ddi_init(dev_priv, PORT_A);
11346 intel_ddi_init(dev_priv, PORT_B);
11347 intel_ddi_init(dev_priv, PORT_TC1);
11348 intel_ddi_init(dev_priv, PORT_TC2);
11349 } else if (DISPLAY_VER(dev_priv) >= 12) {
11350 intel_ddi_init(dev_priv, PORT_A);
11351 intel_ddi_init(dev_priv, PORT_B);
11352 intel_ddi_init(dev_priv, PORT_TC1);
11353 intel_ddi_init(dev_priv, PORT_TC2);
11354 intel_ddi_init(dev_priv, PORT_TC3);
11355 intel_ddi_init(dev_priv, PORT_TC4);
11356 intel_ddi_init(dev_priv, PORT_TC5);
11357 intel_ddi_init(dev_priv, PORT_TC6);
11358 icl_dsi_init(dev_priv);
11359 } else if (IS_JSL_EHL(dev_priv)) {
11360 intel_ddi_init(dev_priv, PORT_A);
11361 intel_ddi_init(dev_priv, PORT_B);
11362 intel_ddi_init(dev_priv, PORT_C);
11363 intel_ddi_init(dev_priv, PORT_D);
11364 icl_dsi_init(dev_priv);
11365 } else if (DISPLAY_VER(dev_priv) == 11) {
11366 intel_ddi_init(dev_priv, PORT_A);
11367 intel_ddi_init(dev_priv, PORT_B);
11368 intel_ddi_init(dev_priv, PORT_C);
11369 intel_ddi_init(dev_priv, PORT_D);
11370 intel_ddi_init(dev_priv, PORT_E);
11371 intel_ddi_init(dev_priv, PORT_F);
11372 icl_dsi_init(dev_priv);
11373 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
11374 intel_ddi_init(dev_priv, PORT_A);
11375 intel_ddi_init(dev_priv, PORT_B);
11376 intel_ddi_init(dev_priv, PORT_C);
11377 vlv_dsi_init(dev_priv);
11378 } else if (DISPLAY_VER(dev_priv) == 10) {
11379 intel_ddi_init(dev_priv, PORT_A);
11380 intel_ddi_init(dev_priv, PORT_B);
11381 intel_ddi_init(dev_priv, PORT_C);
11382 intel_ddi_init(dev_priv, PORT_D);
11383 intel_ddi_init(dev_priv, PORT_E);
11384 intel_ddi_init(dev_priv, PORT_F);
11385 } else if (DISPLAY_VER(dev_priv) >= 9) {
11386 intel_ddi_init(dev_priv, PORT_A);
11387 intel_ddi_init(dev_priv, PORT_B);
11388 intel_ddi_init(dev_priv, PORT_C);
11389 intel_ddi_init(dev_priv, PORT_D);
11390 intel_ddi_init(dev_priv, PORT_E);
11391 } else if (HAS_DDI(dev_priv)) {
11392 u32 found;
11393
11394 if (intel_ddi_crt_present(dev_priv))
11395 intel_crt_init(dev_priv);
11396
11397 /* Haswell uses DDI functions to detect digital outputs. */
11398 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
11399 if (found)
11400 intel_ddi_init(dev_priv, PORT_A);
11401
11402 found = intel_de_read(dev_priv, SFUSE_STRAP);
11403 if (found & SFUSE_STRAP_DDIB_DETECTED)
11404 intel_ddi_init(dev_priv, PORT_B);
11405 if (found & SFUSE_STRAP_DDIC_DETECTED)
11406 intel_ddi_init(dev_priv, PORT_C);
11407 if (found & SFUSE_STRAP_DDID_DETECTED)
11408 intel_ddi_init(dev_priv, PORT_D);
11409 if (found & SFUSE_STRAP_DDIF_DETECTED)
11410 intel_ddi_init(dev_priv, PORT_F);
11411 } else if (HAS_PCH_SPLIT(dev_priv)) {
11412 int found;
11413
11414 /*
11415 * intel_edp_init_connector() depends on this completing first,
11416 * to prevent the registration of both eDP and LVDS and the
11417 * incorrect sharing of the PPS.
11418 */
11419 intel_lvds_init(dev_priv);
11420 intel_crt_init(dev_priv);
11421
11422 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
11423
11424 if (ilk_has_edp_a(dev_priv))
11425 g4x_dp_init(dev_priv, DP_A, PORT_A);
11426
11427 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
11428 /* PCH SDVOB multiplex with HDMIB */
11429 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
11430 if (!found)
11431 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
11432 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
11433 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
11434 }
11435
11436 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
11437 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
11438
11439 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
11440 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
11441
11442 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
11443 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
11444
11445 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
11446 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
11447 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11448 bool has_edp, has_port;
11449
11450 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
11451 intel_crt_init(dev_priv);
11452
11453 /*
11454 * The DP_DETECTED bit is the latched state of the DDC
11455 * SDA pin at boot. However since eDP doesn't require DDC
11456 * (no way to plug in a DP->HDMI dongle) the DDC pins for
11457 * eDP ports may have been muxed to an alternate function.
11458 * Thus we can't rely on the DP_DETECTED bit alone to detect
11459 * eDP ports. Consult the VBT as well as DP_DETECTED to
11460 * detect eDP ports.
11461 *
11462 * Sadly the straps seem to be missing sometimes even for HDMI
11463 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
11464 * and VBT for the presence of the port. Additionally we can't
11465 * trust the port type the VBT declares as we've seen at least
11466 * HDMI ports that the VBT claim are DP or eDP.
11467 */
11468 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
11469 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
11470 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
11471 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
11472 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
11473 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
11474
11475 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
11476 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
11477 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
11478 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
11479 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
11480 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
11481
11482 if (IS_CHERRYVIEW(dev_priv)) {
11483 /*
11484 * eDP not supported on port D,
11485 * so no need to worry about it
11486 */
11487 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
11488 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
11489 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
11490 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
11491 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
11492 }
11493
11494 vlv_dsi_init(dev_priv);
11495 } else if (IS_PINEVIEW(dev_priv)) {
11496 intel_lvds_init(dev_priv);
11497 intel_crt_init(dev_priv);
11498 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
11499 bool found = false;
11500
11501 if (IS_MOBILE(dev_priv))
11502 intel_lvds_init(dev_priv);
11503
11504 intel_crt_init(dev_priv);
11505
11506 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11507 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
11508 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
11509 if (!found && IS_G4X(dev_priv)) {
11510 drm_dbg_kms(&dev_priv->drm,
11511 "probing HDMI on SDVOB\n");
11512 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
11513 }
11514
11515 if (!found && IS_G4X(dev_priv))
11516 g4x_dp_init(dev_priv, DP_B, PORT_B);
11517 }
11518
11519 /* Before G4X SDVOC doesn't have its own detect register */
11520
11521 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11522 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
11523 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
11524 }
11525
11526 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
11527
11528 if (IS_G4X(dev_priv)) {
11529 drm_dbg_kms(&dev_priv->drm,
11530 "probing HDMI on SDVOC\n");
11531 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
11532 }
11533 if (IS_G4X(dev_priv))
11534 g4x_dp_init(dev_priv, DP_C, PORT_C);
11535 }
11536
11537 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
11538 g4x_dp_init(dev_priv, DP_D, PORT_D);
11539
11540 if (SUPPORTS_TV(dev_priv))
11541 intel_tv_init(dev_priv);
11542 } else if (DISPLAY_VER(dev_priv) == 2) {
11543 if (IS_I85X(dev_priv))
11544 intel_lvds_init(dev_priv);
11545
11546 intel_crt_init(dev_priv);
11547 intel_dvo_init(dev_priv);
11548 }
11549
11550 for_each_intel_encoder(&dev_priv->drm, encoder) {
11551 encoder->base.possible_crtcs =
11552 intel_encoder_possible_crtcs(encoder);
11553 encoder->base.possible_clones =
11554 intel_encoder_possible_clones(encoder);
11555 }
11556
11557 intel_init_pch_refclk(dev_priv);
11558
11559 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
11560}
11561
11562static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11563{
11564 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11565
11566 drm_framebuffer_cleanup(fb);
11567
11568 if (intel_fb_uses_dpt(fb))
11569 intel_dpt_destroy(intel_fb->dpt_vm);
11570
11571 intel_frontbuffer_put(intel_fb->frontbuffer);
11572
11573 kfree(intel_fb);
11574}
11575
11576static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11577 struct drm_file *file,
11578 unsigned int *handle)
11579{
11580 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11581 struct drm_i915_private *i915 = to_i915(obj->base.dev);
11582
11583 if (i915_gem_object_is_userptr(obj)) {
11584 drm_dbg(&i915->drm,
11585 "attempting to use a userptr for a framebuffer, denied\n");
11586 return -EINVAL;
11587 }
11588
11589 return drm_gem_handle_create(file, &obj->base, handle);
11590}
11591
11592static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
11593 struct drm_file *file,
11594 unsigned flags, unsigned color,
11595 struct drm_clip_rect *clips,
11596 unsigned num_clips)
11597{
11598 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11599
11600 i915_gem_object_flush_if_display(obj);
11601 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
11602
11603 return 0;
11604}
11605
11606static const struct drm_framebuffer_funcs intel_fb_funcs = {
11607 .destroy = intel_user_framebuffer_destroy,
11608 .create_handle = intel_user_framebuffer_create_handle,
11609 .dirty = intel_user_framebuffer_dirty,
11610};
11611
11612static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
11613 struct drm_i915_gem_object *obj,
11614 struct drm_mode_fb_cmd2 *mode_cmd)
11615{
11616 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
11617 struct drm_framebuffer *fb = &intel_fb->base;
11618 u32 max_stride;
11619 unsigned int tiling, stride;
11620 int ret = -EINVAL;
11621 int i;
11622
11623 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
11624 if (!intel_fb->frontbuffer)
11625 return -ENOMEM;
11626
11627 i915_gem_object_lock(obj, NULL);
11628 tiling = i915_gem_object_get_tiling(obj);
11629 stride = i915_gem_object_get_stride(obj);
11630 i915_gem_object_unlock(obj);
11631
11632 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
11633 /*
11634 * If there's a fence, enforce that
11635 * the fb modifier and tiling mode match.
11636 */
11637 if (tiling != I915_TILING_NONE &&
11638 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11639 drm_dbg_kms(&dev_priv->drm,
11640 "tiling_mode doesn't match fb modifier\n");
11641 goto err;
11642 }
11643 } else {
11644 if (tiling == I915_TILING_X) {
11645 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
11646 } else if (tiling == I915_TILING_Y) {
11647 drm_dbg_kms(&dev_priv->drm,
11648 "No Y tiling for legacy addfb\n");
11649 goto err;
11650 }
11651 }
11652
11653 if (!drm_any_plane_has_format(&dev_priv->drm,
11654 mode_cmd->pixel_format,
11655 mode_cmd->modifier[0])) {
11656 drm_dbg_kms(&dev_priv->drm,
11657 "unsupported pixel format %p4cc / modifier 0x%llx\n",
11658 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
11659 goto err;
11660 }
11661
11662 /*
11663 * gen2/3 display engine uses the fence if present,
11664 * so the tiling mode must match the fb modifier exactly.
11665 */
11666 if (DISPLAY_VER(dev_priv) < 4 &&
11667 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11668 drm_dbg_kms(&dev_priv->drm,
11669 "tiling_mode must match fb modifier exactly on gen2/3\n");
11670 goto err;
11671 }
11672
11673 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
11674 mode_cmd->modifier[0]);
11675 if (mode_cmd->pitches[0] > max_stride) {
11676 drm_dbg_kms(&dev_priv->drm,
11677 "%s pitch (%u) must be at most %d\n",
11678 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
11679 "tiled" : "linear",
11680 mode_cmd->pitches[0], max_stride);
11681 goto err;
11682 }
11683
11684 /*
11685 * If there's a fence, enforce that
11686 * the fb pitch and fence stride match.
11687 */
11688 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
11689 drm_dbg_kms(&dev_priv->drm,
11690 "pitch (%d) must match tiling stride (%d)\n",
11691 mode_cmd->pitches[0], stride);
11692 goto err;
11693 }
11694
11695 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11696 if (mode_cmd->offsets[0] != 0) {
11697 drm_dbg_kms(&dev_priv->drm,
11698 "plane 0 offset (0x%08x) must be 0\n",
11699 mode_cmd->offsets[0]);
11700 goto err;
11701 }
11702
11703 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
11704
11705 for (i = 0; i < fb->format->num_planes; i++) {
11706 u32 stride_alignment;
11707
11708 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
11709 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
11710 i);
11711 goto err;
11712 }
11713
11714 stride_alignment = intel_fb_stride_alignment(fb, i);
11715 if (fb->pitches[i] & (stride_alignment - 1)) {
11716 drm_dbg_kms(&dev_priv->drm,
11717 "plane %d pitch (%d) must be at least %u byte aligned\n",
11718 i, fb->pitches[i], stride_alignment);
11719 goto err;
11720 }
11721
11722 if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
11723 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
11724
11725 if (fb->pitches[i] != ccs_aux_stride) {
11726 drm_dbg_kms(&dev_priv->drm,
11727 "ccs aux plane %d pitch (%d) must be %d\n",
11728 i,
11729 fb->pitches[i], ccs_aux_stride);
11730 goto err;
11731 }
11732 }
11733
11734 /* TODO: Add POT stride remapping support for CCS formats as well. */
11735 if (IS_ALDERLAKE_P(dev_priv) &&
11736 mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
11737 !intel_fb_needs_pot_stride_remap(intel_fb) &&
11738 !is_power_of_2(mode_cmd->pitches[i])) {
11739 drm_dbg_kms(&dev_priv->drm,
11740 "plane %d pitch (%d) must be power of two for tiled buffers\n",
11741 i, mode_cmd->pitches[i]);
11742 goto err;
11743 }
11744
11745 fb->obj[i] = &obj->base;
11746 }
11747
11748 ret = intel_fill_fb_info(dev_priv, intel_fb);
11749 if (ret)
11750 goto err;
11751
11752 if (intel_fb_uses_dpt(fb)) {
11753 struct i915_address_space *vm;
11754
11755 vm = intel_dpt_create(intel_fb);
11756 if (IS_ERR(vm)) {
11757 ret = PTR_ERR(vm);
11758 goto err;
11759 }
11760
11761 intel_fb->dpt_vm = vm;
11762 }
11763
11764 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
11765 if (ret) {
11766 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
11767 goto err;
11768 }
11769
11770 return 0;
11771
11772err:
11773 intel_frontbuffer_put(intel_fb->frontbuffer);
11774 return ret;
11775}
11776
11777static struct drm_framebuffer *
11778intel_user_framebuffer_create(struct drm_device *dev,
11779 struct drm_file *filp,
11780 const struct drm_mode_fb_cmd2 *user_mode_cmd)
11781{
11782 struct drm_framebuffer *fb;
11783 struct drm_i915_gem_object *obj;
11784 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
11785 struct drm_i915_private *i915;
11786
11787 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
11788 if (!obj)
11789 return ERR_PTR(-ENOENT);
11790
11791 /* object is backed with LMEM for discrete */
11792 i915 = to_i915(obj->base.dev);
11793 if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj)) {
11794 /* object is "remote", not in local memory */
11795 i915_gem_object_put(obj);
11796 return ERR_PTR(-EREMOTE);
11797 }
11798
11799 fb = intel_framebuffer_create(obj, &mode_cmd);
11800 i915_gem_object_put(obj);
11801
11802 return fb;
11803}
11804
11805static enum drm_mode_status
11806intel_mode_valid(struct drm_device *dev,
11807 const struct drm_display_mode *mode)
11808{
11809 struct drm_i915_private *dev_priv = to_i915(dev);
11810 int hdisplay_max, htotal_max;
11811 int vdisplay_max, vtotal_max;
11812
11813 /*
11814 * Can't reject DBLSCAN here because Xorg ddxen can add piles
11815 * of DBLSCAN modes to the output's mode list when they detect
11816 * the scaling mode property on the connector. And they don't
11817 * ask the kernel to validate those modes in any way until
11818 * modeset time at which point the client gets a protocol error.
11819 * So in order to not upset those clients we silently ignore the
11820 * DBLSCAN flag on such connectors. For other connectors we will
11821 * reject modes with the DBLSCAN flag in encoder->compute_config().
11822 * And we always reject DBLSCAN modes in connector->mode_valid()
11823 * as we never want such modes on the connector's mode list.
11824 */
11825
11826 if (mode->vscan > 1)
11827 return MODE_NO_VSCAN;
11828
11829 if (mode->flags & DRM_MODE_FLAG_HSKEW)
11830 return MODE_H_ILLEGAL;
11831
11832 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
11833 DRM_MODE_FLAG_NCSYNC |
11834 DRM_MODE_FLAG_PCSYNC))
11835 return MODE_HSYNC;
11836
11837 if (mode->flags & (DRM_MODE_FLAG_BCAST |
11838 DRM_MODE_FLAG_PIXMUX |
11839 DRM_MODE_FLAG_CLKDIV2))
11840 return MODE_BAD;
11841
11842 /* Transcoder timing limits */
11843 if (DISPLAY_VER(dev_priv) >= 11) {
11844 hdisplay_max = 16384;
11845 vdisplay_max = 8192;
11846 htotal_max = 16384;
11847 vtotal_max = 8192;
11848 } else if (DISPLAY_VER(dev_priv) >= 9 ||
11849 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
11850 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
11851 vdisplay_max = 4096;
11852 htotal_max = 8192;
11853 vtotal_max = 8192;
11854 } else if (DISPLAY_VER(dev_priv) >= 3) {
11855 hdisplay_max = 4096;
11856 vdisplay_max = 4096;
11857 htotal_max = 8192;
11858 vtotal_max = 8192;
11859 } else {
11860 hdisplay_max = 2048;
11861 vdisplay_max = 2048;
11862 htotal_max = 4096;
11863 vtotal_max = 4096;
11864 }
11865
11866 if (mode->hdisplay > hdisplay_max ||
11867 mode->hsync_start > htotal_max ||
11868 mode->hsync_end > htotal_max ||
11869 mode->htotal > htotal_max)
11870 return MODE_H_ILLEGAL;
11871
11872 if (mode->vdisplay > vdisplay_max ||
11873 mode->vsync_start > vtotal_max ||
11874 mode->vsync_end > vtotal_max ||
11875 mode->vtotal > vtotal_max)
11876 return MODE_V_ILLEGAL;
11877
11878 if (DISPLAY_VER(dev_priv) >= 5) {
11879 if (mode->hdisplay < 64 ||
11880 mode->htotal - mode->hdisplay < 32)
11881 return MODE_H_ILLEGAL;
11882
11883 if (mode->vtotal - mode->vdisplay < 5)
11884 return MODE_V_ILLEGAL;
11885 } else {
11886 if (mode->htotal - mode->hdisplay < 32)
11887 return MODE_H_ILLEGAL;
11888
11889 if (mode->vtotal - mode->vdisplay < 3)
11890 return MODE_V_ILLEGAL;
11891 }
11892
11893 return MODE_OK;
11894}
11895
11896enum drm_mode_status
11897intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
11898 const struct drm_display_mode *mode,
11899 bool bigjoiner)
11900{
11901 int plane_width_max, plane_height_max;
11902
11903 /*
11904 * intel_mode_valid() should be
11905 * sufficient on older platforms.
11906 */
11907 if (DISPLAY_VER(dev_priv) < 9)
11908 return MODE_OK;
11909
11910 /*
11911 * Most people will probably want a fullscreen
11912 * plane so let's not advertize modes that are
11913 * too big for that.
11914 */
11915 if (DISPLAY_VER(dev_priv) >= 11) {
11916 plane_width_max = 5120 << bigjoiner;
11917 plane_height_max = 4320;
11918 } else {
11919 plane_width_max = 5120;
11920 plane_height_max = 4096;
11921 }
11922
11923 if (mode->hdisplay > plane_width_max)
11924 return MODE_H_ILLEGAL;
11925
11926 if (mode->vdisplay > plane_height_max)
11927 return MODE_V_ILLEGAL;
11928
11929 return MODE_OK;
11930}
11931
11932static const struct drm_mode_config_funcs intel_mode_funcs = {
11933 .fb_create = intel_user_framebuffer_create,
11934 .get_format_info = intel_get_format_info,
11935 .output_poll_changed = intel_fbdev_output_poll_changed,
11936 .mode_valid = intel_mode_valid,
11937 .atomic_check = intel_atomic_check,
11938 .atomic_commit = intel_atomic_commit,
11939 .atomic_state_alloc = intel_atomic_state_alloc,
11940 .atomic_state_clear = intel_atomic_state_clear,
11941 .atomic_state_free = intel_atomic_state_free,
11942};
11943
11944/**
11945 * intel_init_display_hooks - initialize the display modesetting hooks
11946 * @dev_priv: device private
11947 */
11948void intel_init_display_hooks(struct drm_i915_private *dev_priv)
11949{
11950 if (!HAS_DISPLAY(dev_priv))
11951 return;
11952
11953 intel_init_cdclk_hooks(dev_priv);
11954 intel_init_audio_hooks(dev_priv);
11955
11956 intel_dpll_init_clock_hook(dev_priv);
11957
11958 if (DISPLAY_VER(dev_priv) >= 9) {
11959 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11960 dev_priv->display.crtc_enable = hsw_crtc_enable;
11961 dev_priv->display.crtc_disable = hsw_crtc_disable;
11962 } else if (HAS_DDI(dev_priv)) {
11963 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11964 dev_priv->display.crtc_enable = hsw_crtc_enable;
11965 dev_priv->display.crtc_disable = hsw_crtc_disable;
11966 } else if (HAS_PCH_SPLIT(dev_priv)) {
11967 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
11968 dev_priv->display.crtc_enable = ilk_crtc_enable;
11969 dev_priv->display.crtc_disable = ilk_crtc_disable;
11970 } else if (IS_CHERRYVIEW(dev_priv) ||
11971 IS_VALLEYVIEW(dev_priv)) {
11972 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11973 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11974 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11975 } else {
11976 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11977 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11978 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11979 }
11980
11981 intel_fdi_init_hook(dev_priv);
11982
11983 if (DISPLAY_VER(dev_priv) >= 9) {
11984 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
11985 dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
11986 } else {
11987 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
11988 dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
11989 }
11990
11991}
11992
11993void intel_modeset_init_hw(struct drm_i915_private *i915)
11994{
11995 struct intel_cdclk_state *cdclk_state;
11996
11997 if (!HAS_DISPLAY(i915))
11998 return;
11999
12000 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
12001
12002 intel_update_cdclk(i915);
12003 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
12004 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
12005}
12006
12007static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
12008{
12009 struct drm_plane *plane;
12010 struct intel_crtc *crtc;
12011
12012 for_each_intel_crtc(state->dev, crtc) {
12013 struct intel_crtc_state *crtc_state;
12014
12015 crtc_state = intel_atomic_get_crtc_state(state, crtc);
12016 if (IS_ERR(crtc_state))
12017 return PTR_ERR(crtc_state);
12018
12019 if (crtc_state->hw.active) {
12020 /*
12021 * Preserve the inherited flag to avoid
12022 * taking the full modeset path.
12023 */
12024 crtc_state->inherited = true;
12025 }
12026 }
12027
12028 drm_for_each_plane(plane, state->dev) {
12029 struct drm_plane_state *plane_state;
12030
12031 plane_state = drm_atomic_get_plane_state(state, plane);
12032 if (IS_ERR(plane_state))
12033 return PTR_ERR(plane_state);
12034 }
12035
12036 return 0;
12037}
12038
12039/*
12040 * Calculate what we think the watermarks should be for the state we've read
12041 * out of the hardware and then immediately program those watermarks so that
12042 * we ensure the hardware settings match our internal state.
12043 *
12044 * We can calculate what we think WM's should be by creating a duplicate of the
12045 * current state (which was constructed during hardware readout) and running it
12046 * through the atomic check code to calculate new watermark values in the
12047 * state object.
12048 */
12049static void sanitize_watermarks(struct drm_i915_private *dev_priv)
12050{
12051 struct drm_atomic_state *state;
12052 struct intel_atomic_state *intel_state;
12053 struct intel_crtc *crtc;
12054 struct intel_crtc_state *crtc_state;
12055 struct drm_modeset_acquire_ctx ctx;
12056 int ret;
12057 int i;
12058
12059 /* Only supported on platforms that use atomic watermark design */
12060 if (!dev_priv->display.optimize_watermarks)
12061 return;
12062
12063 state = drm_atomic_state_alloc(&dev_priv->drm);
12064 if (drm_WARN_ON(&dev_priv->drm, !state))
12065 return;
12066
12067 intel_state = to_intel_atomic_state(state);
12068
12069 drm_modeset_acquire_init(&ctx, 0);
12070
12071retry:
12072 state->acquire_ctx = &ctx;
12073
12074 /*
12075 * Hardware readout is the only time we don't want to calculate
12076 * intermediate watermarks (since we don't trust the current
12077 * watermarks).
12078 */
12079 if (!HAS_GMCH(dev_priv))
12080 intel_state->skip_intermediate_wm = true;
12081
12082 ret = sanitize_watermarks_add_affected(state);
12083 if (ret)
12084 goto fail;
12085
12086 ret = intel_atomic_check(&dev_priv->drm, state);
12087 if (ret)
12088 goto fail;
12089
12090 /* Write calculated watermark values back */
12091 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
12092 crtc_state->wm.need_postvbl_update = true;
12093 dev_priv->display.optimize_watermarks(intel_state, crtc);
12094
12095 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
12096 }
12097
12098fail:
12099 if (ret == -EDEADLK) {
12100 drm_atomic_state_clear(state);
12101 drm_modeset_backoff(&ctx);
12102 goto retry;
12103 }
12104
12105 /*
12106 * If we fail here, it means that the hardware appears to be
12107 * programmed in a way that shouldn't be possible, given our
12108 * understanding of watermark requirements. This might mean a
12109 * mistake in the hardware readout code or a mistake in the
12110 * watermark calculations for a given platform. Raise a WARN
12111 * so that this is noticeable.
12112 *
12113 * If this actually happens, we'll have to just leave the
12114 * BIOS-programmed watermarks untouched and hope for the best.
12115 */
12116 drm_WARN(&dev_priv->drm, ret,
12117 "Could not determine valid watermarks for inherited state\n");
12118
12119 drm_atomic_state_put(state);
12120
12121 drm_modeset_drop_locks(&ctx);
12122 drm_modeset_acquire_fini(&ctx);
12123}
12124
12125static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
12126{
12127 if (IS_IRONLAKE(dev_priv)) {
12128 u32 fdi_pll_clk =
12129 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
12130
12131 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
12132 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
12133 dev_priv->fdi_pll_freq = 270000;
12134 } else {
12135 return;
12136 }
12137
12138 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
12139}
12140
12141static int intel_initial_commit(struct drm_device *dev)
12142{
12143 struct drm_atomic_state *state = NULL;
12144 struct drm_modeset_acquire_ctx ctx;
12145 struct intel_crtc *crtc;
12146 int ret = 0;
12147
12148 state = drm_atomic_state_alloc(dev);
12149 if (!state)
12150 return -ENOMEM;
12151
12152 drm_modeset_acquire_init(&ctx, 0);
12153
12154retry:
12155 state->acquire_ctx = &ctx;
12156
12157 for_each_intel_crtc(dev, crtc) {
12158 struct intel_crtc_state *crtc_state =
12159 intel_atomic_get_crtc_state(state, crtc);
12160
12161 if (IS_ERR(crtc_state)) {
12162 ret = PTR_ERR(crtc_state);
12163 goto out;
12164 }
12165
12166 if (crtc_state->hw.active) {
12167 struct intel_encoder *encoder;
12168
12169 /*
12170 * We've not yet detected sink capabilities
12171 * (audio,infoframes,etc.) and thus we don't want to
12172 * force a full state recomputation yet. We want that to
12173 * happen only for the first real commit from userspace.
12174 * So preserve the inherited flag for the time being.
12175 */
12176 crtc_state->inherited = true;
12177
12178 ret = drm_atomic_add_affected_planes(state, &crtc->base);
12179 if (ret)
12180 goto out;
12181
12182 /*
12183 * FIXME hack to force a LUT update to avoid the
12184 * plane update forcing the pipe gamma on without
12185 * having a proper LUT loaded. Remove once we
12186 * have readout for pipe gamma enable.
12187 */
12188 crtc_state->uapi.color_mgmt_changed = true;
12189
12190 for_each_intel_encoder_mask(dev, encoder,
12191 crtc_state->uapi.encoder_mask) {
12192 if (encoder->initial_fastset_check &&
12193 !encoder->initial_fastset_check(encoder, crtc_state)) {
12194 ret = drm_atomic_add_affected_connectors(state,
12195 &crtc->base);
12196 if (ret)
12197 goto out;
12198 }
12199 }
12200 }
12201 }
12202
12203 ret = drm_atomic_commit(state);
12204
12205out:
12206 if (ret == -EDEADLK) {
12207 drm_atomic_state_clear(state);
12208 drm_modeset_backoff(&ctx);
12209 goto retry;
12210 }
12211
12212 drm_atomic_state_put(state);
12213
12214 drm_modeset_drop_locks(&ctx);
12215 drm_modeset_acquire_fini(&ctx);
12216
12217 return ret;
12218}
12219
12220static void intel_mode_config_init(struct drm_i915_private *i915)
12221{
12222 struct drm_mode_config *mode_config = &i915->drm.mode_config;
12223
12224 drm_mode_config_init(&i915->drm);
12225 INIT_LIST_HEAD(&i915->global_obj_list);
12226
12227 mode_config->min_width = 0;
12228 mode_config->min_height = 0;
12229
12230 mode_config->preferred_depth = 24;
12231 mode_config->prefer_shadow = 1;
12232
12233 mode_config->funcs = &intel_mode_funcs;
12234
12235 mode_config->async_page_flip = has_async_flips(i915);
12236
12237 /*
12238 * Maximum framebuffer dimensions, chosen to match
12239 * the maximum render engine surface size on gen4+.
12240 */
12241 if (DISPLAY_VER(i915) >= 7) {
12242 mode_config->max_width = 16384;
12243 mode_config->max_height = 16384;
12244 } else if (DISPLAY_VER(i915) >= 4) {
12245 mode_config->max_width = 8192;
12246 mode_config->max_height = 8192;
12247 } else if (DISPLAY_VER(i915) == 3) {
12248 mode_config->max_width = 4096;
12249 mode_config->max_height = 4096;
12250 } else {
12251 mode_config->max_width = 2048;
12252 mode_config->max_height = 2048;
12253 }
12254
12255 if (IS_I845G(i915) || IS_I865G(i915)) {
12256 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
12257 mode_config->cursor_height = 1023;
12258 } else if (IS_I830(i915) || IS_I85X(i915) ||
12259 IS_I915G(i915) || IS_I915GM(i915)) {
12260 mode_config->cursor_width = 64;
12261 mode_config->cursor_height = 64;
12262 } else {
12263 mode_config->cursor_width = 256;
12264 mode_config->cursor_height = 256;
12265 }
12266}
12267
12268static void intel_mode_config_cleanup(struct drm_i915_private *i915)
12269{
12270 intel_atomic_global_obj_cleanup(i915);
12271 drm_mode_config_cleanup(&i915->drm);
12272}
12273
12274static void plane_config_fini(struct intel_initial_plane_config *plane_config)
12275{
12276 if (plane_config->fb) {
12277 struct drm_framebuffer *fb = &plane_config->fb->base;
12278
12279 /* We may only have the stub and not a full framebuffer */
12280 if (drm_framebuffer_read_refcount(fb))
12281 drm_framebuffer_put(fb);
12282 else
12283 kfree(fb);
12284 }
12285
12286 if (plane_config->vma)
12287 i915_vma_put(plane_config->vma);
12288}
12289
12290/* part #1: call before irq install */
12291int intel_modeset_init_noirq(struct drm_i915_private *i915)
12292{
12293 int ret;
12294
12295 if (i915_inject_probe_failure(i915))
12296 return -ENODEV;
12297
12298 if (HAS_DISPLAY(i915)) {
12299 ret = drm_vblank_init(&i915->drm,
12300 INTEL_NUM_PIPES(i915));
12301 if (ret)
12302 return ret;
12303 }
12304
12305 intel_bios_init(i915);
12306
12307 ret = intel_vga_register(i915);
12308 if (ret)
12309 goto cleanup_bios;
12310
12311 /* FIXME: completely on the wrong abstraction layer */
12312 intel_power_domains_init_hw(i915, false);
12313
12314 if (!HAS_DISPLAY(i915))
12315 return 0;
12316
12317 intel_dmc_ucode_init(i915);
12318
12319 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
12320 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
12321 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
12322
12323 i915->framestart_delay = 1; /* 1-4 */
12324
12325 i915->window2_delay = 0; /* No DSB so no window2 delay */
12326
12327 intel_mode_config_init(i915);
12328
12329 ret = intel_cdclk_init(i915);
12330 if (ret)
12331 goto cleanup_vga_client_pw_domain_dmc;
12332
12333 ret = intel_dbuf_init(i915);
12334 if (ret)
12335 goto cleanup_vga_client_pw_domain_dmc;
12336
12337 ret = intel_bw_init(i915);
12338 if (ret)
12339 goto cleanup_vga_client_pw_domain_dmc;
12340
12341 init_llist_head(&i915->atomic_helper.free_list);
12342 INIT_WORK(&i915->atomic_helper.free_work,
12343 intel_atomic_helper_free_state_worker);
12344
12345 intel_init_quirks(i915);
12346
12347 intel_fbc_init(i915);
12348
12349 return 0;
12350
12351cleanup_vga_client_pw_domain_dmc:
12352 intel_dmc_ucode_fini(i915);
12353 intel_power_domains_driver_remove(i915);
12354 intel_vga_unregister(i915);
12355cleanup_bios:
12356 intel_bios_driver_remove(i915);
12357
12358 return ret;
12359}
12360
12361/* part #2: call after irq install, but before gem init */
12362int intel_modeset_init_nogem(struct drm_i915_private *i915)
12363{
12364 struct drm_device *dev = &i915->drm;
12365 enum pipe pipe;
12366 struct intel_crtc *crtc;
12367 int ret;
12368
12369 if (!HAS_DISPLAY(i915))
12370 return 0;
12371
12372 intel_init_pm(i915);
12373
12374 intel_panel_sanitize_ssc(i915);
12375
12376 intel_pps_setup(i915);
12377
12378 intel_gmbus_setup(i915);
12379
12380 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
12381 INTEL_NUM_PIPES(i915),
12382 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
12383
12384 for_each_pipe(i915, pipe) {
12385 ret = intel_crtc_init(i915, pipe);
12386 if (ret) {
12387 intel_mode_config_cleanup(i915);
12388 return ret;
12389 }
12390 }
12391
12392 intel_plane_possible_crtcs_init(i915);
12393 intel_shared_dpll_init(dev);
12394 intel_update_fdi_pll_freq(i915);
12395
12396 intel_update_czclk(i915);
12397 intel_modeset_init_hw(i915);
12398 intel_dpll_update_ref_clks(i915);
12399
12400 intel_hdcp_component_init(i915);
12401
12402 if (i915->max_cdclk_freq == 0)
12403 intel_update_max_cdclk(i915);
12404
12405 /*
12406 * If the platform has HTI, we need to find out whether it has reserved
12407 * any display resources before we create our display outputs.
12408 */
12409 if (INTEL_INFO(i915)->display.has_hti)
12410 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
12411
12412 /* Just disable it once at startup */
12413 intel_vga_disable(i915);
12414 intel_setup_outputs(i915);
12415
12416 drm_modeset_lock_all(dev);
12417 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
12418 drm_modeset_unlock_all(dev);
12419
12420 for_each_intel_crtc(dev, crtc) {
12421 struct intel_initial_plane_config plane_config = {};
12422
12423 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
12424 continue;
12425
12426 /*
12427 * Note that reserving the BIOS fb up front prevents us
12428 * from stuffing other stolen allocations like the ring
12429 * on top. This prevents some ugliness at boot time, and
12430 * can even allow for smooth boot transitions if the BIOS
12431 * fb is large enough for the active pipe configuration.
12432 */
12433 i915->display.get_initial_plane_config(crtc, &plane_config);
12434
12435 /*
12436 * If the fb is shared between multiple heads, we'll
12437 * just get the first one.
12438 */
12439 intel_find_initial_plane_obj(crtc, &plane_config);
12440
12441 plane_config_fini(&plane_config);
12442 }
12443
12444 /*
12445 * Make sure hardware watermarks really match the state we read out.
12446 * Note that we need to do this after reconstructing the BIOS fb's
12447 * since the watermark calculation done here will use pstate->fb.
12448 */
12449 if (!HAS_GMCH(i915))
12450 sanitize_watermarks(i915);
12451
12452 return 0;
12453}
12454
12455/* part #3: call after gem init */
12456int intel_modeset_init(struct drm_i915_private *i915)
12457{
12458 int ret;
12459
12460 if (!HAS_DISPLAY(i915))
12461 return 0;
12462
12463 /*
12464 * Force all active planes to recompute their states. So that on
12465 * mode_setcrtc after probe, all the intel_plane_state variables
12466 * are already calculated and there is no assert_plane warnings
12467 * during bootup.
12468 */
12469 ret = intel_initial_commit(&i915->drm);
12470 if (ret)
12471 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
12472
12473 intel_overlay_setup(i915);
12474
12475 ret = intel_fbdev_init(&i915->drm);
12476 if (ret)
12477 return ret;
12478
12479 /* Only enable hotplug handling once the fbdev is fully set up. */
12480 intel_hpd_init(i915);
12481 intel_hpd_poll_disable(i915);
12482
12483 intel_init_ipc(i915);
12484
12485 return 0;
12486}
12487
12488void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12489{
12490 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12491 /* 640x480@60Hz, ~25175 kHz */
12492 struct dpll clock = {
12493 .m1 = 18,
12494 .m2 = 7,
12495 .p1 = 13,
12496 .p2 = 4,
12497 .n = 2,
12498 };
12499 u32 dpll, fp;
12500 int i;
12501
12502 drm_WARN_ON(&dev_priv->drm,
12503 i9xx_calc_dpll_params(48000, &clock) != 25154);
12504
12505 drm_dbg_kms(&dev_priv->drm,
12506 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
12507 pipe_name(pipe), clock.vco, clock.dot);
12508
12509 fp = i9xx_dpll_compute_fp(&clock);
12510 dpll = DPLL_DVO_2X_MODE |
12511 DPLL_VGA_MODE_DIS |
12512 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
12513 PLL_P2_DIVIDE_BY_4 |
12514 PLL_REF_INPUT_DREFCLK |
12515 DPLL_VCO_ENABLE;
12516
12517 intel_de_write(dev_priv, FP0(pipe), fp);
12518 intel_de_write(dev_priv, FP1(pipe), fp);
12519
12520 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
12521 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
12522 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
12523 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
12524 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
12525 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
12526 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
12527
12528 /*
12529 * Apparently we need to have VGA mode enabled prior to changing
12530 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
12531 * dividers, even though the register value does change.
12532 */
12533 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
12534 intel_de_write(dev_priv, DPLL(pipe), dpll);
12535
12536 /* Wait for the clocks to stabilize. */
12537 intel_de_posting_read(dev_priv, DPLL(pipe));
12538 udelay(150);
12539
12540 /* The pixel multiplier can only be updated once the
12541 * DPLL is enabled and the clocks are stable.
12542 *
12543 * So write it again.
12544 */
12545 intel_de_write(dev_priv, DPLL(pipe), dpll);
12546
12547 /* We do this three times for luck */
12548 for (i = 0; i < 3 ; i++) {
12549 intel_de_write(dev_priv, DPLL(pipe), dpll);
12550 intel_de_posting_read(dev_priv, DPLL(pipe));
12551 udelay(150); /* wait for warmup */
12552 }
12553
12554 intel_de_write(dev_priv, PIPECONF(pipe),
12555 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
12556 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12557
12558 intel_wait_for_pipe_scanline_moving(crtc);
12559}
12560
12561void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12562{
12563 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12564
12565 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
12566 pipe_name(pipe));
12567
12568 drm_WARN_ON(&dev_priv->drm,
12569 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
12570 DISPLAY_PLANE_ENABLE);
12571 drm_WARN_ON(&dev_priv->drm,
12572 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
12573 DISPLAY_PLANE_ENABLE);
12574 drm_WARN_ON(&dev_priv->drm,
12575 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
12576 DISPLAY_PLANE_ENABLE);
12577 drm_WARN_ON(&dev_priv->drm,
12578 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
12579 drm_WARN_ON(&dev_priv->drm,
12580 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
12581
12582 intel_de_write(dev_priv, PIPECONF(pipe), 0);
12583 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12584
12585 intel_wait_for_pipe_scanline_stopped(crtc);
12586
12587 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
12588 intel_de_posting_read(dev_priv, DPLL(pipe));
12589}
12590
12591static void
12592intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
12593{
12594 struct intel_crtc *crtc;
12595
12596 if (DISPLAY_VER(dev_priv) >= 4)
12597 return;
12598
12599 for_each_intel_crtc(&dev_priv->drm, crtc) {
12600 struct intel_plane *plane =
12601 to_intel_plane(crtc->base.primary);
12602 struct intel_crtc *plane_crtc;
12603 enum pipe pipe;
12604
12605 if (!plane->get_hw_state(plane, &pipe))
12606 continue;
12607
12608 if (pipe == crtc->pipe)
12609 continue;
12610
12611 drm_dbg_kms(&dev_priv->drm,
12612 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
12613 plane->base.base.id, plane->base.name);
12614
12615 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12616 intel_plane_disable_noatomic(plane_crtc, plane);
12617 }
12618}
12619
12620static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
12621{
12622 struct drm_device *dev = crtc->base.dev;
12623 struct intel_encoder *encoder;
12624
12625 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
12626 return true;
12627
12628 return false;
12629}
12630
12631static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
12632{
12633 struct drm_device *dev = encoder->base.dev;
12634 struct intel_connector *connector;
12635
12636 for_each_connector_on_encoder(dev, &encoder->base, connector)
12637 return connector;
12638
12639 return NULL;
12640}
12641
12642static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
12643 enum pipe pch_transcoder)
12644{
12645 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
12646 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
12647}
12648
12649static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
12650{
12651 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12652 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12653 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
12654
12655 if (DISPLAY_VER(dev_priv) >= 9 ||
12656 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12657 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
12658 u32 val;
12659
12660 if (transcoder_is_dsi(cpu_transcoder))
12661 return;
12662
12663 val = intel_de_read(dev_priv, reg);
12664 val &= ~HSW_FRAME_START_DELAY_MASK;
12665 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12666 intel_de_write(dev_priv, reg, val);
12667 } else {
12668 i915_reg_t reg = PIPECONF(cpu_transcoder);
12669 u32 val;
12670
12671 val = intel_de_read(dev_priv, reg);
12672 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
12673 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12674 intel_de_write(dev_priv, reg, val);
12675 }
12676
12677 if (!crtc_state->has_pch_encoder)
12678 return;
12679
12680 if (HAS_PCH_IBX(dev_priv)) {
12681 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
12682 u32 val;
12683
12684 val = intel_de_read(dev_priv, reg);
12685 val &= ~TRANS_FRAME_START_DELAY_MASK;
12686 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12687 intel_de_write(dev_priv, reg, val);
12688 } else {
12689 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
12690 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
12691 u32 val;
12692
12693 val = intel_de_read(dev_priv, reg);
12694 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
12695 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12696 intel_de_write(dev_priv, reg, val);
12697 }
12698}
12699
12700static void intel_sanitize_crtc(struct intel_crtc *crtc,
12701 struct drm_modeset_acquire_ctx *ctx)
12702{
12703 struct drm_device *dev = crtc->base.dev;
12704 struct drm_i915_private *dev_priv = to_i915(dev);
12705 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
12706
12707 if (crtc_state->hw.active) {
12708 struct intel_plane *plane;
12709
12710 /* Clear any frame start delays used for debugging left by the BIOS */
12711 intel_sanitize_frame_start_delay(crtc_state);
12712
12713 /* Disable everything but the primary plane */
12714 for_each_intel_plane_on_crtc(dev, crtc, plane) {
12715 const struct intel_plane_state *plane_state =
12716 to_intel_plane_state(plane->base.state);
12717
12718 if (plane_state->uapi.visible &&
12719 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
12720 intel_plane_disable_noatomic(crtc, plane);
12721 }
12722
12723 /*
12724 * Disable any background color set by the BIOS, but enable the
12725 * gamma and CSC to match how we program our planes.
12726 */
12727 if (DISPLAY_VER(dev_priv) >= 9)
12728 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
12729 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
12730 }
12731
12732 /* Adjust the state of the output pipe according to whether we
12733 * have active connectors/encoders. */
12734 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
12735 !crtc_state->bigjoiner_slave)
12736 intel_crtc_disable_noatomic(crtc, ctx);
12737
12738 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
12739 /*
12740 * We start out with underrun reporting disabled to avoid races.
12741 * For correct bookkeeping mark this on active crtcs.
12742 *
12743 * Also on gmch platforms we dont have any hardware bits to
12744 * disable the underrun reporting. Which means we need to start
12745 * out with underrun reporting disabled also on inactive pipes,
12746 * since otherwise we'll complain about the garbage we read when
12747 * e.g. coming up after runtime pm.
12748 *
12749 * No protection against concurrent access is required - at
12750 * worst a fifo underrun happens which also sets this to false.
12751 */
12752 crtc->cpu_fifo_underrun_disabled = true;
12753 /*
12754 * We track the PCH trancoder underrun reporting state
12755 * within the crtc. With crtc for pipe A housing the underrun
12756 * reporting state for PCH transcoder A, crtc for pipe B housing
12757 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
12758 * and marking underrun reporting as disabled for the non-existing
12759 * PCH transcoders B and C would prevent enabling the south
12760 * error interrupt (see cpt_can_enable_serr_int()).
12761 */
12762 if (has_pch_trancoder(dev_priv, crtc->pipe))
12763 crtc->pch_fifo_underrun_disabled = true;
12764 }
12765}
12766
12767static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
12768{
12769 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12770
12771 /*
12772 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
12773 * the hardware when a high res displays plugged in. DPLL P
12774 * divider is zero, and the pipe timings are bonkers. We'll
12775 * try to disable everything in that case.
12776 *
12777 * FIXME would be nice to be able to sanitize this state
12778 * without several WARNs, but for now let's take the easy
12779 * road.
12780 */
12781 return IS_SANDYBRIDGE(dev_priv) &&
12782 crtc_state->hw.active &&
12783 crtc_state->shared_dpll &&
12784 crtc_state->port_clock == 0;
12785}
12786
12787static void intel_sanitize_encoder(struct intel_encoder *encoder)
12788{
12789 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12790 struct intel_connector *connector;
12791 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
12792 struct intel_crtc_state *crtc_state = crtc ?
12793 to_intel_crtc_state(crtc->base.state) : NULL;
12794
12795 /* We need to check both for a crtc link (meaning that the
12796 * encoder is active and trying to read from a pipe) and the
12797 * pipe itself being active. */
12798 bool has_active_crtc = crtc_state &&
12799 crtc_state->hw.active;
12800
12801 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
12802 drm_dbg_kms(&dev_priv->drm,
12803 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
12804 pipe_name(crtc->pipe));
12805 has_active_crtc = false;
12806 }
12807
12808 connector = intel_encoder_find_connector(encoder);
12809 if (connector && !has_active_crtc) {
12810 drm_dbg_kms(&dev_priv->drm,
12811 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12812 encoder->base.base.id,
12813 encoder->base.name);
12814
12815 /* Connector is active, but has no active pipe. This is
12816 * fallout from our resume register restoring. Disable
12817 * the encoder manually again. */
12818 if (crtc_state) {
12819 struct drm_encoder *best_encoder;
12820
12821 drm_dbg_kms(&dev_priv->drm,
12822 "[ENCODER:%d:%s] manually disabled\n",
12823 encoder->base.base.id,
12824 encoder->base.name);
12825
12826 /* avoid oopsing in case the hooks consult best_encoder */
12827 best_encoder = connector->base.state->best_encoder;
12828 connector->base.state->best_encoder = &encoder->base;
12829
12830 /* FIXME NULL atomic state passed! */
12831 if (encoder->disable)
12832 encoder->disable(NULL, encoder, crtc_state,
12833 connector->base.state);
12834 if (encoder->post_disable)
12835 encoder->post_disable(NULL, encoder, crtc_state,
12836 connector->base.state);
12837
12838 connector->base.state->best_encoder = best_encoder;
12839 }
12840 encoder->base.crtc = NULL;
12841
12842 /* Inconsistent output/port/pipe state happens presumably due to
12843 * a bug in one of the get_hw_state functions. Or someplace else
12844 * in our code, like the register restore mess on resume. Clamp
12845 * things to off as a safer default. */
12846
12847 connector->base.dpms = DRM_MODE_DPMS_OFF;
12848 connector->base.encoder = NULL;
12849 }
12850
12851 /* notify opregion of the sanitized encoder state */
12852 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
12853
12854 if (HAS_DDI(dev_priv))
12855 intel_ddi_sanitize_encoder_pll_mapping(encoder);
12856}
12857
12858/* FIXME read out full plane state for all planes */
12859static void readout_plane_state(struct drm_i915_private *dev_priv)
12860{
12861 struct intel_plane *plane;
12862 struct intel_crtc *crtc;
12863
12864 for_each_intel_plane(&dev_priv->drm, plane) {
12865 struct intel_plane_state *plane_state =
12866 to_intel_plane_state(plane->base.state);
12867 struct intel_crtc_state *crtc_state;
12868 enum pipe pipe = PIPE_A;
12869 bool visible;
12870
12871 visible = plane->get_hw_state(plane, &pipe);
12872
12873 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12874 crtc_state = to_intel_crtc_state(crtc->base.state);
12875
12876 intel_set_plane_visible(crtc_state, plane_state, visible);
12877
12878 drm_dbg_kms(&dev_priv->drm,
12879 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
12880 plane->base.base.id, plane->base.name,
12881 enableddisabled(visible), pipe_name(pipe));
12882 }
12883
12884 for_each_intel_crtc(&dev_priv->drm, crtc) {
12885 struct intel_crtc_state *crtc_state =
12886 to_intel_crtc_state(crtc->base.state);
12887
12888 fixup_plane_bitmasks(crtc_state);
12889 }
12890}
12891
12892static void intel_modeset_readout_hw_state(struct drm_device *dev)
12893{
12894 struct drm_i915_private *dev_priv = to_i915(dev);
12895 struct intel_cdclk_state *cdclk_state =
12896 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
12897 struct intel_dbuf_state *dbuf_state =
12898 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
12899 enum pipe pipe;
12900 struct intel_crtc *crtc;
12901 struct intel_encoder *encoder;
12902 struct intel_connector *connector;
12903 struct drm_connector_list_iter conn_iter;
12904 u8 active_pipes = 0;
12905
12906 for_each_intel_crtc(dev, crtc) {
12907 struct intel_crtc_state *crtc_state =
12908 to_intel_crtc_state(crtc->base.state);
12909
12910 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
12911 intel_crtc_free_hw_state(crtc_state);
12912 intel_crtc_state_reset(crtc_state, crtc);
12913
12914 intel_crtc_get_pipe_config(crtc_state);
12915
12916 crtc_state->hw.enable = crtc_state->hw.active;
12917
12918 crtc->base.enabled = crtc_state->hw.enable;
12919 crtc->active = crtc_state->hw.active;
12920
12921 if (crtc_state->hw.active)
12922 active_pipes |= BIT(crtc->pipe);
12923
12924 drm_dbg_kms(&dev_priv->drm,
12925 "[CRTC:%d:%s] hw state readout: %s\n",
12926 crtc->base.base.id, crtc->base.name,
12927 enableddisabled(crtc_state->hw.active));
12928 }
12929
12930 dev_priv->active_pipes = cdclk_state->active_pipes =
12931 dbuf_state->active_pipes = active_pipes;
12932
12933 readout_plane_state(dev_priv);
12934
12935 for_each_intel_encoder(dev, encoder) {
12936 struct intel_crtc_state *crtc_state = NULL;
12937
12938 pipe = 0;
12939
12940 if (encoder->get_hw_state(encoder, &pipe)) {
12941 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12942 crtc_state = to_intel_crtc_state(crtc->base.state);
12943
12944 encoder->base.crtc = &crtc->base;
12945 intel_encoder_get_config(encoder, crtc_state);
12946
12947 /* read out to slave crtc as well for bigjoiner */
12948 if (crtc_state->bigjoiner) {
12949 /* encoder should read be linked to bigjoiner master */
12950 WARN_ON(crtc_state->bigjoiner_slave);
12951
12952 crtc = crtc_state->bigjoiner_linked_crtc;
12953 crtc_state = to_intel_crtc_state(crtc->base.state);
12954 intel_encoder_get_config(encoder, crtc_state);
12955 }
12956 } else {
12957 encoder->base.crtc = NULL;
12958 }
12959
12960 if (encoder->sync_state)
12961 encoder->sync_state(encoder, crtc_state);
12962
12963 drm_dbg_kms(&dev_priv->drm,
12964 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12965 encoder->base.base.id, encoder->base.name,
12966 enableddisabled(encoder->base.crtc),
12967 pipe_name(pipe));
12968 }
12969
12970 intel_dpll_readout_hw_state(dev_priv);
12971
12972 drm_connector_list_iter_begin(dev, &conn_iter);
12973 for_each_intel_connector_iter(connector, &conn_iter) {
12974 if (connector->get_hw_state(connector)) {
12975 struct intel_crtc_state *crtc_state;
12976 struct intel_crtc *crtc;
12977
12978 connector->base.dpms = DRM_MODE_DPMS_ON;
12979
12980 encoder = intel_attached_encoder(connector);
12981 connector->base.encoder = &encoder->base;
12982
12983 crtc = to_intel_crtc(encoder->base.crtc);
12984 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
12985
12986 if (crtc_state && crtc_state->hw.active) {
12987 /*
12988 * This has to be done during hardware readout
12989 * because anything calling .crtc_disable may
12990 * rely on the connector_mask being accurate.
12991 */
12992 crtc_state->uapi.connector_mask |=
12993 drm_connector_mask(&connector->base);
12994 crtc_state->uapi.encoder_mask |=
12995 drm_encoder_mask(&encoder->base);
12996 }
12997 } else {
12998 connector->base.dpms = DRM_MODE_DPMS_OFF;
12999 connector->base.encoder = NULL;
13000 }
13001 drm_dbg_kms(&dev_priv->drm,
13002 "[CONNECTOR:%d:%s] hw state readout: %s\n",
13003 connector->base.base.id, connector->base.name,
13004 enableddisabled(connector->base.encoder));
13005 }
13006 drm_connector_list_iter_end(&conn_iter);
13007
13008 for_each_intel_crtc(dev, crtc) {
13009 struct intel_bw_state *bw_state =
13010 to_intel_bw_state(dev_priv->bw_obj.state);
13011 struct intel_crtc_state *crtc_state =
13012 to_intel_crtc_state(crtc->base.state);
13013 struct intel_plane *plane;
13014 int min_cdclk = 0;
13015
13016 if (crtc_state->bigjoiner_slave)
13017 continue;
13018
13019 if (crtc_state->hw.active) {
13020 /*
13021 * The initial mode needs to be set in order to keep
13022 * the atomic core happy. It wants a valid mode if the
13023 * crtc's enabled, so we do the above call.
13024 *
13025 * But we don't set all the derived state fully, hence
13026 * set a flag to indicate that a full recalculation is
13027 * needed on the next commit.
13028 */
13029 crtc_state->inherited = true;
13030
13031 intel_crtc_update_active_timings(crtc_state);
13032
13033 intel_crtc_copy_hw_to_uapi_state(crtc_state);
13034 }
13035
13036 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13037 const struct intel_plane_state *plane_state =
13038 to_intel_plane_state(plane->base.state);
13039
13040 /*
13041 * FIXME don't have the fb yet, so can't
13042 * use intel_plane_data_rate() :(
13043 */
13044 if (plane_state->uapi.visible)
13045 crtc_state->data_rate[plane->id] =
13046 4 * crtc_state->pixel_rate;
13047 /*
13048 * FIXME don't have the fb yet, so can't
13049 * use plane->min_cdclk() :(
13050 */
13051 if (plane_state->uapi.visible && plane->min_cdclk) {
13052 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
13053 crtc_state->min_cdclk[plane->id] =
13054 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
13055 else
13056 crtc_state->min_cdclk[plane->id] =
13057 crtc_state->pixel_rate;
13058 }
13059 drm_dbg_kms(&dev_priv->drm,
13060 "[PLANE:%d:%s] min_cdclk %d kHz\n",
13061 plane->base.base.id, plane->base.name,
13062 crtc_state->min_cdclk[plane->id]);
13063 }
13064
13065 if (crtc_state->hw.active) {
13066 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
13067 if (drm_WARN_ON(dev, min_cdclk < 0))
13068 min_cdclk = 0;
13069 }
13070
13071 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
13072 cdclk_state->min_voltage_level[crtc->pipe] =
13073 crtc_state->min_voltage_level;
13074
13075 intel_bw_crtc_update(bw_state, crtc_state);
13076
13077 intel_pipe_config_sanity_check(dev_priv, crtc_state);
13078
13079 /* discard our incomplete slave state, copy it from master */
13080 if (crtc_state->bigjoiner && crtc_state->hw.active) {
13081 struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
13082 struct intel_crtc_state *slave_crtc_state =
13083 to_intel_crtc_state(slave->base.state);
13084
13085 copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
13086 slave->base.mode = crtc->base.mode;
13087
13088 cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
13089 cdclk_state->min_voltage_level[slave->pipe] =
13090 crtc_state->min_voltage_level;
13091
13092 for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
13093 const struct intel_plane_state *plane_state =
13094 to_intel_plane_state(plane->base.state);
13095
13096 /*
13097 * FIXME don't have the fb yet, so can't
13098 * use intel_plane_data_rate() :(
13099 */
13100 if (plane_state->uapi.visible)
13101 crtc_state->data_rate[plane->id] =
13102 4 * crtc_state->pixel_rate;
13103 else
13104 crtc_state->data_rate[plane->id] = 0;
13105 }
13106
13107 intel_bw_crtc_update(bw_state, slave_crtc_state);
13108 drm_calc_timestamping_constants(&slave->base,
13109 &slave_crtc_state->hw.adjusted_mode);
13110 }
13111 }
13112}
13113
13114static void
13115get_encoder_power_domains(struct drm_i915_private *dev_priv)
13116{
13117 struct intel_encoder *encoder;
13118
13119 for_each_intel_encoder(&dev_priv->drm, encoder) {
13120 struct intel_crtc_state *crtc_state;
13121
13122 if (!encoder->get_power_domains)
13123 continue;
13124
13125 /*
13126 * MST-primary and inactive encoders don't have a crtc state
13127 * and neither of these require any power domain references.
13128 */
13129 if (!encoder->base.crtc)
13130 continue;
13131
13132 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
13133 encoder->get_power_domains(encoder, crtc_state);
13134 }
13135}
13136
13137static void intel_early_display_was(struct drm_i915_private *dev_priv)
13138{
13139 /*
13140 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
13141 * Also known as Wa_14010480278.
13142 */
13143 if (IS_DISPLAY_VER(dev_priv, 10, 12))
13144 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
13145 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
13146
13147 if (IS_HASWELL(dev_priv)) {
13148 /*
13149 * WaRsPkgCStateDisplayPMReq:hsw
13150 * System hang if this isn't done before disabling all planes!
13151 */
13152 intel_de_write(dev_priv, CHICKEN_PAR1_1,
13153 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
13154 }
13155
13156 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
13157 /* Display WA #1142:kbl,cfl,cml */
13158 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
13159 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
13160 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
13161 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
13162 KBL_ARB_FILL_SPARE_14);
13163 }
13164}
13165
13166static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
13167 enum port port, i915_reg_t hdmi_reg)
13168{
13169 u32 val = intel_de_read(dev_priv, hdmi_reg);
13170
13171 if (val & SDVO_ENABLE ||
13172 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
13173 return;
13174
13175 drm_dbg_kms(&dev_priv->drm,
13176 "Sanitizing transcoder select for HDMI %c\n",
13177 port_name(port));
13178
13179 val &= ~SDVO_PIPE_SEL_MASK;
13180 val |= SDVO_PIPE_SEL(PIPE_A);
13181
13182 intel_de_write(dev_priv, hdmi_reg, val);
13183}
13184
13185static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
13186 enum port port, i915_reg_t dp_reg)
13187{
13188 u32 val = intel_de_read(dev_priv, dp_reg);
13189
13190 if (val & DP_PORT_EN ||
13191 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
13192 return;
13193
13194 drm_dbg_kms(&dev_priv->drm,
13195 "Sanitizing transcoder select for DP %c\n",
13196 port_name(port));
13197
13198 val &= ~DP_PIPE_SEL_MASK;
13199 val |= DP_PIPE_SEL(PIPE_A);
13200
13201 intel_de_write(dev_priv, dp_reg, val);
13202}
13203
13204static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
13205{
13206 /*
13207 * The BIOS may select transcoder B on some of the PCH
13208 * ports even it doesn't enable the port. This would trip
13209 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
13210 * Sanitize the transcoder select bits to prevent that. We
13211 * assume that the BIOS never actually enabled the port,
13212 * because if it did we'd actually have to toggle the port
13213 * on and back off to make the transcoder A select stick
13214 * (see. intel_dp_link_down(), intel_disable_hdmi(),
13215 * intel_disable_sdvo()).
13216 */
13217 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
13218 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
13219 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
13220
13221 /* PCH SDVOB multiplex with HDMIB */
13222 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
13223 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
13224 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
13225}
13226
13227/* Scan out the current hw modeset state,
13228 * and sanitizes it to the current state
13229 */
13230static void
13231intel_modeset_setup_hw_state(struct drm_device *dev,
13232 struct drm_modeset_acquire_ctx *ctx)
13233{
13234 struct drm_i915_private *dev_priv = to_i915(dev);
13235 struct intel_encoder *encoder;
13236 struct intel_crtc *crtc;
13237 intel_wakeref_t wakeref;
13238
13239 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
13240
13241 intel_early_display_was(dev_priv);
13242 intel_modeset_readout_hw_state(dev);
13243
13244 /* HW state is read out, now we need to sanitize this mess. */
13245 get_encoder_power_domains(dev_priv);
13246
13247 if (HAS_PCH_IBX(dev_priv))
13248 ibx_sanitize_pch_ports(dev_priv);
13249
13250 /*
13251 * intel_sanitize_plane_mapping() may need to do vblank
13252 * waits, so we need vblank interrupts restored beforehand.
13253 */
13254 for_each_intel_crtc(&dev_priv->drm, crtc) {
13255 struct intel_crtc_state *crtc_state =
13256 to_intel_crtc_state(crtc->base.state);
13257
13258 drm_crtc_vblank_reset(&crtc->base);
13259
13260 if (crtc_state->hw.active)
13261 intel_crtc_vblank_on(crtc_state);
13262 }
13263
13264 intel_sanitize_plane_mapping(dev_priv);
13265
13266 for_each_intel_encoder(dev, encoder)
13267 intel_sanitize_encoder(encoder);
13268
13269 for_each_intel_crtc(&dev_priv->drm, crtc) {
13270 struct intel_crtc_state *crtc_state =
13271 to_intel_crtc_state(crtc->base.state);
13272
13273 intel_sanitize_crtc(crtc, ctx);
13274 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
13275 }
13276
13277 intel_modeset_update_connector_atomic_state(dev);
13278
13279 intel_dpll_sanitize_state(dev_priv);
13280
13281 if (IS_G4X(dev_priv)) {
13282 g4x_wm_get_hw_state(dev_priv);
13283 g4x_wm_sanitize(dev_priv);
13284 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13285 vlv_wm_get_hw_state(dev_priv);
13286 vlv_wm_sanitize(dev_priv);
13287 } else if (DISPLAY_VER(dev_priv) >= 9) {
13288 skl_wm_get_hw_state(dev_priv);
13289 } else if (HAS_PCH_SPLIT(dev_priv)) {
13290 ilk_wm_get_hw_state(dev_priv);
13291 }
13292
13293 for_each_intel_crtc(dev, crtc) {
13294 struct intel_crtc_state *crtc_state =
13295 to_intel_crtc_state(crtc->base.state);
13296 u64 put_domains;
13297
13298 put_domains = modeset_get_crtc_power_domains(crtc_state);
13299 if (drm_WARN_ON(dev, put_domains))
13300 modeset_put_crtc_power_domains(crtc, put_domains);
13301 }
13302
13303 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
13304}
13305
13306void intel_display_resume(struct drm_device *dev)
13307{
13308 struct drm_i915_private *dev_priv = to_i915(dev);
13309 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
13310 struct drm_modeset_acquire_ctx ctx;
13311 int ret;
13312
13313 if (!HAS_DISPLAY(dev_priv))
13314 return;
13315
13316 dev_priv->modeset_restore_state = NULL;
13317 if (state)
13318 state->acquire_ctx = &ctx;
13319
13320 drm_modeset_acquire_init(&ctx, 0);
13321
13322 while (1) {
13323 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13324 if (ret != -EDEADLK)
13325 break;
13326
13327 drm_modeset_backoff(&ctx);
13328 }
13329
13330 if (!ret)
13331 ret = __intel_display_resume(dev, state, &ctx);
13332
13333 intel_enable_ipc(dev_priv);
13334 drm_modeset_drop_locks(&ctx);
13335 drm_modeset_acquire_fini(&ctx);
13336
13337 if (ret)
13338 drm_err(&dev_priv->drm,
13339 "Restoring old state failed with %i\n", ret);
13340 if (state)
13341 drm_atomic_state_put(state);
13342}
13343
13344static void intel_hpd_poll_fini(struct drm_i915_private *i915)
13345{
13346 struct intel_connector *connector;
13347 struct drm_connector_list_iter conn_iter;
13348
13349 /* Kill all the work that may have been queued by hpd. */
13350 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
13351 for_each_intel_connector_iter(connector, &conn_iter) {
13352 if (connector->modeset_retry_work.func)
13353 cancel_work_sync(&connector->modeset_retry_work);
13354 if (connector->hdcp.shim) {
13355 cancel_delayed_work_sync(&connector->hdcp.check_work);
13356 cancel_work_sync(&connector->hdcp.prop_work);
13357 }
13358 }
13359 drm_connector_list_iter_end(&conn_iter);
13360}
13361
13362/* part #1: call before irq uninstall */
13363void intel_modeset_driver_remove(struct drm_i915_private *i915)
13364{
13365 if (!HAS_DISPLAY(i915))
13366 return;
13367
13368 flush_workqueue(i915->flip_wq);
13369 flush_workqueue(i915->modeset_wq);
13370
13371 flush_work(&i915->atomic_helper.free_work);
13372 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
13373}
13374
13375/* part #2: call after irq uninstall */
13376void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
13377{
13378 if (!HAS_DISPLAY(i915))
13379 return;
13380
13381 /*
13382 * Due to the hpd irq storm handling the hotplug work can re-arm the
13383 * poll handlers. Hence disable polling after hpd handling is shut down.
13384 */
13385 intel_hpd_poll_fini(i915);
13386
13387 /*
13388 * MST topology needs to be suspended so we don't have any calls to
13389 * fbdev after it's finalized. MST will be destroyed later as part of
13390 * drm_mode_config_cleanup()
13391 */
13392 intel_dp_mst_suspend(i915);
13393
13394 /* poll work can call into fbdev, hence clean that up afterwards */
13395 intel_fbdev_fini(i915);
13396
13397 intel_unregister_dsm_handler();
13398
13399 intel_fbc_global_disable(i915);
13400
13401 /* flush any delayed tasks or pending work */
13402 flush_scheduled_work();
13403
13404 intel_hdcp_component_fini(i915);
13405
13406 intel_mode_config_cleanup(i915);
13407
13408 intel_overlay_cleanup(i915);
13409
13410 intel_gmbus_teardown(i915);
13411
13412 destroy_workqueue(i915->flip_wq);
13413 destroy_workqueue(i915->modeset_wq);
13414
13415 intel_fbc_cleanup_cfb(i915);
13416}
13417
13418/* part #3: call after gem init */
13419void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
13420{
13421 intel_dmc_ucode_fini(i915);
13422
13423 intel_power_domains_driver_remove(i915);
13424
13425 intel_vga_unregister(i915);
13426
13427 intel_bios_driver_remove(i915);
13428}
13429
13430void intel_display_driver_register(struct drm_i915_private *i915)
13431{
13432 if (!HAS_DISPLAY(i915))
13433 return;
13434
13435 intel_display_debugfs_register(i915);
13436
13437 /* Must be done after probing outputs */
13438 intel_opregion_register(i915);
13439 acpi_video_register();
13440
13441 intel_audio_init(i915);
13442
13443 /*
13444 * Some ports require correctly set-up hpd registers for
13445 * detection to work properly (leading to ghost connected
13446 * connector status), e.g. VGA on gm45. Hence we can only set
13447 * up the initial fbdev config after hpd irqs are fully
13448 * enabled. We do it last so that the async config cannot run
13449 * before the connectors are registered.
13450 */
13451 intel_fbdev_initial_config_async(&i915->drm);
13452
13453 /*
13454 * We need to coordinate the hotplugs with the asynchronous
13455 * fbdev configuration, for which we use the
13456 * fbdev->async_cookie.
13457 */
13458 drm_kms_helper_poll_init(&i915->drm);
13459}
13460
13461void intel_display_driver_unregister(struct drm_i915_private *i915)
13462{
13463 if (!HAS_DISPLAY(i915))
13464 return;
13465
13466 intel_fbdev_unregister(i915);
13467 intel_audio_deinit(i915);
13468
13469 /*
13470 * After flushing the fbdev (incl. a late async config which
13471 * will have delayed queuing of a hotplug event), then flush
13472 * the hotplug events.
13473 */
13474 drm_kms_helper_poll_fini(&i915->drm);
13475 drm_atomic_helper_shutdown(&i915->drm);
13476
13477 acpi_video_unregister();
13478 intel_opregion_unregister(i915);
13479}