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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Based on arch/arm/kernel/process.c
4 *
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
8 */
9#include <linux/compat.h>
10#include <linux/efi.h>
11#include <linux/elf.h>
12#include <linux/export.h>
13#include <linux/sched.h>
14#include <linux/sched/debug.h>
15#include <linux/sched/task.h>
16#include <linux/sched/task_stack.h>
17#include <linux/kernel.h>
18#include <linux/mman.h>
19#include <linux/mm.h>
20#include <linux/nospec.h>
21#include <linux/stddef.h>
22#include <linux/sysctl.h>
23#include <linux/unistd.h>
24#include <linux/user.h>
25#include <linux/delay.h>
26#include <linux/reboot.h>
27#include <linux/interrupt.h>
28#include <linux/init.h>
29#include <linux/cpu.h>
30#include <linux/elfcore.h>
31#include <linux/pm.h>
32#include <linux/tick.h>
33#include <linux/utsname.h>
34#include <linux/uaccess.h>
35#include <linux/random.h>
36#include <linux/hw_breakpoint.h>
37#include <linux/personality.h>
38#include <linux/notifier.h>
39#include <trace/events/power.h>
40#include <linux/percpu.h>
41#include <linux/thread_info.h>
42#include <linux/prctl.h>
43#include <linux/stacktrace.h>
44
45#include <asm/alternative.h>
46#include <asm/arch_timer.h>
47#include <asm/compat.h>
48#include <asm/cpufeature.h>
49#include <asm/cacheflush.h>
50#include <asm/exec.h>
51#include <asm/fpsimd.h>
52#include <asm/gcs.h>
53#include <asm/mmu_context.h>
54#include <asm/mte.h>
55#include <asm/processor.h>
56#include <asm/pointer_auth.h>
57#include <asm/stacktrace.h>
58#include <asm/switch_to.h>
59#include <asm/system_misc.h>
60
61#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
62#include <linux/stackprotector.h>
63unsigned long __stack_chk_guard __ro_after_init;
64EXPORT_SYMBOL(__stack_chk_guard);
65#endif
66
67/*
68 * Function pointers to optional machine specific functions
69 */
70void (*pm_power_off)(void);
71EXPORT_SYMBOL_GPL(pm_power_off);
72
73#ifdef CONFIG_HOTPLUG_CPU
74void __noreturn arch_cpu_idle_dead(void)
75{
76 cpu_die();
77}
78#endif
79
80/*
81 * Called by kexec, immediately prior to machine_kexec().
82 *
83 * This must completely disable all secondary CPUs; simply causing those CPUs
84 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
85 * kexec'd kernel to use any and all RAM as it sees fit, without having to
86 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
87 * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
88 */
89void machine_shutdown(void)
90{
91 smp_shutdown_nonboot_cpus(reboot_cpu);
92}
93
94/*
95 * Halting simply requires that the secondary CPUs stop performing any
96 * activity (executing tasks, handling interrupts). smp_send_stop()
97 * achieves this.
98 */
99void machine_halt(void)
100{
101 local_irq_disable();
102 smp_send_stop();
103 while (1);
104}
105
106/*
107 * Power-off simply requires that the secondary CPUs stop performing any
108 * activity (executing tasks, handling interrupts). smp_send_stop()
109 * achieves this. When the system power is turned off, it will take all CPUs
110 * with it.
111 */
112void machine_power_off(void)
113{
114 local_irq_disable();
115 smp_send_stop();
116 do_kernel_power_off();
117}
118
119/*
120 * Restart requires that the secondary CPUs stop performing any activity
121 * while the primary CPU resets the system. Systems with multiple CPUs must
122 * provide a HW restart implementation, to ensure that all CPUs reset at once.
123 * This is required so that any code running after reset on the primary CPU
124 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
125 * executing pre-reset code, and using RAM that the primary CPU's code wishes
126 * to use. Implementing such co-ordination would be essentially impossible.
127 */
128void machine_restart(char *cmd)
129{
130 /* Disable interrupts first */
131 local_irq_disable();
132 smp_send_stop();
133
134 /*
135 * UpdateCapsule() depends on the system being reset via
136 * ResetSystem().
137 */
138 if (efi_enabled(EFI_RUNTIME_SERVICES))
139 efi_reboot(reboot_mode, NULL);
140
141 /* Now call the architecture specific reboot code. */
142 do_kernel_restart(cmd);
143
144 /*
145 * Whoops - the architecture was unable to reboot.
146 */
147 printk("Reboot failed -- System halted\n");
148 while (1);
149}
150
151#define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
152static const char *const btypes[] = {
153 bstr(NONE, "--"),
154 bstr( JC, "jc"),
155 bstr( C, "-c"),
156 bstr( J , "j-")
157};
158#undef bstr
159
160static void print_pstate(struct pt_regs *regs)
161{
162 u64 pstate = regs->pstate;
163
164 if (compat_user_mode(regs)) {
165 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c %cDIT %cSSBS)\n",
166 pstate,
167 pstate & PSR_AA32_N_BIT ? 'N' : 'n',
168 pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
169 pstate & PSR_AA32_C_BIT ? 'C' : 'c',
170 pstate & PSR_AA32_V_BIT ? 'V' : 'v',
171 pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
172 pstate & PSR_AA32_T_BIT ? "T32" : "A32",
173 pstate & PSR_AA32_E_BIT ? "BE" : "LE",
174 pstate & PSR_AA32_A_BIT ? 'A' : 'a',
175 pstate & PSR_AA32_I_BIT ? 'I' : 'i',
176 pstate & PSR_AA32_F_BIT ? 'F' : 'f',
177 pstate & PSR_AA32_DIT_BIT ? '+' : '-',
178 pstate & PSR_AA32_SSBS_BIT ? '+' : '-');
179 } else {
180 const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
181 PSR_BTYPE_SHIFT];
182
183 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
184 pstate,
185 pstate & PSR_N_BIT ? 'N' : 'n',
186 pstate & PSR_Z_BIT ? 'Z' : 'z',
187 pstate & PSR_C_BIT ? 'C' : 'c',
188 pstate & PSR_V_BIT ? 'V' : 'v',
189 pstate & PSR_D_BIT ? 'D' : 'd',
190 pstate & PSR_A_BIT ? 'A' : 'a',
191 pstate & PSR_I_BIT ? 'I' : 'i',
192 pstate & PSR_F_BIT ? 'F' : 'f',
193 pstate & PSR_PAN_BIT ? '+' : '-',
194 pstate & PSR_UAO_BIT ? '+' : '-',
195 pstate & PSR_TCO_BIT ? '+' : '-',
196 pstate & PSR_DIT_BIT ? '+' : '-',
197 pstate & PSR_SSBS_BIT ? '+' : '-',
198 btype_str);
199 }
200}
201
202void __show_regs(struct pt_regs *regs)
203{
204 int i, top_reg;
205 u64 lr, sp;
206
207 if (compat_user_mode(regs)) {
208 lr = regs->compat_lr;
209 sp = regs->compat_sp;
210 top_reg = 12;
211 } else {
212 lr = regs->regs[30];
213 sp = regs->sp;
214 top_reg = 29;
215 }
216
217 show_regs_print_info(KERN_DEFAULT);
218 print_pstate(regs);
219
220 if (!user_mode(regs)) {
221 printk("pc : %pS\n", (void *)regs->pc);
222 printk("lr : %pS\n", (void *)ptrauth_strip_kernel_insn_pac(lr));
223 } else {
224 printk("pc : %016llx\n", regs->pc);
225 printk("lr : %016llx\n", lr);
226 }
227
228 printk("sp : %016llx\n", sp);
229
230 if (system_uses_irq_prio_masking())
231 printk("pmr: %08x\n", regs->pmr);
232
233 i = top_reg;
234
235 while (i >= 0) {
236 printk("x%-2d: %016llx", i, regs->regs[i]);
237
238 while (i-- % 3)
239 pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
240
241 pr_cont("\n");
242 }
243}
244
245void show_regs(struct pt_regs *regs)
246{
247 __show_regs(regs);
248 dump_backtrace(regs, NULL, KERN_DEFAULT);
249}
250
251static void tls_thread_flush(void)
252{
253 write_sysreg(0, tpidr_el0);
254 if (system_supports_tpidr2())
255 write_sysreg_s(0, SYS_TPIDR2_EL0);
256
257 if (is_compat_task()) {
258 current->thread.uw.tp_value = 0;
259
260 /*
261 * We need to ensure ordering between the shadow state and the
262 * hardware state, so that we don't corrupt the hardware state
263 * with a stale shadow state during context switch.
264 */
265 barrier();
266 write_sysreg(0, tpidrro_el0);
267 }
268}
269
270static void flush_tagged_addr_state(void)
271{
272 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
273 clear_thread_flag(TIF_TAGGED_ADDR);
274}
275
276static void flush_poe(void)
277{
278 if (!system_supports_poe())
279 return;
280
281 write_sysreg_s(POR_EL0_INIT, SYS_POR_EL0);
282}
283
284#ifdef CONFIG_ARM64_GCS
285
286static void flush_gcs(void)
287{
288 if (!system_supports_gcs())
289 return;
290
291 gcs_free(current);
292 current->thread.gcs_el0_mode = 0;
293 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);
294 write_sysreg_s(0, SYS_GCSPR_EL0);
295}
296
297static int copy_thread_gcs(struct task_struct *p,
298 const struct kernel_clone_args *args)
299{
300 unsigned long gcs;
301
302 if (!system_supports_gcs())
303 return 0;
304
305 p->thread.gcs_base = 0;
306 p->thread.gcs_size = 0;
307
308 gcs = gcs_alloc_thread_stack(p, args);
309 if (IS_ERR_VALUE(gcs))
310 return PTR_ERR((void *)gcs);
311
312 p->thread.gcs_el0_mode = current->thread.gcs_el0_mode;
313 p->thread.gcs_el0_locked = current->thread.gcs_el0_locked;
314
315 return 0;
316}
317
318#else
319
320static void flush_gcs(void) { }
321static int copy_thread_gcs(struct task_struct *p,
322 const struct kernel_clone_args *args)
323{
324 return 0;
325}
326
327#endif
328
329void flush_thread(void)
330{
331 fpsimd_flush_thread();
332 tls_thread_flush();
333 flush_ptrace_hw_breakpoint(current);
334 flush_tagged_addr_state();
335 flush_poe();
336 flush_gcs();
337}
338
339void arch_release_task_struct(struct task_struct *tsk)
340{
341 fpsimd_release_task(tsk);
342 gcs_free(tsk);
343}
344
345int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
346{
347 if (current->mm)
348 fpsimd_preserve_current_state();
349 *dst = *src;
350
351 /*
352 * Detach src's sve_state (if any) from dst so that it does not
353 * get erroneously used or freed prematurely. dst's copies
354 * will be allocated on demand later on if dst uses SVE.
355 * For consistency, also clear TIF_SVE here: this could be done
356 * later in copy_process(), but to avoid tripping up future
357 * maintainers it is best not to leave TIF flags and buffers in
358 * an inconsistent state, even temporarily.
359 */
360 dst->thread.sve_state = NULL;
361 clear_tsk_thread_flag(dst, TIF_SVE);
362
363 /*
364 * In the unlikely event that we create a new thread with ZA
365 * enabled we should retain the ZA and ZT state so duplicate
366 * it here. This may be shortly freed if we exec() or if
367 * CLONE_SETTLS but it's simpler to do it here. To avoid
368 * confusing the rest of the code ensure that we have a
369 * sve_state allocated whenever sme_state is allocated.
370 */
371 if (thread_za_enabled(&src->thread)) {
372 dst->thread.sve_state = kzalloc(sve_state_size(src),
373 GFP_KERNEL);
374 if (!dst->thread.sve_state)
375 return -ENOMEM;
376
377 dst->thread.sme_state = kmemdup(src->thread.sme_state,
378 sme_state_size(src),
379 GFP_KERNEL);
380 if (!dst->thread.sme_state) {
381 kfree(dst->thread.sve_state);
382 dst->thread.sve_state = NULL;
383 return -ENOMEM;
384 }
385 } else {
386 dst->thread.sme_state = NULL;
387 clear_tsk_thread_flag(dst, TIF_SME);
388 }
389
390 dst->thread.fp_type = FP_STATE_FPSIMD;
391
392 /* clear any pending asynchronous tag fault raised by the parent */
393 clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
394
395 return 0;
396}
397
398asmlinkage void ret_from_fork(void) asm("ret_from_fork");
399
400int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
401{
402 unsigned long clone_flags = args->flags;
403 unsigned long stack_start = args->stack;
404 unsigned long tls = args->tls;
405 struct pt_regs *childregs = task_pt_regs(p);
406 int ret;
407
408 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
409
410 /*
411 * In case p was allocated the same task_struct pointer as some
412 * other recently-exited task, make sure p is disassociated from
413 * any cpu that may have run that now-exited task recently.
414 * Otherwise we could erroneously skip reloading the FPSIMD
415 * registers for p.
416 */
417 fpsimd_flush_task_state(p);
418
419 ptrauth_thread_init_kernel(p);
420
421 if (likely(!args->fn)) {
422 *childregs = *current_pt_regs();
423 childregs->regs[0] = 0;
424
425 /*
426 * Read the current TLS pointer from tpidr_el0 as it may be
427 * out-of-sync with the saved value.
428 */
429 *task_user_tls(p) = read_sysreg(tpidr_el0);
430 if (system_supports_tpidr2())
431 p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
432
433 if (system_supports_poe())
434 p->thread.por_el0 = read_sysreg_s(SYS_POR_EL0);
435
436 if (stack_start) {
437 if (is_compat_thread(task_thread_info(p)))
438 childregs->compat_sp = stack_start;
439 else
440 childregs->sp = stack_start;
441 }
442
443 /*
444 * If a TLS pointer was passed to clone, use it for the new
445 * thread. We also reset TPIDR2 if it's in use.
446 */
447 if (clone_flags & CLONE_SETTLS) {
448 p->thread.uw.tp_value = tls;
449 p->thread.tpidr2_el0 = 0;
450 }
451
452 ret = copy_thread_gcs(p, args);
453 if (ret != 0)
454 return ret;
455 } else {
456 /*
457 * A kthread has no context to ERET to, so ensure any buggy
458 * ERET is treated as an illegal exception return.
459 *
460 * When a user task is created from a kthread, childregs will
461 * be initialized by start_thread() or start_compat_thread().
462 */
463 memset(childregs, 0, sizeof(struct pt_regs));
464 childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
465 childregs->stackframe.type = FRAME_META_TYPE_FINAL;
466
467 p->thread.cpu_context.x19 = (unsigned long)args->fn;
468 p->thread.cpu_context.x20 = (unsigned long)args->fn_arg;
469
470 if (system_supports_poe())
471 p->thread.por_el0 = POR_EL0_INIT;
472 }
473 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
474 p->thread.cpu_context.sp = (unsigned long)childregs;
475 /*
476 * For the benefit of the unwinder, set up childregs->stackframe
477 * as the final frame for the new task.
478 */
479 p->thread.cpu_context.fp = (unsigned long)&childregs->stackframe;
480
481 ptrace_hw_copy_thread(p);
482
483 return 0;
484}
485
486void tls_preserve_current_state(void)
487{
488 *task_user_tls(current) = read_sysreg(tpidr_el0);
489 if (system_supports_tpidr2() && !is_compat_task())
490 current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
491}
492
493static void tls_thread_switch(struct task_struct *next)
494{
495 tls_preserve_current_state();
496
497 if (is_compat_thread(task_thread_info(next)))
498 write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
499 else
500 write_sysreg(0, tpidrro_el0);
501
502 write_sysreg(*task_user_tls(next), tpidr_el0);
503 if (system_supports_tpidr2())
504 write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
505}
506
507/*
508 * Force SSBS state on context-switch, since it may be lost after migrating
509 * from a CPU which treats the bit as RES0 in a heterogeneous system.
510 */
511static void ssbs_thread_switch(struct task_struct *next)
512{
513 /*
514 * Nothing to do for kernel threads, but 'regs' may be junk
515 * (e.g. idle task) so check the flags and bail early.
516 */
517 if (unlikely(next->flags & PF_KTHREAD))
518 return;
519
520 /*
521 * If all CPUs implement the SSBS extension, then we just need to
522 * context-switch the PSTATE field.
523 */
524 if (alternative_has_cap_unlikely(ARM64_SSBS))
525 return;
526
527 spectre_v4_enable_task_mitigation(next);
528}
529
530/*
531 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
532 * shadow copy so that we can restore this upon entry from userspace.
533 *
534 * This is *only* for exception entry from EL0, and is not valid until we
535 * __switch_to() a user task.
536 */
537DEFINE_PER_CPU(struct task_struct *, __entry_task);
538
539static void entry_task_switch(struct task_struct *next)
540{
541 __this_cpu_write(__entry_task, next);
542}
543
544#ifdef CONFIG_ARM64_GCS
545
546void gcs_preserve_current_state(void)
547{
548 current->thread.gcspr_el0 = read_sysreg_s(SYS_GCSPR_EL0);
549}
550
551static void gcs_thread_switch(struct task_struct *next)
552{
553 if (!system_supports_gcs())
554 return;
555
556 /* GCSPR_EL0 is always readable */
557 gcs_preserve_current_state();
558 write_sysreg_s(next->thread.gcspr_el0, SYS_GCSPR_EL0);
559
560 if (current->thread.gcs_el0_mode != next->thread.gcs_el0_mode)
561 gcs_set_el0_mode(next);
562
563 /*
564 * Ensure that GCS memory effects of the 'prev' thread are
565 * ordered before other memory accesses with release semantics
566 * (or preceded by a DMB) on the current PE. In addition, any
567 * memory accesses with acquire semantics (or succeeded by a
568 * DMB) are ordered before GCS memory effects of the 'next'
569 * thread. This will ensure that the GCS memory effects are
570 * visible to other PEs in case of migration.
571 */
572 if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next))
573 gcsb_dsync();
574}
575
576#else
577
578static void gcs_thread_switch(struct task_struct *next)
579{
580}
581
582#endif
583
584/*
585 * Handle sysreg updates for ARM erratum 1418040 which affects the 32bit view of
586 * CNTVCT, various other errata which require trapping all CNTVCT{,_EL0}
587 * accesses and prctl(PR_SET_TSC). Ensure access is disabled iff a workaround is
588 * required or PR_TSC_SIGSEGV is set.
589 */
590static void update_cntkctl_el1(struct task_struct *next)
591{
592 struct thread_info *ti = task_thread_info(next);
593
594 if (test_ti_thread_flag(ti, TIF_TSC_SIGSEGV) ||
595 has_erratum_handler(read_cntvct_el0) ||
596 (IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) &&
597 this_cpu_has_cap(ARM64_WORKAROUND_1418040) &&
598 is_compat_thread(ti)))
599 sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0);
600 else
601 sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN);
602}
603
604static void cntkctl_thread_switch(struct task_struct *prev,
605 struct task_struct *next)
606{
607 if ((read_ti_thread_flags(task_thread_info(prev)) &
608 (_TIF_32BIT | _TIF_TSC_SIGSEGV)) !=
609 (read_ti_thread_flags(task_thread_info(next)) &
610 (_TIF_32BIT | _TIF_TSC_SIGSEGV)))
611 update_cntkctl_el1(next);
612}
613
614static int do_set_tsc_mode(unsigned int val)
615{
616 bool tsc_sigsegv;
617
618 if (val == PR_TSC_SIGSEGV)
619 tsc_sigsegv = true;
620 else if (val == PR_TSC_ENABLE)
621 tsc_sigsegv = false;
622 else
623 return -EINVAL;
624
625 preempt_disable();
626 update_thread_flag(TIF_TSC_SIGSEGV, tsc_sigsegv);
627 update_cntkctl_el1(current);
628 preempt_enable();
629
630 return 0;
631}
632
633static void permission_overlay_switch(struct task_struct *next)
634{
635 if (!system_supports_poe())
636 return;
637
638 current->thread.por_el0 = read_sysreg_s(SYS_POR_EL0);
639 if (current->thread.por_el0 != next->thread.por_el0) {
640 write_sysreg_s(next->thread.por_el0, SYS_POR_EL0);
641 }
642}
643
644/*
645 * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
646 * this function must be called with preemption disabled and the update to
647 * sctlr_user must be made in the same preemption disabled block so that
648 * __switch_to() does not see the variable update before the SCTLR_EL1 one.
649 */
650void update_sctlr_el1(u64 sctlr)
651{
652 /*
653 * EnIA must not be cleared while in the kernel as this is necessary for
654 * in-kernel PAC. It will be cleared on kernel exit if needed.
655 */
656 sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
657
658 /* ISB required for the kernel uaccess routines when setting TCF0. */
659 isb();
660}
661
662/*
663 * Thread switching.
664 */
665__notrace_funcgraph __sched
666struct task_struct *__switch_to(struct task_struct *prev,
667 struct task_struct *next)
668{
669 struct task_struct *last;
670
671 fpsimd_thread_switch(next);
672 tls_thread_switch(next);
673 hw_breakpoint_thread_switch(next);
674 contextidr_thread_switch(next);
675 entry_task_switch(next);
676 ssbs_thread_switch(next);
677 cntkctl_thread_switch(prev, next);
678 ptrauth_thread_switch_user(next);
679 permission_overlay_switch(next);
680 gcs_thread_switch(next);
681
682 /*
683 * Complete any pending TLB or cache maintenance on this CPU in case
684 * the thread migrates to a different CPU.
685 * This full barrier is also required by the membarrier system
686 * call.
687 */
688 dsb(ish);
689
690 /*
691 * MTE thread switching must happen after the DSB above to ensure that
692 * any asynchronous tag check faults have been logged in the TFSR*_EL1
693 * registers.
694 */
695 mte_thread_switch(next);
696 /* avoid expensive SCTLR_EL1 accesses if no change */
697 if (prev->thread.sctlr_user != next->thread.sctlr_user)
698 update_sctlr_el1(next->thread.sctlr_user);
699
700 /* the actual thread switch */
701 last = cpu_switch_to(prev, next);
702
703 return last;
704}
705
706struct wchan_info {
707 unsigned long pc;
708 int count;
709};
710
711static bool get_wchan_cb(void *arg, unsigned long pc)
712{
713 struct wchan_info *wchan_info = arg;
714
715 if (!in_sched_functions(pc)) {
716 wchan_info->pc = pc;
717 return false;
718 }
719 return wchan_info->count++ < 16;
720}
721
722unsigned long __get_wchan(struct task_struct *p)
723{
724 struct wchan_info wchan_info = {
725 .pc = 0,
726 .count = 0,
727 };
728
729 if (!try_get_task_stack(p))
730 return 0;
731
732 arch_stack_walk(get_wchan_cb, &wchan_info, p, NULL);
733
734 put_task_stack(p);
735
736 return wchan_info.pc;
737}
738
739unsigned long arch_align_stack(unsigned long sp)
740{
741 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
742 sp -= get_random_u32_below(PAGE_SIZE);
743 return sp & ~0xf;
744}
745
746#ifdef CONFIG_COMPAT
747int compat_elf_check_arch(const struct elf32_hdr *hdr)
748{
749 if (!system_supports_32bit_el0())
750 return false;
751
752 if ((hdr)->e_machine != EM_ARM)
753 return false;
754
755 if (!((hdr)->e_flags & EF_ARM_EABI_MASK))
756 return false;
757
758 /*
759 * Prevent execve() of a 32-bit program from a deadline task
760 * if the restricted affinity mask would be inadmissible on an
761 * asymmetric system.
762 */
763 return !static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
764 !dl_task_check_affinity(current, system_32bit_el0_cpumask());
765}
766#endif
767
768/*
769 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
770 */
771void arch_setup_new_exec(void)
772{
773 unsigned long mmflags = 0;
774
775 if (is_compat_task()) {
776 mmflags = MMCF_AARCH32;
777
778 /*
779 * Restrict the CPU affinity mask for a 32-bit task so that
780 * it contains only 32-bit-capable CPUs.
781 *
782 * From the perspective of the task, this looks similar to
783 * what would happen if the 64-bit-only CPUs were hot-unplugged
784 * at the point of execve(), although we try a bit harder to
785 * honour the cpuset hierarchy.
786 */
787 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
788 force_compatible_cpus_allowed_ptr(current);
789 } else if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) {
790 relax_compatible_cpus_allowed_ptr(current);
791 }
792
793 current->mm->context.flags = mmflags;
794 ptrauth_thread_init_user();
795 mte_thread_init_user();
796 do_set_tsc_mode(PR_TSC_ENABLE);
797
798 if (task_spec_ssb_noexec(current)) {
799 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
800 PR_SPEC_ENABLE);
801 }
802}
803
804#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
805/*
806 * Control the relaxed ABI allowing tagged user addresses into the kernel.
807 */
808static unsigned int tagged_addr_disabled;
809
810long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
811{
812 unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
813 struct thread_info *ti = task_thread_info(task);
814
815 if (is_compat_thread(ti))
816 return -EINVAL;
817
818 if (system_supports_mte())
819 valid_mask |= PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC \
820 | PR_MTE_TAG_MASK;
821
822 if (arg & ~valid_mask)
823 return -EINVAL;
824
825 /*
826 * Do not allow the enabling of the tagged address ABI if globally
827 * disabled via sysctl abi.tagged_addr_disabled.
828 */
829 if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
830 return -EINVAL;
831
832 if (set_mte_ctrl(task, arg) != 0)
833 return -EINVAL;
834
835 update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
836
837 return 0;
838}
839
840long get_tagged_addr_ctrl(struct task_struct *task)
841{
842 long ret = 0;
843 struct thread_info *ti = task_thread_info(task);
844
845 if (is_compat_thread(ti))
846 return -EINVAL;
847
848 if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
849 ret = PR_TAGGED_ADDR_ENABLE;
850
851 ret |= get_mte_ctrl(task);
852
853 return ret;
854}
855
856/*
857 * Global sysctl to disable the tagged user addresses support. This control
858 * only prevents the tagged address ABI enabling via prctl() and does not
859 * disable it for tasks that already opted in to the relaxed ABI.
860 */
861
862static struct ctl_table tagged_addr_sysctl_table[] = {
863 {
864 .procname = "tagged_addr_disabled",
865 .mode = 0644,
866 .data = &tagged_addr_disabled,
867 .maxlen = sizeof(int),
868 .proc_handler = proc_dointvec_minmax,
869 .extra1 = SYSCTL_ZERO,
870 .extra2 = SYSCTL_ONE,
871 },
872};
873
874static int __init tagged_addr_init(void)
875{
876 if (!register_sysctl("abi", tagged_addr_sysctl_table))
877 return -EINVAL;
878 return 0;
879}
880
881core_initcall(tagged_addr_init);
882#endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
883
884#ifdef CONFIG_BINFMT_ELF
885int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
886 bool has_interp, bool is_interp)
887{
888 /*
889 * For dynamically linked executables the interpreter is
890 * responsible for setting PROT_BTI on everything except
891 * itself.
892 */
893 if (is_interp != has_interp)
894 return prot;
895
896 if (!(state->flags & ARM64_ELF_BTI))
897 return prot;
898
899 if (prot & PROT_EXEC)
900 prot |= PROT_BTI;
901
902 return prot;
903}
904#endif
905
906int get_tsc_mode(unsigned long adr)
907{
908 unsigned int val;
909
910 if (is_compat_task())
911 return -EINVAL;
912
913 if (test_thread_flag(TIF_TSC_SIGSEGV))
914 val = PR_TSC_SIGSEGV;
915 else
916 val = PR_TSC_ENABLE;
917
918 return put_user(val, (unsigned int __user *)adr);
919}
920
921int set_tsc_mode(unsigned int val)
922{
923 if (is_compat_task())
924 return -EINVAL;
925
926 return do_set_tsc_mode(val);
927}