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1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36/* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
38 */
39
40/**
41 * DOC: uevents generated by i915 on it's device node
42 *
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
49 *
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
56 *
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
60 */
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65/*
66 * i915_user_extension: Base class for defining a chain of extensions
67 *
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
73 *
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
79 */
80struct i915_user_extension {
81 __u64 next_extension;
82 __u32 name;
83 __u32 flags; /* All undefined bits must be zero. */
84 __u32 rsvd[4]; /* Reserved for future use; must be zero. */
85};
86
87/*
88 * MOCS indexes used for GPU surfaces, defining the cacheability of the
89 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
90 */
91enum i915_mocs_table_index {
92 /*
93 * Not cached anywhere, coherency between CPU and GPU accesses is
94 * guaranteed.
95 */
96 I915_MOCS_UNCACHED,
97 /*
98 * Cacheability and coherency controlled by the kernel automatically
99 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
100 * usage of the surface (used for display scanout or not).
101 */
102 I915_MOCS_PTE,
103 /*
104 * Cached in all GPU caches available on the platform.
105 * Coherency between CPU and GPU accesses to the surface is not
106 * guaranteed without extra synchronization.
107 */
108 I915_MOCS_CACHED,
109};
110
111/*
112 * Different engines serve different roles, and there may be more than one
113 * engine serving each role. enum drm_i915_gem_engine_class provides a
114 * classification of the role of the engine, which may be used when requesting
115 * operations to be performed on a certain subset of engines, or for providing
116 * information about that group.
117 */
118enum drm_i915_gem_engine_class {
119 I915_ENGINE_CLASS_RENDER = 0,
120 I915_ENGINE_CLASS_COPY = 1,
121 I915_ENGINE_CLASS_VIDEO = 2,
122 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
123
124 /* should be kept compact */
125
126 I915_ENGINE_CLASS_INVALID = -1
127};
128
129/*
130 * There may be more than one engine fulfilling any role within the system.
131 * Each engine of a class is given a unique instance number and therefore
132 * any engine can be specified by its class:instance tuplet. APIs that allow
133 * access to any engine in the system will use struct i915_engine_class_instance
134 * for this identification.
135 */
136struct i915_engine_class_instance {
137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
138 __u16 engine_instance;
139#define I915_ENGINE_CLASS_INVALID_NONE -1
140#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
141};
142
143/**
144 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
145 *
146 */
147
148enum drm_i915_pmu_engine_sample {
149 I915_SAMPLE_BUSY = 0,
150 I915_SAMPLE_WAIT = 1,
151 I915_SAMPLE_SEMA = 2
152};
153
154#define I915_PMU_SAMPLE_BITS (4)
155#define I915_PMU_SAMPLE_MASK (0xf)
156#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
157#define I915_PMU_CLASS_SHIFT \
158 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
159
160#define __I915_PMU_ENGINE(class, instance, sample) \
161 ((class) << I915_PMU_CLASS_SHIFT | \
162 (instance) << I915_PMU_SAMPLE_BITS | \
163 (sample))
164
165#define I915_PMU_ENGINE_BUSY(class, instance) \
166 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
167
168#define I915_PMU_ENGINE_WAIT(class, instance) \
169 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
170
171#define I915_PMU_ENGINE_SEMA(class, instance) \
172 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
173
174#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
175
176#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
177#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
178#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
179#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
180
181#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
182
183/* Each region is a minimum of 16k, and there are at most 255 of them.
184 */
185#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
186 * of chars for next/prev indices */
187#define I915_LOG_MIN_TEX_REGION_SIZE 14
188
189typedef struct _drm_i915_init {
190 enum {
191 I915_INIT_DMA = 0x01,
192 I915_CLEANUP_DMA = 0x02,
193 I915_RESUME_DMA = 0x03
194 } func;
195 unsigned int mmio_offset;
196 int sarea_priv_offset;
197 unsigned int ring_start;
198 unsigned int ring_end;
199 unsigned int ring_size;
200 unsigned int front_offset;
201 unsigned int back_offset;
202 unsigned int depth_offset;
203 unsigned int w;
204 unsigned int h;
205 unsigned int pitch;
206 unsigned int pitch_bits;
207 unsigned int back_pitch;
208 unsigned int depth_pitch;
209 unsigned int cpp;
210 unsigned int chipset;
211} drm_i915_init_t;
212
213typedef struct _drm_i915_sarea {
214 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
215 int last_upload; /* last time texture was uploaded */
216 int last_enqueue; /* last time a buffer was enqueued */
217 int last_dispatch; /* age of the most recently dispatched buffer */
218 int ctxOwner; /* last context to upload state */
219 int texAge;
220 int pf_enabled; /* is pageflipping allowed? */
221 int pf_active;
222 int pf_current_page; /* which buffer is being displayed? */
223 int perf_boxes; /* performance boxes to be displayed */
224 int width, height; /* screen size in pixels */
225
226 drm_handle_t front_handle;
227 int front_offset;
228 int front_size;
229
230 drm_handle_t back_handle;
231 int back_offset;
232 int back_size;
233
234 drm_handle_t depth_handle;
235 int depth_offset;
236 int depth_size;
237
238 drm_handle_t tex_handle;
239 int tex_offset;
240 int tex_size;
241 int log_tex_granularity;
242 int pitch;
243 int rotation; /* 0, 90, 180 or 270 */
244 int rotated_offset;
245 int rotated_size;
246 int rotated_pitch;
247 int virtualX, virtualY;
248
249 unsigned int front_tiled;
250 unsigned int back_tiled;
251 unsigned int depth_tiled;
252 unsigned int rotated_tiled;
253 unsigned int rotated2_tiled;
254
255 int pipeA_x;
256 int pipeA_y;
257 int pipeA_w;
258 int pipeA_h;
259 int pipeB_x;
260 int pipeB_y;
261 int pipeB_w;
262 int pipeB_h;
263
264 /* fill out some space for old userspace triple buffer */
265 drm_handle_t unused_handle;
266 __u32 unused1, unused2, unused3;
267
268 /* buffer object handles for static buffers. May change
269 * over the lifetime of the client.
270 */
271 __u32 front_bo_handle;
272 __u32 back_bo_handle;
273 __u32 unused_bo_handle;
274 __u32 depth_bo_handle;
275
276} drm_i915_sarea_t;
277
278/* due to userspace building against these headers we need some compat here */
279#define planeA_x pipeA_x
280#define planeA_y pipeA_y
281#define planeA_w pipeA_w
282#define planeA_h pipeA_h
283#define planeB_x pipeB_x
284#define planeB_y pipeB_y
285#define planeB_w pipeB_w
286#define planeB_h pipeB_h
287
288/* Flags for perf_boxes
289 */
290#define I915_BOX_RING_EMPTY 0x1
291#define I915_BOX_FLIP 0x2
292#define I915_BOX_WAIT 0x4
293#define I915_BOX_TEXTURE_LOAD 0x8
294#define I915_BOX_LOST_CONTEXT 0x10
295
296/*
297 * i915 specific ioctls.
298 *
299 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
300 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
301 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
302 */
303#define DRM_I915_INIT 0x00
304#define DRM_I915_FLUSH 0x01
305#define DRM_I915_FLIP 0x02
306#define DRM_I915_BATCHBUFFER 0x03
307#define DRM_I915_IRQ_EMIT 0x04
308#define DRM_I915_IRQ_WAIT 0x05
309#define DRM_I915_GETPARAM 0x06
310#define DRM_I915_SETPARAM 0x07
311#define DRM_I915_ALLOC 0x08
312#define DRM_I915_FREE 0x09
313#define DRM_I915_INIT_HEAP 0x0a
314#define DRM_I915_CMDBUFFER 0x0b
315#define DRM_I915_DESTROY_HEAP 0x0c
316#define DRM_I915_SET_VBLANK_PIPE 0x0d
317#define DRM_I915_GET_VBLANK_PIPE 0x0e
318#define DRM_I915_VBLANK_SWAP 0x0f
319#define DRM_I915_HWS_ADDR 0x11
320#define DRM_I915_GEM_INIT 0x13
321#define DRM_I915_GEM_EXECBUFFER 0x14
322#define DRM_I915_GEM_PIN 0x15
323#define DRM_I915_GEM_UNPIN 0x16
324#define DRM_I915_GEM_BUSY 0x17
325#define DRM_I915_GEM_THROTTLE 0x18
326#define DRM_I915_GEM_ENTERVT 0x19
327#define DRM_I915_GEM_LEAVEVT 0x1a
328#define DRM_I915_GEM_CREATE 0x1b
329#define DRM_I915_GEM_PREAD 0x1c
330#define DRM_I915_GEM_PWRITE 0x1d
331#define DRM_I915_GEM_MMAP 0x1e
332#define DRM_I915_GEM_SET_DOMAIN 0x1f
333#define DRM_I915_GEM_SW_FINISH 0x20
334#define DRM_I915_GEM_SET_TILING 0x21
335#define DRM_I915_GEM_GET_TILING 0x22
336#define DRM_I915_GEM_GET_APERTURE 0x23
337#define DRM_I915_GEM_MMAP_GTT 0x24
338#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
339#define DRM_I915_GEM_MADVISE 0x26
340#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
341#define DRM_I915_OVERLAY_ATTRS 0x28
342#define DRM_I915_GEM_EXECBUFFER2 0x29
343#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
344#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
345#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
346#define DRM_I915_GEM_WAIT 0x2c
347#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
348#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
349#define DRM_I915_GEM_SET_CACHING 0x2f
350#define DRM_I915_GEM_GET_CACHING 0x30
351#define DRM_I915_REG_READ 0x31
352#define DRM_I915_GET_RESET_STATS 0x32
353#define DRM_I915_GEM_USERPTR 0x33
354#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
355#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
356#define DRM_I915_PERF_OPEN 0x36
357#define DRM_I915_PERF_ADD_CONFIG 0x37
358#define DRM_I915_PERF_REMOVE_CONFIG 0x38
359#define DRM_I915_QUERY 0x39
360#define DRM_I915_GEM_VM_CREATE 0x3a
361#define DRM_I915_GEM_VM_DESTROY 0x3b
362/* Must be kept compact -- no holes */
363
364#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
365#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
366#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
367#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
368#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
369#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
370#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
371#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
372#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
373#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
374#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
375#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
376#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
377#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
378#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
379#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
380#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
381#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
382#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
383#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
384#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
385#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
386#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
387#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
388#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
389#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
390#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
391#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
392#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
393#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
394#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
395#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
396#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
397#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
398#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
399#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
400#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
401#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
402#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
403#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
404#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
405#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
406#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
407#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
408#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
409#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
410#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
411#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
412#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
413#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
414#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
415#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
416#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
417#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
418#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
419#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
420#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
421#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
422#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
423#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
424#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
425
426/* Allow drivers to submit batchbuffers directly to hardware, relying
427 * on the security mechanisms provided by hardware.
428 */
429typedef struct drm_i915_batchbuffer {
430 int start; /* agp offset */
431 int used; /* nr bytes in use */
432 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
433 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
434 int num_cliprects; /* mulitpass with multiple cliprects? */
435 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
436} drm_i915_batchbuffer_t;
437
438/* As above, but pass a pointer to userspace buffer which can be
439 * validated by the kernel prior to sending to hardware.
440 */
441typedef struct _drm_i915_cmdbuffer {
442 char __user *buf; /* pointer to userspace command buffer */
443 int sz; /* nr bytes in buf */
444 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
445 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
446 int num_cliprects; /* mulitpass with multiple cliprects? */
447 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
448} drm_i915_cmdbuffer_t;
449
450/* Userspace can request & wait on irq's:
451 */
452typedef struct drm_i915_irq_emit {
453 int __user *irq_seq;
454} drm_i915_irq_emit_t;
455
456typedef struct drm_i915_irq_wait {
457 int irq_seq;
458} drm_i915_irq_wait_t;
459
460/*
461 * Different modes of per-process Graphics Translation Table,
462 * see I915_PARAM_HAS_ALIASING_PPGTT
463 */
464#define I915_GEM_PPGTT_NONE 0
465#define I915_GEM_PPGTT_ALIASING 1
466#define I915_GEM_PPGTT_FULL 2
467
468/* Ioctl to query kernel params:
469 */
470#define I915_PARAM_IRQ_ACTIVE 1
471#define I915_PARAM_ALLOW_BATCHBUFFER 2
472#define I915_PARAM_LAST_DISPATCH 3
473#define I915_PARAM_CHIPSET_ID 4
474#define I915_PARAM_HAS_GEM 5
475#define I915_PARAM_NUM_FENCES_AVAIL 6
476#define I915_PARAM_HAS_OVERLAY 7
477#define I915_PARAM_HAS_PAGEFLIPPING 8
478#define I915_PARAM_HAS_EXECBUF2 9
479#define I915_PARAM_HAS_BSD 10
480#define I915_PARAM_HAS_BLT 11
481#define I915_PARAM_HAS_RELAXED_FENCING 12
482#define I915_PARAM_HAS_COHERENT_RINGS 13
483#define I915_PARAM_HAS_EXEC_CONSTANTS 14
484#define I915_PARAM_HAS_RELAXED_DELTA 15
485#define I915_PARAM_HAS_GEN7_SOL_RESET 16
486#define I915_PARAM_HAS_LLC 17
487#define I915_PARAM_HAS_ALIASING_PPGTT 18
488#define I915_PARAM_HAS_WAIT_TIMEOUT 19
489#define I915_PARAM_HAS_SEMAPHORES 20
490#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
491#define I915_PARAM_HAS_VEBOX 22
492#define I915_PARAM_HAS_SECURE_BATCHES 23
493#define I915_PARAM_HAS_PINNED_BATCHES 24
494#define I915_PARAM_HAS_EXEC_NO_RELOC 25
495#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
496#define I915_PARAM_HAS_WT 27
497#define I915_PARAM_CMD_PARSER_VERSION 28
498#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
499#define I915_PARAM_MMAP_VERSION 30
500#define I915_PARAM_HAS_BSD2 31
501#define I915_PARAM_REVISION 32
502#define I915_PARAM_SUBSLICE_TOTAL 33
503#define I915_PARAM_EU_TOTAL 34
504#define I915_PARAM_HAS_GPU_RESET 35
505#define I915_PARAM_HAS_RESOURCE_STREAMER 36
506#define I915_PARAM_HAS_EXEC_SOFTPIN 37
507#define I915_PARAM_HAS_POOLED_EU 38
508#define I915_PARAM_MIN_EU_IN_POOL 39
509#define I915_PARAM_MMAP_GTT_VERSION 40
510
511/*
512 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
513 * priorities and the driver will attempt to execute batches in priority order.
514 * The param returns a capability bitmask, nonzero implies that the scheduler
515 * is enabled, with different features present according to the mask.
516 *
517 * The initial priority for each batch is supplied by the context and is
518 * controlled via I915_CONTEXT_PARAM_PRIORITY.
519 */
520#define I915_PARAM_HAS_SCHEDULER 41
521#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
522#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
523#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
524#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
525#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
526
527#define I915_PARAM_HUC_STATUS 42
528
529/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
530 * synchronisation with implicit fencing on individual objects.
531 * See EXEC_OBJECT_ASYNC.
532 */
533#define I915_PARAM_HAS_EXEC_ASYNC 43
534
535/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
536 * both being able to pass in a sync_file fd to wait upon before executing,
537 * and being able to return a new sync_file fd that is signaled when the
538 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
539 */
540#define I915_PARAM_HAS_EXEC_FENCE 44
541
542/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
543 * user specified bufffers for post-mortem debugging of GPU hangs. See
544 * EXEC_OBJECT_CAPTURE.
545 */
546#define I915_PARAM_HAS_EXEC_CAPTURE 45
547
548#define I915_PARAM_SLICE_MASK 46
549
550/* Assuming it's uniform for each slice, this queries the mask of subslices
551 * per-slice for this system.
552 */
553#define I915_PARAM_SUBSLICE_MASK 47
554
555/*
556 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
557 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
558 */
559#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
560
561/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
562 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
563 */
564#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
565
566/*
567 * Query whether every context (both per-file default and user created) is
568 * isolated (insofar as HW supports). If this parameter is not true, then
569 * freshly created contexts may inherit values from an existing context,
570 * rather than default HW values. If true, it also ensures (insofar as HW
571 * supports) that all state set by this context will not leak to any other
572 * context.
573 *
574 * As not every engine across every gen support contexts, the returned
575 * value reports the support of context isolation for individual engines by
576 * returning a bitmask of each engine class set to true if that class supports
577 * isolation.
578 */
579#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
580
581/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
582 * registers. This used to be fixed per platform but from CNL onwards, this
583 * might vary depending on the parts.
584 */
585#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
586
587/*
588 * Once upon a time we supposed that writes through the GGTT would be
589 * immediately in physical memory (once flushed out of the CPU path). However,
590 * on a few different processors and chipsets, this is not necessarily the case
591 * as the writes appear to be buffered internally. Thus a read of the backing
592 * storage (physical memory) via a different path (with different physical tags
593 * to the indirect write via the GGTT) will see stale values from before
594 * the GGTT write. Inside the kernel, we can for the most part keep track of
595 * the different read/write domains in use (e.g. set-domain), but the assumption
596 * of coherency is baked into the ABI, hence reporting its true state in this
597 * parameter.
598 *
599 * Reports true when writes via mmap_gtt are immediately visible following an
600 * lfence to flush the WCB.
601 *
602 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
603 * internal buffer and are _not_ immediately visible to third parties accessing
604 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
605 * communications channel when reporting false is strongly disadvised.
606 */
607#define I915_PARAM_MMAP_GTT_COHERENT 52
608
609/*
610 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
611 * execution through use of explicit fence support.
612 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
613 */
614#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
615
616/*
617 * Revision of the i915-perf uAPI. The value returned helps determine what
618 * i915-perf features are available. See drm_i915_perf_property_id.
619 */
620#define I915_PARAM_PERF_REVISION 54
621
622/* Must be kept compact -- no holes and well documented */
623
624typedef struct drm_i915_getparam {
625 __s32 param;
626 /*
627 * WARNING: Using pointers instead of fixed-size u64 means we need to write
628 * compat32 code. Don't repeat this mistake.
629 */
630 int __user *value;
631} drm_i915_getparam_t;
632
633/* Ioctl to set kernel params:
634 */
635#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
636#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
637#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
638#define I915_SETPARAM_NUM_USED_FENCES 4
639/* Must be kept compact -- no holes */
640
641typedef struct drm_i915_setparam {
642 int param;
643 int value;
644} drm_i915_setparam_t;
645
646/* A memory manager for regions of shared memory:
647 */
648#define I915_MEM_REGION_AGP 1
649
650typedef struct drm_i915_mem_alloc {
651 int region;
652 int alignment;
653 int size;
654 int __user *region_offset; /* offset from start of fb or agp */
655} drm_i915_mem_alloc_t;
656
657typedef struct drm_i915_mem_free {
658 int region;
659 int region_offset;
660} drm_i915_mem_free_t;
661
662typedef struct drm_i915_mem_init_heap {
663 int region;
664 int size;
665 int start;
666} drm_i915_mem_init_heap_t;
667
668/* Allow memory manager to be torn down and re-initialized (eg on
669 * rotate):
670 */
671typedef struct drm_i915_mem_destroy_heap {
672 int region;
673} drm_i915_mem_destroy_heap_t;
674
675/* Allow X server to configure which pipes to monitor for vblank signals
676 */
677#define DRM_I915_VBLANK_PIPE_A 1
678#define DRM_I915_VBLANK_PIPE_B 2
679
680typedef struct drm_i915_vblank_pipe {
681 int pipe;
682} drm_i915_vblank_pipe_t;
683
684/* Schedule buffer swap at given vertical blank:
685 */
686typedef struct drm_i915_vblank_swap {
687 drm_drawable_t drawable;
688 enum drm_vblank_seq_type seqtype;
689 unsigned int sequence;
690} drm_i915_vblank_swap_t;
691
692typedef struct drm_i915_hws_addr {
693 __u64 addr;
694} drm_i915_hws_addr_t;
695
696struct drm_i915_gem_init {
697 /**
698 * Beginning offset in the GTT to be managed by the DRM memory
699 * manager.
700 */
701 __u64 gtt_start;
702 /**
703 * Ending offset in the GTT to be managed by the DRM memory
704 * manager.
705 */
706 __u64 gtt_end;
707};
708
709struct drm_i915_gem_create {
710 /**
711 * Requested size for the object.
712 *
713 * The (page-aligned) allocated size for the object will be returned.
714 */
715 __u64 size;
716 /**
717 * Returned handle for the object.
718 *
719 * Object handles are nonzero.
720 */
721 __u32 handle;
722 __u32 pad;
723};
724
725struct drm_i915_gem_pread {
726 /** Handle for the object being read. */
727 __u32 handle;
728 __u32 pad;
729 /** Offset into the object to read from */
730 __u64 offset;
731 /** Length of data to read */
732 __u64 size;
733 /**
734 * Pointer to write the data into.
735 *
736 * This is a fixed-size type for 32/64 compatibility.
737 */
738 __u64 data_ptr;
739};
740
741struct drm_i915_gem_pwrite {
742 /** Handle for the object being written to. */
743 __u32 handle;
744 __u32 pad;
745 /** Offset into the object to write to */
746 __u64 offset;
747 /** Length of data to write */
748 __u64 size;
749 /**
750 * Pointer to read the data from.
751 *
752 * This is a fixed-size type for 32/64 compatibility.
753 */
754 __u64 data_ptr;
755};
756
757struct drm_i915_gem_mmap {
758 /** Handle for the object being mapped. */
759 __u32 handle;
760 __u32 pad;
761 /** Offset in the object to map. */
762 __u64 offset;
763 /**
764 * Length of data to map.
765 *
766 * The value will be page-aligned.
767 */
768 __u64 size;
769 /**
770 * Returned pointer the data was mapped at.
771 *
772 * This is a fixed-size type for 32/64 compatibility.
773 */
774 __u64 addr_ptr;
775
776 /**
777 * Flags for extended behaviour.
778 *
779 * Added in version 2.
780 */
781 __u64 flags;
782#define I915_MMAP_WC 0x1
783};
784
785struct drm_i915_gem_mmap_gtt {
786 /** Handle for the object being mapped. */
787 __u32 handle;
788 __u32 pad;
789 /**
790 * Fake offset to use for subsequent mmap call
791 *
792 * This is a fixed-size type for 32/64 compatibility.
793 */
794 __u64 offset;
795};
796
797struct drm_i915_gem_mmap_offset {
798 /** Handle for the object being mapped. */
799 __u32 handle;
800 __u32 pad;
801 /**
802 * Fake offset to use for subsequent mmap call
803 *
804 * This is a fixed-size type for 32/64 compatibility.
805 */
806 __u64 offset;
807
808 /**
809 * Flags for extended behaviour.
810 *
811 * It is mandatory that one of the MMAP_OFFSET types
812 * (GTT, WC, WB, UC, etc) should be included.
813 */
814 __u64 flags;
815#define I915_MMAP_OFFSET_GTT 0
816#define I915_MMAP_OFFSET_WC 1
817#define I915_MMAP_OFFSET_WB 2
818#define I915_MMAP_OFFSET_UC 3
819
820 /*
821 * Zero-terminated chain of extensions.
822 *
823 * No current extensions defined; mbz.
824 */
825 __u64 extensions;
826};
827
828struct drm_i915_gem_set_domain {
829 /** Handle for the object */
830 __u32 handle;
831
832 /** New read domains */
833 __u32 read_domains;
834
835 /** New write domain */
836 __u32 write_domain;
837};
838
839struct drm_i915_gem_sw_finish {
840 /** Handle for the object */
841 __u32 handle;
842};
843
844struct drm_i915_gem_relocation_entry {
845 /**
846 * Handle of the buffer being pointed to by this relocation entry.
847 *
848 * It's appealing to make this be an index into the mm_validate_entry
849 * list to refer to the buffer, but this allows the driver to create
850 * a relocation list for state buffers and not re-write it per
851 * exec using the buffer.
852 */
853 __u32 target_handle;
854
855 /**
856 * Value to be added to the offset of the target buffer to make up
857 * the relocation entry.
858 */
859 __u32 delta;
860
861 /** Offset in the buffer the relocation entry will be written into */
862 __u64 offset;
863
864 /**
865 * Offset value of the target buffer that the relocation entry was last
866 * written as.
867 *
868 * If the buffer has the same offset as last time, we can skip syncing
869 * and writing the relocation. This value is written back out by
870 * the execbuffer ioctl when the relocation is written.
871 */
872 __u64 presumed_offset;
873
874 /**
875 * Target memory domains read by this operation.
876 */
877 __u32 read_domains;
878
879 /**
880 * Target memory domains written by this operation.
881 *
882 * Note that only one domain may be written by the whole
883 * execbuffer operation, so that where there are conflicts,
884 * the application will get -EINVAL back.
885 */
886 __u32 write_domain;
887};
888
889/** @{
890 * Intel memory domains
891 *
892 * Most of these just align with the various caches in
893 * the system and are used to flush and invalidate as
894 * objects end up cached in different domains.
895 */
896/** CPU cache */
897#define I915_GEM_DOMAIN_CPU 0x00000001
898/** Render cache, used by 2D and 3D drawing */
899#define I915_GEM_DOMAIN_RENDER 0x00000002
900/** Sampler cache, used by texture engine */
901#define I915_GEM_DOMAIN_SAMPLER 0x00000004
902/** Command queue, used to load batch buffers */
903#define I915_GEM_DOMAIN_COMMAND 0x00000008
904/** Instruction cache, used by shader programs */
905#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
906/** Vertex address cache */
907#define I915_GEM_DOMAIN_VERTEX 0x00000020
908/** GTT domain - aperture and scanout */
909#define I915_GEM_DOMAIN_GTT 0x00000040
910/** WC domain - uncached access */
911#define I915_GEM_DOMAIN_WC 0x00000080
912/** @} */
913
914struct drm_i915_gem_exec_object {
915 /**
916 * User's handle for a buffer to be bound into the GTT for this
917 * operation.
918 */
919 __u32 handle;
920
921 /** Number of relocations to be performed on this buffer */
922 __u32 relocation_count;
923 /**
924 * Pointer to array of struct drm_i915_gem_relocation_entry containing
925 * the relocations to be performed in this buffer.
926 */
927 __u64 relocs_ptr;
928
929 /** Required alignment in graphics aperture */
930 __u64 alignment;
931
932 /**
933 * Returned value of the updated offset of the object, for future
934 * presumed_offset writes.
935 */
936 __u64 offset;
937};
938
939struct drm_i915_gem_execbuffer {
940 /**
941 * List of buffers to be validated with their relocations to be
942 * performend on them.
943 *
944 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
945 *
946 * These buffers must be listed in an order such that all relocations
947 * a buffer is performing refer to buffers that have already appeared
948 * in the validate list.
949 */
950 __u64 buffers_ptr;
951 __u32 buffer_count;
952
953 /** Offset in the batchbuffer to start execution from. */
954 __u32 batch_start_offset;
955 /** Bytes used in batchbuffer from batch_start_offset */
956 __u32 batch_len;
957 __u32 DR1;
958 __u32 DR4;
959 __u32 num_cliprects;
960 /** This is a struct drm_clip_rect *cliprects */
961 __u64 cliprects_ptr;
962};
963
964struct drm_i915_gem_exec_object2 {
965 /**
966 * User's handle for a buffer to be bound into the GTT for this
967 * operation.
968 */
969 __u32 handle;
970
971 /** Number of relocations to be performed on this buffer */
972 __u32 relocation_count;
973 /**
974 * Pointer to array of struct drm_i915_gem_relocation_entry containing
975 * the relocations to be performed in this buffer.
976 */
977 __u64 relocs_ptr;
978
979 /** Required alignment in graphics aperture */
980 __u64 alignment;
981
982 /**
983 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
984 * the user with the GTT offset at which this object will be pinned.
985 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
986 * presumed_offset of the object.
987 * During execbuffer2 the kernel populates it with the value of the
988 * current GTT offset of the object, for future presumed_offset writes.
989 */
990 __u64 offset;
991
992#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
993#define EXEC_OBJECT_NEEDS_GTT (1<<1)
994#define EXEC_OBJECT_WRITE (1<<2)
995#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
996#define EXEC_OBJECT_PINNED (1<<4)
997#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
998/* The kernel implicitly tracks GPU activity on all GEM objects, and
999 * synchronises operations with outstanding rendering. This includes
1000 * rendering on other devices if exported via dma-buf. However, sometimes
1001 * this tracking is too coarse and the user knows better. For example,
1002 * if the object is split into non-overlapping ranges shared between different
1003 * clients or engines (i.e. suballocating objects), the implicit tracking
1004 * by kernel assumes that each operation affects the whole object rather
1005 * than an individual range, causing needless synchronisation between clients.
1006 * The kernel will also forgo any CPU cache flushes prior to rendering from
1007 * the object as the client is expected to be also handling such domain
1008 * tracking.
1009 *
1010 * The kernel maintains the implicit tracking in order to manage resources
1011 * used by the GPU - this flag only disables the synchronisation prior to
1012 * rendering with this object in this execbuf.
1013 *
1014 * Opting out of implicit synhronisation requires the user to do its own
1015 * explicit tracking to avoid rendering corruption. See, for example,
1016 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
1017 */
1018#define EXEC_OBJECT_ASYNC (1<<6)
1019/* Request that the contents of this execobject be copied into the error
1020 * state upon a GPU hang involving this batch for post-mortem debugging.
1021 * These buffers are recorded in no particular order as "user" in
1022 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
1023 * if the kernel supports this flag.
1024 */
1025#define EXEC_OBJECT_CAPTURE (1<<7)
1026/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
1027#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1028 __u64 flags;
1029
1030 union {
1031 __u64 rsvd1;
1032 __u64 pad_to_size;
1033 };
1034 __u64 rsvd2;
1035};
1036
1037struct drm_i915_gem_exec_fence {
1038 /**
1039 * User's handle for a drm_syncobj to wait on or signal.
1040 */
1041 __u32 handle;
1042
1043#define I915_EXEC_FENCE_WAIT (1<<0)
1044#define I915_EXEC_FENCE_SIGNAL (1<<1)
1045#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1046 __u32 flags;
1047};
1048
1049struct drm_i915_gem_execbuffer2 {
1050 /**
1051 * List of gem_exec_object2 structs
1052 */
1053 __u64 buffers_ptr;
1054 __u32 buffer_count;
1055
1056 /** Offset in the batchbuffer to start execution from. */
1057 __u32 batch_start_offset;
1058 /** Bytes used in batchbuffer from batch_start_offset */
1059 __u32 batch_len;
1060 __u32 DR1;
1061 __u32 DR4;
1062 __u32 num_cliprects;
1063 /**
1064 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1065 * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
1066 * struct drm_i915_gem_exec_fence *fences.
1067 */
1068 __u64 cliprects_ptr;
1069#define I915_EXEC_RING_MASK (0x3f)
1070#define I915_EXEC_DEFAULT (0<<0)
1071#define I915_EXEC_RENDER (1<<0)
1072#define I915_EXEC_BSD (2<<0)
1073#define I915_EXEC_BLT (3<<0)
1074#define I915_EXEC_VEBOX (4<<0)
1075
1076/* Used for switching the constants addressing mode on gen4+ RENDER ring.
1077 * Gen6+ only supports relative addressing to dynamic state (default) and
1078 * absolute addressing.
1079 *
1080 * These flags are ignored for the BSD and BLT rings.
1081 */
1082#define I915_EXEC_CONSTANTS_MASK (3<<6)
1083#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1084#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1085#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1086 __u64 flags;
1087 __u64 rsvd1; /* now used for context info */
1088 __u64 rsvd2;
1089};
1090
1091/** Resets the SO write offset registers for transform feedback on gen7. */
1092#define I915_EXEC_GEN7_SOL_RESET (1<<8)
1093
1094/** Request a privileged ("secure") batch buffer. Note only available for
1095 * DRM_ROOT_ONLY | DRM_MASTER processes.
1096 */
1097#define I915_EXEC_SECURE (1<<9)
1098
1099/** Inform the kernel that the batch is and will always be pinned. This
1100 * negates the requirement for a workaround to be performed to avoid
1101 * an incoherent CS (such as can be found on 830/845). If this flag is
1102 * not passed, the kernel will endeavour to make sure the batch is
1103 * coherent with the CS before execution. If this flag is passed,
1104 * userspace assumes the responsibility for ensuring the same.
1105 */
1106#define I915_EXEC_IS_PINNED (1<<10)
1107
1108/** Provide a hint to the kernel that the command stream and auxiliary
1109 * state buffers already holds the correct presumed addresses and so the
1110 * relocation process may be skipped if no buffers need to be moved in
1111 * preparation for the execbuffer.
1112 */
1113#define I915_EXEC_NO_RELOC (1<<11)
1114
1115/** Use the reloc.handle as an index into the exec object array rather
1116 * than as the per-file handle.
1117 */
1118#define I915_EXEC_HANDLE_LUT (1<<12)
1119
1120/** Used for switching BSD rings on the platforms with two BSD rings */
1121#define I915_EXEC_BSD_SHIFT (13)
1122#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1123/* default ping-pong mode */
1124#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1125#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1126#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1127
1128/** Tell the kernel that the batchbuffer is processed by
1129 * the resource streamer.
1130 */
1131#define I915_EXEC_RESOURCE_STREAMER (1<<15)
1132
1133/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1134 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1135 * the batch.
1136 *
1137 * Returns -EINVAL if the sync_file fd cannot be found.
1138 */
1139#define I915_EXEC_FENCE_IN (1<<16)
1140
1141/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1142 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1143 * to the caller, and it should be close() after use. (The fd is a regular
1144 * file descriptor and will be cleaned up on process termination. It holds
1145 * a reference to the request, but nothing else.)
1146 *
1147 * The sync_file fd can be combined with other sync_file and passed either
1148 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1149 * will only occur after this request completes), or to other devices.
1150 *
1151 * Using I915_EXEC_FENCE_OUT requires use of
1152 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1153 * back to userspace. Failure to do so will cause the out-fence to always
1154 * be reported as zero, and the real fence fd to be leaked.
1155 */
1156#define I915_EXEC_FENCE_OUT (1<<17)
1157
1158/*
1159 * Traditionally the execbuf ioctl has only considered the final element in
1160 * the execobject[] to be the executable batch. Often though, the client
1161 * will known the batch object prior to construction and being able to place
1162 * it into the execobject[] array first can simplify the relocation tracking.
1163 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1164 * execobject[] as the * batch instead (the default is to use the last
1165 * element).
1166 */
1167#define I915_EXEC_BATCH_FIRST (1<<18)
1168
1169/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1170 * define an array of i915_gem_exec_fence structures which specify a set of
1171 * dma fences to wait upon or signal.
1172 */
1173#define I915_EXEC_FENCE_ARRAY (1<<19)
1174
1175/*
1176 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1177 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1178 * the batch.
1179 *
1180 * Returns -EINVAL if the sync_file fd cannot be found.
1181 */
1182#define I915_EXEC_FENCE_SUBMIT (1 << 20)
1183
1184#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
1185
1186#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1187#define i915_execbuffer2_set_context_id(eb2, context) \
1188 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1189#define i915_execbuffer2_get_context_id(eb2) \
1190 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1191
1192struct drm_i915_gem_pin {
1193 /** Handle of the buffer to be pinned. */
1194 __u32 handle;
1195 __u32 pad;
1196
1197 /** alignment required within the aperture */
1198 __u64 alignment;
1199
1200 /** Returned GTT offset of the buffer. */
1201 __u64 offset;
1202};
1203
1204struct drm_i915_gem_unpin {
1205 /** Handle of the buffer to be unpinned. */
1206 __u32 handle;
1207 __u32 pad;
1208};
1209
1210struct drm_i915_gem_busy {
1211 /** Handle of the buffer to check for busy */
1212 __u32 handle;
1213
1214 /** Return busy status
1215 *
1216 * A return of 0 implies that the object is idle (after
1217 * having flushed any pending activity), and a non-zero return that
1218 * the object is still in-flight on the GPU. (The GPU has not yet
1219 * signaled completion for all pending requests that reference the
1220 * object.) An object is guaranteed to become idle eventually (so
1221 * long as no new GPU commands are executed upon it). Due to the
1222 * asynchronous nature of the hardware, an object reported
1223 * as busy may become idle before the ioctl is completed.
1224 *
1225 * Furthermore, if the object is busy, which engine is busy is only
1226 * provided as a guide and only indirectly by reporting its class
1227 * (there may be more than one engine in each class). There are race
1228 * conditions which prevent the report of which engines are busy from
1229 * being always accurate. However, the converse is not true. If the
1230 * object is idle, the result of the ioctl, that all engines are idle,
1231 * is accurate.
1232 *
1233 * The returned dword is split into two fields to indicate both
1234 * the engine classess on which the object is being read, and the
1235 * engine class on which it is currently being written (if any).
1236 *
1237 * The low word (bits 0:15) indicate if the object is being written
1238 * to by any engine (there can only be one, as the GEM implicit
1239 * synchronisation rules force writes to be serialised). Only the
1240 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1241 * 1 not 0 etc) for the last write is reported.
1242 *
1243 * The high word (bits 16:31) are a bitmask of which engines classes
1244 * are currently reading from the object. Multiple engines may be
1245 * reading from the object simultaneously.
1246 *
1247 * The value of each engine class is the same as specified in the
1248 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1249 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1250 * reported as active itself. Some hardware may have parallel
1251 * execution engines, e.g. multiple media engines, which are
1252 * mapped to the same class identifier and so are not separately
1253 * reported for busyness.
1254 *
1255 * Caveat emptor:
1256 * Only the boolean result of this query is reliable; that is whether
1257 * the object is idle or busy. The report of which engines are busy
1258 * should be only used as a heuristic.
1259 */
1260 __u32 busy;
1261};
1262
1263/**
1264 * I915_CACHING_NONE
1265 *
1266 * GPU access is not coherent with cpu caches. Default for machines without an
1267 * LLC.
1268 */
1269#define I915_CACHING_NONE 0
1270/**
1271 * I915_CACHING_CACHED
1272 *
1273 * GPU access is coherent with cpu caches and furthermore the data is cached in
1274 * last-level caches shared between cpu cores and the gpu GT. Default on
1275 * machines with HAS_LLC.
1276 */
1277#define I915_CACHING_CACHED 1
1278/**
1279 * I915_CACHING_DISPLAY
1280 *
1281 * Special GPU caching mode which is coherent with the scanout engines.
1282 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1283 * cache mode (like write-through or gfdt flushing) is available. The kernel
1284 * automatically sets this mode when using a buffer as a scanout target.
1285 * Userspace can manually set this mode to avoid a costly stall and clflush in
1286 * the hotpath of drawing the first frame.
1287 */
1288#define I915_CACHING_DISPLAY 2
1289
1290struct drm_i915_gem_caching {
1291 /**
1292 * Handle of the buffer to set/get the caching level of. */
1293 __u32 handle;
1294
1295 /**
1296 * Cacheing level to apply or return value
1297 *
1298 * bits0-15 are for generic caching control (i.e. the above defined
1299 * values). bits16-31 are reserved for platform-specific variations
1300 * (e.g. l3$ caching on gen7). */
1301 __u32 caching;
1302};
1303
1304#define I915_TILING_NONE 0
1305#define I915_TILING_X 1
1306#define I915_TILING_Y 2
1307#define I915_TILING_LAST I915_TILING_Y
1308
1309#define I915_BIT_6_SWIZZLE_NONE 0
1310#define I915_BIT_6_SWIZZLE_9 1
1311#define I915_BIT_6_SWIZZLE_9_10 2
1312#define I915_BIT_6_SWIZZLE_9_11 3
1313#define I915_BIT_6_SWIZZLE_9_10_11 4
1314/* Not seen by userland */
1315#define I915_BIT_6_SWIZZLE_UNKNOWN 5
1316/* Seen by userland. */
1317#define I915_BIT_6_SWIZZLE_9_17 6
1318#define I915_BIT_6_SWIZZLE_9_10_17 7
1319
1320struct drm_i915_gem_set_tiling {
1321 /** Handle of the buffer to have its tiling state updated */
1322 __u32 handle;
1323
1324 /**
1325 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1326 * I915_TILING_Y).
1327 *
1328 * This value is to be set on request, and will be updated by the
1329 * kernel on successful return with the actual chosen tiling layout.
1330 *
1331 * The tiling mode may be demoted to I915_TILING_NONE when the system
1332 * has bit 6 swizzling that can't be managed correctly by GEM.
1333 *
1334 * Buffer contents become undefined when changing tiling_mode.
1335 */
1336 __u32 tiling_mode;
1337
1338 /**
1339 * Stride in bytes for the object when in I915_TILING_X or
1340 * I915_TILING_Y.
1341 */
1342 __u32 stride;
1343
1344 /**
1345 * Returned address bit 6 swizzling required for CPU access through
1346 * mmap mapping.
1347 */
1348 __u32 swizzle_mode;
1349};
1350
1351struct drm_i915_gem_get_tiling {
1352 /** Handle of the buffer to get tiling state for. */
1353 __u32 handle;
1354
1355 /**
1356 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1357 * I915_TILING_Y).
1358 */
1359 __u32 tiling_mode;
1360
1361 /**
1362 * Returned address bit 6 swizzling required for CPU access through
1363 * mmap mapping.
1364 */
1365 __u32 swizzle_mode;
1366
1367 /**
1368 * Returned address bit 6 swizzling required for CPU access through
1369 * mmap mapping whilst bound.
1370 */
1371 __u32 phys_swizzle_mode;
1372};
1373
1374struct drm_i915_gem_get_aperture {
1375 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1376 __u64 aper_size;
1377
1378 /**
1379 * Available space in the aperture used by i915_gem_execbuffer, in
1380 * bytes
1381 */
1382 __u64 aper_available_size;
1383};
1384
1385struct drm_i915_get_pipe_from_crtc_id {
1386 /** ID of CRTC being requested **/
1387 __u32 crtc_id;
1388
1389 /** pipe of requested CRTC **/
1390 __u32 pipe;
1391};
1392
1393#define I915_MADV_WILLNEED 0
1394#define I915_MADV_DONTNEED 1
1395#define __I915_MADV_PURGED 2 /* internal state */
1396
1397struct drm_i915_gem_madvise {
1398 /** Handle of the buffer to change the backing store advice */
1399 __u32 handle;
1400
1401 /* Advice: either the buffer will be needed again in the near future,
1402 * or wont be and could be discarded under memory pressure.
1403 */
1404 __u32 madv;
1405
1406 /** Whether the backing store still exists. */
1407 __u32 retained;
1408};
1409
1410/* flags */
1411#define I915_OVERLAY_TYPE_MASK 0xff
1412#define I915_OVERLAY_YUV_PLANAR 0x01
1413#define I915_OVERLAY_YUV_PACKED 0x02
1414#define I915_OVERLAY_RGB 0x03
1415
1416#define I915_OVERLAY_DEPTH_MASK 0xff00
1417#define I915_OVERLAY_RGB24 0x1000
1418#define I915_OVERLAY_RGB16 0x2000
1419#define I915_OVERLAY_RGB15 0x3000
1420#define I915_OVERLAY_YUV422 0x0100
1421#define I915_OVERLAY_YUV411 0x0200
1422#define I915_OVERLAY_YUV420 0x0300
1423#define I915_OVERLAY_YUV410 0x0400
1424
1425#define I915_OVERLAY_SWAP_MASK 0xff0000
1426#define I915_OVERLAY_NO_SWAP 0x000000
1427#define I915_OVERLAY_UV_SWAP 0x010000
1428#define I915_OVERLAY_Y_SWAP 0x020000
1429#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1430
1431#define I915_OVERLAY_FLAGS_MASK 0xff000000
1432#define I915_OVERLAY_ENABLE 0x01000000
1433
1434struct drm_intel_overlay_put_image {
1435 /* various flags and src format description */
1436 __u32 flags;
1437 /* source picture description */
1438 __u32 bo_handle;
1439 /* stride values and offsets are in bytes, buffer relative */
1440 __u16 stride_Y; /* stride for packed formats */
1441 __u16 stride_UV;
1442 __u32 offset_Y; /* offset for packet formats */
1443 __u32 offset_U;
1444 __u32 offset_V;
1445 /* in pixels */
1446 __u16 src_width;
1447 __u16 src_height;
1448 /* to compensate the scaling factors for partially covered surfaces */
1449 __u16 src_scan_width;
1450 __u16 src_scan_height;
1451 /* output crtc description */
1452 __u32 crtc_id;
1453 __u16 dst_x;
1454 __u16 dst_y;
1455 __u16 dst_width;
1456 __u16 dst_height;
1457};
1458
1459/* flags */
1460#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1461#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1462#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1463struct drm_intel_overlay_attrs {
1464 __u32 flags;
1465 __u32 color_key;
1466 __s32 brightness;
1467 __u32 contrast;
1468 __u32 saturation;
1469 __u32 gamma0;
1470 __u32 gamma1;
1471 __u32 gamma2;
1472 __u32 gamma3;
1473 __u32 gamma4;
1474 __u32 gamma5;
1475};
1476
1477/*
1478 * Intel sprite handling
1479 *
1480 * Color keying works with a min/mask/max tuple. Both source and destination
1481 * color keying is allowed.
1482 *
1483 * Source keying:
1484 * Sprite pixels within the min & max values, masked against the color channels
1485 * specified in the mask field, will be transparent. All other pixels will
1486 * be displayed on top of the primary plane. For RGB surfaces, only the min
1487 * and mask fields will be used; ranged compares are not allowed.
1488 *
1489 * Destination keying:
1490 * Primary plane pixels that match the min value, masked against the color
1491 * channels specified in the mask field, will be replaced by corresponding
1492 * pixels from the sprite plane.
1493 *
1494 * Note that source & destination keying are exclusive; only one can be
1495 * active on a given plane.
1496 */
1497
1498#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1499 * flags==0 to disable colorkeying.
1500 */
1501#define I915_SET_COLORKEY_DESTINATION (1<<1)
1502#define I915_SET_COLORKEY_SOURCE (1<<2)
1503struct drm_intel_sprite_colorkey {
1504 __u32 plane_id;
1505 __u32 min_value;
1506 __u32 channel_mask;
1507 __u32 max_value;
1508 __u32 flags;
1509};
1510
1511struct drm_i915_gem_wait {
1512 /** Handle of BO we shall wait on */
1513 __u32 bo_handle;
1514 __u32 flags;
1515 /** Number of nanoseconds to wait, Returns time remaining. */
1516 __s64 timeout_ns;
1517};
1518
1519struct drm_i915_gem_context_create {
1520 __u32 ctx_id; /* output: id of new context*/
1521 __u32 pad;
1522};
1523
1524struct drm_i915_gem_context_create_ext {
1525 __u32 ctx_id; /* output: id of new context*/
1526 __u32 flags;
1527#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1528#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1529#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1530 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1531 __u64 extensions;
1532};
1533
1534struct drm_i915_gem_context_param {
1535 __u32 ctx_id;
1536 __u32 size;
1537 __u64 param;
1538#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1539#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1540#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1541#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1542#define I915_CONTEXT_PARAM_BANNABLE 0x5
1543#define I915_CONTEXT_PARAM_PRIORITY 0x6
1544#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1545#define I915_CONTEXT_DEFAULT_PRIORITY 0
1546#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1547 /*
1548 * When using the following param, value should be a pointer to
1549 * drm_i915_gem_context_param_sseu.
1550 */
1551#define I915_CONTEXT_PARAM_SSEU 0x7
1552
1553/*
1554 * Not all clients may want to attempt automatic recover of a context after
1555 * a hang (for example, some clients may only submit very small incremental
1556 * batches relying on known logical state of previous batches which will never
1557 * recover correctly and each attempt will hang), and so would prefer that
1558 * the context is forever banned instead.
1559 *
1560 * If set to false (0), after a reset, subsequent (and in flight) rendering
1561 * from this context is discarded, and the client will need to create a new
1562 * context to use instead.
1563 *
1564 * If set to true (1), the kernel will automatically attempt to recover the
1565 * context by skipping the hanging batch and executing the next batch starting
1566 * from the default context state (discarding the incomplete logical context
1567 * state lost due to the reset).
1568 *
1569 * On creation, all new contexts are marked as recoverable.
1570 */
1571#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1572
1573 /*
1574 * The id of the associated virtual memory address space (ppGTT) of
1575 * this context. Can be retrieved and passed to another context
1576 * (on the same fd) for both to use the same ppGTT and so share
1577 * address layouts, and avoid reloading the page tables on context
1578 * switches between themselves.
1579 *
1580 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1581 */
1582#define I915_CONTEXT_PARAM_VM 0x9
1583
1584/*
1585 * I915_CONTEXT_PARAM_ENGINES:
1586 *
1587 * Bind this context to operate on this subset of available engines. Henceforth,
1588 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1589 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1590 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1591 * Use
1592 * engine_class: I915_ENGINE_CLASS_INVALID,
1593 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1594 * to specify a gap in the array that can be filled in later, e.g. by a
1595 * virtual engine used for load balancing.
1596 *
1597 * Setting the number of engines bound to the context to 0, by passing a zero
1598 * sized argument, will revert back to default settings.
1599 *
1600 * See struct i915_context_param_engines.
1601 *
1602 * Extensions:
1603 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1604 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1605 */
1606#define I915_CONTEXT_PARAM_ENGINES 0xa
1607
1608/*
1609 * I915_CONTEXT_PARAM_PERSISTENCE:
1610 *
1611 * Allow the context and active rendering to survive the process until
1612 * completion. Persistence allows fire-and-forget clients to queue up a
1613 * bunch of work, hand the output over to a display server and then quit.
1614 * If the context is marked as not persistent, upon closing (either via
1615 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
1616 * or process termination), the context and any outstanding requests will be
1617 * cancelled (and exported fences for cancelled requests marked as -EIO).
1618 *
1619 * By default, new contexts allow persistence.
1620 */
1621#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1622
1623/*
1624 * I915_CONTEXT_PARAM_RINGSIZE:
1625 *
1626 * Sets the size of the CS ringbuffer to use for logical ring contexts. This
1627 * applies a limit of how many batches can be queued to HW before the caller
1628 * is blocked due to lack of space for more commands.
1629 *
1630 * Only reliably possible to be set prior to first use, i.e. during
1631 * construction. At any later point, the current execution must be flushed as
1632 * the ring can only be changed while the context is idle. Note, the ringsize
1633 * can be specified as a constructor property, see
1634 * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
1635 *
1636 * Only applies to the current set of engine and lost when those engines
1637 * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
1638 *
1639 * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
1640 * Default is 16 KiB.
1641 */
1642#define I915_CONTEXT_PARAM_RINGSIZE 0xc
1643/* Must be kept compact -- no holes and well documented */
1644
1645 __u64 value;
1646};
1647
1648/**
1649 * Context SSEU programming
1650 *
1651 * It may be necessary for either functional or performance reason to configure
1652 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1653 * Sub-slice/EU).
1654 *
1655 * This is done by configuring SSEU configuration using the below
1656 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1657 * userspace intends to use.
1658 *
1659 * Not all GPUs or engines support this functionality in which case an error
1660 * code -ENODEV will be returned.
1661 *
1662 * Also, flexibility of possible SSEU configuration permutations varies between
1663 * GPU generations and software imposed limitations. Requesting such a
1664 * combination will return an error code of -EINVAL.
1665 *
1666 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1667 * favour of a single global setting.
1668 */
1669struct drm_i915_gem_context_param_sseu {
1670 /*
1671 * Engine class & instance to be configured or queried.
1672 */
1673 struct i915_engine_class_instance engine;
1674
1675 /*
1676 * Unknown flags must be cleared to zero.
1677 */
1678 __u32 flags;
1679#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1680
1681 /*
1682 * Mask of slices to enable for the context. Valid values are a subset
1683 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1684 */
1685 __u64 slice_mask;
1686
1687 /*
1688 * Mask of subslices to enable for the context. Valid values are a
1689 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1690 */
1691 __u64 subslice_mask;
1692
1693 /*
1694 * Minimum/Maximum number of EUs to enable per subslice for the
1695 * context. min_eus_per_subslice must be inferior or equal to
1696 * max_eus_per_subslice.
1697 */
1698 __u16 min_eus_per_subslice;
1699 __u16 max_eus_per_subslice;
1700
1701 /*
1702 * Unused for now. Must be cleared to zero.
1703 */
1704 __u32 rsvd;
1705};
1706
1707/*
1708 * i915_context_engines_load_balance:
1709 *
1710 * Enable load balancing across this set of engines.
1711 *
1712 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1713 * used will proxy the execbuffer request onto one of the set of engines
1714 * in such a way as to distribute the load evenly across the set.
1715 *
1716 * The set of engines must be compatible (e.g. the same HW class) as they
1717 * will share the same logical GPU context and ring.
1718 *
1719 * To intermix rendering with the virtual engine and direct rendering onto
1720 * the backing engines (bypassing the load balancing proxy), the context must
1721 * be defined to use a single timeline for all engines.
1722 */
1723struct i915_context_engines_load_balance {
1724 struct i915_user_extension base;
1725
1726 __u16 engine_index;
1727 __u16 num_siblings;
1728 __u32 flags; /* all undefined flags must be zero */
1729
1730 __u64 mbz64; /* reserved for future use; must be zero */
1731
1732 struct i915_engine_class_instance engines[0];
1733} __attribute__((packed));
1734
1735#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1736 struct i915_user_extension base; \
1737 __u16 engine_index; \
1738 __u16 num_siblings; \
1739 __u32 flags; \
1740 __u64 mbz64; \
1741 struct i915_engine_class_instance engines[N__]; \
1742} __attribute__((packed)) name__
1743
1744/*
1745 * i915_context_engines_bond:
1746 *
1747 * Constructed bonded pairs for execution within a virtual engine.
1748 *
1749 * All engines are equal, but some are more equal than others. Given
1750 * the distribution of resources in the HW, it may be preferable to run
1751 * a request on a given subset of engines in parallel to a request on a
1752 * specific engine. We enable this selection of engines within a virtual
1753 * engine by specifying bonding pairs, for any given master engine we will
1754 * only execute on one of the corresponding siblings within the virtual engine.
1755 *
1756 * To execute a request in parallel on the master engine and a sibling requires
1757 * coordination with a I915_EXEC_FENCE_SUBMIT.
1758 */
1759struct i915_context_engines_bond {
1760 struct i915_user_extension base;
1761
1762 struct i915_engine_class_instance master;
1763
1764 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1765 __u16 num_bonds;
1766
1767 __u64 flags; /* all undefined flags must be zero */
1768 __u64 mbz64[4]; /* reserved for future use; must be zero */
1769
1770 struct i915_engine_class_instance engines[0];
1771} __attribute__((packed));
1772
1773#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1774 struct i915_user_extension base; \
1775 struct i915_engine_class_instance master; \
1776 __u16 virtual_index; \
1777 __u16 num_bonds; \
1778 __u64 flags; \
1779 __u64 mbz64[4]; \
1780 struct i915_engine_class_instance engines[N__]; \
1781} __attribute__((packed)) name__
1782
1783struct i915_context_param_engines {
1784 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1785#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1786#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1787 struct i915_engine_class_instance engines[0];
1788} __attribute__((packed));
1789
1790#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1791 __u64 extensions; \
1792 struct i915_engine_class_instance engines[N__]; \
1793} __attribute__((packed)) name__
1794
1795struct drm_i915_gem_context_create_ext_setparam {
1796#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1797 struct i915_user_extension base;
1798 struct drm_i915_gem_context_param param;
1799};
1800
1801struct drm_i915_gem_context_create_ext_clone {
1802#define I915_CONTEXT_CREATE_EXT_CLONE 1
1803 struct i915_user_extension base;
1804 __u32 clone_id;
1805 __u32 flags;
1806#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1807#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1808#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1809#define I915_CONTEXT_CLONE_SSEU (1u << 3)
1810#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1811#define I915_CONTEXT_CLONE_VM (1u << 5)
1812#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1813 __u64 rsvd;
1814};
1815
1816struct drm_i915_gem_context_destroy {
1817 __u32 ctx_id;
1818 __u32 pad;
1819};
1820
1821/*
1822 * DRM_I915_GEM_VM_CREATE -
1823 *
1824 * Create a new virtual memory address space (ppGTT) for use within a context
1825 * on the same file. Extensions can be provided to configure exactly how the
1826 * address space is setup upon creation.
1827 *
1828 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1829 * returned in the outparam @id.
1830 *
1831 * No flags are defined, with all bits reserved and must be zero.
1832 *
1833 * An extension chain maybe provided, starting with @extensions, and terminated
1834 * by the @next_extension being 0. Currently, no extensions are defined.
1835 *
1836 * DRM_I915_GEM_VM_DESTROY -
1837 *
1838 * Destroys a previously created VM id, specified in @id.
1839 *
1840 * No extensions or flags are allowed currently, and so must be zero.
1841 */
1842struct drm_i915_gem_vm_control {
1843 __u64 extensions;
1844 __u32 flags;
1845 __u32 vm_id;
1846};
1847
1848struct drm_i915_reg_read {
1849 /*
1850 * Register offset.
1851 * For 64bit wide registers where the upper 32bits don't immediately
1852 * follow the lower 32bits, the offset of the lower 32bits must
1853 * be specified
1854 */
1855 __u64 offset;
1856#define I915_REG_READ_8B_WA (1ul << 0)
1857
1858 __u64 val; /* Return value */
1859};
1860
1861/* Known registers:
1862 *
1863 * Render engine timestamp - 0x2358 + 64bit - gen7+
1864 * - Note this register returns an invalid value if using the default
1865 * single instruction 8byte read, in order to workaround that pass
1866 * flag I915_REG_READ_8B_WA in offset field.
1867 *
1868 */
1869
1870struct drm_i915_reset_stats {
1871 __u32 ctx_id;
1872 __u32 flags;
1873
1874 /* All resets since boot/module reload, for all contexts */
1875 __u32 reset_count;
1876
1877 /* Number of batches lost when active in GPU, for this context */
1878 __u32 batch_active;
1879
1880 /* Number of batches lost pending for execution, for this context */
1881 __u32 batch_pending;
1882
1883 __u32 pad;
1884};
1885
1886struct drm_i915_gem_userptr {
1887 __u64 user_ptr;
1888 __u64 user_size;
1889 __u32 flags;
1890#define I915_USERPTR_READ_ONLY 0x1
1891#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1892 /**
1893 * Returned handle for the object.
1894 *
1895 * Object handles are nonzero.
1896 */
1897 __u32 handle;
1898};
1899
1900enum drm_i915_oa_format {
1901 I915_OA_FORMAT_A13 = 1, /* HSW only */
1902 I915_OA_FORMAT_A29, /* HSW only */
1903 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
1904 I915_OA_FORMAT_B4_C8, /* HSW only */
1905 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
1906 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
1907 I915_OA_FORMAT_C4_B8, /* HSW+ */
1908
1909 /* Gen8+ */
1910 I915_OA_FORMAT_A12,
1911 I915_OA_FORMAT_A12_B8_C8,
1912 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1913
1914 I915_OA_FORMAT_MAX /* non-ABI */
1915};
1916
1917enum drm_i915_perf_property_id {
1918 /**
1919 * Open the stream for a specific context handle (as used with
1920 * execbuffer2). A stream opened for a specific context this way
1921 * won't typically require root privileges.
1922 *
1923 * This property is available in perf revision 1.
1924 */
1925 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1926
1927 /**
1928 * A value of 1 requests the inclusion of raw OA unit reports as
1929 * part of stream samples.
1930 *
1931 * This property is available in perf revision 1.
1932 */
1933 DRM_I915_PERF_PROP_SAMPLE_OA,
1934
1935 /**
1936 * The value specifies which set of OA unit metrics should be
1937 * configured, defining the contents of any OA unit reports.
1938 *
1939 * This property is available in perf revision 1.
1940 */
1941 DRM_I915_PERF_PROP_OA_METRICS_SET,
1942
1943 /**
1944 * The value specifies the size and layout of OA unit reports.
1945 *
1946 * This property is available in perf revision 1.
1947 */
1948 DRM_I915_PERF_PROP_OA_FORMAT,
1949
1950 /**
1951 * Specifying this property implicitly requests periodic OA unit
1952 * sampling and (at least on Haswell) the sampling frequency is derived
1953 * from this exponent as follows:
1954 *
1955 * 80ns * 2^(period_exponent + 1)
1956 *
1957 * This property is available in perf revision 1.
1958 */
1959 DRM_I915_PERF_PROP_OA_EXPONENT,
1960
1961 /**
1962 * Specifying this property is only valid when specify a context to
1963 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
1964 * will hold preemption of the particular context we want to gather
1965 * performance data about. The execbuf2 submissions must include a
1966 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
1967 *
1968 * This property is available in perf revision 3.
1969 */
1970 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
1971
1972 /**
1973 * Specifying this pins all contexts to the specified SSEU power
1974 * configuration for the duration of the recording.
1975 *
1976 * This parameter's value is a pointer to a struct
1977 * drm_i915_gem_context_param_sseu.
1978 *
1979 * This property is available in perf revision 4.
1980 */
1981 DRM_I915_PERF_PROP_GLOBAL_SSEU,
1982
1983 /**
1984 * This optional parameter specifies the timer interval in nanoseconds
1985 * at which the i915 driver will check the OA buffer for available data.
1986 * Minimum allowed value is 100 microseconds. A default value is used by
1987 * the driver if this parameter is not specified. Note that larger timer
1988 * values will reduce cpu consumption during OA perf captures. However,
1989 * excessively large values would potentially result in OA buffer
1990 * overwrites as captures reach end of the OA buffer.
1991 *
1992 * This property is available in perf revision 5.
1993 */
1994 DRM_I915_PERF_PROP_POLL_OA_PERIOD,
1995
1996 DRM_I915_PERF_PROP_MAX /* non-ABI */
1997};
1998
1999struct drm_i915_perf_open_param {
2000 __u32 flags;
2001#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
2002#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
2003#define I915_PERF_FLAG_DISABLED (1<<2)
2004
2005 /** The number of u64 (id, value) pairs */
2006 __u32 num_properties;
2007
2008 /**
2009 * Pointer to array of u64 (id, value) pairs configuring the stream
2010 * to open.
2011 */
2012 __u64 properties_ptr;
2013};
2014
2015/**
2016 * Enable data capture for a stream that was either opened in a disabled state
2017 * via I915_PERF_FLAG_DISABLED or was later disabled via
2018 * I915_PERF_IOCTL_DISABLE.
2019 *
2020 * It is intended to be cheaper to disable and enable a stream than it may be
2021 * to close and re-open a stream with the same configuration.
2022 *
2023 * It's undefined whether any pending data for the stream will be lost.
2024 *
2025 * This ioctl is available in perf revision 1.
2026 */
2027#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
2028
2029/**
2030 * Disable data capture for a stream.
2031 *
2032 * It is an error to try and read a stream that is disabled.
2033 *
2034 * This ioctl is available in perf revision 1.
2035 */
2036#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
2037
2038/**
2039 * Change metrics_set captured by a stream.
2040 *
2041 * If the stream is bound to a specific context, the configuration change
2042 * will performed inline with that context such that it takes effect before
2043 * the next execbuf submission.
2044 *
2045 * Returns the previously bound metrics set id, or a negative error code.
2046 *
2047 * This ioctl is available in perf revision 2.
2048 */
2049#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
2050
2051/**
2052 * Common to all i915 perf records
2053 */
2054struct drm_i915_perf_record_header {
2055 __u32 type;
2056 __u16 pad;
2057 __u16 size;
2058};
2059
2060enum drm_i915_perf_record_type {
2061
2062 /**
2063 * Samples are the work horse record type whose contents are extensible
2064 * and defined when opening an i915 perf stream based on the given
2065 * properties.
2066 *
2067 * Boolean properties following the naming convention
2068 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
2069 * every sample.
2070 *
2071 * The order of these sample properties given by userspace has no
2072 * affect on the ordering of data within a sample. The order is
2073 * documented here.
2074 *
2075 * struct {
2076 * struct drm_i915_perf_record_header header;
2077 *
2078 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
2079 * };
2080 */
2081 DRM_I915_PERF_RECORD_SAMPLE = 1,
2082
2083 /*
2084 * Indicates that one or more OA reports were not written by the
2085 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
2086 * command collides with periodic sampling - which would be more likely
2087 * at higher sampling frequencies.
2088 */
2089 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
2090
2091 /**
2092 * An error occurred that resulted in all pending OA reports being lost.
2093 */
2094 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
2095
2096 DRM_I915_PERF_RECORD_MAX /* non-ABI */
2097};
2098
2099/**
2100 * Structure to upload perf dynamic configuration into the kernel.
2101 */
2102struct drm_i915_perf_oa_config {
2103 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
2104 char uuid[36];
2105
2106 __u32 n_mux_regs;
2107 __u32 n_boolean_regs;
2108 __u32 n_flex_regs;
2109
2110 /*
2111 * These fields are pointers to tuples of u32 values (register address,
2112 * value). For example the expected length of the buffer pointed by
2113 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
2114 */
2115 __u64 mux_regs_ptr;
2116 __u64 boolean_regs_ptr;
2117 __u64 flex_regs_ptr;
2118};
2119
2120struct drm_i915_query_item {
2121 __u64 query_id;
2122#define DRM_I915_QUERY_TOPOLOGY_INFO 1
2123#define DRM_I915_QUERY_ENGINE_INFO 2
2124#define DRM_I915_QUERY_PERF_CONFIG 3
2125/* Must be kept compact -- no holes and well documented */
2126
2127 /*
2128 * When set to zero by userspace, this is filled with the size of the
2129 * data to be written at the data_ptr pointer. The kernel sets this
2130 * value to a negative value to signal an error on a particular query
2131 * item.
2132 */
2133 __s32 length;
2134
2135 /*
2136 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2137 *
2138 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2139 * following :
2140 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2141 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2142 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2143 */
2144 __u32 flags;
2145#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2146#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2147#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2148
2149 /*
2150 * Data will be written at the location pointed by data_ptr when the
2151 * value of length matches the length of the data to be written by the
2152 * kernel.
2153 */
2154 __u64 data_ptr;
2155};
2156
2157struct drm_i915_query {
2158 __u32 num_items;
2159
2160 /*
2161 * Unused for now. Must be cleared to zero.
2162 */
2163 __u32 flags;
2164
2165 /*
2166 * This points to an array of num_items drm_i915_query_item structures.
2167 */
2168 __u64 items_ptr;
2169};
2170
2171/*
2172 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2173 *
2174 * data: contains the 3 pieces of information :
2175 *
2176 * - the slice mask with one bit per slice telling whether a slice is
2177 * available. The availability of slice X can be queried with the following
2178 * formula :
2179 *
2180 * (data[X / 8] >> (X % 8)) & 1
2181 *
2182 * - the subslice mask for each slice with one bit per subslice telling
2183 * whether a subslice is available. Gen12 has dual-subslices, which are
2184 * similar to two gen11 subslices. For gen12, this array represents dual-
2185 * subslices. The availability of subslice Y in slice X can be queried
2186 * with the following formula :
2187 *
2188 * (data[subslice_offset +
2189 * X * subslice_stride +
2190 * Y / 8] >> (Y % 8)) & 1
2191 *
2192 * - the EU mask for each subslice in each slice with one bit per EU telling
2193 * whether an EU is available. The availability of EU Z in subslice Y in
2194 * slice X can be queried with the following formula :
2195 *
2196 * (data[eu_offset +
2197 * (X * max_subslices + Y) * eu_stride +
2198 * Z / 8] >> (Z % 8)) & 1
2199 */
2200struct drm_i915_query_topology_info {
2201 /*
2202 * Unused for now. Must be cleared to zero.
2203 */
2204 __u16 flags;
2205
2206 __u16 max_slices;
2207 __u16 max_subslices;
2208 __u16 max_eus_per_subslice;
2209
2210 /*
2211 * Offset in data[] at which the subslice masks are stored.
2212 */
2213 __u16 subslice_offset;
2214
2215 /*
2216 * Stride at which each of the subslice masks for each slice are
2217 * stored.
2218 */
2219 __u16 subslice_stride;
2220
2221 /*
2222 * Offset in data[] at which the EU masks are stored.
2223 */
2224 __u16 eu_offset;
2225
2226 /*
2227 * Stride at which each of the EU masks for each subslice are stored.
2228 */
2229 __u16 eu_stride;
2230
2231 __u8 data[];
2232};
2233
2234/**
2235 * struct drm_i915_engine_info
2236 *
2237 * Describes one engine and it's capabilities as known to the driver.
2238 */
2239struct drm_i915_engine_info {
2240 /** Engine class and instance. */
2241 struct i915_engine_class_instance engine;
2242
2243 /** Reserved field. */
2244 __u32 rsvd0;
2245
2246 /** Engine flags. */
2247 __u64 flags;
2248
2249 /** Capabilities of this engine. */
2250 __u64 capabilities;
2251#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2252#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2253
2254 /** Reserved fields. */
2255 __u64 rsvd1[4];
2256};
2257
2258/**
2259 * struct drm_i915_query_engine_info
2260 *
2261 * Engine info query enumerates all engines known to the driver by filling in
2262 * an array of struct drm_i915_engine_info structures.
2263 */
2264struct drm_i915_query_engine_info {
2265 /** Number of struct drm_i915_engine_info structs following. */
2266 __u32 num_engines;
2267
2268 /** MBZ */
2269 __u32 rsvd[3];
2270
2271 /** Marker for drm_i915_engine_info structures. */
2272 struct drm_i915_engine_info engines[];
2273};
2274
2275/*
2276 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2277 */
2278struct drm_i915_query_perf_config {
2279 union {
2280 /*
2281 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2282 * this fields to the number of configurations available.
2283 */
2284 __u64 n_configs;
2285
2286 /*
2287 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2288 * i915 will use the value in this field as configuration
2289 * identifier to decide what data to write into config_ptr.
2290 */
2291 __u64 config;
2292
2293 /*
2294 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2295 * i915 will use the value in this field as configuration
2296 * identifier to decide what data to write into config_ptr.
2297 *
2298 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2299 */
2300 char uuid[36];
2301 };
2302
2303 /*
2304 * Unused for now. Must be cleared to zero.
2305 */
2306 __u32 flags;
2307
2308 /*
2309 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2310 * write an array of __u64 of configuration identifiers.
2311 *
2312 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2313 * write a struct drm_i915_perf_oa_config. If the following fields of
2314 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2315 * the associated pointers the values of submitted when the
2316 * configuration was created :
2317 *
2318 * - n_mux_regs
2319 * - n_boolean_regs
2320 * - n_flex_regs
2321 */
2322 __u8 data[];
2323};
2324
2325#if defined(__cplusplus)
2326}
2327#endif
2328
2329#endif /* _UAPI_I915_DRM_H_ */