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1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/* 7.12.xx - Use STATIC functions wherever possible */
141/* - Clean up deprecated MODULE_PARM calls */
142/* 7.12.05 - Remove Version Matching per IBM request */
143/*****************************************************************************/
144
145/*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
181#include <linux/dma-mapping.h>
182
183#include <scsi/sg.h>
184#include "scsi.h"
185#include <scsi/scsi_host.h>
186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203/*
204 * DRIVER_VER
205 */
206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
210#warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
211#endif
212
213#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
214 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
215 PCI_DMA_BIDIRECTIONAL : \
216 scb->scsi_cmd->sc_data_direction)
217
218#ifdef IPS_DEBUG
219#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
220#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
221#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
222#else
223#define METHOD_TRACE(s, i)
224#define DEBUG(i, s)
225#define DEBUG_VAR(i, s, v...)
226#endif
227
228/*
229 * Function prototypes
230 */
231static int ips_detect(struct scsi_host_template *);
232static int ips_release(struct Scsi_Host *);
233static int ips_eh_abort(struct scsi_cmnd *);
234static int ips_eh_reset(struct scsi_cmnd *);
235static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
236static const char *ips_info(struct Scsi_Host *);
237static irqreturn_t do_ipsintr(int, void *);
238static int ips_hainit(ips_ha_t *);
239static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
240static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
241static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
242static int ips_online(ips_ha_t *, ips_scb_t *);
243static int ips_inquiry(ips_ha_t *, ips_scb_t *);
244static int ips_rdcap(ips_ha_t *, ips_scb_t *);
245static int ips_msense(ips_ha_t *, ips_scb_t *);
246static int ips_reqsen(ips_ha_t *, ips_scb_t *);
247static int ips_deallocatescbs(ips_ha_t *, int);
248static int ips_allocatescbs(ips_ha_t *);
249static int ips_reset_copperhead(ips_ha_t *);
250static int ips_reset_copperhead_memio(ips_ha_t *);
251static int ips_reset_morpheus(ips_ha_t *);
252static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
253static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
254static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
255static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
256static int ips_isintr_copperhead(ips_ha_t *);
257static int ips_isintr_copperhead_memio(ips_ha_t *);
258static int ips_isintr_morpheus(ips_ha_t *);
259static int ips_wait(ips_ha_t *, int, int);
260static int ips_write_driver_status(ips_ha_t *, int);
261static int ips_read_adapter_status(ips_ha_t *, int);
262static int ips_read_subsystem_parameters(ips_ha_t *, int);
263static int ips_read_config(ips_ha_t *, int);
264static int ips_clear_adapter(ips_ha_t *, int);
265static int ips_readwrite_page5(ips_ha_t *, int, int);
266static int ips_init_copperhead(ips_ha_t *);
267static int ips_init_copperhead_memio(ips_ha_t *);
268static int ips_init_morpheus(ips_ha_t *);
269static int ips_isinit_copperhead(ips_ha_t *);
270static int ips_isinit_copperhead_memio(ips_ha_t *);
271static int ips_isinit_morpheus(ips_ha_t *);
272static int ips_erase_bios(ips_ha_t *);
273static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
274static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
275static int ips_erase_bios_memio(ips_ha_t *);
276static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
277static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
278static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
279static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
280static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
281static void ips_free_flash_copperhead(ips_ha_t * ha);
282static void ips_get_bios_version(ips_ha_t *, int);
283static void ips_identify_controller(ips_ha_t *);
284static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
285static void ips_enable_int_copperhead(ips_ha_t *);
286static void ips_enable_int_copperhead_memio(ips_ha_t *);
287static void ips_enable_int_morpheus(ips_ha_t *);
288static int ips_intr_copperhead(ips_ha_t *);
289static int ips_intr_morpheus(ips_ha_t *);
290static void ips_next(ips_ha_t *, int);
291static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
292static void ipsintr_done(ips_ha_t *, struct ips_scb *);
293static void ips_done(ips_ha_t *, ips_scb_t *);
294static void ips_free(ips_ha_t *);
295static void ips_init_scb(ips_ha_t *, ips_scb_t *);
296static void ips_freescb(ips_ha_t *, ips_scb_t *);
297static void ips_setup_funclist(ips_ha_t *);
298static void ips_statinit(ips_ha_t *);
299static void ips_statinit_memio(ips_ha_t *);
300static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
301static void ips_ffdc_reset(ips_ha_t *, int);
302static void ips_ffdc_time(ips_ha_t *);
303static uint32_t ips_statupd_copperhead(ips_ha_t *);
304static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
305static uint32_t ips_statupd_morpheus(ips_ha_t *);
306static ips_scb_t *ips_getscb(ips_ha_t *);
307static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
308static void ips_putq_wait_tail(ips_wait_queue_t *, struct scsi_cmnd *);
309static void ips_putq_copp_tail(ips_copp_queue_t *,
310 ips_copp_wait_item_t *);
311static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
312static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
313static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
314static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *,
315 struct scsi_cmnd *);
316static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
317 ips_copp_wait_item_t *);
318static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
319
320static int ips_is_passthru(struct scsi_cmnd *);
321static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
322static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
323static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
324static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
325 unsigned int count);
326static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
327 unsigned int count);
328
329static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
330static int ips_host_info(ips_ha_t *, char *, off_t, int);
331static void copy_mem_info(IPS_INFOSTR *, char *, int);
332static int copy_info(IPS_INFOSTR *, char *, ...);
333static int ips_abort_init(ips_ha_t * ha, int index);
334static int ips_init_phase2(int index);
335
336static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
337static int ips_register_scsi(int index);
338
339static int ips_poll_for_flush_complete(ips_ha_t * ha);
340static void ips_flush_and_reset(ips_ha_t *ha);
341
342/*
343 * global variables
344 */
345static const char ips_name[] = "ips";
346static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
347static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
348static unsigned int ips_next_controller;
349static unsigned int ips_num_controllers;
350static unsigned int ips_released_controllers;
351static int ips_hotplug;
352static int ips_cmd_timeout = 60;
353static int ips_reset_timeout = 60 * 5;
354static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
355static int ips_force_i2o = 1; /* Always use I2O command delivery */
356static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
357static int ips_cd_boot; /* Booting from Manager CD */
358static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
359static dma_addr_t ips_flashbusaddr;
360static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
361static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
362static struct scsi_host_template ips_driver_template = {
363 .detect = ips_detect,
364 .release = ips_release,
365 .info = ips_info,
366 .queuecommand = ips_queue,
367 .eh_abort_handler = ips_eh_abort,
368 .eh_host_reset_handler = ips_eh_reset,
369 .proc_name = "ips",
370 .proc_info = ips_proc_info,
371 .slave_configure = ips_slave_configure,
372 .bios_param = ips_biosparam,
373 .this_id = -1,
374 .sg_tablesize = IPS_MAX_SG,
375 .cmd_per_lun = 3,
376 .use_clustering = ENABLE_CLUSTERING,
377};
378
379
380/* This table describes all ServeRAID Adapters */
381static struct pci_device_id ips_pci_table[] = {
382 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
383 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
384 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
385 { 0, }
386};
387
388MODULE_DEVICE_TABLE( pci, ips_pci_table );
389
390static char ips_hot_plug_name[] = "ips";
391
392static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
393static void __devexit ips_remove_device(struct pci_dev *pci_dev);
394
395static struct pci_driver ips_pci_driver = {
396 .name = ips_hot_plug_name,
397 .id_table = ips_pci_table,
398 .probe = ips_insert_device,
399 .remove = __devexit_p(ips_remove_device),
400};
401
402
403/*
404 * Necessary forward function protoypes
405 */
406static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
407
408#define MAX_ADAPTER_NAME 15
409
410static char ips_adapter_name[][30] = {
411 "ServeRAID",
412 "ServeRAID II",
413 "ServeRAID on motherboard",
414 "ServeRAID on motherboard",
415 "ServeRAID 3H",
416 "ServeRAID 3L",
417 "ServeRAID 4H",
418 "ServeRAID 4M",
419 "ServeRAID 4L",
420 "ServeRAID 4Mx",
421 "ServeRAID 4Lx",
422 "ServeRAID 5i",
423 "ServeRAID 5i",
424 "ServeRAID 6M",
425 "ServeRAID 6i",
426 "ServeRAID 7t",
427 "ServeRAID 7k",
428 "ServeRAID 7M"
429};
430
431static struct notifier_block ips_notifier = {
432 ips_halt, NULL, 0
433};
434
435/*
436 * Direction table
437 */
438static char ips_command_direction[] = {
439 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
440 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
441 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
442 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
444 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
445 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
446 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
447 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
449 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
450 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
451 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
452 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
453 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
454 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
473 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
474 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
475 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
487 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
490};
491
492
493/****************************************************************************/
494/* */
495/* Routine Name: ips_setup */
496/* */
497/* Routine Description: */
498/* */
499/* setup parameters to the driver */
500/* */
501/****************************************************************************/
502static int
503ips_setup(char *ips_str)
504{
505
506 int i;
507 char *key;
508 char *value;
509 IPS_OPTION options[] = {
510 {"noi2o", &ips_force_i2o, 0},
511 {"nommap", &ips_force_memio, 0},
512 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
513 {"cdboot", &ips_cd_boot, 0},
514 {"maxcmds", &MaxLiteCmds, 32},
515 };
516
517 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
518 /* Search for value */
519 while ((key = strsep(&ips_str, ",."))) {
520 if (!*key)
521 continue;
522 value = strchr(key, ':');
523 if (value)
524 *value++ = '\0';
525 /*
526 * We now have key/value pairs.
527 * Update the variables
528 */
529 for (i = 0; i < ARRAY_SIZE(options); i++) {
530 if (strnicmp
531 (key, options[i].option_name,
532 strlen(options[i].option_name)) == 0) {
533 if (value)
534 *options[i].option_flag =
535 simple_strtoul(value, NULL, 0);
536 else
537 *options[i].option_flag =
538 options[i].option_value;
539 break;
540 }
541 }
542 }
543
544 return (1);
545}
546
547__setup("ips=", ips_setup);
548
549/****************************************************************************/
550/* */
551/* Routine Name: ips_detect */
552/* */
553/* Routine Description: */
554/* */
555/* Detect and initialize the driver */
556/* */
557/* NOTE: this routine is called under the io_request_lock spinlock */
558/* */
559/****************************************************************************/
560static int
561ips_detect(struct scsi_host_template * SHT)
562{
563 int i;
564
565 METHOD_TRACE("ips_detect", 1);
566
567#ifdef MODULE
568 if (ips)
569 ips_setup(ips);
570#endif
571
572 for (i = 0; i < ips_num_controllers; i++) {
573 if (ips_register_scsi(i))
574 ips_free(ips_ha[i]);
575 ips_released_controllers++;
576 }
577 ips_hotplug = 1;
578 return (ips_num_controllers);
579}
580
581/****************************************************************************/
582/* configure the function pointers to use the functions that will work */
583/* with the found version of the adapter */
584/****************************************************************************/
585static void
586ips_setup_funclist(ips_ha_t * ha)
587{
588
589 /*
590 * Setup Functions
591 */
592 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
593 /* morpheus / marco / sebring */
594 ha->func.isintr = ips_isintr_morpheus;
595 ha->func.isinit = ips_isinit_morpheus;
596 ha->func.issue = ips_issue_i2o_memio;
597 ha->func.init = ips_init_morpheus;
598 ha->func.statupd = ips_statupd_morpheus;
599 ha->func.reset = ips_reset_morpheus;
600 ha->func.intr = ips_intr_morpheus;
601 ha->func.enableint = ips_enable_int_morpheus;
602 } else if (IPS_USE_MEMIO(ha)) {
603 /* copperhead w/MEMIO */
604 ha->func.isintr = ips_isintr_copperhead_memio;
605 ha->func.isinit = ips_isinit_copperhead_memio;
606 ha->func.init = ips_init_copperhead_memio;
607 ha->func.statupd = ips_statupd_copperhead_memio;
608 ha->func.statinit = ips_statinit_memio;
609 ha->func.reset = ips_reset_copperhead_memio;
610 ha->func.intr = ips_intr_copperhead;
611 ha->func.erasebios = ips_erase_bios_memio;
612 ha->func.programbios = ips_program_bios_memio;
613 ha->func.verifybios = ips_verify_bios_memio;
614 ha->func.enableint = ips_enable_int_copperhead_memio;
615 if (IPS_USE_I2O_DELIVER(ha))
616 ha->func.issue = ips_issue_i2o_memio;
617 else
618 ha->func.issue = ips_issue_copperhead_memio;
619 } else {
620 /* copperhead */
621 ha->func.isintr = ips_isintr_copperhead;
622 ha->func.isinit = ips_isinit_copperhead;
623 ha->func.init = ips_init_copperhead;
624 ha->func.statupd = ips_statupd_copperhead;
625 ha->func.statinit = ips_statinit;
626 ha->func.reset = ips_reset_copperhead;
627 ha->func.intr = ips_intr_copperhead;
628 ha->func.erasebios = ips_erase_bios;
629 ha->func.programbios = ips_program_bios;
630 ha->func.verifybios = ips_verify_bios;
631 ha->func.enableint = ips_enable_int_copperhead;
632
633 if (IPS_USE_I2O_DELIVER(ha))
634 ha->func.issue = ips_issue_i2o;
635 else
636 ha->func.issue = ips_issue_copperhead;
637 }
638}
639
640/****************************************************************************/
641/* */
642/* Routine Name: ips_release */
643/* */
644/* Routine Description: */
645/* */
646/* Remove a driver */
647/* */
648/****************************************************************************/
649static int
650ips_release(struct Scsi_Host *sh)
651{
652 ips_scb_t *scb;
653 ips_ha_t *ha;
654 int i;
655
656 METHOD_TRACE("ips_release", 1);
657
658 scsi_remove_host(sh);
659
660 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
661
662 if (i == IPS_MAX_ADAPTERS) {
663 printk(KERN_WARNING
664 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
665 BUG();
666 return (FALSE);
667 }
668
669 ha = IPS_HA(sh);
670
671 if (!ha)
672 return (FALSE);
673
674 /* flush the cache on the controller */
675 scb = &ha->scbs[ha->max_cmds - 1];
676
677 ips_init_scb(ha, scb);
678
679 scb->timeout = ips_cmd_timeout;
680 scb->cdb[0] = IPS_CMD_FLUSH;
681
682 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
683 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
684 scb->cmd.flush_cache.state = IPS_NORM_STATE;
685 scb->cmd.flush_cache.reserved = 0;
686 scb->cmd.flush_cache.reserved2 = 0;
687 scb->cmd.flush_cache.reserved3 = 0;
688 scb->cmd.flush_cache.reserved4 = 0;
689
690 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
691
692 /* send command */
693 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
694 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
695
696 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
697
698 ips_sh[i] = NULL;
699 ips_ha[i] = NULL;
700
701 /* free extra memory */
702 ips_free(ha);
703
704 /* free IRQ */
705 free_irq(ha->pcidev->irq, ha);
706
707 scsi_host_put(sh);
708
709 ips_released_controllers++;
710
711 return (FALSE);
712}
713
714/****************************************************************************/
715/* */
716/* Routine Name: ips_halt */
717/* */
718/* Routine Description: */
719/* */
720/* Perform cleanup when the system reboots */
721/* */
722/****************************************************************************/
723static int
724ips_halt(struct notifier_block *nb, ulong event, void *buf)
725{
726 ips_scb_t *scb;
727 ips_ha_t *ha;
728 int i;
729
730 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
731 (event != SYS_POWER_OFF))
732 return (NOTIFY_DONE);
733
734 for (i = 0; i < ips_next_controller; i++) {
735 ha = (ips_ha_t *) ips_ha[i];
736
737 if (!ha)
738 continue;
739
740 if (!ha->active)
741 continue;
742
743 /* flush the cache on the controller */
744 scb = &ha->scbs[ha->max_cmds - 1];
745
746 ips_init_scb(ha, scb);
747
748 scb->timeout = ips_cmd_timeout;
749 scb->cdb[0] = IPS_CMD_FLUSH;
750
751 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
752 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
753 scb->cmd.flush_cache.state = IPS_NORM_STATE;
754 scb->cmd.flush_cache.reserved = 0;
755 scb->cmd.flush_cache.reserved2 = 0;
756 scb->cmd.flush_cache.reserved3 = 0;
757 scb->cmd.flush_cache.reserved4 = 0;
758
759 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
760
761 /* send command */
762 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
763 IPS_FAILURE)
764 IPS_PRINTK(KERN_WARNING, ha->pcidev,
765 "Incomplete Flush.\n");
766 else
767 IPS_PRINTK(KERN_WARNING, ha->pcidev,
768 "Flushing Complete.\n");
769 }
770
771 return (NOTIFY_OK);
772}
773
774/****************************************************************************/
775/* */
776/* Routine Name: ips_eh_abort */
777/* */
778/* Routine Description: */
779/* */
780/* Abort a command (using the new error code stuff) */
781/* Note: this routine is called under the io_request_lock */
782/****************************************************************************/
783int ips_eh_abort(struct scsi_cmnd *SC)
784{
785 ips_ha_t *ha;
786 ips_copp_wait_item_t *item;
787 int ret;
788 struct Scsi_Host *host;
789
790 METHOD_TRACE("ips_eh_abort", 1);
791
792 if (!SC)
793 return (FAILED);
794
795 host = SC->device->host;
796 ha = (ips_ha_t *) SC->device->host->hostdata;
797
798 if (!ha)
799 return (FAILED);
800
801 if (!ha->active)
802 return (FAILED);
803
804 spin_lock(host->host_lock);
805
806 /* See if the command is on the copp queue */
807 item = ha->copp_waitlist.head;
808 while ((item) && (item->scsi_cmd != SC))
809 item = item->next;
810
811 if (item) {
812 /* Found it */
813 ips_removeq_copp(&ha->copp_waitlist, item);
814 ret = (SUCCESS);
815
816 /* See if the command is on the wait queue */
817 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
818 /* command not sent yet */
819 ret = (SUCCESS);
820 } else {
821 /* command must have already been sent */
822 ret = (FAILED);
823 }
824
825 spin_unlock(host->host_lock);
826 return ret;
827}
828
829/****************************************************************************/
830/* */
831/* Routine Name: ips_eh_reset */
832/* */
833/* Routine Description: */
834/* */
835/* Reset the controller (with new eh error code) */
836/* */
837/* NOTE: this routine is called under the io_request_lock spinlock */
838/* */
839/****************************************************************************/
840static int __ips_eh_reset(struct scsi_cmnd *SC)
841{
842 int ret;
843 int i;
844 ips_ha_t *ha;
845 ips_scb_t *scb;
846 ips_copp_wait_item_t *item;
847
848 METHOD_TRACE("ips_eh_reset", 1);
849
850#ifdef NO_IPS_RESET
851 return (FAILED);
852#else
853
854 if (!SC) {
855 DEBUG(1, "Reset called with NULL scsi command");
856
857 return (FAILED);
858 }
859
860 ha = (ips_ha_t *) SC->device->host->hostdata;
861
862 if (!ha) {
863 DEBUG(1, "Reset called with NULL ha struct");
864
865 return (FAILED);
866 }
867
868 if (!ha->active)
869 return (FAILED);
870
871 /* See if the command is on the copp queue */
872 item = ha->copp_waitlist.head;
873 while ((item) && (item->scsi_cmd != SC))
874 item = item->next;
875
876 if (item) {
877 /* Found it */
878 ips_removeq_copp(&ha->copp_waitlist, item);
879 return (SUCCESS);
880 }
881
882 /* See if the command is on the wait queue */
883 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
884 /* command not sent yet */
885 return (SUCCESS);
886 }
887
888 /* An explanation for the casual observer: */
889 /* Part of the function of a RAID controller is automatic error */
890 /* detection and recovery. As such, the only problem that physically */
891 /* resetting an adapter will ever fix is when, for some reason, */
892 /* the driver is not successfully communicating with the adapter. */
893 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
894 /* then there's no real purpose in a physical reset. This will complete */
895 /* much faster and avoids any problems that might be caused by a */
896 /* physical reset ( such as having to fail all the outstanding I/O's ). */
897
898 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
899 scb = &ha->scbs[ha->max_cmds - 1];
900
901 ips_init_scb(ha, scb);
902
903 scb->timeout = ips_cmd_timeout;
904 scb->cdb[0] = IPS_CMD_FLUSH;
905
906 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
907 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
908 scb->cmd.flush_cache.state = IPS_NORM_STATE;
909 scb->cmd.flush_cache.reserved = 0;
910 scb->cmd.flush_cache.reserved2 = 0;
911 scb->cmd.flush_cache.reserved3 = 0;
912 scb->cmd.flush_cache.reserved4 = 0;
913
914 /* Attempt the flush command */
915 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
916 if (ret == IPS_SUCCESS) {
917 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
918 "Reset Request - Flushed Cache\n");
919 return (SUCCESS);
920 }
921 }
922
923 /* Either we can't communicate with the adapter or it's an IOCTL request */
924 /* from a utility. A physical reset is needed at this point. */
925
926 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
927
928 /*
929 * command must have already been sent
930 * reset the controller
931 */
932 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
933 ret = (*ha->func.reset) (ha);
934
935 if (!ret) {
936 struct scsi_cmnd *scsi_cmd;
937
938 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
939 "Controller reset failed - controller now offline.\n");
940
941 /* Now fail all of the active commands */
942 DEBUG_VAR(1, "(%s%d) Failing active commands",
943 ips_name, ha->host_num);
944
945 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
946 scb->scsi_cmd->result = DID_ERROR << 16;
947 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
948 ips_freescb(ha, scb);
949 }
950
951 /* Now fail all of the pending commands */
952 DEBUG_VAR(1, "(%s%d) Failing pending commands",
953 ips_name, ha->host_num);
954
955 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
956 scsi_cmd->result = DID_ERROR;
957 scsi_cmd->scsi_done(scsi_cmd);
958 }
959
960 ha->active = FALSE;
961 return (FAILED);
962 }
963
964 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
965 struct scsi_cmnd *scsi_cmd;
966
967 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
968 "Controller reset failed - controller now offline.\n");
969
970 /* Now fail all of the active commands */
971 DEBUG_VAR(1, "(%s%d) Failing active commands",
972 ips_name, ha->host_num);
973
974 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
975 scb->scsi_cmd->result = DID_ERROR << 16;
976 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
977 ips_freescb(ha, scb);
978 }
979
980 /* Now fail all of the pending commands */
981 DEBUG_VAR(1, "(%s%d) Failing pending commands",
982 ips_name, ha->host_num);
983
984 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
985 scsi_cmd->result = DID_ERROR << 16;
986 scsi_cmd->scsi_done(scsi_cmd);
987 }
988
989 ha->active = FALSE;
990 return (FAILED);
991 }
992
993 /* FFDC */
994 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
995 struct timeval tv;
996
997 do_gettimeofday(&tv);
998 ha->last_ffdc = tv.tv_sec;
999 ha->reset_count++;
1000 ips_ffdc_reset(ha, IPS_INTR_IORL);
1001 }
1002
1003 /* Now fail all of the active commands */
1004 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1005
1006 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1007 scb->scsi_cmd->result = DID_RESET << 16;
1008 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1009 ips_freescb(ha, scb);
1010 }
1011
1012 /* Reset DCDB active command bits */
1013 for (i = 1; i < ha->nbus; i++)
1014 ha->dcdb_active[i - 1] = 0;
1015
1016 /* Reset the number of active IOCTLs */
1017 ha->num_ioctl = 0;
1018
1019 ips_next(ha, IPS_INTR_IORL);
1020
1021 return (SUCCESS);
1022#endif /* NO_IPS_RESET */
1023
1024}
1025
1026static int ips_eh_reset(struct scsi_cmnd *SC)
1027{
1028 int rc;
1029
1030 spin_lock_irq(SC->device->host->host_lock);
1031 rc = __ips_eh_reset(SC);
1032 spin_unlock_irq(SC->device->host->host_lock);
1033
1034 return rc;
1035}
1036
1037/****************************************************************************/
1038/* */
1039/* Routine Name: ips_queue */
1040/* */
1041/* Routine Description: */
1042/* */
1043/* Send a command to the controller */
1044/* */
1045/* NOTE: */
1046/* Linux obtains io_request_lock before calling this function */
1047/* */
1048/****************************************************************************/
1049static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1050{
1051 ips_ha_t *ha;
1052 ips_passthru_t *pt;
1053
1054 METHOD_TRACE("ips_queue", 1);
1055
1056 ha = (ips_ha_t *) SC->device->host->hostdata;
1057
1058 if (!ha)
1059 return (1);
1060
1061 if (!ha->active)
1062 return (DID_ERROR);
1063
1064 if (ips_is_passthru(SC)) {
1065 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1066 SC->result = DID_BUS_BUSY << 16;
1067 done(SC);
1068
1069 return (0);
1070 }
1071 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1072 SC->result = DID_BUS_BUSY << 16;
1073 done(SC);
1074
1075 return (0);
1076 }
1077
1078 SC->scsi_done = done;
1079
1080 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1081 ips_name,
1082 ha->host_num,
1083 SC->cmnd[0],
1084 SC->device->channel, SC->device->id, SC->device->lun);
1085
1086 /* Check for command to initiator IDs */
1087 if ((scmd_channel(SC) > 0)
1088 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1089 SC->result = DID_NO_CONNECT << 16;
1090 done(SC);
1091
1092 return (0);
1093 }
1094
1095 if (ips_is_passthru(SC)) {
1096
1097 ips_copp_wait_item_t *scratch;
1098
1099 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1100 /* There can never be any system activity ( network or disk ), but check */
1101 /* anyway just as a good practice. */
1102 pt = (ips_passthru_t *) scsi_sglist(SC);
1103 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1104 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1105 if (ha->scb_activelist.count != 0) {
1106 SC->result = DID_BUS_BUSY << 16;
1107 done(SC);
1108 return (0);
1109 }
1110 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1111 __ips_eh_reset(SC);
1112 SC->result = DID_OK << 16;
1113 SC->scsi_done(SC);
1114 return (0);
1115 }
1116
1117 /* allocate space for the scribble */
1118 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1119
1120 if (!scratch) {
1121 SC->result = DID_ERROR << 16;
1122 done(SC);
1123
1124 return (0);
1125 }
1126
1127 scratch->scsi_cmd = SC;
1128 scratch->next = NULL;
1129
1130 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1131 } else {
1132 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1133 }
1134
1135 ips_next(ha, IPS_INTR_IORL);
1136
1137 return (0);
1138}
1139
1140static DEF_SCSI_QCMD(ips_queue)
1141
1142/****************************************************************************/
1143/* */
1144/* Routine Name: ips_biosparam */
1145/* */
1146/* Routine Description: */
1147/* */
1148/* Set bios geometry for the controller */
1149/* */
1150/****************************************************************************/
1151static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1152 sector_t capacity, int geom[])
1153{
1154 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1155 int heads;
1156 int sectors;
1157 int cylinders;
1158
1159 METHOD_TRACE("ips_biosparam", 1);
1160
1161 if (!ha)
1162 /* ?!?! host adater info invalid */
1163 return (0);
1164
1165 if (!ha->active)
1166 return (0);
1167
1168 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1169 /* ?!?! Enquiry command failed */
1170 return (0);
1171
1172 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1173 heads = IPS_NORM_HEADS;
1174 sectors = IPS_NORM_SECTORS;
1175 } else {
1176 heads = IPS_COMP_HEADS;
1177 sectors = IPS_COMP_SECTORS;
1178 }
1179
1180 cylinders = (unsigned long) capacity / (heads * sectors);
1181
1182 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1183 heads, sectors, cylinders);
1184
1185 geom[0] = heads;
1186 geom[1] = sectors;
1187 geom[2] = cylinders;
1188
1189 return (0);
1190}
1191
1192/****************************************************************************/
1193/* */
1194/* Routine Name: ips_slave_configure */
1195/* */
1196/* Routine Description: */
1197/* */
1198/* Set queue depths on devices once scan is complete */
1199/* */
1200/****************************************************************************/
1201static int
1202ips_slave_configure(struct scsi_device * SDptr)
1203{
1204 ips_ha_t *ha;
1205 int min;
1206
1207 ha = IPS_HA(SDptr->host);
1208 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1209 min = ha->max_cmds / 2;
1210 if (ha->enq->ucLogDriveCount <= 2)
1211 min = ha->max_cmds - 1;
1212 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1213 }
1214
1215 SDptr->skip_ms_page_8 = 1;
1216 SDptr->skip_ms_page_3f = 1;
1217 return 0;
1218}
1219
1220/****************************************************************************/
1221/* */
1222/* Routine Name: do_ipsintr */
1223/* */
1224/* Routine Description: */
1225/* */
1226/* Wrapper for the interrupt handler */
1227/* */
1228/****************************************************************************/
1229static irqreturn_t
1230do_ipsintr(int irq, void *dev_id)
1231{
1232 ips_ha_t *ha;
1233 struct Scsi_Host *host;
1234 int irqstatus;
1235
1236 METHOD_TRACE("do_ipsintr", 2);
1237
1238 ha = (ips_ha_t *) dev_id;
1239 if (!ha)
1240 return IRQ_NONE;
1241 host = ips_sh[ha->host_num];
1242 /* interrupt during initialization */
1243 if (!host) {
1244 (*ha->func.intr) (ha);
1245 return IRQ_HANDLED;
1246 }
1247
1248 spin_lock(host->host_lock);
1249
1250 if (!ha->active) {
1251 spin_unlock(host->host_lock);
1252 return IRQ_HANDLED;
1253 }
1254
1255 irqstatus = (*ha->func.intr) (ha);
1256
1257 spin_unlock(host->host_lock);
1258
1259 /* start the next command */
1260 ips_next(ha, IPS_INTR_ON);
1261 return IRQ_RETVAL(irqstatus);
1262}
1263
1264/****************************************************************************/
1265/* */
1266/* Routine Name: ips_intr_copperhead */
1267/* */
1268/* Routine Description: */
1269/* */
1270/* Polling interrupt handler */
1271/* */
1272/* ASSUMES interrupts are disabled */
1273/* */
1274/****************************************************************************/
1275int
1276ips_intr_copperhead(ips_ha_t * ha)
1277{
1278 ips_stat_t *sp;
1279 ips_scb_t *scb;
1280 IPS_STATUS cstatus;
1281 int intrstatus;
1282
1283 METHOD_TRACE("ips_intr", 2);
1284
1285 if (!ha)
1286 return 0;
1287
1288 if (!ha->active)
1289 return 0;
1290
1291 intrstatus = (*ha->func.isintr) (ha);
1292
1293 if (!intrstatus) {
1294 /*
1295 * Unexpected/Shared interrupt
1296 */
1297
1298 return 0;
1299 }
1300
1301 while (TRUE) {
1302 sp = &ha->sp;
1303
1304 intrstatus = (*ha->func.isintr) (ha);
1305
1306 if (!intrstatus)
1307 break;
1308 else
1309 cstatus.value = (*ha->func.statupd) (ha);
1310
1311 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1312 /* Spurious Interrupt ? */
1313 continue;
1314 }
1315
1316 ips_chkstatus(ha, &cstatus);
1317 scb = (ips_scb_t *) sp->scb_addr;
1318
1319 /*
1320 * use the callback function to finish things up
1321 * NOTE: interrupts are OFF for this
1322 */
1323 (*scb->callback) (ha, scb);
1324 } /* end while */
1325 return 1;
1326}
1327
1328/****************************************************************************/
1329/* */
1330/* Routine Name: ips_intr_morpheus */
1331/* */
1332/* Routine Description: */
1333/* */
1334/* Polling interrupt handler */
1335/* */
1336/* ASSUMES interrupts are disabled */
1337/* */
1338/****************************************************************************/
1339int
1340ips_intr_morpheus(ips_ha_t * ha)
1341{
1342 ips_stat_t *sp;
1343 ips_scb_t *scb;
1344 IPS_STATUS cstatus;
1345 int intrstatus;
1346
1347 METHOD_TRACE("ips_intr_morpheus", 2);
1348
1349 if (!ha)
1350 return 0;
1351
1352 if (!ha->active)
1353 return 0;
1354
1355 intrstatus = (*ha->func.isintr) (ha);
1356
1357 if (!intrstatus) {
1358 /*
1359 * Unexpected/Shared interrupt
1360 */
1361
1362 return 0;
1363 }
1364
1365 while (TRUE) {
1366 sp = &ha->sp;
1367
1368 intrstatus = (*ha->func.isintr) (ha);
1369
1370 if (!intrstatus)
1371 break;
1372 else
1373 cstatus.value = (*ha->func.statupd) (ha);
1374
1375 if (cstatus.value == 0xffffffff)
1376 /* No more to process */
1377 break;
1378
1379 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1380 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1381 "Spurious interrupt; no ccb.\n");
1382
1383 continue;
1384 }
1385
1386 ips_chkstatus(ha, &cstatus);
1387 scb = (ips_scb_t *) sp->scb_addr;
1388
1389 /*
1390 * use the callback function to finish things up
1391 * NOTE: interrupts are OFF for this
1392 */
1393 (*scb->callback) (ha, scb);
1394 } /* end while */
1395 return 1;
1396}
1397
1398/****************************************************************************/
1399/* */
1400/* Routine Name: ips_info */
1401/* */
1402/* Routine Description: */
1403/* */
1404/* Return info about the driver */
1405/* */
1406/****************************************************************************/
1407static const char *
1408ips_info(struct Scsi_Host *SH)
1409{
1410 static char buffer[256];
1411 char *bp;
1412 ips_ha_t *ha;
1413
1414 METHOD_TRACE("ips_info", 1);
1415
1416 ha = IPS_HA(SH);
1417
1418 if (!ha)
1419 return (NULL);
1420
1421 bp = &buffer[0];
1422 memset(bp, 0, sizeof (buffer));
1423
1424 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1425 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1426
1427 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1428 strcat(bp, " <");
1429 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1430 strcat(bp, ">");
1431 }
1432
1433 return (bp);
1434}
1435
1436/****************************************************************************/
1437/* */
1438/* Routine Name: ips_proc_info */
1439/* */
1440/* Routine Description: */
1441/* */
1442/* The passthru interface for the driver */
1443/* */
1444/****************************************************************************/
1445static int
1446ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1447 int length, int func)
1448{
1449 int i;
1450 int ret;
1451 ips_ha_t *ha = NULL;
1452
1453 METHOD_TRACE("ips_proc_info", 1);
1454
1455 /* Find our host structure */
1456 for (i = 0; i < ips_next_controller; i++) {
1457 if (ips_sh[i]) {
1458 if (ips_sh[i] == host) {
1459 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1460 break;
1461 }
1462 }
1463 }
1464
1465 if (!ha)
1466 return (-EINVAL);
1467
1468 if (func) {
1469 /* write */
1470 return (0);
1471 } else {
1472 /* read */
1473 if (start)
1474 *start = buffer;
1475
1476 ret = ips_host_info(ha, buffer, offset, length);
1477
1478 return (ret);
1479 }
1480}
1481
1482/*--------------------------------------------------------------------------*/
1483/* Helper Functions */
1484/*--------------------------------------------------------------------------*/
1485
1486/****************************************************************************/
1487/* */
1488/* Routine Name: ips_is_passthru */
1489/* */
1490/* Routine Description: */
1491/* */
1492/* Determine if the specified SCSI command is really a passthru command */
1493/* */
1494/****************************************************************************/
1495static int ips_is_passthru(struct scsi_cmnd *SC)
1496{
1497 unsigned long flags;
1498
1499 METHOD_TRACE("ips_is_passthru", 1);
1500
1501 if (!SC)
1502 return (0);
1503
1504 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1505 (SC->device->channel == 0) &&
1506 (SC->device->id == IPS_ADAPTER_ID) &&
1507 (SC->device->lun == 0) && scsi_sglist(SC)) {
1508 struct scatterlist *sg = scsi_sglist(SC);
1509 char *buffer;
1510
1511 /* kmap_atomic() ensures addressability of the user buffer.*/
1512 /* local_irq_save() protects the KM_IRQ0 address slot. */
1513 local_irq_save(flags);
1514 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
1515 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1516 buffer[2] == 'P' && buffer[3] == 'P') {
1517 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1518 local_irq_restore(flags);
1519 return 1;
1520 }
1521 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1522 local_irq_restore(flags);
1523 }
1524 return 0;
1525}
1526
1527/****************************************************************************/
1528/* */
1529/* Routine Name: ips_alloc_passthru_buffer */
1530/* */
1531/* Routine Description: */
1532/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1533/* is too small or doesn't exist */
1534/****************************************************************************/
1535static int
1536ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1537{
1538 void *bigger_buf;
1539 dma_addr_t dma_busaddr;
1540
1541 if (ha->ioctl_data && length <= ha->ioctl_len)
1542 return 0;
1543 /* there is no buffer or it's not big enough, allocate a new one */
1544 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1545 if (bigger_buf) {
1546 /* free the old memory */
1547 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1548 ha->ioctl_busaddr);
1549 /* use the new memory */
1550 ha->ioctl_data = (char *) bigger_buf;
1551 ha->ioctl_len = length;
1552 ha->ioctl_busaddr = dma_busaddr;
1553 } else {
1554 return -1;
1555 }
1556 return 0;
1557}
1558
1559/****************************************************************************/
1560/* */
1561/* Routine Name: ips_make_passthru */
1562/* */
1563/* Routine Description: */
1564/* */
1565/* Make a passthru command out of the info in the Scsi block */
1566/* */
1567/****************************************************************************/
1568static int
1569ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1570{
1571 ips_passthru_t *pt;
1572 int length = 0;
1573 int i, ret;
1574 struct scatterlist *sg = scsi_sglist(SC);
1575
1576 METHOD_TRACE("ips_make_passthru", 1);
1577
1578 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1579 length += sg->length;
1580
1581 if (length < sizeof (ips_passthru_t)) {
1582 /* wrong size */
1583 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1584 ips_name, ha->host_num);
1585 return (IPS_FAILURE);
1586 }
1587 if (ips_alloc_passthru_buffer(ha, length)) {
1588 /* allocation failure! If ha->ioctl_data exists, use it to return
1589 some error codes. Return a failed command to the scsi layer. */
1590 if (ha->ioctl_data) {
1591 pt = (ips_passthru_t *) ha->ioctl_data;
1592 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1593 pt->BasicStatus = 0x0B;
1594 pt->ExtendedStatus = 0x00;
1595 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1596 }
1597 return IPS_FAILURE;
1598 }
1599 ha->ioctl_datasize = length;
1600
1601 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1602 pt = (ips_passthru_t *) ha->ioctl_data;
1603
1604 /*
1605 * Some notes about the passthru interface used
1606 *
1607 * IF the scsi op_code == 0x0d then we assume
1608 * that the data came along with/goes with the
1609 * packet we received from the sg driver. In this
1610 * case the CmdBSize field of the pt structure is
1611 * used for the size of the buffer.
1612 */
1613
1614 switch (pt->CoppCmd) {
1615 case IPS_NUMCTRLS:
1616 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1617 &ips_num_controllers, sizeof (int));
1618 ips_scmd_buf_write(SC, ha->ioctl_data,
1619 sizeof (ips_passthru_t) + sizeof (int));
1620 SC->result = DID_OK << 16;
1621
1622 return (IPS_SUCCESS_IMM);
1623
1624 case IPS_COPPUSRCMD:
1625 case IPS_COPPIOCCMD:
1626 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1627 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1628 /* wrong size */
1629 DEBUG_VAR(1,
1630 "(%s%d) Passthru structure wrong size",
1631 ips_name, ha->host_num);
1632
1633 return (IPS_FAILURE);
1634 }
1635
1636 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1637 pt->CoppCP.cmd.flashfw.op_code ==
1638 IPS_CMD_RW_BIOSFW) {
1639 ret = ips_flash_copperhead(ha, pt, scb);
1640 ips_scmd_buf_write(SC, ha->ioctl_data,
1641 sizeof (ips_passthru_t));
1642 return ret;
1643 }
1644 if (ips_usrcmd(ha, pt, scb))
1645 return (IPS_SUCCESS);
1646 else
1647 return (IPS_FAILURE);
1648 }
1649
1650 break;
1651
1652 } /* end switch */
1653
1654 return (IPS_FAILURE);
1655}
1656
1657/****************************************************************************/
1658/* Routine Name: ips_flash_copperhead */
1659/* Routine Description: */
1660/* Flash the BIOS/FW on a Copperhead style controller */
1661/****************************************************************************/
1662static int
1663ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1664{
1665 int datasize;
1666
1667 /* Trombone is the only copperhead that can do packet flash, but only
1668 * for firmware. No one said it had to make sense. */
1669 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1670 if (ips_usrcmd(ha, pt, scb))
1671 return IPS_SUCCESS;
1672 else
1673 return IPS_FAILURE;
1674 }
1675 pt->BasicStatus = 0x0B;
1676 pt->ExtendedStatus = 0;
1677 scb->scsi_cmd->result = DID_OK << 16;
1678 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1679 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1680 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1681 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1682 pt->BasicStatus = 0;
1683 return ips_flash_bios(ha, pt, scb);
1684 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1685 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1686 ha->flash_data = ips_FlashData;
1687 ha->flash_busaddr = ips_flashbusaddr;
1688 ha->flash_len = PAGE_SIZE << 7;
1689 ha->flash_datasize = 0;
1690 } else if (!ha->flash_data) {
1691 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1692 pt->CoppCP.cmd.flashfw.count;
1693 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1694 datasize,
1695 &ha->flash_busaddr);
1696 if (!ha->flash_data){
1697 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1698 return IPS_FAILURE;
1699 }
1700 ha->flash_datasize = 0;
1701 ha->flash_len = datasize;
1702 } else
1703 return IPS_FAILURE;
1704 } else {
1705 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1706 ha->flash_len) {
1707 ips_free_flash_copperhead(ha);
1708 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1709 "failed size sanity check\n");
1710 return IPS_FAILURE;
1711 }
1712 }
1713 if (!ha->flash_data)
1714 return IPS_FAILURE;
1715 pt->BasicStatus = 0;
1716 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1717 pt->CoppCP.cmd.flashfw.count);
1718 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1719 if (pt->CoppCP.cmd.flashfw.packet_num ==
1720 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1721 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1722 return ips_flash_bios(ha, pt, scb);
1723 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1724 return ips_flash_firmware(ha, pt, scb);
1725 }
1726 return IPS_SUCCESS_IMM;
1727}
1728
1729/****************************************************************************/
1730/* Routine Name: ips_flash_bios */
1731/* Routine Description: */
1732/* flashes the bios of a copperhead adapter */
1733/****************************************************************************/
1734static int
1735ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1736{
1737
1738 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1739 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1740 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1741 (!ha->func.verifybios))
1742 goto error;
1743 if ((*ha->func.erasebios) (ha)) {
1744 DEBUG_VAR(1,
1745 "(%s%d) flash bios failed - unable to erase flash",
1746 ips_name, ha->host_num);
1747 goto error;
1748 } else
1749 if ((*ha->func.programbios) (ha,
1750 ha->flash_data +
1751 IPS_BIOS_HEADER,
1752 ha->flash_datasize -
1753 IPS_BIOS_HEADER, 0)) {
1754 DEBUG_VAR(1,
1755 "(%s%d) flash bios failed - unable to flash",
1756 ips_name, ha->host_num);
1757 goto error;
1758 } else
1759 if ((*ha->func.verifybios) (ha,
1760 ha->flash_data +
1761 IPS_BIOS_HEADER,
1762 ha->flash_datasize -
1763 IPS_BIOS_HEADER, 0)) {
1764 DEBUG_VAR(1,
1765 "(%s%d) flash bios failed - unable to verify flash",
1766 ips_name, ha->host_num);
1767 goto error;
1768 }
1769 ips_free_flash_copperhead(ha);
1770 return IPS_SUCCESS_IMM;
1771 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1772 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1773 if (!ha->func.erasebios)
1774 goto error;
1775 if ((*ha->func.erasebios) (ha)) {
1776 DEBUG_VAR(1,
1777 "(%s%d) flash bios failed - unable to erase flash",
1778 ips_name, ha->host_num);
1779 goto error;
1780 }
1781 return IPS_SUCCESS_IMM;
1782 }
1783 error:
1784 pt->BasicStatus = 0x0B;
1785 pt->ExtendedStatus = 0x00;
1786 ips_free_flash_copperhead(ha);
1787 return IPS_FAILURE;
1788}
1789
1790/****************************************************************************/
1791/* */
1792/* Routine Name: ips_fill_scb_sg_single */
1793/* */
1794/* Routine Description: */
1795/* Fill in a single scb sg_list element from an address */
1796/* return a -1 if a breakup occurred */
1797/****************************************************************************/
1798static int
1799ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1800 ips_scb_t * scb, int indx, unsigned int e_len)
1801{
1802
1803 int ret_val = 0;
1804
1805 if ((scb->data_len + e_len) > ha->max_xfer) {
1806 e_len = ha->max_xfer - scb->data_len;
1807 scb->breakup = indx;
1808 ++scb->sg_break;
1809 ret_val = -1;
1810 } else {
1811 scb->breakup = 0;
1812 scb->sg_break = 0;
1813 }
1814 if (IPS_USE_ENH_SGLIST(ha)) {
1815 scb->sg_list.enh_list[indx].address_lo =
1816 cpu_to_le32(pci_dma_lo32(busaddr));
1817 scb->sg_list.enh_list[indx].address_hi =
1818 cpu_to_le32(pci_dma_hi32(busaddr));
1819 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1820 } else {
1821 scb->sg_list.std_list[indx].address =
1822 cpu_to_le32(pci_dma_lo32(busaddr));
1823 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1824 }
1825
1826 ++scb->sg_len;
1827 scb->data_len += e_len;
1828 return ret_val;
1829}
1830
1831/****************************************************************************/
1832/* Routine Name: ips_flash_firmware */
1833/* Routine Description: */
1834/* flashes the firmware of a copperhead adapter */
1835/****************************************************************************/
1836static int
1837ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1838{
1839 IPS_SG_LIST sg_list;
1840 uint32_t cmd_busaddr;
1841
1842 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1843 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1844 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1845 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1846 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1847 } else {
1848 pt->BasicStatus = 0x0B;
1849 pt->ExtendedStatus = 0x00;
1850 ips_free_flash_copperhead(ha);
1851 return IPS_FAILURE;
1852 }
1853 /* Save the S/G list pointer so it doesn't get clobbered */
1854 sg_list.list = scb->sg_list.list;
1855 cmd_busaddr = scb->scb_busaddr;
1856 /* copy in the CP */
1857 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1858 /* FIX stuff that might be wrong */
1859 scb->sg_list.list = sg_list.list;
1860 scb->scb_busaddr = cmd_busaddr;
1861 scb->bus = scb->scsi_cmd->device->channel;
1862 scb->target_id = scb->scsi_cmd->device->id;
1863 scb->lun = scb->scsi_cmd->device->lun;
1864 scb->sg_len = 0;
1865 scb->data_len = 0;
1866 scb->flags = 0;
1867 scb->op_code = 0;
1868 scb->callback = ipsintr_done;
1869 scb->timeout = ips_cmd_timeout;
1870
1871 scb->data_len = ha->flash_datasize;
1872 scb->data_busaddr =
1873 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1874 IPS_DMA_DIR(scb));
1875 scb->flags |= IPS_SCB_MAP_SINGLE;
1876 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1877 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1878 if (pt->TimeOut)
1879 scb->timeout = pt->TimeOut;
1880 scb->scsi_cmd->result = DID_OK << 16;
1881 return IPS_SUCCESS;
1882}
1883
1884/****************************************************************************/
1885/* Routine Name: ips_free_flash_copperhead */
1886/* Routine Description: */
1887/* release the memory resources used to hold the flash image */
1888/****************************************************************************/
1889static void
1890ips_free_flash_copperhead(ips_ha_t * ha)
1891{
1892 if (ha->flash_data == ips_FlashData)
1893 test_and_clear_bit(0, &ips_FlashDataInUse);
1894 else if (ha->flash_data)
1895 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1896 ha->flash_busaddr);
1897 ha->flash_data = NULL;
1898}
1899
1900/****************************************************************************/
1901/* */
1902/* Routine Name: ips_usrcmd */
1903/* */
1904/* Routine Description: */
1905/* */
1906/* Process a user command and make it ready to send */
1907/* */
1908/****************************************************************************/
1909static int
1910ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1911{
1912 IPS_SG_LIST sg_list;
1913 uint32_t cmd_busaddr;
1914
1915 METHOD_TRACE("ips_usrcmd", 1);
1916
1917 if ((!scb) || (!pt) || (!ha))
1918 return (0);
1919
1920 /* Save the S/G list pointer so it doesn't get clobbered */
1921 sg_list.list = scb->sg_list.list;
1922 cmd_busaddr = scb->scb_busaddr;
1923 /* copy in the CP */
1924 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1925 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1926
1927 /* FIX stuff that might be wrong */
1928 scb->sg_list.list = sg_list.list;
1929 scb->scb_busaddr = cmd_busaddr;
1930 scb->bus = scb->scsi_cmd->device->channel;
1931 scb->target_id = scb->scsi_cmd->device->id;
1932 scb->lun = scb->scsi_cmd->device->lun;
1933 scb->sg_len = 0;
1934 scb->data_len = 0;
1935 scb->flags = 0;
1936 scb->op_code = 0;
1937 scb->callback = ipsintr_done;
1938 scb->timeout = ips_cmd_timeout;
1939 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1940
1941 /* we don't support DCDB/READ/WRITE Scatter Gather */
1942 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1943 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1944 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1945 return (0);
1946
1947 if (pt->CmdBSize) {
1948 scb->data_len = pt->CmdBSize;
1949 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1950 } else {
1951 scb->data_busaddr = 0L;
1952 }
1953
1954 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1955 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1956 (unsigned long) &scb->
1957 dcdb -
1958 (unsigned long) scb);
1959
1960 if (pt->CmdBSize) {
1961 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1962 scb->dcdb.buffer_pointer =
1963 cpu_to_le32(scb->data_busaddr);
1964 else
1965 scb->cmd.basic_io.sg_addr =
1966 cpu_to_le32(scb->data_busaddr);
1967 }
1968
1969 /* set timeouts */
1970 if (pt->TimeOut) {
1971 scb->timeout = pt->TimeOut;
1972
1973 if (pt->TimeOut <= 10)
1974 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1975 else if (pt->TimeOut <= 60)
1976 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1977 else
1978 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1979 }
1980
1981 /* assume success */
1982 scb->scsi_cmd->result = DID_OK << 16;
1983
1984 /* success */
1985 return (1);
1986}
1987
1988/****************************************************************************/
1989/* */
1990/* Routine Name: ips_cleanup_passthru */
1991/* */
1992/* Routine Description: */
1993/* */
1994/* Cleanup after a passthru command */
1995/* */
1996/****************************************************************************/
1997static void
1998ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1999{
2000 ips_passthru_t *pt;
2001
2002 METHOD_TRACE("ips_cleanup_passthru", 1);
2003
2004 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
2005 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2006 ips_name, ha->host_num);
2007
2008 return;
2009 }
2010 pt = (ips_passthru_t *) ha->ioctl_data;
2011
2012 /* Copy data back to the user */
2013 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2014 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2015
2016 pt->BasicStatus = scb->basic_status;
2017 pt->ExtendedStatus = scb->extended_status;
2018 pt->AdapterType = ha->ad_type;
2019
2020 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2021 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2022 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2023 ips_free_flash_copperhead(ha);
2024
2025 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2026}
2027
2028/****************************************************************************/
2029/* */
2030/* Routine Name: ips_host_info */
2031/* */
2032/* Routine Description: */
2033/* */
2034/* The passthru interface for the driver */
2035/* */
2036/****************************************************************************/
2037static int
2038ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2039{
2040 IPS_INFOSTR info;
2041
2042 METHOD_TRACE("ips_host_info", 1);
2043
2044 info.buffer = ptr;
2045 info.length = len;
2046 info.offset = offset;
2047 info.pos = 0;
2048 info.localpos = 0;
2049
2050 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2051
2052 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2053 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2054 copy_info(&info, "\tController Type : %s\n",
2055 ips_adapter_name[ha->ad_type - 1]);
2056 else
2057 copy_info(&info,
2058 "\tController Type : Unknown\n");
2059
2060 if (ha->io_addr)
2061 copy_info(&info,
2062 "\tIO region : 0x%lx (%d bytes)\n",
2063 ha->io_addr, ha->io_len);
2064
2065 if (ha->mem_addr) {
2066 copy_info(&info,
2067 "\tMemory region : 0x%lx (%d bytes)\n",
2068 ha->mem_addr, ha->mem_len);
2069 copy_info(&info,
2070 "\tShared memory address : 0x%lx\n",
2071 ha->mem_ptr);
2072 }
2073
2074 copy_info(&info, "\tIRQ number : %d\n", ha->pcidev->irq);
2075
2076 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2077 /* That keeps everything happy for "text" operations on the proc file. */
2078
2079 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2080 if (ha->nvram->bios_low[3] == 0) {
2081 copy_info(&info,
2082 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2083 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2084 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2085 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2086 ha->nvram->bios_low[2]);
2087
2088 } else {
2089 copy_info(&info,
2090 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2091 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2092 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2093 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2094 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2095 }
2096
2097 }
2098
2099 if (ha->enq->CodeBlkVersion[7] == 0) {
2100 copy_info(&info,
2101 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2102 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2103 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2104 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2105 ha->enq->CodeBlkVersion[6]);
2106 } else {
2107 copy_info(&info,
2108 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2109 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2110 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2111 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2112 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2113 }
2114
2115 if (ha->enq->BootBlkVersion[7] == 0) {
2116 copy_info(&info,
2117 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2118 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2119 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2120 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2121 ha->enq->BootBlkVersion[6]);
2122 } else {
2123 copy_info(&info,
2124 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2125 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2126 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2127 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2128 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2129 }
2130
2131 copy_info(&info, "\tDriver Version : %s%s\n",
2132 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2133
2134 copy_info(&info, "\tDriver Build : %d\n",
2135 IPS_BUILD_IDENT);
2136
2137 copy_info(&info, "\tMax Physical Devices : %d\n",
2138 ha->enq->ucMaxPhysicalDevices);
2139 copy_info(&info, "\tMax Active Commands : %d\n",
2140 ha->max_cmds);
2141 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2142 ha->scb_waitlist.count);
2143 copy_info(&info, "\tCurrent Active Commands : %d\n",
2144 ha->scb_activelist.count - ha->num_ioctl);
2145 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2146 ha->copp_waitlist.count);
2147 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2148 ha->num_ioctl);
2149
2150 copy_info(&info, "\n");
2151
2152 return (info.localpos);
2153}
2154
2155/****************************************************************************/
2156/* */
2157/* Routine Name: copy_mem_info */
2158/* */
2159/* Routine Description: */
2160/* */
2161/* Copy data into an IPS_INFOSTR structure */
2162/* */
2163/****************************************************************************/
2164static void
2165copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2166{
2167 METHOD_TRACE("copy_mem_info", 1);
2168
2169 if (info->pos + len < info->offset) {
2170 info->pos += len;
2171 return;
2172 }
2173
2174 if (info->pos < info->offset) {
2175 data += (info->offset - info->pos);
2176 len -= (info->offset - info->pos);
2177 info->pos += (info->offset - info->pos);
2178 }
2179
2180 if (info->localpos + len > info->length)
2181 len = info->length - info->localpos;
2182
2183 if (len > 0) {
2184 memcpy(info->buffer + info->localpos, data, len);
2185 info->pos += len;
2186 info->localpos += len;
2187 }
2188}
2189
2190/****************************************************************************/
2191/* */
2192/* Routine Name: copy_info */
2193/* */
2194/* Routine Description: */
2195/* */
2196/* printf style wrapper for an info structure */
2197/* */
2198/****************************************************************************/
2199static int
2200copy_info(IPS_INFOSTR * info, char *fmt, ...)
2201{
2202 va_list args;
2203 char buf[128];
2204 int len;
2205
2206 METHOD_TRACE("copy_info", 1);
2207
2208 va_start(args, fmt);
2209 len = vsprintf(buf, fmt, args);
2210 va_end(args);
2211
2212 copy_mem_info(info, buf, len);
2213
2214 return (len);
2215}
2216
2217/****************************************************************************/
2218/* */
2219/* Routine Name: ips_identify_controller */
2220/* */
2221/* Routine Description: */
2222/* */
2223/* Identify this controller */
2224/* */
2225/****************************************************************************/
2226static void
2227ips_identify_controller(ips_ha_t * ha)
2228{
2229 METHOD_TRACE("ips_identify_controller", 1);
2230
2231 switch (ha->pcidev->device) {
2232 case IPS_DEVICEID_COPPERHEAD:
2233 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2234 ha->ad_type = IPS_ADTYPE_SERVERAID;
2235 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2236 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2237 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2238 ha->ad_type = IPS_ADTYPE_NAVAJO;
2239 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2240 && (ha->slot_num == 0)) {
2241 ha->ad_type = IPS_ADTYPE_KIOWA;
2242 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2243 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2244 if (ha->enq->ucMaxPhysicalDevices == 15)
2245 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2246 else
2247 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2248 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2249 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2250 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2251 }
2252 break;
2253
2254 case IPS_DEVICEID_MORPHEUS:
2255 switch (ha->pcidev->subsystem_device) {
2256 case IPS_SUBDEVICEID_4L:
2257 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2258 break;
2259
2260 case IPS_SUBDEVICEID_4M:
2261 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2262 break;
2263
2264 case IPS_SUBDEVICEID_4MX:
2265 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2266 break;
2267
2268 case IPS_SUBDEVICEID_4LX:
2269 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2270 break;
2271
2272 case IPS_SUBDEVICEID_5I2:
2273 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2274 break;
2275
2276 case IPS_SUBDEVICEID_5I1:
2277 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2278 break;
2279 }
2280
2281 break;
2282
2283 case IPS_DEVICEID_MARCO:
2284 switch (ha->pcidev->subsystem_device) {
2285 case IPS_SUBDEVICEID_6M:
2286 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2287 break;
2288 case IPS_SUBDEVICEID_6I:
2289 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2290 break;
2291 case IPS_SUBDEVICEID_7k:
2292 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2293 break;
2294 case IPS_SUBDEVICEID_7M:
2295 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2296 break;
2297 }
2298 break;
2299 }
2300}
2301
2302/****************************************************************************/
2303/* */
2304/* Routine Name: ips_get_bios_version */
2305/* */
2306/* Routine Description: */
2307/* */
2308/* Get the BIOS revision number */
2309/* */
2310/****************************************************************************/
2311static void
2312ips_get_bios_version(ips_ha_t * ha, int intr)
2313{
2314 ips_scb_t *scb;
2315 int ret;
2316 uint8_t major;
2317 uint8_t minor;
2318 uint8_t subminor;
2319 uint8_t *buffer;
2320 char hexDigits[] =
2321 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2322 'D', 'E', 'F' };
2323
2324 METHOD_TRACE("ips_get_bios_version", 1);
2325
2326 major = 0;
2327 minor = 0;
2328
2329 strncpy(ha->bios_version, " ?", 8);
2330
2331 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2332 if (IPS_USE_MEMIO(ha)) {
2333 /* Memory Mapped I/O */
2334
2335 /* test 1st byte */
2336 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2337 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2338 udelay(25); /* 25 us */
2339
2340 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2341 return;
2342
2343 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2344 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2345 udelay(25); /* 25 us */
2346
2347 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2348 return;
2349
2350 /* Get Major version */
2351 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2352 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2353 udelay(25); /* 25 us */
2354
2355 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2356
2357 /* Get Minor version */
2358 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2360 udelay(25); /* 25 us */
2361 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2362
2363 /* Get SubMinor version */
2364 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2365 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2366 udelay(25); /* 25 us */
2367 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2368
2369 } else {
2370 /* Programmed I/O */
2371
2372 /* test 1st byte */
2373 outl(0, ha->io_addr + IPS_REG_FLAP);
2374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2375 udelay(25); /* 25 us */
2376
2377 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2378 return;
2379
2380 outl(1, ha->io_addr + IPS_REG_FLAP);
2381 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2382 udelay(25); /* 25 us */
2383
2384 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2385 return;
2386
2387 /* Get Major version */
2388 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2389 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2390 udelay(25); /* 25 us */
2391
2392 major = inb(ha->io_addr + IPS_REG_FLDP);
2393
2394 /* Get Minor version */
2395 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2396 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2397 udelay(25); /* 25 us */
2398
2399 minor = inb(ha->io_addr + IPS_REG_FLDP);
2400
2401 /* Get SubMinor version */
2402 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2404 udelay(25); /* 25 us */
2405
2406 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2407
2408 }
2409 } else {
2410 /* Morpheus Family - Send Command to the card */
2411
2412 buffer = ha->ioctl_data;
2413
2414 memset(buffer, 0, 0x1000);
2415
2416 scb = &ha->scbs[ha->max_cmds - 1];
2417
2418 ips_init_scb(ha, scb);
2419
2420 scb->timeout = ips_cmd_timeout;
2421 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2422
2423 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2424 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2425 scb->cmd.flashfw.type = 1;
2426 scb->cmd.flashfw.direction = 0;
2427 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2428 scb->cmd.flashfw.total_packets = 1;
2429 scb->cmd.flashfw.packet_num = 0;
2430 scb->data_len = 0x1000;
2431 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2432
2433 /* issue the command */
2434 if (((ret =
2435 ips_send_wait(ha, scb, ips_cmd_timeout,
2436 intr)) == IPS_FAILURE)
2437 || (ret == IPS_SUCCESS_IMM)
2438 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2439 /* Error occurred */
2440
2441 return;
2442 }
2443
2444 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2445 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2446 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2447 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2448 } else {
2449 return;
2450 }
2451 }
2452
2453 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2454 ha->bios_version[1] = '.';
2455 ha->bios_version[2] = hexDigits[major & 0x0F];
2456 ha->bios_version[3] = hexDigits[subminor];
2457 ha->bios_version[4] = '.';
2458 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2459 ha->bios_version[6] = hexDigits[minor & 0x0F];
2460 ha->bios_version[7] = 0;
2461}
2462
2463/****************************************************************************/
2464/* */
2465/* Routine Name: ips_hainit */
2466/* */
2467/* Routine Description: */
2468/* */
2469/* Initialize the controller */
2470/* */
2471/* NOTE: Assumes to be called from with a lock */
2472/* */
2473/****************************************************************************/
2474static int
2475ips_hainit(ips_ha_t * ha)
2476{
2477 int i;
2478 struct timeval tv;
2479
2480 METHOD_TRACE("ips_hainit", 1);
2481
2482 if (!ha)
2483 return (0);
2484
2485 if (ha->func.statinit)
2486 (*ha->func.statinit) (ha);
2487
2488 if (ha->func.enableint)
2489 (*ha->func.enableint) (ha);
2490
2491 /* Send FFDC */
2492 ha->reset_count = 1;
2493 do_gettimeofday(&tv);
2494 ha->last_ffdc = tv.tv_sec;
2495 ips_ffdc_reset(ha, IPS_INTR_IORL);
2496
2497 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2498 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2499 "unable to read config from controller.\n");
2500
2501 return (0);
2502 }
2503 /* end if */
2504 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2505 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2506 "unable to read controller status.\n");
2507
2508 return (0);
2509 }
2510
2511 /* Identify this controller */
2512 ips_identify_controller(ha);
2513
2514 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2515 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2516 "unable to read subsystem parameters.\n");
2517
2518 return (0);
2519 }
2520
2521 /* write nvram user page 5 */
2522 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2523 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2524 "unable to write driver info to controller.\n");
2525
2526 return (0);
2527 }
2528
2529 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2530 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2531 ips_clear_adapter(ha, IPS_INTR_IORL);
2532
2533 /* set limits on SID, LUN, BUS */
2534 ha->ntargets = IPS_MAX_TARGETS + 1;
2535 ha->nlun = 1;
2536 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2537
2538 switch (ha->conf->logical_drive[0].ucStripeSize) {
2539 case 4:
2540 ha->max_xfer = 0x10000;
2541 break;
2542
2543 case 5:
2544 ha->max_xfer = 0x20000;
2545 break;
2546
2547 case 6:
2548 ha->max_xfer = 0x40000;
2549 break;
2550
2551 case 7:
2552 default:
2553 ha->max_xfer = 0x80000;
2554 break;
2555 }
2556
2557 /* setup max concurrent commands */
2558 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2559 /* Use the new method */
2560 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2561 } else {
2562 /* use the old method */
2563 switch (ha->conf->logical_drive[0].ucStripeSize) {
2564 case 4:
2565 ha->max_cmds = 32;
2566 break;
2567
2568 case 5:
2569 ha->max_cmds = 16;
2570 break;
2571
2572 case 6:
2573 ha->max_cmds = 8;
2574 break;
2575
2576 case 7:
2577 default:
2578 ha->max_cmds = 4;
2579 break;
2580 }
2581 }
2582
2583 /* Limit the Active Commands on a Lite Adapter */
2584 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2585 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2586 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2587 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2588 ha->max_cmds = MaxLiteCmds;
2589 }
2590
2591 /* set controller IDs */
2592 ha->ha_id[0] = IPS_ADAPTER_ID;
2593 for (i = 1; i < ha->nbus; i++) {
2594 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2595 ha->dcdb_active[i - 1] = 0;
2596 }
2597
2598 return (1);
2599}
2600
2601/****************************************************************************/
2602/* */
2603/* Routine Name: ips_next */
2604/* */
2605/* Routine Description: */
2606/* */
2607/* Take the next command off the queue and send it to the controller */
2608/* */
2609/****************************************************************************/
2610static void
2611ips_next(ips_ha_t * ha, int intr)
2612{
2613 ips_scb_t *scb;
2614 struct scsi_cmnd *SC;
2615 struct scsi_cmnd *p;
2616 struct scsi_cmnd *q;
2617 ips_copp_wait_item_t *item;
2618 int ret;
2619 struct Scsi_Host *host;
2620 METHOD_TRACE("ips_next", 1);
2621
2622 if (!ha)
2623 return;
2624 host = ips_sh[ha->host_num];
2625 /*
2626 * Block access to the queue function so
2627 * this command won't time out
2628 */
2629 if (intr == IPS_INTR_ON)
2630 spin_lock(host->host_lock);
2631
2632 if ((ha->subsys->param[3] & 0x300000)
2633 && (ha->scb_activelist.count == 0)) {
2634 struct timeval tv;
2635
2636 do_gettimeofday(&tv);
2637
2638 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2639 ha->last_ffdc = tv.tv_sec;
2640 ips_ffdc_time(ha);
2641 }
2642 }
2643
2644 /*
2645 * Send passthru commands
2646 * These have priority over normal I/O
2647 * but shouldn't affect performance too much
2648 * since we limit the number that can be active
2649 * on the card at any one time
2650 */
2651 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2652 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2653
2654 item = ips_removeq_copp_head(&ha->copp_waitlist);
2655 ha->num_ioctl++;
2656 if (intr == IPS_INTR_ON)
2657 spin_unlock(host->host_lock);
2658 scb->scsi_cmd = item->scsi_cmd;
2659 kfree(item);
2660
2661 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2662
2663 if (intr == IPS_INTR_ON)
2664 spin_lock(host->host_lock);
2665 switch (ret) {
2666 case IPS_FAILURE:
2667 if (scb->scsi_cmd) {
2668 scb->scsi_cmd->result = DID_ERROR << 16;
2669 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2670 }
2671
2672 ips_freescb(ha, scb);
2673 break;
2674 case IPS_SUCCESS_IMM:
2675 if (scb->scsi_cmd) {
2676 scb->scsi_cmd->result = DID_OK << 16;
2677 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2678 }
2679
2680 ips_freescb(ha, scb);
2681 break;
2682 default:
2683 break;
2684 } /* end case */
2685
2686 if (ret != IPS_SUCCESS) {
2687 ha->num_ioctl--;
2688 continue;
2689 }
2690
2691 ret = ips_send_cmd(ha, scb);
2692
2693 if (ret == IPS_SUCCESS)
2694 ips_putq_scb_head(&ha->scb_activelist, scb);
2695 else
2696 ha->num_ioctl--;
2697
2698 switch (ret) {
2699 case IPS_FAILURE:
2700 if (scb->scsi_cmd) {
2701 scb->scsi_cmd->result = DID_ERROR << 16;
2702 }
2703
2704 ips_freescb(ha, scb);
2705 break;
2706 case IPS_SUCCESS_IMM:
2707 ips_freescb(ha, scb);
2708 break;
2709 default:
2710 break;
2711 } /* end case */
2712
2713 }
2714
2715 /*
2716 * Send "Normal" I/O commands
2717 */
2718
2719 p = ha->scb_waitlist.head;
2720 while ((p) && (scb = ips_getscb(ha))) {
2721 if ((scmd_channel(p) > 0)
2722 && (ha->
2723 dcdb_active[scmd_channel(p) -
2724 1] & (1 << scmd_id(p)))) {
2725 ips_freescb(ha, scb);
2726 p = (struct scsi_cmnd *) p->host_scribble;
2727 continue;
2728 }
2729
2730 q = p;
2731 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2732
2733 if (intr == IPS_INTR_ON)
2734 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2735
2736 SC->result = DID_OK;
2737 SC->host_scribble = NULL;
2738
2739 scb->target_id = SC->device->id;
2740 scb->lun = SC->device->lun;
2741 scb->bus = SC->device->channel;
2742 scb->scsi_cmd = SC;
2743 scb->breakup = 0;
2744 scb->data_len = 0;
2745 scb->callback = ipsintr_done;
2746 scb->timeout = ips_cmd_timeout;
2747 memset(&scb->cmd, 0, 16);
2748
2749 /* copy in the CDB */
2750 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2751
2752 scb->sg_count = scsi_dma_map(SC);
2753 BUG_ON(scb->sg_count < 0);
2754 if (scb->sg_count) {
2755 struct scatterlist *sg;
2756 int i;
2757
2758 scb->flags |= IPS_SCB_MAP_SG;
2759
2760 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2761 if (ips_fill_scb_sg_single
2762 (ha, sg_dma_address(sg), scb, i,
2763 sg_dma_len(sg)) < 0)
2764 break;
2765 }
2766 scb->dcdb.transfer_length = scb->data_len;
2767 } else {
2768 scb->data_busaddr = 0L;
2769 scb->sg_len = 0;
2770 scb->data_len = 0;
2771 scb->dcdb.transfer_length = 0;
2772 }
2773
2774 scb->dcdb.cmd_attribute =
2775 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2776
2777 /* Allow a WRITE BUFFER Command to Have no Data */
2778 /* This is Used by Tape Flash Utilites */
2779 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2780 (scb->data_len == 0))
2781 scb->dcdb.cmd_attribute = 0;
2782
2783 if (!(scb->dcdb.cmd_attribute & 0x3))
2784 scb->dcdb.transfer_length = 0;
2785
2786 if (scb->data_len >= IPS_MAX_XFER) {
2787 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2788 scb->dcdb.transfer_length = 0;
2789 }
2790 if (intr == IPS_INTR_ON)
2791 spin_lock(host->host_lock);
2792
2793 ret = ips_send_cmd(ha, scb);
2794
2795 switch (ret) {
2796 case IPS_SUCCESS:
2797 ips_putq_scb_head(&ha->scb_activelist, scb);
2798 break;
2799 case IPS_FAILURE:
2800 if (scb->scsi_cmd) {
2801 scb->scsi_cmd->result = DID_ERROR << 16;
2802 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2803 }
2804
2805 if (scb->bus)
2806 ha->dcdb_active[scb->bus - 1] &=
2807 ~(1 << scb->target_id);
2808
2809 ips_freescb(ha, scb);
2810 break;
2811 case IPS_SUCCESS_IMM:
2812 if (scb->scsi_cmd)
2813 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2814
2815 if (scb->bus)
2816 ha->dcdb_active[scb->bus - 1] &=
2817 ~(1 << scb->target_id);
2818
2819 ips_freescb(ha, scb);
2820 break;
2821 default:
2822 break;
2823 } /* end case */
2824
2825 p = (struct scsi_cmnd *) p->host_scribble;
2826
2827 } /* end while */
2828
2829 if (intr == IPS_INTR_ON)
2830 spin_unlock(host->host_lock);
2831}
2832
2833/****************************************************************************/
2834/* */
2835/* Routine Name: ips_putq_scb_head */
2836/* */
2837/* Routine Description: */
2838/* */
2839/* Add an item to the head of the queue */
2840/* */
2841/* ASSUMED to be called from within the HA lock */
2842/* */
2843/****************************************************************************/
2844static void
2845ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2846{
2847 METHOD_TRACE("ips_putq_scb_head", 1);
2848
2849 if (!item)
2850 return;
2851
2852 item->q_next = queue->head;
2853 queue->head = item;
2854
2855 if (!queue->tail)
2856 queue->tail = item;
2857
2858 queue->count++;
2859}
2860
2861/****************************************************************************/
2862/* */
2863/* Routine Name: ips_removeq_scb_head */
2864/* */
2865/* Routine Description: */
2866/* */
2867/* Remove the head of the queue */
2868/* */
2869/* ASSUMED to be called from within the HA lock */
2870/* */
2871/****************************************************************************/
2872static ips_scb_t *
2873ips_removeq_scb_head(ips_scb_queue_t * queue)
2874{
2875 ips_scb_t *item;
2876
2877 METHOD_TRACE("ips_removeq_scb_head", 1);
2878
2879 item = queue->head;
2880
2881 if (!item) {
2882 return (NULL);
2883 }
2884
2885 queue->head = item->q_next;
2886 item->q_next = NULL;
2887
2888 if (queue->tail == item)
2889 queue->tail = NULL;
2890
2891 queue->count--;
2892
2893 return (item);
2894}
2895
2896/****************************************************************************/
2897/* */
2898/* Routine Name: ips_removeq_scb */
2899/* */
2900/* Routine Description: */
2901/* */
2902/* Remove an item from a queue */
2903/* */
2904/* ASSUMED to be called from within the HA lock */
2905/* */
2906/****************************************************************************/
2907static ips_scb_t *
2908ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2909{
2910 ips_scb_t *p;
2911
2912 METHOD_TRACE("ips_removeq_scb", 1);
2913
2914 if (!item)
2915 return (NULL);
2916
2917 if (item == queue->head) {
2918 return (ips_removeq_scb_head(queue));
2919 }
2920
2921 p = queue->head;
2922
2923 while ((p) && (item != p->q_next))
2924 p = p->q_next;
2925
2926 if (p) {
2927 /* found a match */
2928 p->q_next = item->q_next;
2929
2930 if (!item->q_next)
2931 queue->tail = p;
2932
2933 item->q_next = NULL;
2934 queue->count--;
2935
2936 return (item);
2937 }
2938
2939 return (NULL);
2940}
2941
2942/****************************************************************************/
2943/* */
2944/* Routine Name: ips_putq_wait_tail */
2945/* */
2946/* Routine Description: */
2947/* */
2948/* Add an item to the tail of the queue */
2949/* */
2950/* ASSUMED to be called from within the HA lock */
2951/* */
2952/****************************************************************************/
2953static void ips_putq_wait_tail(ips_wait_queue_t *queue, struct scsi_cmnd *item)
2954{
2955 METHOD_TRACE("ips_putq_wait_tail", 1);
2956
2957 if (!item)
2958 return;
2959
2960 item->host_scribble = NULL;
2961
2962 if (queue->tail)
2963 queue->tail->host_scribble = (char *) item;
2964
2965 queue->tail = item;
2966
2967 if (!queue->head)
2968 queue->head = item;
2969
2970 queue->count++;
2971}
2972
2973/****************************************************************************/
2974/* */
2975/* Routine Name: ips_removeq_wait_head */
2976/* */
2977/* Routine Description: */
2978/* */
2979/* Remove the head of the queue */
2980/* */
2981/* ASSUMED to be called from within the HA lock */
2982/* */
2983/****************************************************************************/
2984static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *queue)
2985{
2986 struct scsi_cmnd *item;
2987
2988 METHOD_TRACE("ips_removeq_wait_head", 1);
2989
2990 item = queue->head;
2991
2992 if (!item) {
2993 return (NULL);
2994 }
2995
2996 queue->head = (struct scsi_cmnd *) item->host_scribble;
2997 item->host_scribble = NULL;
2998
2999 if (queue->tail == item)
3000 queue->tail = NULL;
3001
3002 queue->count--;
3003
3004 return (item);
3005}
3006
3007/****************************************************************************/
3008/* */
3009/* Routine Name: ips_removeq_wait */
3010/* */
3011/* Routine Description: */
3012/* */
3013/* Remove an item from a queue */
3014/* */
3015/* ASSUMED to be called from within the HA lock */
3016/* */
3017/****************************************************************************/
3018static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *queue,
3019 struct scsi_cmnd *item)
3020{
3021 struct scsi_cmnd *p;
3022
3023 METHOD_TRACE("ips_removeq_wait", 1);
3024
3025 if (!item)
3026 return (NULL);
3027
3028 if (item == queue->head) {
3029 return (ips_removeq_wait_head(queue));
3030 }
3031
3032 p = queue->head;
3033
3034 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
3035 p = (struct scsi_cmnd *) p->host_scribble;
3036
3037 if (p) {
3038 /* found a match */
3039 p->host_scribble = item->host_scribble;
3040
3041 if (!item->host_scribble)
3042 queue->tail = p;
3043
3044 item->host_scribble = NULL;
3045 queue->count--;
3046
3047 return (item);
3048 }
3049
3050 return (NULL);
3051}
3052
3053/****************************************************************************/
3054/* */
3055/* Routine Name: ips_putq_copp_tail */
3056/* */
3057/* Routine Description: */
3058/* */
3059/* Add an item to the tail of the queue */
3060/* */
3061/* ASSUMED to be called from within the HA lock */
3062/* */
3063/****************************************************************************/
3064static void
3065ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3066{
3067 METHOD_TRACE("ips_putq_copp_tail", 1);
3068
3069 if (!item)
3070 return;
3071
3072 item->next = NULL;
3073
3074 if (queue->tail)
3075 queue->tail->next = item;
3076
3077 queue->tail = item;
3078
3079 if (!queue->head)
3080 queue->head = item;
3081
3082 queue->count++;
3083}
3084
3085/****************************************************************************/
3086/* */
3087/* Routine Name: ips_removeq_copp_head */
3088/* */
3089/* Routine Description: */
3090/* */
3091/* Remove the head of the queue */
3092/* */
3093/* ASSUMED to be called from within the HA lock */
3094/* */
3095/****************************************************************************/
3096static ips_copp_wait_item_t *
3097ips_removeq_copp_head(ips_copp_queue_t * queue)
3098{
3099 ips_copp_wait_item_t *item;
3100
3101 METHOD_TRACE("ips_removeq_copp_head", 1);
3102
3103 item = queue->head;
3104
3105 if (!item) {
3106 return (NULL);
3107 }
3108
3109 queue->head = item->next;
3110 item->next = NULL;
3111
3112 if (queue->tail == item)
3113 queue->tail = NULL;
3114
3115 queue->count--;
3116
3117 return (item);
3118}
3119
3120/****************************************************************************/
3121/* */
3122/* Routine Name: ips_removeq_copp */
3123/* */
3124/* Routine Description: */
3125/* */
3126/* Remove an item from a queue */
3127/* */
3128/* ASSUMED to be called from within the HA lock */
3129/* */
3130/****************************************************************************/
3131static ips_copp_wait_item_t *
3132ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3133{
3134 ips_copp_wait_item_t *p;
3135
3136 METHOD_TRACE("ips_removeq_copp", 1);
3137
3138 if (!item)
3139 return (NULL);
3140
3141 if (item == queue->head) {
3142 return (ips_removeq_copp_head(queue));
3143 }
3144
3145 p = queue->head;
3146
3147 while ((p) && (item != p->next))
3148 p = p->next;
3149
3150 if (p) {
3151 /* found a match */
3152 p->next = item->next;
3153
3154 if (!item->next)
3155 queue->tail = p;
3156
3157 item->next = NULL;
3158 queue->count--;
3159
3160 return (item);
3161 }
3162
3163 return (NULL);
3164}
3165
3166/****************************************************************************/
3167/* */
3168/* Routine Name: ipsintr_blocking */
3169/* */
3170/* Routine Description: */
3171/* */
3172/* Finalize an interrupt for internal commands */
3173/* */
3174/****************************************************************************/
3175static void
3176ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3177{
3178 METHOD_TRACE("ipsintr_blocking", 2);
3179
3180 ips_freescb(ha, scb);
3181 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3182 ha->waitflag = FALSE;
3183
3184 return;
3185 }
3186}
3187
3188/****************************************************************************/
3189/* */
3190/* Routine Name: ipsintr_done */
3191/* */
3192/* Routine Description: */
3193/* */
3194/* Finalize an interrupt for non-internal commands */
3195/* */
3196/****************************************************************************/
3197static void
3198ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3199{
3200 METHOD_TRACE("ipsintr_done", 2);
3201
3202 if (!scb) {
3203 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3204 "Spurious interrupt; scb NULL.\n");
3205
3206 return;
3207 }
3208
3209 if (scb->scsi_cmd == NULL) {
3210 /* unexpected interrupt */
3211 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3212 "Spurious interrupt; scsi_cmd not set.\n");
3213
3214 return;
3215 }
3216
3217 ips_done(ha, scb);
3218}
3219
3220/****************************************************************************/
3221/* */
3222/* Routine Name: ips_done */
3223/* */
3224/* Routine Description: */
3225/* */
3226/* Do housekeeping on completed commands */
3227/* ASSUMED to be called form within the request lock */
3228/****************************************************************************/
3229static void
3230ips_done(ips_ha_t * ha, ips_scb_t * scb)
3231{
3232 int ret;
3233
3234 METHOD_TRACE("ips_done", 1);
3235
3236 if (!scb)
3237 return;
3238
3239 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3240 ips_cleanup_passthru(ha, scb);
3241 ha->num_ioctl--;
3242 } else {
3243 /*
3244 * Check to see if this command had too much
3245 * data and had to be broke up. If so, queue
3246 * the rest of the data and continue.
3247 */
3248 if ((scb->breakup) || (scb->sg_break)) {
3249 struct scatterlist *sg;
3250 int i, sg_dma_index, ips_sg_index = 0;
3251
3252 /* we had a data breakup */
3253 scb->data_len = 0;
3254
3255 sg = scsi_sglist(scb->scsi_cmd);
3256
3257 /* Spin forward to last dma chunk */
3258 sg_dma_index = scb->breakup;
3259 for (i = 0; i < scb->breakup; i++)
3260 sg = sg_next(sg);
3261
3262 /* Take care of possible partial on last chunk */
3263 ips_fill_scb_sg_single(ha,
3264 sg_dma_address(sg),
3265 scb, ips_sg_index++,
3266 sg_dma_len(sg));
3267
3268 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3269 sg_dma_index++, sg = sg_next(sg)) {
3270 if (ips_fill_scb_sg_single
3271 (ha,
3272 sg_dma_address(sg),
3273 scb, ips_sg_index++,
3274 sg_dma_len(sg)) < 0)
3275 break;
3276 }
3277
3278 scb->dcdb.transfer_length = scb->data_len;
3279 scb->dcdb.cmd_attribute |=
3280 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3281
3282 if (!(scb->dcdb.cmd_attribute & 0x3))
3283 scb->dcdb.transfer_length = 0;
3284
3285 if (scb->data_len >= IPS_MAX_XFER) {
3286 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3287 scb->dcdb.transfer_length = 0;
3288 }
3289
3290 ret = ips_send_cmd(ha, scb);
3291
3292 switch (ret) {
3293 case IPS_FAILURE:
3294 if (scb->scsi_cmd) {
3295 scb->scsi_cmd->result = DID_ERROR << 16;
3296 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3297 }
3298
3299 ips_freescb(ha, scb);
3300 break;
3301 case IPS_SUCCESS_IMM:
3302 if (scb->scsi_cmd) {
3303 scb->scsi_cmd->result = DID_ERROR << 16;
3304 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3305 }
3306
3307 ips_freescb(ha, scb);
3308 break;
3309 default:
3310 break;
3311 } /* end case */
3312
3313 return;
3314 }
3315 } /* end if passthru */
3316
3317 if (scb->bus) {
3318 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3319 }
3320
3321 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3322
3323 ips_freescb(ha, scb);
3324}
3325
3326/****************************************************************************/
3327/* */
3328/* Routine Name: ips_map_status */
3329/* */
3330/* Routine Description: */
3331/* */
3332/* Map Controller Error codes to Linux Error Codes */
3333/* */
3334/****************************************************************************/
3335static int
3336ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3337{
3338 int errcode;
3339 int device_error;
3340 uint32_t transfer_len;
3341 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3342 IPS_SCSI_INQ_DATA inquiryData;
3343
3344 METHOD_TRACE("ips_map_status", 1);
3345
3346 if (scb->bus) {
3347 DEBUG_VAR(2,
3348 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3349 ips_name, ha->host_num,
3350 scb->scsi_cmd->device->channel,
3351 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3352 scb->basic_status, scb->extended_status,
3353 scb->extended_status ==
3354 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3355 scb->extended_status ==
3356 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3357 scb->extended_status ==
3358 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3359 }
3360
3361 /* default driver error */
3362 errcode = DID_ERROR;
3363 device_error = 0;
3364
3365 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3366 case IPS_CMD_TIMEOUT:
3367 errcode = DID_TIME_OUT;
3368 break;
3369
3370 case IPS_INVAL_OPCO:
3371 case IPS_INVAL_CMD_BLK:
3372 case IPS_INVAL_PARM_BLK:
3373 case IPS_LD_ERROR:
3374 case IPS_CMD_CMPLT_WERROR:
3375 break;
3376
3377 case IPS_PHYS_DRV_ERROR:
3378 switch (scb->extended_status) {
3379 case IPS_ERR_SEL_TO:
3380 if (scb->bus)
3381 errcode = DID_NO_CONNECT;
3382
3383 break;
3384
3385 case IPS_ERR_OU_RUN:
3386 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3387 (scb->cmd.dcdb.op_code ==
3388 IPS_CMD_EXTENDED_DCDB_SG)) {
3389 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3390 transfer_len = tapeDCDB->transfer_length;
3391 } else {
3392 transfer_len =
3393 (uint32_t) scb->dcdb.transfer_length;
3394 }
3395
3396 if ((scb->bus) && (transfer_len < scb->data_len)) {
3397 /* Underrun - set default to no error */
3398 errcode = DID_OK;
3399
3400 /* Restrict access to physical DASD */
3401 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3402 ips_scmd_buf_read(scb->scsi_cmd,
3403 &inquiryData, sizeof (inquiryData));
3404 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3405 errcode = DID_TIME_OUT;
3406 break;
3407 }
3408 }
3409 } else
3410 errcode = DID_ERROR;
3411
3412 break;
3413
3414 case IPS_ERR_RECOVERY:
3415 /* don't fail recovered errors */
3416 if (scb->bus)
3417 errcode = DID_OK;
3418
3419 break;
3420
3421 case IPS_ERR_HOST_RESET:
3422 case IPS_ERR_DEV_RESET:
3423 errcode = DID_RESET;
3424 break;
3425
3426 case IPS_ERR_CKCOND:
3427 if (scb->bus) {
3428 if ((scb->cmd.dcdb.op_code ==
3429 IPS_CMD_EXTENDED_DCDB)
3430 || (scb->cmd.dcdb.op_code ==
3431 IPS_CMD_EXTENDED_DCDB_SG)) {
3432 tapeDCDB =
3433 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3434 memcpy(scb->scsi_cmd->sense_buffer,
3435 tapeDCDB->sense_info,
3436 SCSI_SENSE_BUFFERSIZE);
3437 } else {
3438 memcpy(scb->scsi_cmd->sense_buffer,
3439 scb->dcdb.sense_info,
3440 SCSI_SENSE_BUFFERSIZE);
3441 }
3442 device_error = 2; /* check condition */
3443 }
3444
3445 errcode = DID_OK;
3446
3447 break;
3448
3449 default:
3450 errcode = DID_ERROR;
3451 break;
3452
3453 } /* end switch */
3454 } /* end switch */
3455
3456 scb->scsi_cmd->result = device_error | (errcode << 16);
3457
3458 return (1);
3459}
3460
3461/****************************************************************************/
3462/* */
3463/* Routine Name: ips_send_wait */
3464/* */
3465/* Routine Description: */
3466/* */
3467/* Send a command to the controller and wait for it to return */
3468/* */
3469/* The FFDC Time Stamp use this function for the callback, but doesn't */
3470/* actually need to wait. */
3471/****************************************************************************/
3472static int
3473ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3474{
3475 int ret;
3476
3477 METHOD_TRACE("ips_send_wait", 1);
3478
3479 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3480 ha->waitflag = TRUE;
3481 ha->cmd_in_progress = scb->cdb[0];
3482 }
3483 scb->callback = ipsintr_blocking;
3484 ret = ips_send_cmd(ha, scb);
3485
3486 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3487 return (ret);
3488
3489 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3490 ret = ips_wait(ha, timeout, intr);
3491
3492 return (ret);
3493}
3494
3495/****************************************************************************/
3496/* */
3497/* Routine Name: ips_scmd_buf_write */
3498/* */
3499/* Routine Description: */
3500/* Write data to struct scsi_cmnd request_buffer at proper offsets */
3501/****************************************************************************/
3502static void
3503ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3504{
3505 unsigned long flags;
3506
3507 local_irq_save(flags);
3508 scsi_sg_copy_from_buffer(scmd, data, count);
3509 local_irq_restore(flags);
3510}
3511
3512/****************************************************************************/
3513/* */
3514/* Routine Name: ips_scmd_buf_read */
3515/* */
3516/* Routine Description: */
3517/* Copy data from a struct scsi_cmnd to a new, linear buffer */
3518/****************************************************************************/
3519static void
3520ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3521{
3522 unsigned long flags;
3523
3524 local_irq_save(flags);
3525 scsi_sg_copy_to_buffer(scmd, data, count);
3526 local_irq_restore(flags);
3527}
3528
3529/****************************************************************************/
3530/* */
3531/* Routine Name: ips_send_cmd */
3532/* */
3533/* Routine Description: */
3534/* */
3535/* Map SCSI commands to ServeRAID commands for logical drives */
3536/* */
3537/****************************************************************************/
3538static int
3539ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3540{
3541 int ret;
3542 char *sp;
3543 int device_error;
3544 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3545 int TimeOut;
3546
3547 METHOD_TRACE("ips_send_cmd", 1);
3548
3549 ret = IPS_SUCCESS;
3550
3551 if (!scb->scsi_cmd) {
3552 /* internal command */
3553
3554 if (scb->bus > 0) {
3555 /* Controller commands can't be issued */
3556 /* to real devices -- fail them */
3557 if ((ha->waitflag == TRUE) &&
3558 (ha->cmd_in_progress == scb->cdb[0])) {
3559 ha->waitflag = FALSE;
3560 }
3561
3562 return (1);
3563 }
3564 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3565 /* command to logical bus -- interpret */
3566 ret = IPS_SUCCESS_IMM;
3567
3568 switch (scb->scsi_cmd->cmnd[0]) {
3569 case ALLOW_MEDIUM_REMOVAL:
3570 case REZERO_UNIT:
3571 case ERASE:
3572 case WRITE_FILEMARKS:
3573 case SPACE:
3574 scb->scsi_cmd->result = DID_ERROR << 16;
3575 break;
3576
3577 case START_STOP:
3578 scb->scsi_cmd->result = DID_OK << 16;
3579
3580 case TEST_UNIT_READY:
3581 case INQUIRY:
3582 if (scb->target_id == IPS_ADAPTER_ID) {
3583 /*
3584 * Either we have a TUR
3585 * or we have a SCSI inquiry
3586 */
3587 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3588 scb->scsi_cmd->result = DID_OK << 16;
3589
3590 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3591 IPS_SCSI_INQ_DATA inquiry;
3592
3593 memset(&inquiry, 0,
3594 sizeof (IPS_SCSI_INQ_DATA));
3595
3596 inquiry.DeviceType =
3597 IPS_SCSI_INQ_TYPE_PROCESSOR;
3598 inquiry.DeviceTypeQualifier =
3599 IPS_SCSI_INQ_LU_CONNECTED;
3600 inquiry.Version = IPS_SCSI_INQ_REV2;
3601 inquiry.ResponseDataFormat =
3602 IPS_SCSI_INQ_RD_REV2;
3603 inquiry.AdditionalLength = 31;
3604 inquiry.Flags[0] =
3605 IPS_SCSI_INQ_Address16;
3606 inquiry.Flags[1] =
3607 IPS_SCSI_INQ_WBus16 |
3608 IPS_SCSI_INQ_Sync;
3609 strncpy(inquiry.VendorId, "IBM ",
3610 8);
3611 strncpy(inquiry.ProductId,
3612 "SERVERAID ", 16);
3613 strncpy(inquiry.ProductRevisionLevel,
3614 "1.00", 4);
3615
3616 ips_scmd_buf_write(scb->scsi_cmd,
3617 &inquiry,
3618 sizeof (inquiry));
3619
3620 scb->scsi_cmd->result = DID_OK << 16;
3621 }
3622 } else {
3623 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3624 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3625 scb->cmd.logical_info.reserved = 0;
3626 scb->cmd.logical_info.reserved2 = 0;
3627 scb->data_len = sizeof (IPS_LD_INFO);
3628 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3629 scb->flags = 0;
3630 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3631 ret = IPS_SUCCESS;
3632 }
3633
3634 break;
3635
3636 case REQUEST_SENSE:
3637 ips_reqsen(ha, scb);
3638 scb->scsi_cmd->result = DID_OK << 16;
3639 break;
3640
3641 case READ_6:
3642 case WRITE_6:
3643 if (!scb->sg_len) {
3644 scb->cmd.basic_io.op_code =
3645 (scb->scsi_cmd->cmnd[0] ==
3646 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3647 scb->cmd.basic_io.enhanced_sg = 0;
3648 scb->cmd.basic_io.sg_addr =
3649 cpu_to_le32(scb->data_busaddr);
3650 } else {
3651 scb->cmd.basic_io.op_code =
3652 (scb->scsi_cmd->cmnd[0] ==
3653 READ_6) ? IPS_CMD_READ_SG :
3654 IPS_CMD_WRITE_SG;
3655 scb->cmd.basic_io.enhanced_sg =
3656 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3657 scb->cmd.basic_io.sg_addr =
3658 cpu_to_le32(scb->sg_busaddr);
3659 }
3660
3661 scb->cmd.basic_io.segment_4G = 0;
3662 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3663 scb->cmd.basic_io.log_drv = scb->target_id;
3664 scb->cmd.basic_io.sg_count = scb->sg_len;
3665
3666 if (scb->cmd.basic_io.lba)
3667 le32_add_cpu(&scb->cmd.basic_io.lba,
3668 le16_to_cpu(scb->cmd.basic_io.
3669 sector_count));
3670 else
3671 scb->cmd.basic_io.lba =
3672 (((scb->scsi_cmd->
3673 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3674 cmnd[2] << 8) |
3675 (scb->scsi_cmd->cmnd[3]));
3676
3677 scb->cmd.basic_io.sector_count =
3678 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3679
3680 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3681 scb->cmd.basic_io.sector_count =
3682 cpu_to_le16(256);
3683
3684 ret = IPS_SUCCESS;
3685 break;
3686
3687 case READ_10:
3688 case WRITE_10:
3689 if (!scb->sg_len) {
3690 scb->cmd.basic_io.op_code =
3691 (scb->scsi_cmd->cmnd[0] ==
3692 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3693 scb->cmd.basic_io.enhanced_sg = 0;
3694 scb->cmd.basic_io.sg_addr =
3695 cpu_to_le32(scb->data_busaddr);
3696 } else {
3697 scb->cmd.basic_io.op_code =
3698 (scb->scsi_cmd->cmnd[0] ==
3699 READ_10) ? IPS_CMD_READ_SG :
3700 IPS_CMD_WRITE_SG;
3701 scb->cmd.basic_io.enhanced_sg =
3702 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3703 scb->cmd.basic_io.sg_addr =
3704 cpu_to_le32(scb->sg_busaddr);
3705 }
3706
3707 scb->cmd.basic_io.segment_4G = 0;
3708 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3709 scb->cmd.basic_io.log_drv = scb->target_id;
3710 scb->cmd.basic_io.sg_count = scb->sg_len;
3711
3712 if (scb->cmd.basic_io.lba)
3713 le32_add_cpu(&scb->cmd.basic_io.lba,
3714 le16_to_cpu(scb->cmd.basic_io.
3715 sector_count));
3716 else
3717 scb->cmd.basic_io.lba =
3718 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3719 scsi_cmd->
3720 cmnd[3]
3721 << 16) |
3722 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3723 scsi_cmd->cmnd[5]);
3724
3725 scb->cmd.basic_io.sector_count =
3726 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3727
3728 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3729 /*
3730 * This is a null condition
3731 * we don't have to do anything
3732 * so just return
3733 */
3734 scb->scsi_cmd->result = DID_OK << 16;
3735 } else
3736 ret = IPS_SUCCESS;
3737
3738 break;
3739
3740 case RESERVE:
3741 case RELEASE:
3742 scb->scsi_cmd->result = DID_OK << 16;
3743 break;
3744
3745 case MODE_SENSE:
3746 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3747 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3748 scb->cmd.basic_io.segment_4G = 0;
3749 scb->cmd.basic_io.enhanced_sg = 0;
3750 scb->data_len = sizeof (*ha->enq);
3751 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3752 ret = IPS_SUCCESS;
3753 break;
3754
3755 case READ_CAPACITY:
3756 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3757 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3758 scb->cmd.logical_info.reserved = 0;
3759 scb->cmd.logical_info.reserved2 = 0;
3760 scb->cmd.logical_info.reserved3 = 0;
3761 scb->data_len = sizeof (IPS_LD_INFO);
3762 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3763 scb->flags = 0;
3764 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3765 ret = IPS_SUCCESS;
3766 break;
3767
3768 case SEND_DIAGNOSTIC:
3769 case REASSIGN_BLOCKS:
3770 case FORMAT_UNIT:
3771 case SEEK_10:
3772 case VERIFY:
3773 case READ_DEFECT_DATA:
3774 case READ_BUFFER:
3775 case WRITE_BUFFER:
3776 scb->scsi_cmd->result = DID_OK << 16;
3777 break;
3778
3779 default:
3780 /* Set the Return Info to appear like the Command was */
3781 /* attempted, a Check Condition occurred, and Sense */
3782 /* Data indicating an Invalid CDB OpCode is returned. */
3783 sp = (char *) scb->scsi_cmd->sense_buffer;
3784
3785 sp[0] = 0x70; /* Error Code */
3786 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3787 sp[7] = 0x0A; /* Additional Sense Length */
3788 sp[12] = 0x20; /* ASC = Invalid OpCode */
3789 sp[13] = 0x00; /* ASCQ */
3790
3791 device_error = 2; /* Indicate Check Condition */
3792 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3793 break;
3794 } /* end switch */
3795 }
3796 /* end if */
3797 if (ret == IPS_SUCCESS_IMM)
3798 return (ret);
3799
3800 /* setup DCDB */
3801 if (scb->bus > 0) {
3802
3803 /* If we already know the Device is Not there, no need to attempt a Command */
3804 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3805 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3806 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3807 return (IPS_SUCCESS_IMM);
3808 }
3809
3810 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3811 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3812 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3813 (unsigned long) &scb->
3814 dcdb -
3815 (unsigned long) scb);
3816 scb->cmd.dcdb.reserved = 0;
3817 scb->cmd.dcdb.reserved2 = 0;
3818 scb->cmd.dcdb.reserved3 = 0;
3819 scb->cmd.dcdb.segment_4G = 0;
3820 scb->cmd.dcdb.enhanced_sg = 0;
3821
3822 TimeOut = scb->scsi_cmd->request->timeout;
3823
3824 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3825 if (!scb->sg_len) {
3826 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3827 } else {
3828 scb->cmd.dcdb.op_code =
3829 IPS_CMD_EXTENDED_DCDB_SG;
3830 scb->cmd.dcdb.enhanced_sg =
3831 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3832 }
3833
3834 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3835 tapeDCDB->device_address =
3836 ((scb->bus - 1) << 4) | scb->target_id;
3837 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3838 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3839
3840 if (TimeOut) {
3841 if (TimeOut < (10 * HZ))
3842 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3843 else if (TimeOut < (60 * HZ))
3844 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3845 else if (TimeOut < (1200 * HZ))
3846 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3847 }
3848
3849 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3850 tapeDCDB->reserved_for_LUN = 0;
3851 tapeDCDB->transfer_length = scb->data_len;
3852 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3853 tapeDCDB->buffer_pointer =
3854 cpu_to_le32(scb->sg_busaddr);
3855 else
3856 tapeDCDB->buffer_pointer =
3857 cpu_to_le32(scb->data_busaddr);
3858 tapeDCDB->sg_count = scb->sg_len;
3859 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3860 tapeDCDB->scsi_status = 0;
3861 tapeDCDB->reserved = 0;
3862 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3863 scb->scsi_cmd->cmd_len);
3864 } else {
3865 if (!scb->sg_len) {
3866 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3867 } else {
3868 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3869 scb->cmd.dcdb.enhanced_sg =
3870 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3871 }
3872
3873 scb->dcdb.device_address =
3874 ((scb->bus - 1) << 4) | scb->target_id;
3875 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3876
3877 if (TimeOut) {
3878 if (TimeOut < (10 * HZ))
3879 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3880 else if (TimeOut < (60 * HZ))
3881 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3882 else if (TimeOut < (1200 * HZ))
3883 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3884 }
3885
3886 scb->dcdb.transfer_length = scb->data_len;
3887 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3888 scb->dcdb.transfer_length = 0;
3889 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3890 scb->dcdb.buffer_pointer =
3891 cpu_to_le32(scb->sg_busaddr);
3892 else
3893 scb->dcdb.buffer_pointer =
3894 cpu_to_le32(scb->data_busaddr);
3895 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3896 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3897 scb->dcdb.sg_count = scb->sg_len;
3898 scb->dcdb.reserved = 0;
3899 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3900 scb->scsi_cmd->cmd_len);
3901 scb->dcdb.scsi_status = 0;
3902 scb->dcdb.reserved2[0] = 0;
3903 scb->dcdb.reserved2[1] = 0;
3904 scb->dcdb.reserved2[2] = 0;
3905 }
3906 }
3907
3908 return ((*ha->func.issue) (ha, scb));
3909}
3910
3911/****************************************************************************/
3912/* */
3913/* Routine Name: ips_chk_status */
3914/* */
3915/* Routine Description: */
3916/* */
3917/* Check the status of commands to logical drives */
3918/* Assumed to be called with the HA lock */
3919/****************************************************************************/
3920static void
3921ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3922{
3923 ips_scb_t *scb;
3924 ips_stat_t *sp;
3925 uint8_t basic_status;
3926 uint8_t ext_status;
3927 int errcode;
3928 IPS_SCSI_INQ_DATA inquiryData;
3929
3930 METHOD_TRACE("ips_chkstatus", 1);
3931
3932 scb = &ha->scbs[pstatus->fields.command_id];
3933 scb->basic_status = basic_status =
3934 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3935 scb->extended_status = ext_status = pstatus->fields.extended_status;
3936
3937 sp = &ha->sp;
3938 sp->residue_len = 0;
3939 sp->scb_addr = (void *) scb;
3940
3941 /* Remove the item from the active queue */
3942 ips_removeq_scb(&ha->scb_activelist, scb);
3943
3944 if (!scb->scsi_cmd)
3945 /* internal commands are handled in do_ipsintr */
3946 return;
3947
3948 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3949 ips_name,
3950 ha->host_num,
3951 scb->cdb[0],
3952 scb->cmd.basic_io.command_id,
3953 scb->bus, scb->target_id, scb->lun);
3954
3955 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3956 /* passthru - just returns the raw result */
3957 return;
3958
3959 errcode = DID_OK;
3960
3961 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3962 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3963
3964 if (scb->bus == 0) {
3965 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3966 IPS_CMD_RECOVERED_ERROR) {
3967 DEBUG_VAR(1,
3968 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3969 ips_name, ha->host_num,
3970 scb->cmd.basic_io.op_code,
3971 basic_status, ext_status);
3972 }
3973
3974 switch (scb->scsi_cmd->cmnd[0]) {
3975 case ALLOW_MEDIUM_REMOVAL:
3976 case REZERO_UNIT:
3977 case ERASE:
3978 case WRITE_FILEMARKS:
3979 case SPACE:
3980 errcode = DID_ERROR;
3981 break;
3982
3983 case START_STOP:
3984 break;
3985
3986 case TEST_UNIT_READY:
3987 if (!ips_online(ha, scb)) {
3988 errcode = DID_TIME_OUT;
3989 }
3990 break;
3991
3992 case INQUIRY:
3993 if (ips_online(ha, scb)) {
3994 ips_inquiry(ha, scb);
3995 } else {
3996 errcode = DID_TIME_OUT;
3997 }
3998 break;
3999
4000 case REQUEST_SENSE:
4001 ips_reqsen(ha, scb);
4002 break;
4003
4004 case READ_6:
4005 case WRITE_6:
4006 case READ_10:
4007 case WRITE_10:
4008 case RESERVE:
4009 case RELEASE:
4010 break;
4011
4012 case MODE_SENSE:
4013 if (!ips_online(ha, scb)
4014 || !ips_msense(ha, scb)) {
4015 errcode = DID_ERROR;
4016 }
4017 break;
4018
4019 case READ_CAPACITY:
4020 if (ips_online(ha, scb))
4021 ips_rdcap(ha, scb);
4022 else {
4023 errcode = DID_TIME_OUT;
4024 }
4025 break;
4026
4027 case SEND_DIAGNOSTIC:
4028 case REASSIGN_BLOCKS:
4029 break;
4030
4031 case FORMAT_UNIT:
4032 errcode = DID_ERROR;
4033 break;
4034
4035 case SEEK_10:
4036 case VERIFY:
4037 case READ_DEFECT_DATA:
4038 case READ_BUFFER:
4039 case WRITE_BUFFER:
4040 break;
4041
4042 default:
4043 errcode = DID_ERROR;
4044 } /* end switch */
4045
4046 scb->scsi_cmd->result = errcode << 16;
4047 } else { /* bus == 0 */
4048 /* restrict access to physical drives */
4049 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
4050 ips_scmd_buf_read(scb->scsi_cmd,
4051 &inquiryData, sizeof (inquiryData));
4052 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
4053 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4054 }
4055 } /* else */
4056 } else { /* recovered error / success */
4057 if (scb->bus == 0) {
4058 DEBUG_VAR(1,
4059 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4060 ips_name, ha->host_num,
4061 scb->cmd.basic_io.op_code, basic_status,
4062 ext_status);
4063 }
4064
4065 ips_map_status(ha, scb, sp);
4066 } /* else */
4067}
4068
4069/****************************************************************************/
4070/* */
4071/* Routine Name: ips_online */
4072/* */
4073/* Routine Description: */
4074/* */
4075/* Determine if a logical drive is online */
4076/* */
4077/****************************************************************************/
4078static int
4079ips_online(ips_ha_t * ha, ips_scb_t * scb)
4080{
4081 METHOD_TRACE("ips_online", 1);
4082
4083 if (scb->target_id >= IPS_MAX_LD)
4084 return (0);
4085
4086 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4087 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4088 return (0);
4089 }
4090
4091 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4092 IPS_LD_OFFLINE
4093 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4094 IPS_LD_FREE
4095 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4096 IPS_LD_CRS
4097 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4098 IPS_LD_SYS)
4099 return (1);
4100 else
4101 return (0);
4102}
4103
4104/****************************************************************************/
4105/* */
4106/* Routine Name: ips_inquiry */
4107/* */
4108/* Routine Description: */
4109/* */
4110/* Simulate an inquiry command to a logical drive */
4111/* */
4112/****************************************************************************/
4113static int
4114ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4115{
4116 IPS_SCSI_INQ_DATA inquiry;
4117
4118 METHOD_TRACE("ips_inquiry", 1);
4119
4120 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4121
4122 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4123 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4124 inquiry.Version = IPS_SCSI_INQ_REV2;
4125 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4126 inquiry.AdditionalLength = 31;
4127 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4128 inquiry.Flags[1] =
4129 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4130 strncpy(inquiry.VendorId, "IBM ", 8);
4131 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4132 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4133
4134 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4135
4136 return (1);
4137}
4138
4139/****************************************************************************/
4140/* */
4141/* Routine Name: ips_rdcap */
4142/* */
4143/* Routine Description: */
4144/* */
4145/* Simulate a read capacity command to a logical drive */
4146/* */
4147/****************************************************************************/
4148static int
4149ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4150{
4151 IPS_SCSI_CAPACITY cap;
4152
4153 METHOD_TRACE("ips_rdcap", 1);
4154
4155 if (scsi_bufflen(scb->scsi_cmd) < 8)
4156 return (0);
4157
4158 cap.lba =
4159 cpu_to_be32(le32_to_cpu
4160 (ha->logical_drive_info->
4161 drive_info[scb->target_id].sector_count) - 1);
4162 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4163
4164 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4165
4166 return (1);
4167}
4168
4169/****************************************************************************/
4170/* */
4171/* Routine Name: ips_msense */
4172/* */
4173/* Routine Description: */
4174/* */
4175/* Simulate a mode sense command to a logical drive */
4176/* */
4177/****************************************************************************/
4178static int
4179ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4180{
4181 uint16_t heads;
4182 uint16_t sectors;
4183 uint32_t cylinders;
4184 IPS_SCSI_MODE_PAGE_DATA mdata;
4185
4186 METHOD_TRACE("ips_msense", 1);
4187
4188 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4189 (ha->enq->ucMiscFlag & 0x8) == 0) {
4190 heads = IPS_NORM_HEADS;
4191 sectors = IPS_NORM_SECTORS;
4192 } else {
4193 heads = IPS_COMP_HEADS;
4194 sectors = IPS_COMP_SECTORS;
4195 }
4196
4197 cylinders =
4198 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4199 1) / (heads * sectors);
4200
4201 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4202
4203 mdata.hdr.BlockDescLength = 8;
4204
4205 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4206 case 0x03: /* page 3 */
4207 mdata.pdata.pg3.PageCode = 3;
4208 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4209 mdata.hdr.DataLength =
4210 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4211 mdata.pdata.pg3.TracksPerZone = 0;
4212 mdata.pdata.pg3.AltSectorsPerZone = 0;
4213 mdata.pdata.pg3.AltTracksPerZone = 0;
4214 mdata.pdata.pg3.AltTracksPerVolume = 0;
4215 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4216 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4217 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4218 mdata.pdata.pg3.TrackSkew = 0;
4219 mdata.pdata.pg3.CylinderSkew = 0;
4220 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4221 break;
4222
4223 case 0x4:
4224 mdata.pdata.pg4.PageCode = 4;
4225 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4226 mdata.hdr.DataLength =
4227 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4228 mdata.pdata.pg4.CylindersHigh =
4229 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4230 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4231 mdata.pdata.pg4.Heads = heads;
4232 mdata.pdata.pg4.WritePrecompHigh = 0;
4233 mdata.pdata.pg4.WritePrecompLow = 0;
4234 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4235 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4236 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4237 mdata.pdata.pg4.LandingZoneHigh = 0;
4238 mdata.pdata.pg4.LandingZoneLow = 0;
4239 mdata.pdata.pg4.flags = 0;
4240 mdata.pdata.pg4.RotationalOffset = 0;
4241 mdata.pdata.pg4.MediumRotationRate = 0;
4242 break;
4243 case 0x8:
4244 mdata.pdata.pg8.PageCode = 8;
4245 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4246 mdata.hdr.DataLength =
4247 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4248 /* everything else is left set to 0 */
4249 break;
4250
4251 default:
4252 return (0);
4253 } /* end switch */
4254
4255 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4256
4257 return (1);
4258}
4259
4260/****************************************************************************/
4261/* */
4262/* Routine Name: ips_reqsen */
4263/* */
4264/* Routine Description: */
4265/* */
4266/* Simulate a request sense command to a logical drive */
4267/* */
4268/****************************************************************************/
4269static int
4270ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4271{
4272 IPS_SCSI_REQSEN reqsen;
4273
4274 METHOD_TRACE("ips_reqsen", 1);
4275
4276 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4277
4278 reqsen.ResponseCode =
4279 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4280 reqsen.AdditionalLength = 10;
4281 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4282 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4283
4284 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4285
4286 return (1);
4287}
4288
4289/****************************************************************************/
4290/* */
4291/* Routine Name: ips_free */
4292/* */
4293/* Routine Description: */
4294/* */
4295/* Free any allocated space for this controller */
4296/* */
4297/****************************************************************************/
4298static void
4299ips_free(ips_ha_t * ha)
4300{
4301
4302 METHOD_TRACE("ips_free", 1);
4303
4304 if (ha) {
4305 if (ha->enq) {
4306 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4307 ha->enq, ha->enq_busaddr);
4308 ha->enq = NULL;
4309 }
4310
4311 kfree(ha->conf);
4312 ha->conf = NULL;
4313
4314 if (ha->adapt) {
4315 pci_free_consistent(ha->pcidev,
4316 sizeof (IPS_ADAPTER) +
4317 sizeof (IPS_IO_CMD), ha->adapt,
4318 ha->adapt->hw_status_start);
4319 ha->adapt = NULL;
4320 }
4321
4322 if (ha->logical_drive_info) {
4323 pci_free_consistent(ha->pcidev,
4324 sizeof (IPS_LD_INFO),
4325 ha->logical_drive_info,
4326 ha->logical_drive_info_dma_addr);
4327 ha->logical_drive_info = NULL;
4328 }
4329
4330 kfree(ha->nvram);
4331 ha->nvram = NULL;
4332
4333 kfree(ha->subsys);
4334 ha->subsys = NULL;
4335
4336 if (ha->ioctl_data) {
4337 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4338 ha->ioctl_data, ha->ioctl_busaddr);
4339 ha->ioctl_data = NULL;
4340 ha->ioctl_datasize = 0;
4341 ha->ioctl_len = 0;
4342 }
4343 ips_deallocatescbs(ha, ha->max_cmds);
4344
4345 /* free memory mapped (if applicable) */
4346 if (ha->mem_ptr) {
4347 iounmap(ha->ioremap_ptr);
4348 ha->ioremap_ptr = NULL;
4349 ha->mem_ptr = NULL;
4350 }
4351
4352 ha->mem_addr = 0;
4353
4354 }
4355}
4356
4357/****************************************************************************/
4358/* */
4359/* Routine Name: ips_deallocatescbs */
4360/* */
4361/* Routine Description: */
4362/* */
4363/* Free the command blocks */
4364/* */
4365/****************************************************************************/
4366static int
4367ips_deallocatescbs(ips_ha_t * ha, int cmds)
4368{
4369 if (ha->scbs) {
4370 pci_free_consistent(ha->pcidev,
4371 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4372 ha->scbs->sg_list.list,
4373 ha->scbs->sg_busaddr);
4374 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4375 ha->scbs, ha->scbs->scb_busaddr);
4376 ha->scbs = NULL;
4377 } /* end if */
4378 return 1;
4379}
4380
4381/****************************************************************************/
4382/* */
4383/* Routine Name: ips_allocatescbs */
4384/* */
4385/* Routine Description: */
4386/* */
4387/* Allocate the command blocks */
4388/* */
4389/****************************************************************************/
4390static int
4391ips_allocatescbs(ips_ha_t * ha)
4392{
4393 ips_scb_t *scb_p;
4394 IPS_SG_LIST ips_sg;
4395 int i;
4396 dma_addr_t command_dma, sg_dma;
4397
4398 METHOD_TRACE("ips_allocatescbs", 1);
4399
4400 /* Allocate memory for the SCBs */
4401 ha->scbs =
4402 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4403 &command_dma);
4404 if (ha->scbs == NULL)
4405 return 0;
4406 ips_sg.list =
4407 pci_alloc_consistent(ha->pcidev,
4408 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4409 ha->max_cmds, &sg_dma);
4410 if (ips_sg.list == NULL) {
4411 pci_free_consistent(ha->pcidev,
4412 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4413 command_dma);
4414 return 0;
4415 }
4416
4417 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4418
4419 for (i = 0; i < ha->max_cmds; i++) {
4420 scb_p = &ha->scbs[i];
4421 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4422 /* set up S/G list */
4423 if (IPS_USE_ENH_SGLIST(ha)) {
4424 scb_p->sg_list.enh_list =
4425 ips_sg.enh_list + i * IPS_MAX_SG;
4426 scb_p->sg_busaddr =
4427 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4428 } else {
4429 scb_p->sg_list.std_list =
4430 ips_sg.std_list + i * IPS_MAX_SG;
4431 scb_p->sg_busaddr =
4432 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4433 }
4434
4435 /* add to the free list */
4436 if (i < ha->max_cmds - 1) {
4437 scb_p->q_next = ha->scb_freelist;
4438 ha->scb_freelist = scb_p;
4439 }
4440 }
4441
4442 /* success */
4443 return (1);
4444}
4445
4446/****************************************************************************/
4447/* */
4448/* Routine Name: ips_init_scb */
4449/* */
4450/* Routine Description: */
4451/* */
4452/* Initialize a CCB to default values */
4453/* */
4454/****************************************************************************/
4455static void
4456ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4457{
4458 IPS_SG_LIST sg_list;
4459 uint32_t cmd_busaddr, sg_busaddr;
4460 METHOD_TRACE("ips_init_scb", 1);
4461
4462 if (scb == NULL)
4463 return;
4464
4465 sg_list.list = scb->sg_list.list;
4466 cmd_busaddr = scb->scb_busaddr;
4467 sg_busaddr = scb->sg_busaddr;
4468 /* zero fill */
4469 memset(scb, 0, sizeof (ips_scb_t));
4470 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4471
4472 /* Initialize dummy command bucket */
4473 ha->dummy->op_code = 0xFF;
4474 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4475 + sizeof (IPS_ADAPTER));
4476 ha->dummy->command_id = IPS_MAX_CMDS;
4477
4478 /* set bus address of scb */
4479 scb->scb_busaddr = cmd_busaddr;
4480 scb->sg_busaddr = sg_busaddr;
4481 scb->sg_list.list = sg_list.list;
4482
4483 /* Neptune Fix */
4484 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4485 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4486 + sizeof (IPS_ADAPTER));
4487}
4488
4489/****************************************************************************/
4490/* */
4491/* Routine Name: ips_get_scb */
4492/* */
4493/* Routine Description: */
4494/* */
4495/* Initialize a CCB to default values */
4496/* */
4497/* ASSUMED to be callled from within a lock */
4498/* */
4499/****************************************************************************/
4500static ips_scb_t *
4501ips_getscb(ips_ha_t * ha)
4502{
4503 ips_scb_t *scb;
4504
4505 METHOD_TRACE("ips_getscb", 1);
4506
4507 if ((scb = ha->scb_freelist) == NULL) {
4508
4509 return (NULL);
4510 }
4511
4512 ha->scb_freelist = scb->q_next;
4513 scb->flags = 0;
4514 scb->q_next = NULL;
4515
4516 ips_init_scb(ha, scb);
4517
4518 return (scb);
4519}
4520
4521/****************************************************************************/
4522/* */
4523/* Routine Name: ips_free_scb */
4524/* */
4525/* Routine Description: */
4526/* */
4527/* Return an unused CCB back to the free list */
4528/* */
4529/* ASSUMED to be called from within a lock */
4530/* */
4531/****************************************************************************/
4532static void
4533ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4534{
4535
4536 METHOD_TRACE("ips_freescb", 1);
4537 if (scb->flags & IPS_SCB_MAP_SG)
4538 scsi_dma_unmap(scb->scsi_cmd);
4539 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4540 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4541 IPS_DMA_DIR(scb));
4542
4543 /* check to make sure this is not our "special" scb */
4544 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4545 scb->q_next = ha->scb_freelist;
4546 ha->scb_freelist = scb;
4547 }
4548}
4549
4550/****************************************************************************/
4551/* */
4552/* Routine Name: ips_isinit_copperhead */
4553/* */
4554/* Routine Description: */
4555/* */
4556/* Is controller initialized ? */
4557/* */
4558/****************************************************************************/
4559static int
4560ips_isinit_copperhead(ips_ha_t * ha)
4561{
4562 uint8_t scpr;
4563 uint8_t isr;
4564
4565 METHOD_TRACE("ips_isinit_copperhead", 1);
4566
4567 isr = inb(ha->io_addr + IPS_REG_HISR);
4568 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4569
4570 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4571 return (0);
4572 else
4573 return (1);
4574}
4575
4576/****************************************************************************/
4577/* */
4578/* Routine Name: ips_isinit_copperhead_memio */
4579/* */
4580/* Routine Description: */
4581/* */
4582/* Is controller initialized ? */
4583/* */
4584/****************************************************************************/
4585static int
4586ips_isinit_copperhead_memio(ips_ha_t * ha)
4587{
4588 uint8_t isr = 0;
4589 uint8_t scpr;
4590
4591 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4592
4593 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4594 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4595
4596 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4597 return (0);
4598 else
4599 return (1);
4600}
4601
4602/****************************************************************************/
4603/* */
4604/* Routine Name: ips_isinit_morpheus */
4605/* */
4606/* Routine Description: */
4607/* */
4608/* Is controller initialized ? */
4609/* */
4610/****************************************************************************/
4611static int
4612ips_isinit_morpheus(ips_ha_t * ha)
4613{
4614 uint32_t post;
4615 uint32_t bits;
4616
4617 METHOD_TRACE("ips_is_init_morpheus", 1);
4618
4619 if (ips_isintr_morpheus(ha))
4620 ips_flush_and_reset(ha);
4621
4622 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4623 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4624
4625 if (post == 0)
4626 return (0);
4627 else if (bits & 0x3)
4628 return (0);
4629 else
4630 return (1);
4631}
4632
4633/****************************************************************************/
4634/* */
4635/* Routine Name: ips_flush_and_reset */
4636/* */
4637/* Routine Description: */
4638/* */
4639/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4640/* state ( was trying to INIT and an interrupt was already pending ) ... */
4641/* */
4642/****************************************************************************/
4643static void
4644ips_flush_and_reset(ips_ha_t *ha)
4645{
4646 ips_scb_t *scb;
4647 int ret;
4648 int time;
4649 int done;
4650 dma_addr_t command_dma;
4651
4652 /* Create a usuable SCB */
4653 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4654 if (scb) {
4655 memset(scb, 0, sizeof(ips_scb_t));
4656 ips_init_scb(ha, scb);
4657 scb->scb_busaddr = command_dma;
4658
4659 scb->timeout = ips_cmd_timeout;
4660 scb->cdb[0] = IPS_CMD_FLUSH;
4661
4662 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4663 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4664 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4665 scb->cmd.flush_cache.reserved = 0;
4666 scb->cmd.flush_cache.reserved2 = 0;
4667 scb->cmd.flush_cache.reserved3 = 0;
4668 scb->cmd.flush_cache.reserved4 = 0;
4669
4670 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4671
4672 if (ret == IPS_SUCCESS) {
4673 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4674 done = 0;
4675
4676 while ((time > 0) && (!done)) {
4677 done = ips_poll_for_flush_complete(ha);
4678 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4679 udelay(1000);
4680 time--;
4681 }
4682 }
4683 }
4684
4685 /* Now RESET and INIT the adapter */
4686 (*ha->func.reset) (ha);
4687
4688 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4689 return;
4690}
4691
4692/****************************************************************************/
4693/* */
4694/* Routine Name: ips_poll_for_flush_complete */
4695/* */
4696/* Routine Description: */
4697/* */
4698/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4699/* All other responses are just taken off the queue and ignored */
4700/* */
4701/****************************************************************************/
4702static int
4703ips_poll_for_flush_complete(ips_ha_t * ha)
4704{
4705 IPS_STATUS cstatus;
4706
4707 while (TRUE) {
4708 cstatus.value = (*ha->func.statupd) (ha);
4709
4710 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4711 break;
4712
4713 /* Success is when we see the Flush Command ID */
4714 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4715 return 1;
4716 }
4717
4718 return 0;
4719}
4720
4721/****************************************************************************/
4722/* */
4723/* Routine Name: ips_enable_int_copperhead */
4724/* */
4725/* Routine Description: */
4726/* Turn on interrupts */
4727/* */
4728/****************************************************************************/
4729static void
4730ips_enable_int_copperhead(ips_ha_t * ha)
4731{
4732 METHOD_TRACE("ips_enable_int_copperhead", 1);
4733
4734 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4735 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4736}
4737
4738/****************************************************************************/
4739/* */
4740/* Routine Name: ips_enable_int_copperhead_memio */
4741/* */
4742/* Routine Description: */
4743/* Turn on interrupts */
4744/* */
4745/****************************************************************************/
4746static void
4747ips_enable_int_copperhead_memio(ips_ha_t * ha)
4748{
4749 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4750
4751 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4752 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4753}
4754
4755/****************************************************************************/
4756/* */
4757/* Routine Name: ips_enable_int_morpheus */
4758/* */
4759/* Routine Description: */
4760/* Turn on interrupts */
4761/* */
4762/****************************************************************************/
4763static void
4764ips_enable_int_morpheus(ips_ha_t * ha)
4765{
4766 uint32_t Oimr;
4767
4768 METHOD_TRACE("ips_enable_int_morpheus", 1);
4769
4770 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4771 Oimr &= ~0x08;
4772 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4773 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4774}
4775
4776/****************************************************************************/
4777/* */
4778/* Routine Name: ips_init_copperhead */
4779/* */
4780/* Routine Description: */
4781/* */
4782/* Initialize a copperhead controller */
4783/* */
4784/****************************************************************************/
4785static int
4786ips_init_copperhead(ips_ha_t * ha)
4787{
4788 uint8_t Isr;
4789 uint8_t Cbsp;
4790 uint8_t PostByte[IPS_MAX_POST_BYTES];
4791 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4792 int i, j;
4793
4794 METHOD_TRACE("ips_init_copperhead", 1);
4795
4796 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4797 for (j = 0; j < 45; j++) {
4798 Isr = inb(ha->io_addr + IPS_REG_HISR);
4799 if (Isr & IPS_BIT_GHI)
4800 break;
4801
4802 /* Delay for 1 Second */
4803 MDELAY(IPS_ONE_SEC);
4804 }
4805
4806 if (j >= 45)
4807 /* error occurred */
4808 return (0);
4809
4810 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4811 outb(Isr, ha->io_addr + IPS_REG_HISR);
4812 }
4813
4814 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4815 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4816 "reset controller fails (post status %x %x).\n",
4817 PostByte[0], PostByte[1]);
4818
4819 return (0);
4820 }
4821
4822 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4823 for (j = 0; j < 240; j++) {
4824 Isr = inb(ha->io_addr + IPS_REG_HISR);
4825 if (Isr & IPS_BIT_GHI)
4826 break;
4827
4828 /* Delay for 1 Second */
4829 MDELAY(IPS_ONE_SEC);
4830 }
4831
4832 if (j >= 240)
4833 /* error occurred */
4834 return (0);
4835
4836 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4837 outb(Isr, ha->io_addr + IPS_REG_HISR);
4838 }
4839
4840 for (i = 0; i < 240; i++) {
4841 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4842
4843 if ((Cbsp & IPS_BIT_OP) == 0)
4844 break;
4845
4846 /* Delay for 1 Second */
4847 MDELAY(IPS_ONE_SEC);
4848 }
4849
4850 if (i >= 240)
4851 /* reset failed */
4852 return (0);
4853
4854 /* setup CCCR */
4855 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4856
4857 /* Enable busmastering */
4858 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4859
4860 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4861 /* fix for anaconda64 */
4862 outl(0, ha->io_addr + IPS_REG_NDAE);
4863
4864 /* Enable interrupts */
4865 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4866
4867 return (1);
4868}
4869
4870/****************************************************************************/
4871/* */
4872/* Routine Name: ips_init_copperhead_memio */
4873/* */
4874/* Routine Description: */
4875/* */
4876/* Initialize a copperhead controller with memory mapped I/O */
4877/* */
4878/****************************************************************************/
4879static int
4880ips_init_copperhead_memio(ips_ha_t * ha)
4881{
4882 uint8_t Isr = 0;
4883 uint8_t Cbsp;
4884 uint8_t PostByte[IPS_MAX_POST_BYTES];
4885 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4886 int i, j;
4887
4888 METHOD_TRACE("ips_init_copperhead_memio", 1);
4889
4890 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4891 for (j = 0; j < 45; j++) {
4892 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4893 if (Isr & IPS_BIT_GHI)
4894 break;
4895
4896 /* Delay for 1 Second */
4897 MDELAY(IPS_ONE_SEC);
4898 }
4899
4900 if (j >= 45)
4901 /* error occurred */
4902 return (0);
4903
4904 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4905 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4906 }
4907
4908 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4909 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4910 "reset controller fails (post status %x %x).\n",
4911 PostByte[0], PostByte[1]);
4912
4913 return (0);
4914 }
4915
4916 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4917 for (j = 0; j < 240; j++) {
4918 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4919 if (Isr & IPS_BIT_GHI)
4920 break;
4921
4922 /* Delay for 1 Second */
4923 MDELAY(IPS_ONE_SEC);
4924 }
4925
4926 if (j >= 240)
4927 /* error occurred */
4928 return (0);
4929
4930 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4931 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4932 }
4933
4934 for (i = 0; i < 240; i++) {
4935 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4936
4937 if ((Cbsp & IPS_BIT_OP) == 0)
4938 break;
4939
4940 /* Delay for 1 Second */
4941 MDELAY(IPS_ONE_SEC);
4942 }
4943
4944 if (i >= 240)
4945 /* error occurred */
4946 return (0);
4947
4948 /* setup CCCR */
4949 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4950
4951 /* Enable busmastering */
4952 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4953
4954 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4955 /* fix for anaconda64 */
4956 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4957
4958 /* Enable interrupts */
4959 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4960
4961 /* if we get here then everything went OK */
4962 return (1);
4963}
4964
4965/****************************************************************************/
4966/* */
4967/* Routine Name: ips_init_morpheus */
4968/* */
4969/* Routine Description: */
4970/* */
4971/* Initialize a morpheus controller */
4972/* */
4973/****************************************************************************/
4974static int
4975ips_init_morpheus(ips_ha_t * ha)
4976{
4977 uint32_t Post;
4978 uint32_t Config;
4979 uint32_t Isr;
4980 uint32_t Oimr;
4981 int i;
4982
4983 METHOD_TRACE("ips_init_morpheus", 1);
4984
4985 /* Wait up to 45 secs for Post */
4986 for (i = 0; i < 45; i++) {
4987 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4988
4989 if (Isr & IPS_BIT_I960_MSG0I)
4990 break;
4991
4992 /* Delay for 1 Second */
4993 MDELAY(IPS_ONE_SEC);
4994 }
4995
4996 if (i >= 45) {
4997 /* error occurred */
4998 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4999 "timeout waiting for post.\n");
5000
5001 return (0);
5002 }
5003
5004 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5005
5006 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5007 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5008 "Flashing Battery PIC, Please wait ...\n");
5009
5010 /* Clear the interrupt bit */
5011 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5012 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5013
5014 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5015 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5016 if (Post != 0x4F00)
5017 break;
5018 /* Delay for 1 Second */
5019 MDELAY(IPS_ONE_SEC);
5020 }
5021
5022 if (i >= 120) {
5023 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5024 "timeout waiting for Battery PIC Flash\n");
5025 return (0);
5026 }
5027
5028 }
5029
5030 /* Clear the interrupt bit */
5031 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5032 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5033
5034 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5035 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5036 "reset controller fails (post status %x).\n", Post);
5037
5038 return (0);
5039 }
5040
5041 /* Wait up to 240 secs for config bytes */
5042 for (i = 0; i < 240; i++) {
5043 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5044
5045 if (Isr & IPS_BIT_I960_MSG1I)
5046 break;
5047
5048 /* Delay for 1 Second */
5049 MDELAY(IPS_ONE_SEC);
5050 }
5051
5052 if (i >= 240) {
5053 /* error occurred */
5054 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5055 "timeout waiting for config.\n");
5056
5057 return (0);
5058 }
5059
5060 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5061
5062 /* Clear interrupt bit */
5063 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5064 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5065
5066 /* Turn on the interrupts */
5067 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5068 Oimr &= ~0x8;
5069 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5070
5071 /* if we get here then everything went OK */
5072
5073 /* Since we did a RESET, an EraseStripeLock may be needed */
5074 if (Post == 0xEF10) {
5075 if ((Config == 0x000F) || (Config == 0x0009))
5076 ha->requires_esl = 1;
5077 }
5078
5079 return (1);
5080}
5081
5082/****************************************************************************/
5083/* */
5084/* Routine Name: ips_reset_copperhead */
5085/* */
5086/* Routine Description: */
5087/* */
5088/* Reset the controller */
5089/* */
5090/****************************************************************************/
5091static int
5092ips_reset_copperhead(ips_ha_t * ha)
5093{
5094 int reset_counter;
5095
5096 METHOD_TRACE("ips_reset_copperhead", 1);
5097
5098 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5099 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5100
5101 reset_counter = 0;
5102
5103 while (reset_counter < 2) {
5104 reset_counter++;
5105
5106 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5107
5108 /* Delay for 1 Second */
5109 MDELAY(IPS_ONE_SEC);
5110
5111 outb(0, ha->io_addr + IPS_REG_SCPR);
5112
5113 /* Delay for 1 Second */
5114 MDELAY(IPS_ONE_SEC);
5115
5116 if ((*ha->func.init) (ha))
5117 break;
5118 else if (reset_counter >= 2) {
5119
5120 return (0);
5121 }
5122 }
5123
5124 return (1);
5125}
5126
5127/****************************************************************************/
5128/* */
5129/* Routine Name: ips_reset_copperhead_memio */
5130/* */
5131/* Routine Description: */
5132/* */
5133/* Reset the controller */
5134/* */
5135/****************************************************************************/
5136static int
5137ips_reset_copperhead_memio(ips_ha_t * ha)
5138{
5139 int reset_counter;
5140
5141 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5142
5143 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5144 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5145
5146 reset_counter = 0;
5147
5148 while (reset_counter < 2) {
5149 reset_counter++;
5150
5151 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5152
5153 /* Delay for 1 Second */
5154 MDELAY(IPS_ONE_SEC);
5155
5156 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5157
5158 /* Delay for 1 Second */
5159 MDELAY(IPS_ONE_SEC);
5160
5161 if ((*ha->func.init) (ha))
5162 break;
5163 else if (reset_counter >= 2) {
5164
5165 return (0);
5166 }
5167 }
5168
5169 return (1);
5170}
5171
5172/****************************************************************************/
5173/* */
5174/* Routine Name: ips_reset_morpheus */
5175/* */
5176/* Routine Description: */
5177/* */
5178/* Reset the controller */
5179/* */
5180/****************************************************************************/
5181static int
5182ips_reset_morpheus(ips_ha_t * ha)
5183{
5184 int reset_counter;
5185 uint8_t junk;
5186
5187 METHOD_TRACE("ips_reset_morpheus", 1);
5188
5189 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5190 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5191
5192 reset_counter = 0;
5193
5194 while (reset_counter < 2) {
5195 reset_counter++;
5196
5197 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5198
5199 /* Delay for 5 Seconds */
5200 MDELAY(5 * IPS_ONE_SEC);
5201
5202 /* Do a PCI config read to wait for adapter */
5203 pci_read_config_byte(ha->pcidev, 4, &junk);
5204
5205 if ((*ha->func.init) (ha))
5206 break;
5207 else if (reset_counter >= 2) {
5208
5209 return (0);
5210 }
5211 }
5212
5213 return (1);
5214}
5215
5216/****************************************************************************/
5217/* */
5218/* Routine Name: ips_statinit */
5219/* */
5220/* Routine Description: */
5221/* */
5222/* Initialize the status queues on the controller */
5223/* */
5224/****************************************************************************/
5225static void
5226ips_statinit(ips_ha_t * ha)
5227{
5228 uint32_t phys_status_start;
5229
5230 METHOD_TRACE("ips_statinit", 1);
5231
5232 ha->adapt->p_status_start = ha->adapt->status;
5233 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5234 ha->adapt->p_status_tail = ha->adapt->status;
5235
5236 phys_status_start = ha->adapt->hw_status_start;
5237 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5238 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5239 ha->io_addr + IPS_REG_SQER);
5240 outl(phys_status_start + IPS_STATUS_SIZE,
5241 ha->io_addr + IPS_REG_SQHR);
5242 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5243
5244 ha->adapt->hw_status_tail = phys_status_start;
5245}
5246
5247/****************************************************************************/
5248/* */
5249/* Routine Name: ips_statinit_memio */
5250/* */
5251/* Routine Description: */
5252/* */
5253/* Initialize the status queues on the controller */
5254/* */
5255/****************************************************************************/
5256static void
5257ips_statinit_memio(ips_ha_t * ha)
5258{
5259 uint32_t phys_status_start;
5260
5261 METHOD_TRACE("ips_statinit_memio", 1);
5262
5263 ha->adapt->p_status_start = ha->adapt->status;
5264 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5265 ha->adapt->p_status_tail = ha->adapt->status;
5266
5267 phys_status_start = ha->adapt->hw_status_start;
5268 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5269 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5270 ha->mem_ptr + IPS_REG_SQER);
5271 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5272 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5273
5274 ha->adapt->hw_status_tail = phys_status_start;
5275}
5276
5277/****************************************************************************/
5278/* */
5279/* Routine Name: ips_statupd_copperhead */
5280/* */
5281/* Routine Description: */
5282/* */
5283/* Remove an element from the status queue */
5284/* */
5285/****************************************************************************/
5286static uint32_t
5287ips_statupd_copperhead(ips_ha_t * ha)
5288{
5289 METHOD_TRACE("ips_statupd_copperhead", 1);
5290
5291 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5292 ha->adapt->p_status_tail++;
5293 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5294 } else {
5295 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5296 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5297 }
5298
5299 outl(ha->adapt->hw_status_tail,
5300 ha->io_addr + IPS_REG_SQTR);
5301
5302 return (ha->adapt->p_status_tail->value);
5303}
5304
5305/****************************************************************************/
5306/* */
5307/* Routine Name: ips_statupd_copperhead_memio */
5308/* */
5309/* Routine Description: */
5310/* */
5311/* Remove an element from the status queue */
5312/* */
5313/****************************************************************************/
5314static uint32_t
5315ips_statupd_copperhead_memio(ips_ha_t * ha)
5316{
5317 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5318
5319 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5320 ha->adapt->p_status_tail++;
5321 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5322 } else {
5323 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5324 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5325 }
5326
5327 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5328
5329 return (ha->adapt->p_status_tail->value);
5330}
5331
5332/****************************************************************************/
5333/* */
5334/* Routine Name: ips_statupd_morpheus */
5335/* */
5336/* Routine Description: */
5337/* */
5338/* Remove an element from the status queue */
5339/* */
5340/****************************************************************************/
5341static uint32_t
5342ips_statupd_morpheus(ips_ha_t * ha)
5343{
5344 uint32_t val;
5345
5346 METHOD_TRACE("ips_statupd_morpheus", 1);
5347
5348 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5349
5350 return (val);
5351}
5352
5353/****************************************************************************/
5354/* */
5355/* Routine Name: ips_issue_copperhead */
5356/* */
5357/* Routine Description: */
5358/* */
5359/* Send a command down to the controller */
5360/* */
5361/****************************************************************************/
5362static int
5363ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5364{
5365 uint32_t TimeOut;
5366 uint32_t val;
5367
5368 METHOD_TRACE("ips_issue_copperhead", 1);
5369
5370 if (scb->scsi_cmd) {
5371 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5372 ips_name,
5373 ha->host_num,
5374 scb->cdb[0],
5375 scb->cmd.basic_io.command_id,
5376 scb->bus, scb->target_id, scb->lun);
5377 } else {
5378 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5379 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5380 }
5381
5382 TimeOut = 0;
5383
5384 while ((val =
5385 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5386 udelay(1000);
5387
5388 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5389 if (!(val & IPS_BIT_START_STOP))
5390 break;
5391
5392 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5393 "ips_issue val [0x%x].\n", val);
5394 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5395 "ips_issue semaphore chk timeout.\n");
5396
5397 return (IPS_FAILURE);
5398 } /* end if */
5399 } /* end while */
5400
5401 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5402 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5403
5404 return (IPS_SUCCESS);
5405}
5406
5407/****************************************************************************/
5408/* */
5409/* Routine Name: ips_issue_copperhead_memio */
5410/* */
5411/* Routine Description: */
5412/* */
5413/* Send a command down to the controller */
5414/* */
5415/****************************************************************************/
5416static int
5417ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5418{
5419 uint32_t TimeOut;
5420 uint32_t val;
5421
5422 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5423
5424 if (scb->scsi_cmd) {
5425 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5426 ips_name,
5427 ha->host_num,
5428 scb->cdb[0],
5429 scb->cmd.basic_io.command_id,
5430 scb->bus, scb->target_id, scb->lun);
5431 } else {
5432 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5433 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5434 }
5435
5436 TimeOut = 0;
5437
5438 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5439 udelay(1000);
5440
5441 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5442 if (!(val & IPS_BIT_START_STOP))
5443 break;
5444
5445 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5446 "ips_issue val [0x%x].\n", val);
5447 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5448 "ips_issue semaphore chk timeout.\n");
5449
5450 return (IPS_FAILURE);
5451 } /* end if */
5452 } /* end while */
5453
5454 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5455 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5456
5457 return (IPS_SUCCESS);
5458}
5459
5460/****************************************************************************/
5461/* */
5462/* Routine Name: ips_issue_i2o */
5463/* */
5464/* Routine Description: */
5465/* */
5466/* Send a command down to the controller */
5467/* */
5468/****************************************************************************/
5469static int
5470ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5471{
5472
5473 METHOD_TRACE("ips_issue_i2o", 1);
5474
5475 if (scb->scsi_cmd) {
5476 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5477 ips_name,
5478 ha->host_num,
5479 scb->cdb[0],
5480 scb->cmd.basic_io.command_id,
5481 scb->bus, scb->target_id, scb->lun);
5482 } else {
5483 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5484 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5485 }
5486
5487 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5488
5489 return (IPS_SUCCESS);
5490}
5491
5492/****************************************************************************/
5493/* */
5494/* Routine Name: ips_issue_i2o_memio */
5495/* */
5496/* Routine Description: */
5497/* */
5498/* Send a command down to the controller */
5499/* */
5500/****************************************************************************/
5501static int
5502ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5503{
5504
5505 METHOD_TRACE("ips_issue_i2o_memio", 1);
5506
5507 if (scb->scsi_cmd) {
5508 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5509 ips_name,
5510 ha->host_num,
5511 scb->cdb[0],
5512 scb->cmd.basic_io.command_id,
5513 scb->bus, scb->target_id, scb->lun);
5514 } else {
5515 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5516 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5517 }
5518
5519 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5520
5521 return (IPS_SUCCESS);
5522}
5523
5524/****************************************************************************/
5525/* */
5526/* Routine Name: ips_isintr_copperhead */
5527/* */
5528/* Routine Description: */
5529/* */
5530/* Test to see if an interrupt is for us */
5531/* */
5532/****************************************************************************/
5533static int
5534ips_isintr_copperhead(ips_ha_t * ha)
5535{
5536 uint8_t Isr;
5537
5538 METHOD_TRACE("ips_isintr_copperhead", 2);
5539
5540 Isr = inb(ha->io_addr + IPS_REG_HISR);
5541
5542 if (Isr == 0xFF)
5543 /* ?!?! Nothing really there */
5544 return (0);
5545
5546 if (Isr & IPS_BIT_SCE)
5547 return (1);
5548 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5549 /* status queue overflow or GHI */
5550 /* just clear the interrupt */
5551 outb(Isr, ha->io_addr + IPS_REG_HISR);
5552 }
5553
5554 return (0);
5555}
5556
5557/****************************************************************************/
5558/* */
5559/* Routine Name: ips_isintr_copperhead_memio */
5560/* */
5561/* Routine Description: */
5562/* */
5563/* Test to see if an interrupt is for us */
5564/* */
5565/****************************************************************************/
5566static int
5567ips_isintr_copperhead_memio(ips_ha_t * ha)
5568{
5569 uint8_t Isr;
5570
5571 METHOD_TRACE("ips_isintr_memio", 2);
5572
5573 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5574
5575 if (Isr == 0xFF)
5576 /* ?!?! Nothing really there */
5577 return (0);
5578
5579 if (Isr & IPS_BIT_SCE)
5580 return (1);
5581 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5582 /* status queue overflow or GHI */
5583 /* just clear the interrupt */
5584 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5585 }
5586
5587 return (0);
5588}
5589
5590/****************************************************************************/
5591/* */
5592/* Routine Name: ips_isintr_morpheus */
5593/* */
5594/* Routine Description: */
5595/* */
5596/* Test to see if an interrupt is for us */
5597/* */
5598/****************************************************************************/
5599static int
5600ips_isintr_morpheus(ips_ha_t * ha)
5601{
5602 uint32_t Isr;
5603
5604 METHOD_TRACE("ips_isintr_morpheus", 2);
5605
5606 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5607
5608 if (Isr & IPS_BIT_I2O_OPQI)
5609 return (1);
5610 else
5611 return (0);
5612}
5613
5614/****************************************************************************/
5615/* */
5616/* Routine Name: ips_wait */
5617/* */
5618/* Routine Description: */
5619/* */
5620/* Wait for a command to complete */
5621/* */
5622/****************************************************************************/
5623static int
5624ips_wait(ips_ha_t * ha, int time, int intr)
5625{
5626 int ret;
5627 int done;
5628
5629 METHOD_TRACE("ips_wait", 1);
5630
5631 ret = IPS_FAILURE;
5632 done = FALSE;
5633
5634 time *= IPS_ONE_SEC; /* convert seconds */
5635
5636 while ((time > 0) && (!done)) {
5637 if (intr == IPS_INTR_ON) {
5638 if (ha->waitflag == FALSE) {
5639 ret = IPS_SUCCESS;
5640 done = TRUE;
5641 break;
5642 }
5643 } else if (intr == IPS_INTR_IORL) {
5644 if (ha->waitflag == FALSE) {
5645 /*
5646 * controller generated an interrupt to
5647 * acknowledge completion of the command
5648 * and ips_intr() has serviced the interrupt.
5649 */
5650 ret = IPS_SUCCESS;
5651 done = TRUE;
5652 break;
5653 }
5654
5655 /*
5656 * NOTE: we already have the io_request_lock so
5657 * even if we get an interrupt it won't get serviced
5658 * until after we finish.
5659 */
5660
5661 (*ha->func.intr) (ha);
5662 }
5663
5664 /* This looks like a very evil loop, but it only does this during start-up */
5665 udelay(1000);
5666 time--;
5667 }
5668
5669 return (ret);
5670}
5671
5672/****************************************************************************/
5673/* */
5674/* Routine Name: ips_write_driver_status */
5675/* */
5676/* Routine Description: */
5677/* */
5678/* Write OS/Driver version to Page 5 of the nvram on the controller */
5679/* */
5680/****************************************************************************/
5681static int
5682ips_write_driver_status(ips_ha_t * ha, int intr)
5683{
5684 METHOD_TRACE("ips_write_driver_status", 1);
5685
5686 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5687 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5688 "unable to read NVRAM page 5.\n");
5689
5690 return (0);
5691 }
5692
5693 /* check to make sure the page has a valid */
5694 /* signature */
5695 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5696 DEBUG_VAR(1,
5697 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5698 ips_name, ha->host_num, ha->nvram->signature);
5699 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5700 }
5701
5702 DEBUG_VAR(2,
5703 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5704 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5705 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5706 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5707 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5708 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5709 ha->nvram->bios_low[3]);
5710
5711 ips_get_bios_version(ha, intr);
5712
5713 /* change values (as needed) */
5714 ha->nvram->operating_system = IPS_OS_LINUX;
5715 ha->nvram->adapter_type = ha->ad_type;
5716 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5717 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5718 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5719 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5720
5721 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5722
5723 /* now update the page */
5724 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5725 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5726 "unable to write NVRAM page 5.\n");
5727
5728 return (0);
5729 }
5730
5731 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5732 ha->slot_num = ha->nvram->adapter_slot;
5733
5734 return (1);
5735}
5736
5737/****************************************************************************/
5738/* */
5739/* Routine Name: ips_read_adapter_status */
5740/* */
5741/* Routine Description: */
5742/* */
5743/* Do an Inquiry command to the adapter */
5744/* */
5745/****************************************************************************/
5746static int
5747ips_read_adapter_status(ips_ha_t * ha, int intr)
5748{
5749 ips_scb_t *scb;
5750 int ret;
5751
5752 METHOD_TRACE("ips_read_adapter_status", 1);
5753
5754 scb = &ha->scbs[ha->max_cmds - 1];
5755
5756 ips_init_scb(ha, scb);
5757
5758 scb->timeout = ips_cmd_timeout;
5759 scb->cdb[0] = IPS_CMD_ENQUIRY;
5760
5761 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5762 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5763 scb->cmd.basic_io.sg_count = 0;
5764 scb->cmd.basic_io.lba = 0;
5765 scb->cmd.basic_io.sector_count = 0;
5766 scb->cmd.basic_io.log_drv = 0;
5767 scb->data_len = sizeof (*ha->enq);
5768 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5769
5770 /* send command */
5771 if (((ret =
5772 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5773 || (ret == IPS_SUCCESS_IMM)
5774 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5775 return (0);
5776
5777 return (1);
5778}
5779
5780/****************************************************************************/
5781/* */
5782/* Routine Name: ips_read_subsystem_parameters */
5783/* */
5784/* Routine Description: */
5785/* */
5786/* Read subsystem parameters from the adapter */
5787/* */
5788/****************************************************************************/
5789static int
5790ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5791{
5792 ips_scb_t *scb;
5793 int ret;
5794
5795 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5796
5797 scb = &ha->scbs[ha->max_cmds - 1];
5798
5799 ips_init_scb(ha, scb);
5800
5801 scb->timeout = ips_cmd_timeout;
5802 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5803
5804 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5805 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5806 scb->cmd.basic_io.sg_count = 0;
5807 scb->cmd.basic_io.lba = 0;
5808 scb->cmd.basic_io.sector_count = 0;
5809 scb->cmd.basic_io.log_drv = 0;
5810 scb->data_len = sizeof (*ha->subsys);
5811 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5812
5813 /* send command */
5814 if (((ret =
5815 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5816 || (ret == IPS_SUCCESS_IMM)
5817 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5818 return (0);
5819
5820 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5821 return (1);
5822}
5823
5824/****************************************************************************/
5825/* */
5826/* Routine Name: ips_read_config */
5827/* */
5828/* Routine Description: */
5829/* */
5830/* Read the configuration on the adapter */
5831/* */
5832/****************************************************************************/
5833static int
5834ips_read_config(ips_ha_t * ha, int intr)
5835{
5836 ips_scb_t *scb;
5837 int i;
5838 int ret;
5839
5840 METHOD_TRACE("ips_read_config", 1);
5841
5842 /* set defaults for initiator IDs */
5843 for (i = 0; i < 4; i++)
5844 ha->conf->init_id[i] = 7;
5845
5846 scb = &ha->scbs[ha->max_cmds - 1];
5847
5848 ips_init_scb(ha, scb);
5849
5850 scb->timeout = ips_cmd_timeout;
5851 scb->cdb[0] = IPS_CMD_READ_CONF;
5852
5853 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5854 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5855 scb->data_len = sizeof (*ha->conf);
5856 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5857
5858 /* send command */
5859 if (((ret =
5860 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5861 || (ret == IPS_SUCCESS_IMM)
5862 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5863
5864 memset(ha->conf, 0, sizeof (IPS_CONF));
5865
5866 /* reset initiator IDs */
5867 for (i = 0; i < 4; i++)
5868 ha->conf->init_id[i] = 7;
5869
5870 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5871 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5872 IPS_CMD_CMPLT_WERROR)
5873 return (1);
5874
5875 return (0);
5876 }
5877
5878 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5879 return (1);
5880}
5881
5882/****************************************************************************/
5883/* */
5884/* Routine Name: ips_readwrite_page5 */
5885/* */
5886/* Routine Description: */
5887/* */
5888/* Read nvram page 5 from the adapter */
5889/* */
5890/****************************************************************************/
5891static int
5892ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5893{
5894 ips_scb_t *scb;
5895 int ret;
5896
5897 METHOD_TRACE("ips_readwrite_page5", 1);
5898
5899 scb = &ha->scbs[ha->max_cmds - 1];
5900
5901 ips_init_scb(ha, scb);
5902
5903 scb->timeout = ips_cmd_timeout;
5904 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5905
5906 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5907 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5908 scb->cmd.nvram.page = 5;
5909 scb->cmd.nvram.write = write;
5910 scb->cmd.nvram.reserved = 0;
5911 scb->cmd.nvram.reserved2 = 0;
5912 scb->data_len = sizeof (*ha->nvram);
5913 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5914 if (write)
5915 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5916
5917 /* issue the command */
5918 if (((ret =
5919 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5920 || (ret == IPS_SUCCESS_IMM)
5921 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5922
5923 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5924
5925 return (0);
5926 }
5927 if (!write)
5928 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5929 return (1);
5930}
5931
5932/****************************************************************************/
5933/* */
5934/* Routine Name: ips_clear_adapter */
5935/* */
5936/* Routine Description: */
5937/* */
5938/* Clear the stripe lock tables */
5939/* */
5940/****************************************************************************/
5941static int
5942ips_clear_adapter(ips_ha_t * ha, int intr)
5943{
5944 ips_scb_t *scb;
5945 int ret;
5946
5947 METHOD_TRACE("ips_clear_adapter", 1);
5948
5949 scb = &ha->scbs[ha->max_cmds - 1];
5950
5951 ips_init_scb(ha, scb);
5952
5953 scb->timeout = ips_reset_timeout;
5954 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5955
5956 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5957 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5958 scb->cmd.config_sync.channel = 0;
5959 scb->cmd.config_sync.source_target = IPS_POCL;
5960 scb->cmd.config_sync.reserved = 0;
5961 scb->cmd.config_sync.reserved2 = 0;
5962 scb->cmd.config_sync.reserved3 = 0;
5963
5964 /* issue command */
5965 if (((ret =
5966 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5967 || (ret == IPS_SUCCESS_IMM)
5968 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5969 return (0);
5970
5971 /* send unlock stripe command */
5972 ips_init_scb(ha, scb);
5973
5974 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5975 scb->timeout = ips_reset_timeout;
5976
5977 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5978 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5979 scb->cmd.unlock_stripe.log_drv = 0;
5980 scb->cmd.unlock_stripe.control = IPS_CSL;
5981 scb->cmd.unlock_stripe.reserved = 0;
5982 scb->cmd.unlock_stripe.reserved2 = 0;
5983 scb->cmd.unlock_stripe.reserved3 = 0;
5984
5985 /* issue command */
5986 if (((ret =
5987 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5988 || (ret == IPS_SUCCESS_IMM)
5989 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5990 return (0);
5991
5992 return (1);
5993}
5994
5995/****************************************************************************/
5996/* */
5997/* Routine Name: ips_ffdc_reset */
5998/* */
5999/* Routine Description: */
6000/* */
6001/* FFDC: write reset info */
6002/* */
6003/****************************************************************************/
6004static void
6005ips_ffdc_reset(ips_ha_t * ha, int intr)
6006{
6007 ips_scb_t *scb;
6008
6009 METHOD_TRACE("ips_ffdc_reset", 1);
6010
6011 scb = &ha->scbs[ha->max_cmds - 1];
6012
6013 ips_init_scb(ha, scb);
6014
6015 scb->timeout = ips_cmd_timeout;
6016 scb->cdb[0] = IPS_CMD_FFDC;
6017 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6018 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6019 scb->cmd.ffdc.reset_count = ha->reset_count;
6020 scb->cmd.ffdc.reset_type = 0x80;
6021
6022 /* convert time to what the card wants */
6023 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6024
6025 /* issue command */
6026 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6027}
6028
6029/****************************************************************************/
6030/* */
6031/* Routine Name: ips_ffdc_time */
6032/* */
6033/* Routine Description: */
6034/* */
6035/* FFDC: write time info */
6036/* */
6037/****************************************************************************/
6038static void
6039ips_ffdc_time(ips_ha_t * ha)
6040{
6041 ips_scb_t *scb;
6042
6043 METHOD_TRACE("ips_ffdc_time", 1);
6044
6045 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6046
6047 scb = &ha->scbs[ha->max_cmds - 1];
6048
6049 ips_init_scb(ha, scb);
6050
6051 scb->timeout = ips_cmd_timeout;
6052 scb->cdb[0] = IPS_CMD_FFDC;
6053 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6054 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6055 scb->cmd.ffdc.reset_count = 0;
6056 scb->cmd.ffdc.reset_type = 0;
6057
6058 /* convert time to what the card wants */
6059 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6060
6061 /* issue command */
6062 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6063}
6064
6065/****************************************************************************/
6066/* */
6067/* Routine Name: ips_fix_ffdc_time */
6068/* */
6069/* Routine Description: */
6070/* Adjust time_t to what the card wants */
6071/* */
6072/****************************************************************************/
6073static void
6074ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6075{
6076 long days;
6077 long rem;
6078 int i;
6079 int year;
6080 int yleap;
6081 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6082 int month_lengths[12][2] = { {31, 31},
6083 {28, 29},
6084 {31, 31},
6085 {30, 30},
6086 {31, 31},
6087 {30, 30},
6088 {31, 31},
6089 {31, 31},
6090 {30, 30},
6091 {31, 31},
6092 {30, 30},
6093 {31, 31}
6094 };
6095
6096 METHOD_TRACE("ips_fix_ffdc_time", 1);
6097
6098 days = current_time / IPS_SECS_DAY;
6099 rem = current_time % IPS_SECS_DAY;
6100
6101 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6102 rem = rem % IPS_SECS_HOUR;
6103 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6104 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6105
6106 year = IPS_EPOCH_YEAR;
6107 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6108 int newy;
6109
6110 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6111 if (days < 0)
6112 --newy;
6113 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6114 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6115 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6116 year = newy;
6117 }
6118
6119 scb->cmd.ffdc.yearH = year / 100;
6120 scb->cmd.ffdc.yearL = year % 100;
6121
6122 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6123 days -= month_lengths[i][yleap];
6124
6125 scb->cmd.ffdc.month = i + 1;
6126 scb->cmd.ffdc.day = days + 1;
6127}
6128
6129/****************************************************************************
6130 * BIOS Flash Routines *
6131 ****************************************************************************/
6132
6133/****************************************************************************/
6134/* */
6135/* Routine Name: ips_erase_bios */
6136/* */
6137/* Routine Description: */
6138/* Erase the BIOS on the adapter */
6139/* */
6140/****************************************************************************/
6141static int
6142ips_erase_bios(ips_ha_t * ha)
6143{
6144 int timeout;
6145 uint8_t status = 0;
6146
6147 METHOD_TRACE("ips_erase_bios", 1);
6148
6149 status = 0;
6150
6151 /* Clear the status register */
6152 outl(0, ha->io_addr + IPS_REG_FLAP);
6153 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6154 udelay(25); /* 25 us */
6155
6156 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6157 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6158 udelay(25); /* 25 us */
6159
6160 /* Erase Setup */
6161 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6162 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6163 udelay(25); /* 25 us */
6164
6165 /* Erase Confirm */
6166 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6167 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6168 udelay(25); /* 25 us */
6169
6170 /* Erase Status */
6171 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6172 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6173 udelay(25); /* 25 us */
6174
6175 timeout = 80000; /* 80 seconds */
6176
6177 while (timeout > 0) {
6178 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6179 outl(0, ha->io_addr + IPS_REG_FLAP);
6180 udelay(25); /* 25 us */
6181 }
6182
6183 status = inb(ha->io_addr + IPS_REG_FLDP);
6184
6185 if (status & 0x80)
6186 break;
6187
6188 MDELAY(1);
6189 timeout--;
6190 }
6191
6192 /* check for timeout */
6193 if (timeout <= 0) {
6194 /* timeout */
6195
6196 /* try to suspend the erase */
6197 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6198 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6199 udelay(25); /* 25 us */
6200
6201 /* wait for 10 seconds */
6202 timeout = 10000;
6203 while (timeout > 0) {
6204 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6205 outl(0, ha->io_addr + IPS_REG_FLAP);
6206 udelay(25); /* 25 us */
6207 }
6208
6209 status = inb(ha->io_addr + IPS_REG_FLDP);
6210
6211 if (status & 0xC0)
6212 break;
6213
6214 MDELAY(1);
6215 timeout--;
6216 }
6217
6218 return (1);
6219 }
6220
6221 /* check for valid VPP */
6222 if (status & 0x08)
6223 /* VPP failure */
6224 return (1);
6225
6226 /* check for successful flash */
6227 if (status & 0x30)
6228 /* sequence error */
6229 return (1);
6230
6231 /* Otherwise, we were successful */
6232 /* clear status */
6233 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6234 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6235 udelay(25); /* 25 us */
6236
6237 /* enable reads */
6238 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6239 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6240 udelay(25); /* 25 us */
6241
6242 return (0);
6243}
6244
6245/****************************************************************************/
6246/* */
6247/* Routine Name: ips_erase_bios_memio */
6248/* */
6249/* Routine Description: */
6250/* Erase the BIOS on the adapter */
6251/* */
6252/****************************************************************************/
6253static int
6254ips_erase_bios_memio(ips_ha_t * ha)
6255{
6256 int timeout;
6257 uint8_t status;
6258
6259 METHOD_TRACE("ips_erase_bios_memio", 1);
6260
6261 status = 0;
6262
6263 /* Clear the status register */
6264 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6266 udelay(25); /* 25 us */
6267
6268 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6269 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6270 udelay(25); /* 25 us */
6271
6272 /* Erase Setup */
6273 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6274 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6275 udelay(25); /* 25 us */
6276
6277 /* Erase Confirm */
6278 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6279 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6280 udelay(25); /* 25 us */
6281
6282 /* Erase Status */
6283 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6284 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6285 udelay(25); /* 25 us */
6286
6287 timeout = 80000; /* 80 seconds */
6288
6289 while (timeout > 0) {
6290 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6291 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6292 udelay(25); /* 25 us */
6293 }
6294
6295 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6296
6297 if (status & 0x80)
6298 break;
6299
6300 MDELAY(1);
6301 timeout--;
6302 }
6303
6304 /* check for timeout */
6305 if (timeout <= 0) {
6306 /* timeout */
6307
6308 /* try to suspend the erase */
6309 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6311 udelay(25); /* 25 us */
6312
6313 /* wait for 10 seconds */
6314 timeout = 10000;
6315 while (timeout > 0) {
6316 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6317 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6318 udelay(25); /* 25 us */
6319 }
6320
6321 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6322
6323 if (status & 0xC0)
6324 break;
6325
6326 MDELAY(1);
6327 timeout--;
6328 }
6329
6330 return (1);
6331 }
6332
6333 /* check for valid VPP */
6334 if (status & 0x08)
6335 /* VPP failure */
6336 return (1);
6337
6338 /* check for successful flash */
6339 if (status & 0x30)
6340 /* sequence error */
6341 return (1);
6342
6343 /* Otherwise, we were successful */
6344 /* clear status */
6345 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6346 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6347 udelay(25); /* 25 us */
6348
6349 /* enable reads */
6350 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6351 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6352 udelay(25); /* 25 us */
6353
6354 return (0);
6355}
6356
6357/****************************************************************************/
6358/* */
6359/* Routine Name: ips_program_bios */
6360/* */
6361/* Routine Description: */
6362/* Program the BIOS on the adapter */
6363/* */
6364/****************************************************************************/
6365static int
6366ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6367 uint32_t offset)
6368{
6369 int i;
6370 int timeout;
6371 uint8_t status = 0;
6372
6373 METHOD_TRACE("ips_program_bios", 1);
6374
6375 status = 0;
6376
6377 for (i = 0; i < buffersize; i++) {
6378 /* write a byte */
6379 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6380 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6381 udelay(25); /* 25 us */
6382
6383 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6384 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6385 udelay(25); /* 25 us */
6386
6387 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6388 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6389 udelay(25); /* 25 us */
6390
6391 /* wait up to one second */
6392 timeout = 1000;
6393 while (timeout > 0) {
6394 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6395 outl(0, ha->io_addr + IPS_REG_FLAP);
6396 udelay(25); /* 25 us */
6397 }
6398
6399 status = inb(ha->io_addr + IPS_REG_FLDP);
6400
6401 if (status & 0x80)
6402 break;
6403
6404 MDELAY(1);
6405 timeout--;
6406 }
6407
6408 if (timeout == 0) {
6409 /* timeout error */
6410 outl(0, ha->io_addr + IPS_REG_FLAP);
6411 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6412 udelay(25); /* 25 us */
6413
6414 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6415 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6416 udelay(25); /* 25 us */
6417
6418 return (1);
6419 }
6420
6421 /* check the status */
6422 if (status & 0x18) {
6423 /* programming error */
6424 outl(0, ha->io_addr + IPS_REG_FLAP);
6425 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6426 udelay(25); /* 25 us */
6427
6428 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6429 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6430 udelay(25); /* 25 us */
6431
6432 return (1);
6433 }
6434 } /* end for */
6435
6436 /* Enable reading */
6437 outl(0, ha->io_addr + IPS_REG_FLAP);
6438 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6439 udelay(25); /* 25 us */
6440
6441 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6442 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6443 udelay(25); /* 25 us */
6444
6445 return (0);
6446}
6447
6448/****************************************************************************/
6449/* */
6450/* Routine Name: ips_program_bios_memio */
6451/* */
6452/* Routine Description: */
6453/* Program the BIOS on the adapter */
6454/* */
6455/****************************************************************************/
6456static int
6457ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6458 uint32_t offset)
6459{
6460 int i;
6461 int timeout;
6462 uint8_t status = 0;
6463
6464 METHOD_TRACE("ips_program_bios_memio", 1);
6465
6466 status = 0;
6467
6468 for (i = 0; i < buffersize; i++) {
6469 /* write a byte */
6470 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6471 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6472 udelay(25); /* 25 us */
6473
6474 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6475 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6476 udelay(25); /* 25 us */
6477
6478 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6479 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6480 udelay(25); /* 25 us */
6481
6482 /* wait up to one second */
6483 timeout = 1000;
6484 while (timeout > 0) {
6485 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6486 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6487 udelay(25); /* 25 us */
6488 }
6489
6490 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6491
6492 if (status & 0x80)
6493 break;
6494
6495 MDELAY(1);
6496 timeout--;
6497 }
6498
6499 if (timeout == 0) {
6500 /* timeout error */
6501 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6502 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6503 udelay(25); /* 25 us */
6504
6505 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6506 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6507 udelay(25); /* 25 us */
6508
6509 return (1);
6510 }
6511
6512 /* check the status */
6513 if (status & 0x18) {
6514 /* programming error */
6515 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6516 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6517 udelay(25); /* 25 us */
6518
6519 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6520 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6521 udelay(25); /* 25 us */
6522
6523 return (1);
6524 }
6525 } /* end for */
6526
6527 /* Enable reading */
6528 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6529 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6530 udelay(25); /* 25 us */
6531
6532 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6533 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6534 udelay(25); /* 25 us */
6535
6536 return (0);
6537}
6538
6539/****************************************************************************/
6540/* */
6541/* Routine Name: ips_verify_bios */
6542/* */
6543/* Routine Description: */
6544/* Verify the BIOS on the adapter */
6545/* */
6546/****************************************************************************/
6547static int
6548ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6549 uint32_t offset)
6550{
6551 uint8_t checksum;
6552 int i;
6553
6554 METHOD_TRACE("ips_verify_bios", 1);
6555
6556 /* test 1st byte */
6557 outl(0, ha->io_addr + IPS_REG_FLAP);
6558 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6559 udelay(25); /* 25 us */
6560
6561 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6562 return (1);
6563
6564 outl(1, ha->io_addr + IPS_REG_FLAP);
6565 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6566 udelay(25); /* 25 us */
6567 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6568 return (1);
6569
6570 checksum = 0xff;
6571 for (i = 2; i < buffersize; i++) {
6572
6573 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6574 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6575 udelay(25); /* 25 us */
6576
6577 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6578 }
6579
6580 if (checksum != 0)
6581 /* failure */
6582 return (1);
6583 else
6584 /* success */
6585 return (0);
6586}
6587
6588/****************************************************************************/
6589/* */
6590/* Routine Name: ips_verify_bios_memio */
6591/* */
6592/* Routine Description: */
6593/* Verify the BIOS on the adapter */
6594/* */
6595/****************************************************************************/
6596static int
6597ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6598 uint32_t offset)
6599{
6600 uint8_t checksum;
6601 int i;
6602
6603 METHOD_TRACE("ips_verify_bios_memio", 1);
6604
6605 /* test 1st byte */
6606 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6607 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6608 udelay(25); /* 25 us */
6609
6610 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6611 return (1);
6612
6613 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6614 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6615 udelay(25); /* 25 us */
6616 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6617 return (1);
6618
6619 checksum = 0xff;
6620 for (i = 2; i < buffersize; i++) {
6621
6622 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6623 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6624 udelay(25); /* 25 us */
6625
6626 checksum =
6627 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6628 }
6629
6630 if (checksum != 0)
6631 /* failure */
6632 return (1);
6633 else
6634 /* success */
6635 return (0);
6636}
6637
6638/****************************************************************************/
6639/* */
6640/* Routine Name: ips_abort_init */
6641/* */
6642/* Routine Description: */
6643/* cleanup routine for a failed adapter initialization */
6644/****************************************************************************/
6645static int
6646ips_abort_init(ips_ha_t * ha, int index)
6647{
6648 ha->active = 0;
6649 ips_free(ha);
6650 ips_ha[index] = NULL;
6651 ips_sh[index] = NULL;
6652 return -1;
6653}
6654
6655/****************************************************************************/
6656/* */
6657/* Routine Name: ips_shift_controllers */
6658/* */
6659/* Routine Description: */
6660/* helper function for ordering adapters */
6661/****************************************************************************/
6662static void
6663ips_shift_controllers(int lowindex, int highindex)
6664{
6665 ips_ha_t *ha_sav = ips_ha[highindex];
6666 struct Scsi_Host *sh_sav = ips_sh[highindex];
6667 int i;
6668
6669 for (i = highindex; i > lowindex; i--) {
6670 ips_ha[i] = ips_ha[i - 1];
6671 ips_sh[i] = ips_sh[i - 1];
6672 ips_ha[i]->host_num = i;
6673 }
6674 ha_sav->host_num = lowindex;
6675 ips_ha[lowindex] = ha_sav;
6676 ips_sh[lowindex] = sh_sav;
6677}
6678
6679/****************************************************************************/
6680/* */
6681/* Routine Name: ips_order_controllers */
6682/* */
6683/* Routine Description: */
6684/* place controllers is the "proper" boot order */
6685/****************************************************************************/
6686static void
6687ips_order_controllers(void)
6688{
6689 int i, j, tmp, position = 0;
6690 IPS_NVRAM_P5 *nvram;
6691 if (!ips_ha[0])
6692 return;
6693 nvram = ips_ha[0]->nvram;
6694
6695 if (nvram->adapter_order[0]) {
6696 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6697 for (j = position; j < ips_num_controllers; j++) {
6698 switch (ips_ha[j]->ad_type) {
6699 case IPS_ADTYPE_SERVERAID6M:
6700 case IPS_ADTYPE_SERVERAID7M:
6701 if (nvram->adapter_order[i] == 'M') {
6702 ips_shift_controllers(position,
6703 j);
6704 position++;
6705 }
6706 break;
6707 case IPS_ADTYPE_SERVERAID4L:
6708 case IPS_ADTYPE_SERVERAID4M:
6709 case IPS_ADTYPE_SERVERAID4MX:
6710 case IPS_ADTYPE_SERVERAID4LX:
6711 if (nvram->adapter_order[i] == 'N') {
6712 ips_shift_controllers(position,
6713 j);
6714 position++;
6715 }
6716 break;
6717 case IPS_ADTYPE_SERVERAID6I:
6718 case IPS_ADTYPE_SERVERAID5I2:
6719 case IPS_ADTYPE_SERVERAID5I1:
6720 case IPS_ADTYPE_SERVERAID7k:
6721 if (nvram->adapter_order[i] == 'S') {
6722 ips_shift_controllers(position,
6723 j);
6724 position++;
6725 }
6726 break;
6727 case IPS_ADTYPE_SERVERAID:
6728 case IPS_ADTYPE_SERVERAID2:
6729 case IPS_ADTYPE_NAVAJO:
6730 case IPS_ADTYPE_KIOWA:
6731 case IPS_ADTYPE_SERVERAID3L:
6732 case IPS_ADTYPE_SERVERAID3:
6733 case IPS_ADTYPE_SERVERAID4H:
6734 if (nvram->adapter_order[i] == 'A') {
6735 ips_shift_controllers(position,
6736 j);
6737 position++;
6738 }
6739 break;
6740 default:
6741 break;
6742 }
6743 }
6744 }
6745 /* if adapter_order[0], then ordering is complete */
6746 return;
6747 }
6748 /* old bios, use older ordering */
6749 tmp = 0;
6750 for (i = position; i < ips_num_controllers; i++) {
6751 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6752 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6753 ips_shift_controllers(position, i);
6754 position++;
6755 tmp = 1;
6756 }
6757 }
6758 /* if there were no 5I cards, then don't do any extra ordering */
6759 if (!tmp)
6760 return;
6761 for (i = position; i < ips_num_controllers; i++) {
6762 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6763 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6764 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6765 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6766 ips_shift_controllers(position, i);
6767 position++;
6768 }
6769 }
6770
6771 return;
6772}
6773
6774/****************************************************************************/
6775/* */
6776/* Routine Name: ips_register_scsi */
6777/* */
6778/* Routine Description: */
6779/* perform any registration and setup with the scsi layer */
6780/****************************************************************************/
6781static int
6782ips_register_scsi(int index)
6783{
6784 struct Scsi_Host *sh;
6785 ips_ha_t *ha, *oldha = ips_ha[index];
6786 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6787 if (!sh) {
6788 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6789 "Unable to register controller with SCSI subsystem\n");
6790 return -1;
6791 }
6792 ha = IPS_HA(sh);
6793 memcpy(ha, oldha, sizeof (ips_ha_t));
6794 free_irq(oldha->pcidev->irq, oldha);
6795 /* Install the interrupt handler with the new ha */
6796 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6798 "Unable to install interrupt handler\n");
6799 goto err_out_sh;
6800 }
6801
6802 kfree(oldha);
6803
6804 /* Store away needed values for later use */
6805 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6806 sh->sg_tablesize = sh->hostt->sg_tablesize;
6807 sh->can_queue = sh->hostt->can_queue;
6808 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6809 sh->use_clustering = sh->hostt->use_clustering;
6810 sh->max_sectors = 128;
6811
6812 sh->max_id = ha->ntargets;
6813 sh->max_lun = ha->nlun;
6814 sh->max_channel = ha->nbus - 1;
6815 sh->can_queue = ha->max_cmds - 1;
6816
6817 if (scsi_add_host(sh, &ha->pcidev->dev))
6818 goto err_out;
6819
6820 ips_sh[index] = sh;
6821 ips_ha[index] = ha;
6822
6823 scsi_scan_host(sh);
6824
6825 return 0;
6826
6827err_out:
6828 free_irq(ha->pcidev->irq, ha);
6829err_out_sh:
6830 scsi_host_put(sh);
6831 return -1;
6832}
6833
6834/*---------------------------------------------------------------------------*/
6835/* Routine Name: ips_remove_device */
6836/* */
6837/* Routine Description: */
6838/* Remove one Adapter ( Hot Plugging ) */
6839/*---------------------------------------------------------------------------*/
6840static void __devexit
6841ips_remove_device(struct pci_dev *pci_dev)
6842{
6843 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6844
6845 pci_set_drvdata(pci_dev, NULL);
6846
6847 ips_release(sh);
6848
6849 pci_release_regions(pci_dev);
6850 pci_disable_device(pci_dev);
6851}
6852
6853/****************************************************************************/
6854/* */
6855/* Routine Name: ips_module_init */
6856/* */
6857/* Routine Description: */
6858/* function called on module load */
6859/****************************************************************************/
6860static int __init
6861ips_module_init(void)
6862{
6863 if (pci_register_driver(&ips_pci_driver) < 0)
6864 return -ENODEV;
6865 ips_driver_template.module = THIS_MODULE;
6866 ips_order_controllers();
6867 if (!ips_detect(&ips_driver_template)) {
6868 pci_unregister_driver(&ips_pci_driver);
6869 return -ENODEV;
6870 }
6871 register_reboot_notifier(&ips_notifier);
6872 return 0;
6873}
6874
6875/****************************************************************************/
6876/* */
6877/* Routine Name: ips_module_exit */
6878/* */
6879/* Routine Description: */
6880/* function called on module unload */
6881/****************************************************************************/
6882static void __exit
6883ips_module_exit(void)
6884{
6885 pci_unregister_driver(&ips_pci_driver);
6886 unregister_reboot_notifier(&ips_notifier);
6887}
6888
6889module_init(ips_module_init);
6890module_exit(ips_module_exit);
6891
6892/*---------------------------------------------------------------------------*/
6893/* Routine Name: ips_insert_device */
6894/* */
6895/* Routine Description: */
6896/* Add One Adapter ( Hot Plug ) */
6897/* */
6898/* Return Value: */
6899/* 0 if Successful, else non-zero */
6900/*---------------------------------------------------------------------------*/
6901static int __devinit
6902ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6903{
6904 int index = -1;
6905 int rc;
6906
6907 METHOD_TRACE("ips_insert_device", 1);
6908 rc = pci_enable_device(pci_dev);
6909 if (rc)
6910 return rc;
6911
6912 rc = pci_request_regions(pci_dev, "ips");
6913 if (rc)
6914 goto err_out;
6915
6916 rc = ips_init_phase1(pci_dev, &index);
6917 if (rc == SUCCESS)
6918 rc = ips_init_phase2(index);
6919
6920 if (ips_hotplug)
6921 if (ips_register_scsi(index)) {
6922 ips_free(ips_ha[index]);
6923 rc = -1;
6924 }
6925
6926 if (rc == SUCCESS)
6927 ips_num_controllers++;
6928
6929 ips_next_controller = ips_num_controllers;
6930
6931 if (rc < 0) {
6932 rc = -ENODEV;
6933 goto err_out_regions;
6934 }
6935
6936 pci_set_drvdata(pci_dev, ips_sh[index]);
6937 return 0;
6938
6939err_out_regions:
6940 pci_release_regions(pci_dev);
6941err_out:
6942 pci_disable_device(pci_dev);
6943 return rc;
6944}
6945
6946/*---------------------------------------------------------------------------*/
6947/* Routine Name: ips_init_phase1 */
6948/* */
6949/* Routine Description: */
6950/* Adapter Initialization */
6951/* */
6952/* Return Value: */
6953/* 0 if Successful, else non-zero */
6954/*---------------------------------------------------------------------------*/
6955static int
6956ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6957{
6958 ips_ha_t *ha;
6959 uint32_t io_addr;
6960 uint32_t mem_addr;
6961 uint32_t io_len;
6962 uint32_t mem_len;
6963 uint8_t bus;
6964 uint8_t func;
6965 int j;
6966 int index;
6967 dma_addr_t dma_address;
6968 char __iomem *ioremap_ptr;
6969 char __iomem *mem_ptr;
6970 uint32_t IsDead;
6971
6972 METHOD_TRACE("ips_init_phase1", 1);
6973 index = IPS_MAX_ADAPTERS;
6974 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6975 if (ips_ha[j] == NULL) {
6976 index = j;
6977 break;
6978 }
6979 }
6980
6981 if (index >= IPS_MAX_ADAPTERS)
6982 return -1;
6983
6984 /* stuff that we get in dev */
6985 bus = pci_dev->bus->number;
6986 func = pci_dev->devfn;
6987
6988 /* Init MEM/IO addresses to 0 */
6989 mem_addr = 0;
6990 io_addr = 0;
6991 mem_len = 0;
6992 io_len = 0;
6993
6994 for (j = 0; j < 2; j++) {
6995 if (!pci_resource_start(pci_dev, j))
6996 break;
6997
6998 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6999 io_addr = pci_resource_start(pci_dev, j);
7000 io_len = pci_resource_len(pci_dev, j);
7001 } else {
7002 mem_addr = pci_resource_start(pci_dev, j);
7003 mem_len = pci_resource_len(pci_dev, j);
7004 }
7005 }
7006
7007 /* setup memory mapped area (if applicable) */
7008 if (mem_addr) {
7009 uint32_t base;
7010 uint32_t offs;
7011
7012 base = mem_addr & PAGE_MASK;
7013 offs = mem_addr - base;
7014 ioremap_ptr = ioremap(base, PAGE_SIZE);
7015 if (!ioremap_ptr)
7016 return -1;
7017 mem_ptr = ioremap_ptr + offs;
7018 } else {
7019 ioremap_ptr = NULL;
7020 mem_ptr = NULL;
7021 }
7022
7023 /* found a controller */
7024 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
7025 if (ha == NULL) {
7026 IPS_PRINTK(KERN_WARNING, pci_dev,
7027 "Unable to allocate temporary ha struct\n");
7028 return -1;
7029 }
7030
7031 ips_sh[index] = NULL;
7032 ips_ha[index] = ha;
7033 ha->active = 1;
7034
7035 /* Store info in HA structure */
7036 ha->io_addr = io_addr;
7037 ha->io_len = io_len;
7038 ha->mem_addr = mem_addr;
7039 ha->mem_len = mem_len;
7040 ha->mem_ptr = mem_ptr;
7041 ha->ioremap_ptr = ioremap_ptr;
7042 ha->host_num = (uint32_t) index;
7043 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7044 ha->pcidev = pci_dev;
7045
7046 /*
7047 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7048 * addressing so don't enable it if the adapter can't support
7049 * it! Also, don't use 64bit addressing if dma addresses
7050 * are guaranteed to be < 4G.
7051 */
7052 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7053 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) {
7054 (ha)->flags |= IPS_HA_ENH_SG;
7055 } else {
7056 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) {
7057 printk(KERN_WARNING "Unable to set DMA Mask\n");
7058 return ips_abort_init(ha, index);
7059 }
7060 }
7061 if(ips_cd_boot && !ips_FlashData){
7062 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7063 &ips_flashbusaddr);
7064 }
7065
7066 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7067 &ha->enq_busaddr);
7068 if (!ha->enq) {
7069 IPS_PRINTK(KERN_WARNING, pci_dev,
7070 "Unable to allocate host inquiry structure\n");
7071 return ips_abort_init(ha, index);
7072 }
7073
7074 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7075 sizeof (IPS_IO_CMD), &dma_address);
7076 if (!ha->adapt) {
7077 IPS_PRINTK(KERN_WARNING, pci_dev,
7078 "Unable to allocate host adapt & dummy structures\n");
7079 return ips_abort_init(ha, index);
7080 }
7081 ha->adapt->hw_status_start = dma_address;
7082 ha->dummy = (void *) (ha->adapt + 1);
7083
7084
7085
7086 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7087 if (!ha->logical_drive_info) {
7088 IPS_PRINTK(KERN_WARNING, pci_dev,
7089 "Unable to allocate logical drive info structure\n");
7090 return ips_abort_init(ha, index);
7091 }
7092 ha->logical_drive_info_dma_addr = dma_address;
7093
7094
7095 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7096
7097 if (!ha->conf) {
7098 IPS_PRINTK(KERN_WARNING, pci_dev,
7099 "Unable to allocate host conf structure\n");
7100 return ips_abort_init(ha, index);
7101 }
7102
7103 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7104
7105 if (!ha->nvram) {
7106 IPS_PRINTK(KERN_WARNING, pci_dev,
7107 "Unable to allocate host NVRAM structure\n");
7108 return ips_abort_init(ha, index);
7109 }
7110
7111 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7112
7113 if (!ha->subsys) {
7114 IPS_PRINTK(KERN_WARNING, pci_dev,
7115 "Unable to allocate host subsystem structure\n");
7116 return ips_abort_init(ha, index);
7117 }
7118
7119 /* the ioctl buffer is now used during adapter initialization, so its
7120 * successful allocation is now required */
7121 if (ips_ioctlsize < PAGE_SIZE)
7122 ips_ioctlsize = PAGE_SIZE;
7123
7124 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7125 &ha->ioctl_busaddr);
7126 ha->ioctl_len = ips_ioctlsize;
7127 if (!ha->ioctl_data) {
7128 IPS_PRINTK(KERN_WARNING, pci_dev,
7129 "Unable to allocate IOCTL data\n");
7130 return ips_abort_init(ha, index);
7131 }
7132
7133 /*
7134 * Setup Functions
7135 */
7136 ips_setup_funclist(ha);
7137
7138 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7139 /* If Morpheus appears dead, reset it */
7140 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7141 if (IsDead == 0xDEADBEEF) {
7142 ips_reset_morpheus(ha);
7143 }
7144 }
7145
7146 /*
7147 * Initialize the card if it isn't already
7148 */
7149
7150 if (!(*ha->func.isinit) (ha)) {
7151 if (!(*ha->func.init) (ha)) {
7152 /*
7153 * Initialization failed
7154 */
7155 IPS_PRINTK(KERN_WARNING, pci_dev,
7156 "Unable to initialize controller\n");
7157 return ips_abort_init(ha, index);
7158 }
7159 }
7160
7161 *indexPtr = index;
7162 return SUCCESS;
7163}
7164
7165/*---------------------------------------------------------------------------*/
7166/* Routine Name: ips_init_phase2 */
7167/* */
7168/* Routine Description: */
7169/* Adapter Initialization Phase 2 */
7170/* */
7171/* Return Value: */
7172/* 0 if Successful, else non-zero */
7173/*---------------------------------------------------------------------------*/
7174static int
7175ips_init_phase2(int index)
7176{
7177 ips_ha_t *ha;
7178
7179 ha = ips_ha[index];
7180
7181 METHOD_TRACE("ips_init_phase2", 1);
7182 if (!ha->active) {
7183 ips_ha[index] = NULL;
7184 return -1;
7185 }
7186
7187 /* Install the interrupt handler */
7188 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7189 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7190 "Unable to install interrupt handler\n");
7191 return ips_abort_init(ha, index);
7192 }
7193
7194 /*
7195 * Allocate a temporary SCB for initialization
7196 */
7197 ha->max_cmds = 1;
7198 if (!ips_allocatescbs(ha)) {
7199 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7200 "Unable to allocate a CCB\n");
7201 free_irq(ha->pcidev->irq, ha);
7202 return ips_abort_init(ha, index);
7203 }
7204
7205 if (!ips_hainit(ha)) {
7206 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7207 "Unable to initialize controller\n");
7208 free_irq(ha->pcidev->irq, ha);
7209 return ips_abort_init(ha, index);
7210 }
7211 /* Free the temporary SCB */
7212 ips_deallocatescbs(ha, 1);
7213
7214 /* allocate CCBs */
7215 if (!ips_allocatescbs(ha)) {
7216 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7217 "Unable to allocate CCBs\n");
7218 free_irq(ha->pcidev->irq, ha);
7219 return ips_abort_init(ha, index);
7220 }
7221
7222 return SUCCESS;
7223}
7224
7225MODULE_LICENSE("GPL");
7226MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7227MODULE_VERSION(IPS_VER_STRING);
7228
7229
7230/*
7231 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7232 * Emacs will notice this stuff at the end of the file and automatically
7233 * adjust the settings for this buffer only. This must remain at the end
7234 * of the file.
7235 * ---------------------------------------------------------------------------
7236 * Local variables:
7237 * c-indent-level: 2
7238 * c-brace-imaginary-offset: 0
7239 * c-brace-offset: -2
7240 * c-argdecl-indent: 2
7241 * c-label-offset: -2
7242 * c-continued-statement-offset: 2
7243 * c-continued-brace-offset: 0
7244 * indent-tabs-mode: nil
7245 * tab-width: 8
7246 * End:
7247 */
1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/* 7.12.xx - Use STATIC functions wherever possible */
141/* - Clean up deprecated MODULE_PARM calls */
142/* 7.12.05 - Remove Version Matching per IBM request */
143/*****************************************************************************/
144
145/*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
181#include <linux/dma-mapping.h>
182
183#include <scsi/sg.h>
184#include "scsi.h"
185#include <scsi/scsi_host.h>
186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203/*
204 * DRIVER_VER
205 */
206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
211 DMA_BIDIRECTIONAL : \
212 scb->scsi_cmd->sc_data_direction)
213
214#ifdef IPS_DEBUG
215#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
216#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
217#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
218#else
219#define METHOD_TRACE(s, i)
220#define DEBUG(i, s)
221#define DEBUG_VAR(i, s, v...)
222#endif
223
224/*
225 * Function prototypes
226 */
227static int ips_eh_abort(struct scsi_cmnd *);
228static int ips_eh_reset(struct scsi_cmnd *);
229static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
230static const char *ips_info(struct Scsi_Host *);
231static irqreturn_t do_ipsintr(int, void *);
232static int ips_hainit(ips_ha_t *);
233static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
234static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
235static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
236static int ips_online(ips_ha_t *, ips_scb_t *);
237static int ips_inquiry(ips_ha_t *, ips_scb_t *);
238static int ips_rdcap(ips_ha_t *, ips_scb_t *);
239static int ips_msense(ips_ha_t *, ips_scb_t *);
240static int ips_reqsen(ips_ha_t *, ips_scb_t *);
241static int ips_deallocatescbs(ips_ha_t *, int);
242static int ips_allocatescbs(ips_ha_t *);
243static int ips_reset_copperhead(ips_ha_t *);
244static int ips_reset_copperhead_memio(ips_ha_t *);
245static int ips_reset_morpheus(ips_ha_t *);
246static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
247static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
248static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
249static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
250static int ips_isintr_copperhead(ips_ha_t *);
251static int ips_isintr_copperhead_memio(ips_ha_t *);
252static int ips_isintr_morpheus(ips_ha_t *);
253static int ips_wait(ips_ha_t *, int, int);
254static int ips_write_driver_status(ips_ha_t *, int);
255static int ips_read_adapter_status(ips_ha_t *, int);
256static int ips_read_subsystem_parameters(ips_ha_t *, int);
257static int ips_read_config(ips_ha_t *, int);
258static int ips_clear_adapter(ips_ha_t *, int);
259static int ips_readwrite_page5(ips_ha_t *, int, int);
260static int ips_init_copperhead(ips_ha_t *);
261static int ips_init_copperhead_memio(ips_ha_t *);
262static int ips_init_morpheus(ips_ha_t *);
263static int ips_isinit_copperhead(ips_ha_t *);
264static int ips_isinit_copperhead_memio(ips_ha_t *);
265static int ips_isinit_morpheus(ips_ha_t *);
266static int ips_erase_bios(ips_ha_t *);
267static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
268static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
269static int ips_erase_bios_memio(ips_ha_t *);
270static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
271static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
272static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
273static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
274static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
275static void ips_free_flash_copperhead(ips_ha_t * ha);
276static void ips_get_bios_version(ips_ha_t *, int);
277static void ips_identify_controller(ips_ha_t *);
278static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
279static void ips_enable_int_copperhead(ips_ha_t *);
280static void ips_enable_int_copperhead_memio(ips_ha_t *);
281static void ips_enable_int_morpheus(ips_ha_t *);
282static int ips_intr_copperhead(ips_ha_t *);
283static int ips_intr_morpheus(ips_ha_t *);
284static void ips_next(ips_ha_t *, int);
285static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
286static void ipsintr_done(ips_ha_t *, struct ips_scb *);
287static void ips_done(ips_ha_t *, ips_scb_t *);
288static void ips_free(ips_ha_t *);
289static void ips_init_scb(ips_ha_t *, ips_scb_t *);
290static void ips_freescb(ips_ha_t *, ips_scb_t *);
291static void ips_setup_funclist(ips_ha_t *);
292static void ips_statinit(ips_ha_t *);
293static void ips_statinit_memio(ips_ha_t *);
294static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t);
295static void ips_ffdc_reset(ips_ha_t *, int);
296static void ips_ffdc_time(ips_ha_t *);
297static uint32_t ips_statupd_copperhead(ips_ha_t *);
298static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
299static uint32_t ips_statupd_morpheus(ips_ha_t *);
300static ips_scb_t *ips_getscb(ips_ha_t *);
301static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
302static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
303static void ips_putq_copp_tail(ips_copp_queue_t *,
304 ips_copp_wait_item_t *);
305static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
306static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
307static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
308static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
309 struct scsi_cmnd *);
310static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
311 ips_copp_wait_item_t *);
312static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
313
314static int ips_is_passthru(struct scsi_cmnd *);
315static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
316static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
317static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
318static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
319 unsigned int count);
320static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
321 unsigned int count);
322
323static int ips_write_info(struct Scsi_Host *, char *, int);
324static int ips_show_info(struct seq_file *, struct Scsi_Host *);
325static int ips_host_info(ips_ha_t *, struct seq_file *);
326static int ips_abort_init(ips_ha_t * ha, int index);
327static int ips_init_phase2(int index);
328
329static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
330static int ips_register_scsi(int index);
331
332static int ips_poll_for_flush_complete(ips_ha_t * ha);
333static void ips_flush_and_reset(ips_ha_t *ha);
334
335/*
336 * global variables
337 */
338static const char ips_name[] = "ips";
339static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
340static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
341static unsigned int ips_next_controller;
342static unsigned int ips_num_controllers;
343static unsigned int ips_released_controllers;
344static int ips_hotplug;
345static int ips_cmd_timeout = 60;
346static int ips_reset_timeout = 60 * 5;
347static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
348static int ips_force_i2o = 1; /* Always use I2O command delivery */
349static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
350static int ips_cd_boot; /* Booting from Manager CD */
351static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
352static dma_addr_t ips_flashbusaddr;
353static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
354static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
355static struct scsi_host_template ips_driver_template = {
356 .info = ips_info,
357 .queuecommand = ips_queue,
358 .eh_abort_handler = ips_eh_abort,
359 .eh_host_reset_handler = ips_eh_reset,
360 .proc_name = "ips",
361 .show_info = ips_show_info,
362 .write_info = ips_write_info,
363 .slave_configure = ips_slave_configure,
364 .bios_param = ips_biosparam,
365 .this_id = -1,
366 .sg_tablesize = IPS_MAX_SG,
367 .cmd_per_lun = 3,
368 .no_write_same = 1,
369};
370
371
372/* This table describes all ServeRAID Adapters */
373static struct pci_device_id ips_pci_table[] = {
374 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
375 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
376 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
377 { 0, }
378};
379
380MODULE_DEVICE_TABLE( pci, ips_pci_table );
381
382static char ips_hot_plug_name[] = "ips";
383
384static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
385static void ips_remove_device(struct pci_dev *pci_dev);
386
387static struct pci_driver ips_pci_driver = {
388 .name = ips_hot_plug_name,
389 .id_table = ips_pci_table,
390 .probe = ips_insert_device,
391 .remove = ips_remove_device,
392};
393
394
395/*
396 * Necessary forward function protoypes
397 */
398static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
399
400#define MAX_ADAPTER_NAME 15
401
402static char ips_adapter_name[][30] = {
403 "ServeRAID",
404 "ServeRAID II",
405 "ServeRAID on motherboard",
406 "ServeRAID on motherboard",
407 "ServeRAID 3H",
408 "ServeRAID 3L",
409 "ServeRAID 4H",
410 "ServeRAID 4M",
411 "ServeRAID 4L",
412 "ServeRAID 4Mx",
413 "ServeRAID 4Lx",
414 "ServeRAID 5i",
415 "ServeRAID 5i",
416 "ServeRAID 6M",
417 "ServeRAID 6i",
418 "ServeRAID 7t",
419 "ServeRAID 7k",
420 "ServeRAID 7M"
421};
422
423static struct notifier_block ips_notifier = {
424 ips_halt, NULL, 0
425};
426
427/*
428 * Direction table
429 */
430static char ips_command_direction[] = {
431 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
432 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
433 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
434 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
435 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
436 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
437 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
438 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
439 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
441 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
442 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
444 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
445 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
446 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
447 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
448 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
449 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
450 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
451 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
465 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
466 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
467 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
482};
483
484
485/****************************************************************************/
486/* */
487/* Routine Name: ips_setup */
488/* */
489/* Routine Description: */
490/* */
491/* setup parameters to the driver */
492/* */
493/****************************************************************************/
494static int
495ips_setup(char *ips_str)
496{
497
498 int i;
499 char *key;
500 char *value;
501 static const IPS_OPTION options[] = {
502 {"noi2o", &ips_force_i2o, 0},
503 {"nommap", &ips_force_memio, 0},
504 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
505 {"cdboot", &ips_cd_boot, 0},
506 {"maxcmds", &MaxLiteCmds, 32},
507 };
508
509 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
510 /* Search for value */
511 while ((key = strsep(&ips_str, ",."))) {
512 if (!*key)
513 continue;
514 value = strchr(key, ':');
515 if (value)
516 *value++ = '\0';
517 /*
518 * We now have key/value pairs.
519 * Update the variables
520 */
521 for (i = 0; i < ARRAY_SIZE(options); i++) {
522 if (strncasecmp
523 (key, options[i].option_name,
524 strlen(options[i].option_name)) == 0) {
525 if (value)
526 *options[i].option_flag =
527 simple_strtoul(value, NULL, 0);
528 else
529 *options[i].option_flag =
530 options[i].option_value;
531 break;
532 }
533 }
534 }
535
536 return (1);
537}
538
539__setup("ips=", ips_setup);
540
541/****************************************************************************/
542/* */
543/* Routine Name: ips_detect */
544/* */
545/* Routine Description: */
546/* */
547/* Detect and initialize the driver */
548/* */
549/* NOTE: this routine is called under the io_request_lock spinlock */
550/* */
551/****************************************************************************/
552static int
553ips_detect(struct scsi_host_template * SHT)
554{
555 int i;
556
557 METHOD_TRACE("ips_detect", 1);
558
559#ifdef MODULE
560 if (ips)
561 ips_setup(ips);
562#endif
563
564 for (i = 0; i < ips_num_controllers; i++) {
565 if (ips_register_scsi(i))
566 ips_free(ips_ha[i]);
567 ips_released_controllers++;
568 }
569 ips_hotplug = 1;
570 return (ips_num_controllers);
571}
572
573/****************************************************************************/
574/* configure the function pointers to use the functions that will work */
575/* with the found version of the adapter */
576/****************************************************************************/
577static void
578ips_setup_funclist(ips_ha_t * ha)
579{
580
581 /*
582 * Setup Functions
583 */
584 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
585 /* morpheus / marco / sebring */
586 ha->func.isintr = ips_isintr_morpheus;
587 ha->func.isinit = ips_isinit_morpheus;
588 ha->func.issue = ips_issue_i2o_memio;
589 ha->func.init = ips_init_morpheus;
590 ha->func.statupd = ips_statupd_morpheus;
591 ha->func.reset = ips_reset_morpheus;
592 ha->func.intr = ips_intr_morpheus;
593 ha->func.enableint = ips_enable_int_morpheus;
594 } else if (IPS_USE_MEMIO(ha)) {
595 /* copperhead w/MEMIO */
596 ha->func.isintr = ips_isintr_copperhead_memio;
597 ha->func.isinit = ips_isinit_copperhead_memio;
598 ha->func.init = ips_init_copperhead_memio;
599 ha->func.statupd = ips_statupd_copperhead_memio;
600 ha->func.statinit = ips_statinit_memio;
601 ha->func.reset = ips_reset_copperhead_memio;
602 ha->func.intr = ips_intr_copperhead;
603 ha->func.erasebios = ips_erase_bios_memio;
604 ha->func.programbios = ips_program_bios_memio;
605 ha->func.verifybios = ips_verify_bios_memio;
606 ha->func.enableint = ips_enable_int_copperhead_memio;
607 if (IPS_USE_I2O_DELIVER(ha))
608 ha->func.issue = ips_issue_i2o_memio;
609 else
610 ha->func.issue = ips_issue_copperhead_memio;
611 } else {
612 /* copperhead */
613 ha->func.isintr = ips_isintr_copperhead;
614 ha->func.isinit = ips_isinit_copperhead;
615 ha->func.init = ips_init_copperhead;
616 ha->func.statupd = ips_statupd_copperhead;
617 ha->func.statinit = ips_statinit;
618 ha->func.reset = ips_reset_copperhead;
619 ha->func.intr = ips_intr_copperhead;
620 ha->func.erasebios = ips_erase_bios;
621 ha->func.programbios = ips_program_bios;
622 ha->func.verifybios = ips_verify_bios;
623 ha->func.enableint = ips_enable_int_copperhead;
624
625 if (IPS_USE_I2O_DELIVER(ha))
626 ha->func.issue = ips_issue_i2o;
627 else
628 ha->func.issue = ips_issue_copperhead;
629 }
630}
631
632/****************************************************************************/
633/* */
634/* Routine Name: ips_release */
635/* */
636/* Routine Description: */
637/* */
638/* Remove a driver */
639/* */
640/****************************************************************************/
641static int
642ips_release(struct Scsi_Host *sh)
643{
644 ips_scb_t *scb;
645 ips_ha_t *ha;
646 int i;
647
648 METHOD_TRACE("ips_release", 1);
649
650 scsi_remove_host(sh);
651
652 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
653
654 if (i == IPS_MAX_ADAPTERS) {
655 printk(KERN_WARNING
656 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
657 BUG();
658 return (FALSE);
659 }
660
661 ha = IPS_HA(sh);
662
663 if (!ha)
664 return (FALSE);
665
666 /* flush the cache on the controller */
667 scb = &ha->scbs[ha->max_cmds - 1];
668
669 ips_init_scb(ha, scb);
670
671 scb->timeout = ips_cmd_timeout;
672 scb->cdb[0] = IPS_CMD_FLUSH;
673
674 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
675 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
676 scb->cmd.flush_cache.state = IPS_NORM_STATE;
677 scb->cmd.flush_cache.reserved = 0;
678 scb->cmd.flush_cache.reserved2 = 0;
679 scb->cmd.flush_cache.reserved3 = 0;
680 scb->cmd.flush_cache.reserved4 = 0;
681
682 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
683
684 /* send command */
685 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
686 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
687
688 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
689
690 ips_sh[i] = NULL;
691 ips_ha[i] = NULL;
692
693 /* free extra memory */
694 ips_free(ha);
695
696 /* free IRQ */
697 free_irq(ha->pcidev->irq, ha);
698
699 scsi_host_put(sh);
700
701 ips_released_controllers++;
702
703 return (FALSE);
704}
705
706/****************************************************************************/
707/* */
708/* Routine Name: ips_halt */
709/* */
710/* Routine Description: */
711/* */
712/* Perform cleanup when the system reboots */
713/* */
714/****************************************************************************/
715static int
716ips_halt(struct notifier_block *nb, ulong event, void *buf)
717{
718 ips_scb_t *scb;
719 ips_ha_t *ha;
720 int i;
721
722 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
723 (event != SYS_POWER_OFF))
724 return (NOTIFY_DONE);
725
726 for (i = 0; i < ips_next_controller; i++) {
727 ha = (ips_ha_t *) ips_ha[i];
728
729 if (!ha)
730 continue;
731
732 if (!ha->active)
733 continue;
734
735 /* flush the cache on the controller */
736 scb = &ha->scbs[ha->max_cmds - 1];
737
738 ips_init_scb(ha, scb);
739
740 scb->timeout = ips_cmd_timeout;
741 scb->cdb[0] = IPS_CMD_FLUSH;
742
743 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
744 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
745 scb->cmd.flush_cache.state = IPS_NORM_STATE;
746 scb->cmd.flush_cache.reserved = 0;
747 scb->cmd.flush_cache.reserved2 = 0;
748 scb->cmd.flush_cache.reserved3 = 0;
749 scb->cmd.flush_cache.reserved4 = 0;
750
751 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
752
753 /* send command */
754 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
755 IPS_FAILURE)
756 IPS_PRINTK(KERN_WARNING, ha->pcidev,
757 "Incomplete Flush.\n");
758 else
759 IPS_PRINTK(KERN_WARNING, ha->pcidev,
760 "Flushing Complete.\n");
761 }
762
763 return (NOTIFY_OK);
764}
765
766/****************************************************************************/
767/* */
768/* Routine Name: ips_eh_abort */
769/* */
770/* Routine Description: */
771/* */
772/* Abort a command (using the new error code stuff) */
773/* Note: this routine is called under the io_request_lock */
774/****************************************************************************/
775int ips_eh_abort(struct scsi_cmnd *SC)
776{
777 ips_ha_t *ha;
778 ips_copp_wait_item_t *item;
779 int ret;
780 struct Scsi_Host *host;
781
782 METHOD_TRACE("ips_eh_abort", 1);
783
784 if (!SC)
785 return (FAILED);
786
787 host = SC->device->host;
788 ha = (ips_ha_t *) SC->device->host->hostdata;
789
790 if (!ha)
791 return (FAILED);
792
793 if (!ha->active)
794 return (FAILED);
795
796 spin_lock(host->host_lock);
797
798 /* See if the command is on the copp queue */
799 item = ha->copp_waitlist.head;
800 while ((item) && (item->scsi_cmd != SC))
801 item = item->next;
802
803 if (item) {
804 /* Found it */
805 ips_removeq_copp(&ha->copp_waitlist, item);
806 ret = (SUCCESS);
807
808 /* See if the command is on the wait queue */
809 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
810 /* command not sent yet */
811 ret = (SUCCESS);
812 } else {
813 /* command must have already been sent */
814 ret = (FAILED);
815 }
816
817 spin_unlock(host->host_lock);
818 return ret;
819}
820
821/****************************************************************************/
822/* */
823/* Routine Name: ips_eh_reset */
824/* */
825/* Routine Description: */
826/* */
827/* Reset the controller (with new eh error code) */
828/* */
829/* NOTE: this routine is called under the io_request_lock spinlock */
830/* */
831/****************************************************************************/
832static int __ips_eh_reset(struct scsi_cmnd *SC)
833{
834 int ret;
835 int i;
836 ips_ha_t *ha;
837 ips_scb_t *scb;
838 ips_copp_wait_item_t *item;
839
840 METHOD_TRACE("ips_eh_reset", 1);
841
842#ifdef NO_IPS_RESET
843 return (FAILED);
844#else
845
846 if (!SC) {
847 DEBUG(1, "Reset called with NULL scsi command");
848
849 return (FAILED);
850 }
851
852 ha = (ips_ha_t *) SC->device->host->hostdata;
853
854 if (!ha) {
855 DEBUG(1, "Reset called with NULL ha struct");
856
857 return (FAILED);
858 }
859
860 if (!ha->active)
861 return (FAILED);
862
863 /* See if the command is on the copp queue */
864 item = ha->copp_waitlist.head;
865 while ((item) && (item->scsi_cmd != SC))
866 item = item->next;
867
868 if (item) {
869 /* Found it */
870 ips_removeq_copp(&ha->copp_waitlist, item);
871 return (SUCCESS);
872 }
873
874 /* See if the command is on the wait queue */
875 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
876 /* command not sent yet */
877 return (SUCCESS);
878 }
879
880 /* An explanation for the casual observer: */
881 /* Part of the function of a RAID controller is automatic error */
882 /* detection and recovery. As such, the only problem that physically */
883 /* resetting an adapter will ever fix is when, for some reason, */
884 /* the driver is not successfully communicating with the adapter. */
885 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
886 /* then there's no real purpose in a physical reset. This will complete */
887 /* much faster and avoids any problems that might be caused by a */
888 /* physical reset ( such as having to fail all the outstanding I/O's ). */
889
890 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
891 scb = &ha->scbs[ha->max_cmds - 1];
892
893 ips_init_scb(ha, scb);
894
895 scb->timeout = ips_cmd_timeout;
896 scb->cdb[0] = IPS_CMD_FLUSH;
897
898 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
899 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
900 scb->cmd.flush_cache.state = IPS_NORM_STATE;
901 scb->cmd.flush_cache.reserved = 0;
902 scb->cmd.flush_cache.reserved2 = 0;
903 scb->cmd.flush_cache.reserved3 = 0;
904 scb->cmd.flush_cache.reserved4 = 0;
905
906 /* Attempt the flush command */
907 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
908 if (ret == IPS_SUCCESS) {
909 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
910 "Reset Request - Flushed Cache\n");
911 return (SUCCESS);
912 }
913 }
914
915 /* Either we can't communicate with the adapter or it's an IOCTL request */
916 /* from a utility. A physical reset is needed at this point. */
917
918 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
919
920 /*
921 * command must have already been sent
922 * reset the controller
923 */
924 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
925 ret = (*ha->func.reset) (ha);
926
927 if (!ret) {
928 struct scsi_cmnd *scsi_cmd;
929
930 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
931 "Controller reset failed - controller now offline.\n");
932
933 /* Now fail all of the active commands */
934 DEBUG_VAR(1, "(%s%d) Failing active commands",
935 ips_name, ha->host_num);
936
937 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
938 scb->scsi_cmd->result = DID_ERROR << 16;
939 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
940 ips_freescb(ha, scb);
941 }
942
943 /* Now fail all of the pending commands */
944 DEBUG_VAR(1, "(%s%d) Failing pending commands",
945 ips_name, ha->host_num);
946
947 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
948 scsi_cmd->result = DID_ERROR;
949 scsi_cmd->scsi_done(scsi_cmd);
950 }
951
952 ha->active = FALSE;
953 return (FAILED);
954 }
955
956 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
957 struct scsi_cmnd *scsi_cmd;
958
959 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
960 "Controller reset failed - controller now offline.\n");
961
962 /* Now fail all of the active commands */
963 DEBUG_VAR(1, "(%s%d) Failing active commands",
964 ips_name, ha->host_num);
965
966 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
967 scb->scsi_cmd->result = DID_ERROR << 16;
968 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
969 ips_freescb(ha, scb);
970 }
971
972 /* Now fail all of the pending commands */
973 DEBUG_VAR(1, "(%s%d) Failing pending commands",
974 ips_name, ha->host_num);
975
976 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
977 scsi_cmd->result = DID_ERROR << 16;
978 scsi_cmd->scsi_done(scsi_cmd);
979 }
980
981 ha->active = FALSE;
982 return (FAILED);
983 }
984
985 /* FFDC */
986 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
987 ha->last_ffdc = ktime_get_real_seconds();
988 ha->reset_count++;
989 ips_ffdc_reset(ha, IPS_INTR_IORL);
990 }
991
992 /* Now fail all of the active commands */
993 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
994
995 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
996 scb->scsi_cmd->result = DID_RESET << 16;
997 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
998 ips_freescb(ha, scb);
999 }
1000
1001 /* Reset DCDB active command bits */
1002 for (i = 1; i < ha->nbus; i++)
1003 ha->dcdb_active[i - 1] = 0;
1004
1005 /* Reset the number of active IOCTLs */
1006 ha->num_ioctl = 0;
1007
1008 ips_next(ha, IPS_INTR_IORL);
1009
1010 return (SUCCESS);
1011#endif /* NO_IPS_RESET */
1012
1013}
1014
1015static int ips_eh_reset(struct scsi_cmnd *SC)
1016{
1017 int rc;
1018
1019 spin_lock_irq(SC->device->host->host_lock);
1020 rc = __ips_eh_reset(SC);
1021 spin_unlock_irq(SC->device->host->host_lock);
1022
1023 return rc;
1024}
1025
1026/****************************************************************************/
1027/* */
1028/* Routine Name: ips_queue */
1029/* */
1030/* Routine Description: */
1031/* */
1032/* Send a command to the controller */
1033/* */
1034/* NOTE: */
1035/* Linux obtains io_request_lock before calling this function */
1036/* */
1037/****************************************************************************/
1038static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1039{
1040 ips_ha_t *ha;
1041 ips_passthru_t *pt;
1042
1043 METHOD_TRACE("ips_queue", 1);
1044
1045 ha = (ips_ha_t *) SC->device->host->hostdata;
1046
1047 if (!ha)
1048 return (1);
1049
1050 if (!ha->active)
1051 return (DID_ERROR);
1052
1053 if (ips_is_passthru(SC)) {
1054 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1055 SC->result = DID_BUS_BUSY << 16;
1056 done(SC);
1057
1058 return (0);
1059 }
1060 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1061 SC->result = DID_BUS_BUSY << 16;
1062 done(SC);
1063
1064 return (0);
1065 }
1066
1067 SC->scsi_done = done;
1068
1069 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1070 ips_name,
1071 ha->host_num,
1072 SC->cmnd[0],
1073 SC->device->channel, SC->device->id, SC->device->lun);
1074
1075 /* Check for command to initiator IDs */
1076 if ((scmd_channel(SC) > 0)
1077 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1078 SC->result = DID_NO_CONNECT << 16;
1079 done(SC);
1080
1081 return (0);
1082 }
1083
1084 if (ips_is_passthru(SC)) {
1085
1086 ips_copp_wait_item_t *scratch;
1087
1088 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1089 /* There can never be any system activity ( network or disk ), but check */
1090 /* anyway just as a good practice. */
1091 pt = (ips_passthru_t *) scsi_sglist(SC);
1092 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1093 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1094 if (ha->scb_activelist.count != 0) {
1095 SC->result = DID_BUS_BUSY << 16;
1096 done(SC);
1097 return (0);
1098 }
1099 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1100 __ips_eh_reset(SC);
1101 SC->result = DID_OK << 16;
1102 SC->scsi_done(SC);
1103 return (0);
1104 }
1105
1106 /* allocate space for the scribble */
1107 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1108
1109 if (!scratch) {
1110 SC->result = DID_ERROR << 16;
1111 done(SC);
1112
1113 return (0);
1114 }
1115
1116 scratch->scsi_cmd = SC;
1117 scratch->next = NULL;
1118
1119 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1120 } else {
1121 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1122 }
1123
1124 ips_next(ha, IPS_INTR_IORL);
1125
1126 return (0);
1127}
1128
1129static DEF_SCSI_QCMD(ips_queue)
1130
1131/****************************************************************************/
1132/* */
1133/* Routine Name: ips_biosparam */
1134/* */
1135/* Routine Description: */
1136/* */
1137/* Set bios geometry for the controller */
1138/* */
1139/****************************************************************************/
1140static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1141 sector_t capacity, int geom[])
1142{
1143 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1144 int heads;
1145 int sectors;
1146 int cylinders;
1147
1148 METHOD_TRACE("ips_biosparam", 1);
1149
1150 if (!ha)
1151 /* ?!?! host adater info invalid */
1152 return (0);
1153
1154 if (!ha->active)
1155 return (0);
1156
1157 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1158 /* ?!?! Enquiry command failed */
1159 return (0);
1160
1161 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1162 heads = IPS_NORM_HEADS;
1163 sectors = IPS_NORM_SECTORS;
1164 } else {
1165 heads = IPS_COMP_HEADS;
1166 sectors = IPS_COMP_SECTORS;
1167 }
1168
1169 cylinders = (unsigned long) capacity / (heads * sectors);
1170
1171 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1172 heads, sectors, cylinders);
1173
1174 geom[0] = heads;
1175 geom[1] = sectors;
1176 geom[2] = cylinders;
1177
1178 return (0);
1179}
1180
1181/****************************************************************************/
1182/* */
1183/* Routine Name: ips_slave_configure */
1184/* */
1185/* Routine Description: */
1186/* */
1187/* Set queue depths on devices once scan is complete */
1188/* */
1189/****************************************************************************/
1190static int
1191ips_slave_configure(struct scsi_device * SDptr)
1192{
1193 ips_ha_t *ha;
1194 int min;
1195
1196 ha = IPS_HA(SDptr->host);
1197 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1198 min = ha->max_cmds / 2;
1199 if (ha->enq->ucLogDriveCount <= 2)
1200 min = ha->max_cmds - 1;
1201 scsi_change_queue_depth(SDptr, min);
1202 }
1203
1204 SDptr->skip_ms_page_8 = 1;
1205 SDptr->skip_ms_page_3f = 1;
1206 return 0;
1207}
1208
1209/****************************************************************************/
1210/* */
1211/* Routine Name: do_ipsintr */
1212/* */
1213/* Routine Description: */
1214/* */
1215/* Wrapper for the interrupt handler */
1216/* */
1217/****************************************************************************/
1218static irqreturn_t
1219do_ipsintr(int irq, void *dev_id)
1220{
1221 ips_ha_t *ha;
1222 struct Scsi_Host *host;
1223 int irqstatus;
1224
1225 METHOD_TRACE("do_ipsintr", 2);
1226
1227 ha = (ips_ha_t *) dev_id;
1228 if (!ha)
1229 return IRQ_NONE;
1230 host = ips_sh[ha->host_num];
1231 /* interrupt during initialization */
1232 if (!host) {
1233 (*ha->func.intr) (ha);
1234 return IRQ_HANDLED;
1235 }
1236
1237 spin_lock(host->host_lock);
1238
1239 if (!ha->active) {
1240 spin_unlock(host->host_lock);
1241 return IRQ_HANDLED;
1242 }
1243
1244 irqstatus = (*ha->func.intr) (ha);
1245
1246 spin_unlock(host->host_lock);
1247
1248 /* start the next command */
1249 ips_next(ha, IPS_INTR_ON);
1250 return IRQ_RETVAL(irqstatus);
1251}
1252
1253/****************************************************************************/
1254/* */
1255/* Routine Name: ips_intr_copperhead */
1256/* */
1257/* Routine Description: */
1258/* */
1259/* Polling interrupt handler */
1260/* */
1261/* ASSUMES interrupts are disabled */
1262/* */
1263/****************************************************************************/
1264int
1265ips_intr_copperhead(ips_ha_t * ha)
1266{
1267 ips_stat_t *sp;
1268 ips_scb_t *scb;
1269 IPS_STATUS cstatus;
1270 int intrstatus;
1271
1272 METHOD_TRACE("ips_intr", 2);
1273
1274 if (!ha)
1275 return 0;
1276
1277 if (!ha->active)
1278 return 0;
1279
1280 intrstatus = (*ha->func.isintr) (ha);
1281
1282 if (!intrstatus) {
1283 /*
1284 * Unexpected/Shared interrupt
1285 */
1286
1287 return 0;
1288 }
1289
1290 while (TRUE) {
1291 sp = &ha->sp;
1292
1293 intrstatus = (*ha->func.isintr) (ha);
1294
1295 if (!intrstatus)
1296 break;
1297 else
1298 cstatus.value = (*ha->func.statupd) (ha);
1299
1300 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1301 /* Spurious Interrupt ? */
1302 continue;
1303 }
1304
1305 ips_chkstatus(ha, &cstatus);
1306 scb = (ips_scb_t *) sp->scb_addr;
1307
1308 /*
1309 * use the callback function to finish things up
1310 * NOTE: interrupts are OFF for this
1311 */
1312 (*scb->callback) (ha, scb);
1313 } /* end while */
1314 return 1;
1315}
1316
1317/****************************************************************************/
1318/* */
1319/* Routine Name: ips_intr_morpheus */
1320/* */
1321/* Routine Description: */
1322/* */
1323/* Polling interrupt handler */
1324/* */
1325/* ASSUMES interrupts are disabled */
1326/* */
1327/****************************************************************************/
1328int
1329ips_intr_morpheus(ips_ha_t * ha)
1330{
1331 ips_stat_t *sp;
1332 ips_scb_t *scb;
1333 IPS_STATUS cstatus;
1334 int intrstatus;
1335
1336 METHOD_TRACE("ips_intr_morpheus", 2);
1337
1338 if (!ha)
1339 return 0;
1340
1341 if (!ha->active)
1342 return 0;
1343
1344 intrstatus = (*ha->func.isintr) (ha);
1345
1346 if (!intrstatus) {
1347 /*
1348 * Unexpected/Shared interrupt
1349 */
1350
1351 return 0;
1352 }
1353
1354 while (TRUE) {
1355 sp = &ha->sp;
1356
1357 intrstatus = (*ha->func.isintr) (ha);
1358
1359 if (!intrstatus)
1360 break;
1361 else
1362 cstatus.value = (*ha->func.statupd) (ha);
1363
1364 if (cstatus.value == 0xffffffff)
1365 /* No more to process */
1366 break;
1367
1368 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1369 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1370 "Spurious interrupt; no ccb.\n");
1371
1372 continue;
1373 }
1374
1375 ips_chkstatus(ha, &cstatus);
1376 scb = (ips_scb_t *) sp->scb_addr;
1377
1378 /*
1379 * use the callback function to finish things up
1380 * NOTE: interrupts are OFF for this
1381 */
1382 (*scb->callback) (ha, scb);
1383 } /* end while */
1384 return 1;
1385}
1386
1387/****************************************************************************/
1388/* */
1389/* Routine Name: ips_info */
1390/* */
1391/* Routine Description: */
1392/* */
1393/* Return info about the driver */
1394/* */
1395/****************************************************************************/
1396static const char *
1397ips_info(struct Scsi_Host *SH)
1398{
1399 static char buffer[256];
1400 char *bp;
1401 ips_ha_t *ha;
1402
1403 METHOD_TRACE("ips_info", 1);
1404
1405 ha = IPS_HA(SH);
1406
1407 if (!ha)
1408 return (NULL);
1409
1410 bp = &buffer[0];
1411 memset(bp, 0, sizeof (buffer));
1412
1413 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1414 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1415
1416 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1417 strcat(bp, " <");
1418 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1419 strcat(bp, ">");
1420 }
1421
1422 return (bp);
1423}
1424
1425static int
1426ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1427{
1428 int i;
1429 ips_ha_t *ha = NULL;
1430
1431 /* Find our host structure */
1432 for (i = 0; i < ips_next_controller; i++) {
1433 if (ips_sh[i]) {
1434 if (ips_sh[i] == host) {
1435 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1436 break;
1437 }
1438 }
1439 }
1440
1441 if (!ha)
1442 return (-EINVAL);
1443
1444 return 0;
1445}
1446
1447static int
1448ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1449{
1450 int i;
1451 ips_ha_t *ha = NULL;
1452
1453 /* Find our host structure */
1454 for (i = 0; i < ips_next_controller; i++) {
1455 if (ips_sh[i]) {
1456 if (ips_sh[i] == host) {
1457 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1458 break;
1459 }
1460 }
1461 }
1462
1463 if (!ha)
1464 return (-EINVAL);
1465
1466 return ips_host_info(ha, m);
1467}
1468
1469/*--------------------------------------------------------------------------*/
1470/* Helper Functions */
1471/*--------------------------------------------------------------------------*/
1472
1473/****************************************************************************/
1474/* */
1475/* Routine Name: ips_is_passthru */
1476/* */
1477/* Routine Description: */
1478/* */
1479/* Determine if the specified SCSI command is really a passthru command */
1480/* */
1481/****************************************************************************/
1482static int ips_is_passthru(struct scsi_cmnd *SC)
1483{
1484 unsigned long flags;
1485
1486 METHOD_TRACE("ips_is_passthru", 1);
1487
1488 if (!SC)
1489 return (0);
1490
1491 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1492 (SC->device->channel == 0) &&
1493 (SC->device->id == IPS_ADAPTER_ID) &&
1494 (SC->device->lun == 0) && scsi_sglist(SC)) {
1495 struct scatterlist *sg = scsi_sglist(SC);
1496 char *buffer;
1497
1498 /* kmap_atomic() ensures addressability of the user buffer.*/
1499 /* local_irq_save() protects the KM_IRQ0 address slot. */
1500 local_irq_save(flags);
1501 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
1502 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1503 buffer[2] == 'P' && buffer[3] == 'P') {
1504 kunmap_atomic(buffer - sg->offset);
1505 local_irq_restore(flags);
1506 return 1;
1507 }
1508 kunmap_atomic(buffer - sg->offset);
1509 local_irq_restore(flags);
1510 }
1511 return 0;
1512}
1513
1514/****************************************************************************/
1515/* */
1516/* Routine Name: ips_alloc_passthru_buffer */
1517/* */
1518/* Routine Description: */
1519/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1520/* is too small or doesn't exist */
1521/****************************************************************************/
1522static int
1523ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1524{
1525 void *bigger_buf;
1526 dma_addr_t dma_busaddr;
1527
1528 if (ha->ioctl_data && length <= ha->ioctl_len)
1529 return 0;
1530 /* there is no buffer or it's not big enough, allocate a new one */
1531 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr,
1532 GFP_KERNEL);
1533 if (bigger_buf) {
1534 /* free the old memory */
1535 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
1536 ha->ioctl_data, ha->ioctl_busaddr);
1537 /* use the new memory */
1538 ha->ioctl_data = (char *) bigger_buf;
1539 ha->ioctl_len = length;
1540 ha->ioctl_busaddr = dma_busaddr;
1541 } else {
1542 return -1;
1543 }
1544 return 0;
1545}
1546
1547/****************************************************************************/
1548/* */
1549/* Routine Name: ips_make_passthru */
1550/* */
1551/* Routine Description: */
1552/* */
1553/* Make a passthru command out of the info in the Scsi block */
1554/* */
1555/****************************************************************************/
1556static int
1557ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1558{
1559 ips_passthru_t *pt;
1560 int length = 0;
1561 int i, ret;
1562 struct scatterlist *sg = scsi_sglist(SC);
1563
1564 METHOD_TRACE("ips_make_passthru", 1);
1565
1566 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1567 length += sg->length;
1568
1569 if (length < sizeof (ips_passthru_t)) {
1570 /* wrong size */
1571 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1572 ips_name, ha->host_num);
1573 return (IPS_FAILURE);
1574 }
1575 if (ips_alloc_passthru_buffer(ha, length)) {
1576 /* allocation failure! If ha->ioctl_data exists, use it to return
1577 some error codes. Return a failed command to the scsi layer. */
1578 if (ha->ioctl_data) {
1579 pt = (ips_passthru_t *) ha->ioctl_data;
1580 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1581 pt->BasicStatus = 0x0B;
1582 pt->ExtendedStatus = 0x00;
1583 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1584 }
1585 return IPS_FAILURE;
1586 }
1587 ha->ioctl_datasize = length;
1588
1589 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1590 pt = (ips_passthru_t *) ha->ioctl_data;
1591
1592 /*
1593 * Some notes about the passthru interface used
1594 *
1595 * IF the scsi op_code == 0x0d then we assume
1596 * that the data came along with/goes with the
1597 * packet we received from the sg driver. In this
1598 * case the CmdBSize field of the pt structure is
1599 * used for the size of the buffer.
1600 */
1601
1602 switch (pt->CoppCmd) {
1603 case IPS_NUMCTRLS:
1604 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1605 &ips_num_controllers, sizeof (int));
1606 ips_scmd_buf_write(SC, ha->ioctl_data,
1607 sizeof (ips_passthru_t) + sizeof (int));
1608 SC->result = DID_OK << 16;
1609
1610 return (IPS_SUCCESS_IMM);
1611
1612 case IPS_COPPUSRCMD:
1613 case IPS_COPPIOCCMD:
1614 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1615 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1616 /* wrong size */
1617 DEBUG_VAR(1,
1618 "(%s%d) Passthru structure wrong size",
1619 ips_name, ha->host_num);
1620
1621 return (IPS_FAILURE);
1622 }
1623
1624 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1625 pt->CoppCP.cmd.flashfw.op_code ==
1626 IPS_CMD_RW_BIOSFW) {
1627 ret = ips_flash_copperhead(ha, pt, scb);
1628 ips_scmd_buf_write(SC, ha->ioctl_data,
1629 sizeof (ips_passthru_t));
1630 return ret;
1631 }
1632 if (ips_usrcmd(ha, pt, scb))
1633 return (IPS_SUCCESS);
1634 else
1635 return (IPS_FAILURE);
1636 }
1637
1638 break;
1639
1640 } /* end switch */
1641
1642 return (IPS_FAILURE);
1643}
1644
1645/****************************************************************************/
1646/* Routine Name: ips_flash_copperhead */
1647/* Routine Description: */
1648/* Flash the BIOS/FW on a Copperhead style controller */
1649/****************************************************************************/
1650static int
1651ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1652{
1653 int datasize;
1654
1655 /* Trombone is the only copperhead that can do packet flash, but only
1656 * for firmware. No one said it had to make sense. */
1657 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1658 if (ips_usrcmd(ha, pt, scb))
1659 return IPS_SUCCESS;
1660 else
1661 return IPS_FAILURE;
1662 }
1663 pt->BasicStatus = 0x0B;
1664 pt->ExtendedStatus = 0;
1665 scb->scsi_cmd->result = DID_OK << 16;
1666 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1667 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1668 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1669 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1670 pt->BasicStatus = 0;
1671 return ips_flash_bios(ha, pt, scb);
1672 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1673 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1674 ha->flash_data = ips_FlashData;
1675 ha->flash_busaddr = ips_flashbusaddr;
1676 ha->flash_len = PAGE_SIZE << 7;
1677 ha->flash_datasize = 0;
1678 } else if (!ha->flash_data) {
1679 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1680 pt->CoppCP.cmd.flashfw.count;
1681 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev,
1682 datasize, &ha->flash_busaddr, GFP_KERNEL);
1683 if (!ha->flash_data){
1684 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1685 return IPS_FAILURE;
1686 }
1687 ha->flash_datasize = 0;
1688 ha->flash_len = datasize;
1689 } else
1690 return IPS_FAILURE;
1691 } else {
1692 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1693 ha->flash_len) {
1694 ips_free_flash_copperhead(ha);
1695 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1696 "failed size sanity check\n");
1697 return IPS_FAILURE;
1698 }
1699 }
1700 if (!ha->flash_data)
1701 return IPS_FAILURE;
1702 pt->BasicStatus = 0;
1703 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1704 pt->CoppCP.cmd.flashfw.count);
1705 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1706 if (pt->CoppCP.cmd.flashfw.packet_num ==
1707 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1708 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1709 return ips_flash_bios(ha, pt, scb);
1710 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1711 return ips_flash_firmware(ha, pt, scb);
1712 }
1713 return IPS_SUCCESS_IMM;
1714}
1715
1716/****************************************************************************/
1717/* Routine Name: ips_flash_bios */
1718/* Routine Description: */
1719/* flashes the bios of a copperhead adapter */
1720/****************************************************************************/
1721static int
1722ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1723{
1724
1725 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1726 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1727 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1728 (!ha->func.verifybios))
1729 goto error;
1730 if ((*ha->func.erasebios) (ha)) {
1731 DEBUG_VAR(1,
1732 "(%s%d) flash bios failed - unable to erase flash",
1733 ips_name, ha->host_num);
1734 goto error;
1735 } else
1736 if ((*ha->func.programbios) (ha,
1737 ha->flash_data +
1738 IPS_BIOS_HEADER,
1739 ha->flash_datasize -
1740 IPS_BIOS_HEADER, 0)) {
1741 DEBUG_VAR(1,
1742 "(%s%d) flash bios failed - unable to flash",
1743 ips_name, ha->host_num);
1744 goto error;
1745 } else
1746 if ((*ha->func.verifybios) (ha,
1747 ha->flash_data +
1748 IPS_BIOS_HEADER,
1749 ha->flash_datasize -
1750 IPS_BIOS_HEADER, 0)) {
1751 DEBUG_VAR(1,
1752 "(%s%d) flash bios failed - unable to verify flash",
1753 ips_name, ha->host_num);
1754 goto error;
1755 }
1756 ips_free_flash_copperhead(ha);
1757 return IPS_SUCCESS_IMM;
1758 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1759 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1760 if (!ha->func.erasebios)
1761 goto error;
1762 if ((*ha->func.erasebios) (ha)) {
1763 DEBUG_VAR(1,
1764 "(%s%d) flash bios failed - unable to erase flash",
1765 ips_name, ha->host_num);
1766 goto error;
1767 }
1768 return IPS_SUCCESS_IMM;
1769 }
1770 error:
1771 pt->BasicStatus = 0x0B;
1772 pt->ExtendedStatus = 0x00;
1773 ips_free_flash_copperhead(ha);
1774 return IPS_FAILURE;
1775}
1776
1777/****************************************************************************/
1778/* */
1779/* Routine Name: ips_fill_scb_sg_single */
1780/* */
1781/* Routine Description: */
1782/* Fill in a single scb sg_list element from an address */
1783/* return a -1 if a breakup occurred */
1784/****************************************************************************/
1785static int
1786ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1787 ips_scb_t * scb, int indx, unsigned int e_len)
1788{
1789
1790 int ret_val = 0;
1791
1792 if ((scb->data_len + e_len) > ha->max_xfer) {
1793 e_len = ha->max_xfer - scb->data_len;
1794 scb->breakup = indx;
1795 ++scb->sg_break;
1796 ret_val = -1;
1797 } else {
1798 scb->breakup = 0;
1799 scb->sg_break = 0;
1800 }
1801 if (IPS_USE_ENH_SGLIST(ha)) {
1802 scb->sg_list.enh_list[indx].address_lo =
1803 cpu_to_le32(lower_32_bits(busaddr));
1804 scb->sg_list.enh_list[indx].address_hi =
1805 cpu_to_le32(upper_32_bits(busaddr));
1806 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1807 } else {
1808 scb->sg_list.std_list[indx].address =
1809 cpu_to_le32(lower_32_bits(busaddr));
1810 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1811 }
1812
1813 ++scb->sg_len;
1814 scb->data_len += e_len;
1815 return ret_val;
1816}
1817
1818/****************************************************************************/
1819/* Routine Name: ips_flash_firmware */
1820/* Routine Description: */
1821/* flashes the firmware of a copperhead adapter */
1822/****************************************************************************/
1823static int
1824ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1825{
1826 IPS_SG_LIST sg_list;
1827 uint32_t cmd_busaddr;
1828
1829 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1830 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1831 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1832 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1833 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1834 } else {
1835 pt->BasicStatus = 0x0B;
1836 pt->ExtendedStatus = 0x00;
1837 ips_free_flash_copperhead(ha);
1838 return IPS_FAILURE;
1839 }
1840 /* Save the S/G list pointer so it doesn't get clobbered */
1841 sg_list.list = scb->sg_list.list;
1842 cmd_busaddr = scb->scb_busaddr;
1843 /* copy in the CP */
1844 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1845 /* FIX stuff that might be wrong */
1846 scb->sg_list.list = sg_list.list;
1847 scb->scb_busaddr = cmd_busaddr;
1848 scb->bus = scb->scsi_cmd->device->channel;
1849 scb->target_id = scb->scsi_cmd->device->id;
1850 scb->lun = scb->scsi_cmd->device->lun;
1851 scb->sg_len = 0;
1852 scb->data_len = 0;
1853 scb->flags = 0;
1854 scb->op_code = 0;
1855 scb->callback = ipsintr_done;
1856 scb->timeout = ips_cmd_timeout;
1857
1858 scb->data_len = ha->flash_datasize;
1859 scb->data_busaddr =
1860 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len,
1861 IPS_DMA_DIR(scb));
1862 scb->flags |= IPS_SCB_MAP_SINGLE;
1863 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1864 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1865 if (pt->TimeOut)
1866 scb->timeout = pt->TimeOut;
1867 scb->scsi_cmd->result = DID_OK << 16;
1868 return IPS_SUCCESS;
1869}
1870
1871/****************************************************************************/
1872/* Routine Name: ips_free_flash_copperhead */
1873/* Routine Description: */
1874/* release the memory resources used to hold the flash image */
1875/****************************************************************************/
1876static void
1877ips_free_flash_copperhead(ips_ha_t * ha)
1878{
1879 if (ha->flash_data == ips_FlashData)
1880 test_and_clear_bit(0, &ips_FlashDataInUse);
1881 else if (ha->flash_data)
1882 dma_free_coherent(&ha->pcidev->dev, ha->flash_len,
1883 ha->flash_data, ha->flash_busaddr);
1884 ha->flash_data = NULL;
1885}
1886
1887/****************************************************************************/
1888/* */
1889/* Routine Name: ips_usrcmd */
1890/* */
1891/* Routine Description: */
1892/* */
1893/* Process a user command and make it ready to send */
1894/* */
1895/****************************************************************************/
1896static int
1897ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1898{
1899 IPS_SG_LIST sg_list;
1900 uint32_t cmd_busaddr;
1901
1902 METHOD_TRACE("ips_usrcmd", 1);
1903
1904 if ((!scb) || (!pt) || (!ha))
1905 return (0);
1906
1907 /* Save the S/G list pointer so it doesn't get clobbered */
1908 sg_list.list = scb->sg_list.list;
1909 cmd_busaddr = scb->scb_busaddr;
1910 /* copy in the CP */
1911 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1912 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1913
1914 /* FIX stuff that might be wrong */
1915 scb->sg_list.list = sg_list.list;
1916 scb->scb_busaddr = cmd_busaddr;
1917 scb->bus = scb->scsi_cmd->device->channel;
1918 scb->target_id = scb->scsi_cmd->device->id;
1919 scb->lun = scb->scsi_cmd->device->lun;
1920 scb->sg_len = 0;
1921 scb->data_len = 0;
1922 scb->flags = 0;
1923 scb->op_code = 0;
1924 scb->callback = ipsintr_done;
1925 scb->timeout = ips_cmd_timeout;
1926 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1927
1928 /* we don't support DCDB/READ/WRITE Scatter Gather */
1929 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1930 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1931 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1932 return (0);
1933
1934 if (pt->CmdBSize) {
1935 scb->data_len = pt->CmdBSize;
1936 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1937 } else {
1938 scb->data_busaddr = 0L;
1939 }
1940
1941 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1942 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1943 (unsigned long) &scb->
1944 dcdb -
1945 (unsigned long) scb);
1946
1947 if (pt->CmdBSize) {
1948 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1949 scb->dcdb.buffer_pointer =
1950 cpu_to_le32(scb->data_busaddr);
1951 else
1952 scb->cmd.basic_io.sg_addr =
1953 cpu_to_le32(scb->data_busaddr);
1954 }
1955
1956 /* set timeouts */
1957 if (pt->TimeOut) {
1958 scb->timeout = pt->TimeOut;
1959
1960 if (pt->TimeOut <= 10)
1961 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1962 else if (pt->TimeOut <= 60)
1963 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1964 else
1965 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1966 }
1967
1968 /* assume success */
1969 scb->scsi_cmd->result = DID_OK << 16;
1970
1971 /* success */
1972 return (1);
1973}
1974
1975/****************************************************************************/
1976/* */
1977/* Routine Name: ips_cleanup_passthru */
1978/* */
1979/* Routine Description: */
1980/* */
1981/* Cleanup after a passthru command */
1982/* */
1983/****************************************************************************/
1984static void
1985ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1986{
1987 ips_passthru_t *pt;
1988
1989 METHOD_TRACE("ips_cleanup_passthru", 1);
1990
1991 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
1992 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
1993 ips_name, ha->host_num);
1994
1995 return;
1996 }
1997 pt = (ips_passthru_t *) ha->ioctl_data;
1998
1999 /* Copy data back to the user */
2000 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2001 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2002
2003 pt->BasicStatus = scb->basic_status;
2004 pt->ExtendedStatus = scb->extended_status;
2005 pt->AdapterType = ha->ad_type;
2006
2007 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2008 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2009 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2010 ips_free_flash_copperhead(ha);
2011
2012 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2013}
2014
2015/****************************************************************************/
2016/* */
2017/* Routine Name: ips_host_info */
2018/* */
2019/* Routine Description: */
2020/* */
2021/* The passthru interface for the driver */
2022/* */
2023/****************************************************************************/
2024static int
2025ips_host_info(ips_ha_t *ha, struct seq_file *m)
2026{
2027 METHOD_TRACE("ips_host_info", 1);
2028
2029 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2030
2031 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2032 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2033 seq_printf(m, "\tController Type : %s\n",
2034 ips_adapter_name[ha->ad_type - 1]);
2035 else
2036 seq_puts(m, "\tController Type : Unknown\n");
2037
2038 if (ha->io_addr)
2039 seq_printf(m,
2040 "\tIO region : 0x%x (%d bytes)\n",
2041 ha->io_addr, ha->io_len);
2042
2043 if (ha->mem_addr) {
2044 seq_printf(m,
2045 "\tMemory region : 0x%x (%d bytes)\n",
2046 ha->mem_addr, ha->mem_len);
2047 seq_printf(m,
2048 "\tShared memory address : 0x%lx\n",
2049 (unsigned long)ha->mem_ptr);
2050 }
2051
2052 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2053
2054 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2055 /* That keeps everything happy for "text" operations on the proc file. */
2056
2057 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2058 if (ha->nvram->bios_low[3] == 0) {
2059 seq_printf(m,
2060 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2061 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2062 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2063 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2064 ha->nvram->bios_low[2]);
2065
2066 } else {
2067 seq_printf(m,
2068 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2069 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2070 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2071 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2072 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2073 }
2074
2075 }
2076
2077 if (ha->enq->CodeBlkVersion[7] == 0) {
2078 seq_printf(m,
2079 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2080 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2081 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2082 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2083 ha->enq->CodeBlkVersion[6]);
2084 } else {
2085 seq_printf(m,
2086 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2087 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2088 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2089 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2090 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2091 }
2092
2093 if (ha->enq->BootBlkVersion[7] == 0) {
2094 seq_printf(m,
2095 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2096 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2097 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2098 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2099 ha->enq->BootBlkVersion[6]);
2100 } else {
2101 seq_printf(m,
2102 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2103 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2104 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2105 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2106 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2107 }
2108
2109 seq_printf(m, "\tDriver Version : %s%s\n",
2110 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2111
2112 seq_printf(m, "\tDriver Build : %d\n",
2113 IPS_BUILD_IDENT);
2114
2115 seq_printf(m, "\tMax Physical Devices : %d\n",
2116 ha->enq->ucMaxPhysicalDevices);
2117 seq_printf(m, "\tMax Active Commands : %d\n",
2118 ha->max_cmds);
2119 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2120 ha->scb_waitlist.count);
2121 seq_printf(m, "\tCurrent Active Commands : %d\n",
2122 ha->scb_activelist.count - ha->num_ioctl);
2123 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2124 ha->copp_waitlist.count);
2125 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2126 ha->num_ioctl);
2127
2128 seq_putc(m, '\n');
2129
2130 return 0;
2131}
2132
2133/****************************************************************************/
2134/* */
2135/* Routine Name: ips_identify_controller */
2136/* */
2137/* Routine Description: */
2138/* */
2139/* Identify this controller */
2140/* */
2141/****************************************************************************/
2142static void
2143ips_identify_controller(ips_ha_t * ha)
2144{
2145 METHOD_TRACE("ips_identify_controller", 1);
2146
2147 switch (ha->pcidev->device) {
2148 case IPS_DEVICEID_COPPERHEAD:
2149 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2150 ha->ad_type = IPS_ADTYPE_SERVERAID;
2151 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2152 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2153 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2154 ha->ad_type = IPS_ADTYPE_NAVAJO;
2155 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2156 && (ha->slot_num == 0)) {
2157 ha->ad_type = IPS_ADTYPE_KIOWA;
2158 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2159 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2160 if (ha->enq->ucMaxPhysicalDevices == 15)
2161 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2162 else
2163 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2164 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2165 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2166 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2167 }
2168 break;
2169
2170 case IPS_DEVICEID_MORPHEUS:
2171 switch (ha->pcidev->subsystem_device) {
2172 case IPS_SUBDEVICEID_4L:
2173 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2174 break;
2175
2176 case IPS_SUBDEVICEID_4M:
2177 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2178 break;
2179
2180 case IPS_SUBDEVICEID_4MX:
2181 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2182 break;
2183
2184 case IPS_SUBDEVICEID_4LX:
2185 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2186 break;
2187
2188 case IPS_SUBDEVICEID_5I2:
2189 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2190 break;
2191
2192 case IPS_SUBDEVICEID_5I1:
2193 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2194 break;
2195 }
2196
2197 break;
2198
2199 case IPS_DEVICEID_MARCO:
2200 switch (ha->pcidev->subsystem_device) {
2201 case IPS_SUBDEVICEID_6M:
2202 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2203 break;
2204 case IPS_SUBDEVICEID_6I:
2205 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2206 break;
2207 case IPS_SUBDEVICEID_7k:
2208 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2209 break;
2210 case IPS_SUBDEVICEID_7M:
2211 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2212 break;
2213 }
2214 break;
2215 }
2216}
2217
2218/****************************************************************************/
2219/* */
2220/* Routine Name: ips_get_bios_version */
2221/* */
2222/* Routine Description: */
2223/* */
2224/* Get the BIOS revision number */
2225/* */
2226/****************************************************************************/
2227static void
2228ips_get_bios_version(ips_ha_t * ha, int intr)
2229{
2230 ips_scb_t *scb;
2231 int ret;
2232 uint8_t major;
2233 uint8_t minor;
2234 uint8_t subminor;
2235 uint8_t *buffer;
2236
2237 METHOD_TRACE("ips_get_bios_version", 1);
2238
2239 major = 0;
2240 minor = 0;
2241
2242 memcpy(ha->bios_version, " ?", 8);
2243
2244 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2245 if (IPS_USE_MEMIO(ha)) {
2246 /* Memory Mapped I/O */
2247
2248 /* test 1st byte */
2249 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2250 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2251 udelay(25); /* 25 us */
2252
2253 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2254 return;
2255
2256 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2257 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2258 udelay(25); /* 25 us */
2259
2260 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2261 return;
2262
2263 /* Get Major version */
2264 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2266 udelay(25); /* 25 us */
2267
2268 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2269
2270 /* Get Minor version */
2271 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2272 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2273 udelay(25); /* 25 us */
2274 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2275
2276 /* Get SubMinor version */
2277 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2278 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2279 udelay(25); /* 25 us */
2280 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2281
2282 } else {
2283 /* Programmed I/O */
2284
2285 /* test 1st byte */
2286 outl(0, ha->io_addr + IPS_REG_FLAP);
2287 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2288 udelay(25); /* 25 us */
2289
2290 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2291 return;
2292
2293 outl(1, ha->io_addr + IPS_REG_FLAP);
2294 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2295 udelay(25); /* 25 us */
2296
2297 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2298 return;
2299
2300 /* Get Major version */
2301 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2302 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2303 udelay(25); /* 25 us */
2304
2305 major = inb(ha->io_addr + IPS_REG_FLDP);
2306
2307 /* Get Minor version */
2308 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2309 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2310 udelay(25); /* 25 us */
2311
2312 minor = inb(ha->io_addr + IPS_REG_FLDP);
2313
2314 /* Get SubMinor version */
2315 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2316 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2317 udelay(25); /* 25 us */
2318
2319 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2320
2321 }
2322 } else {
2323 /* Morpheus Family - Send Command to the card */
2324
2325 buffer = ha->ioctl_data;
2326
2327 memset(buffer, 0, 0x1000);
2328
2329 scb = &ha->scbs[ha->max_cmds - 1];
2330
2331 ips_init_scb(ha, scb);
2332
2333 scb->timeout = ips_cmd_timeout;
2334 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2335
2336 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2337 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2338 scb->cmd.flashfw.type = 1;
2339 scb->cmd.flashfw.direction = 0;
2340 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2341 scb->cmd.flashfw.total_packets = 1;
2342 scb->cmd.flashfw.packet_num = 0;
2343 scb->data_len = 0x1000;
2344 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2345
2346 /* issue the command */
2347 if (((ret =
2348 ips_send_wait(ha, scb, ips_cmd_timeout,
2349 intr)) == IPS_FAILURE)
2350 || (ret == IPS_SUCCESS_IMM)
2351 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2352 /* Error occurred */
2353
2354 return;
2355 }
2356
2357 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2358 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2359 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2360 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2361 } else {
2362 return;
2363 }
2364 }
2365
2366 ha->bios_version[0] = hex_asc_upper_hi(major);
2367 ha->bios_version[1] = '.';
2368 ha->bios_version[2] = hex_asc_upper_lo(major);
2369 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2370 ha->bios_version[4] = '.';
2371 ha->bios_version[5] = hex_asc_upper_hi(minor);
2372 ha->bios_version[6] = hex_asc_upper_lo(minor);
2373 ha->bios_version[7] = 0;
2374}
2375
2376/****************************************************************************/
2377/* */
2378/* Routine Name: ips_hainit */
2379/* */
2380/* Routine Description: */
2381/* */
2382/* Initialize the controller */
2383/* */
2384/* NOTE: Assumes to be called from with a lock */
2385/* */
2386/****************************************************************************/
2387static int
2388ips_hainit(ips_ha_t * ha)
2389{
2390 int i;
2391
2392 METHOD_TRACE("ips_hainit", 1);
2393
2394 if (!ha)
2395 return (0);
2396
2397 if (ha->func.statinit)
2398 (*ha->func.statinit) (ha);
2399
2400 if (ha->func.enableint)
2401 (*ha->func.enableint) (ha);
2402
2403 /* Send FFDC */
2404 ha->reset_count = 1;
2405 ha->last_ffdc = ktime_get_real_seconds();
2406 ips_ffdc_reset(ha, IPS_INTR_IORL);
2407
2408 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2409 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2410 "unable to read config from controller.\n");
2411
2412 return (0);
2413 }
2414 /* end if */
2415 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2416 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2417 "unable to read controller status.\n");
2418
2419 return (0);
2420 }
2421
2422 /* Identify this controller */
2423 ips_identify_controller(ha);
2424
2425 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2426 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2427 "unable to read subsystem parameters.\n");
2428
2429 return (0);
2430 }
2431
2432 /* write nvram user page 5 */
2433 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2434 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2435 "unable to write driver info to controller.\n");
2436
2437 return (0);
2438 }
2439
2440 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2441 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2442 ips_clear_adapter(ha, IPS_INTR_IORL);
2443
2444 /* set limits on SID, LUN, BUS */
2445 ha->ntargets = IPS_MAX_TARGETS + 1;
2446 ha->nlun = 1;
2447 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2448
2449 switch (ha->conf->logical_drive[0].ucStripeSize) {
2450 case 4:
2451 ha->max_xfer = 0x10000;
2452 break;
2453
2454 case 5:
2455 ha->max_xfer = 0x20000;
2456 break;
2457
2458 case 6:
2459 ha->max_xfer = 0x40000;
2460 break;
2461
2462 case 7:
2463 default:
2464 ha->max_xfer = 0x80000;
2465 break;
2466 }
2467
2468 /* setup max concurrent commands */
2469 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2470 /* Use the new method */
2471 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2472 } else {
2473 /* use the old method */
2474 switch (ha->conf->logical_drive[0].ucStripeSize) {
2475 case 4:
2476 ha->max_cmds = 32;
2477 break;
2478
2479 case 5:
2480 ha->max_cmds = 16;
2481 break;
2482
2483 case 6:
2484 ha->max_cmds = 8;
2485 break;
2486
2487 case 7:
2488 default:
2489 ha->max_cmds = 4;
2490 break;
2491 }
2492 }
2493
2494 /* Limit the Active Commands on a Lite Adapter */
2495 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2496 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2497 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2498 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2499 ha->max_cmds = MaxLiteCmds;
2500 }
2501
2502 /* set controller IDs */
2503 ha->ha_id[0] = IPS_ADAPTER_ID;
2504 for (i = 1; i < ha->nbus; i++) {
2505 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2506 ha->dcdb_active[i - 1] = 0;
2507 }
2508
2509 return (1);
2510}
2511
2512/****************************************************************************/
2513/* */
2514/* Routine Name: ips_next */
2515/* */
2516/* Routine Description: */
2517/* */
2518/* Take the next command off the queue and send it to the controller */
2519/* */
2520/****************************************************************************/
2521static void
2522ips_next(ips_ha_t * ha, int intr)
2523{
2524 ips_scb_t *scb;
2525 struct scsi_cmnd *SC;
2526 struct scsi_cmnd *p;
2527 struct scsi_cmnd *q;
2528 ips_copp_wait_item_t *item;
2529 int ret;
2530 struct Scsi_Host *host;
2531 METHOD_TRACE("ips_next", 1);
2532
2533 if (!ha)
2534 return;
2535 host = ips_sh[ha->host_num];
2536 /*
2537 * Block access to the queue function so
2538 * this command won't time out
2539 */
2540 if (intr == IPS_INTR_ON)
2541 spin_lock(host->host_lock);
2542
2543 if ((ha->subsys->param[3] & 0x300000)
2544 && (ha->scb_activelist.count == 0)) {
2545 time64_t now = ktime_get_real_seconds();
2546 if (now - ha->last_ffdc > IPS_SECS_8HOURS) {
2547 ha->last_ffdc = now;
2548 ips_ffdc_time(ha);
2549 }
2550 }
2551
2552 /*
2553 * Send passthru commands
2554 * These have priority over normal I/O
2555 * but shouldn't affect performance too much
2556 * since we limit the number that can be active
2557 * on the card at any one time
2558 */
2559 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2560 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2561
2562 item = ips_removeq_copp_head(&ha->copp_waitlist);
2563 ha->num_ioctl++;
2564 if (intr == IPS_INTR_ON)
2565 spin_unlock(host->host_lock);
2566 scb->scsi_cmd = item->scsi_cmd;
2567 kfree(item);
2568
2569 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2570
2571 if (intr == IPS_INTR_ON)
2572 spin_lock(host->host_lock);
2573 switch (ret) {
2574 case IPS_FAILURE:
2575 if (scb->scsi_cmd) {
2576 scb->scsi_cmd->result = DID_ERROR << 16;
2577 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2578 }
2579
2580 ips_freescb(ha, scb);
2581 break;
2582 case IPS_SUCCESS_IMM:
2583 if (scb->scsi_cmd) {
2584 scb->scsi_cmd->result = DID_OK << 16;
2585 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2586 }
2587
2588 ips_freescb(ha, scb);
2589 break;
2590 default:
2591 break;
2592 } /* end case */
2593
2594 if (ret != IPS_SUCCESS) {
2595 ha->num_ioctl--;
2596 continue;
2597 }
2598
2599 ret = ips_send_cmd(ha, scb);
2600
2601 if (ret == IPS_SUCCESS)
2602 ips_putq_scb_head(&ha->scb_activelist, scb);
2603 else
2604 ha->num_ioctl--;
2605
2606 switch (ret) {
2607 case IPS_FAILURE:
2608 if (scb->scsi_cmd) {
2609 scb->scsi_cmd->result = DID_ERROR << 16;
2610 }
2611
2612 ips_freescb(ha, scb);
2613 break;
2614 case IPS_SUCCESS_IMM:
2615 ips_freescb(ha, scb);
2616 break;
2617 default:
2618 break;
2619 } /* end case */
2620
2621 }
2622
2623 /*
2624 * Send "Normal" I/O commands
2625 */
2626
2627 p = ha->scb_waitlist.head;
2628 while ((p) && (scb = ips_getscb(ha))) {
2629 if ((scmd_channel(p) > 0)
2630 && (ha->
2631 dcdb_active[scmd_channel(p) -
2632 1] & (1 << scmd_id(p)))) {
2633 ips_freescb(ha, scb);
2634 p = (struct scsi_cmnd *) p->host_scribble;
2635 continue;
2636 }
2637
2638 q = p;
2639 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2640
2641 if (intr == IPS_INTR_ON)
2642 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2643
2644 SC->result = DID_OK;
2645 SC->host_scribble = NULL;
2646
2647 scb->target_id = SC->device->id;
2648 scb->lun = SC->device->lun;
2649 scb->bus = SC->device->channel;
2650 scb->scsi_cmd = SC;
2651 scb->breakup = 0;
2652 scb->data_len = 0;
2653 scb->callback = ipsintr_done;
2654 scb->timeout = ips_cmd_timeout;
2655 memset(&scb->cmd, 0, 16);
2656
2657 /* copy in the CDB */
2658 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2659
2660 scb->sg_count = scsi_dma_map(SC);
2661 BUG_ON(scb->sg_count < 0);
2662 if (scb->sg_count) {
2663 struct scatterlist *sg;
2664 int i;
2665
2666 scb->flags |= IPS_SCB_MAP_SG;
2667
2668 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2669 if (ips_fill_scb_sg_single
2670 (ha, sg_dma_address(sg), scb, i,
2671 sg_dma_len(sg)) < 0)
2672 break;
2673 }
2674 scb->dcdb.transfer_length = scb->data_len;
2675 } else {
2676 scb->data_busaddr = 0L;
2677 scb->sg_len = 0;
2678 scb->data_len = 0;
2679 scb->dcdb.transfer_length = 0;
2680 }
2681
2682 scb->dcdb.cmd_attribute =
2683 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2684
2685 /* Allow a WRITE BUFFER Command to Have no Data */
2686 /* This is Used by Tape Flash Utilites */
2687 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2688 (scb->data_len == 0))
2689 scb->dcdb.cmd_attribute = 0;
2690
2691 if (!(scb->dcdb.cmd_attribute & 0x3))
2692 scb->dcdb.transfer_length = 0;
2693
2694 if (scb->data_len >= IPS_MAX_XFER) {
2695 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2696 scb->dcdb.transfer_length = 0;
2697 }
2698 if (intr == IPS_INTR_ON)
2699 spin_lock(host->host_lock);
2700
2701 ret = ips_send_cmd(ha, scb);
2702
2703 switch (ret) {
2704 case IPS_SUCCESS:
2705 ips_putq_scb_head(&ha->scb_activelist, scb);
2706 break;
2707 case IPS_FAILURE:
2708 if (scb->scsi_cmd) {
2709 scb->scsi_cmd->result = DID_ERROR << 16;
2710 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2711 }
2712
2713 if (scb->bus)
2714 ha->dcdb_active[scb->bus - 1] &=
2715 ~(1 << scb->target_id);
2716
2717 ips_freescb(ha, scb);
2718 break;
2719 case IPS_SUCCESS_IMM:
2720 if (scb->scsi_cmd)
2721 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2722
2723 if (scb->bus)
2724 ha->dcdb_active[scb->bus - 1] &=
2725 ~(1 << scb->target_id);
2726
2727 ips_freescb(ha, scb);
2728 break;
2729 default:
2730 break;
2731 } /* end case */
2732
2733 p = (struct scsi_cmnd *) p->host_scribble;
2734
2735 } /* end while */
2736
2737 if (intr == IPS_INTR_ON)
2738 spin_unlock(host->host_lock);
2739}
2740
2741/****************************************************************************/
2742/* */
2743/* Routine Name: ips_putq_scb_head */
2744/* */
2745/* Routine Description: */
2746/* */
2747/* Add an item to the head of the queue */
2748/* */
2749/* ASSUMED to be called from within the HA lock */
2750/* */
2751/****************************************************************************/
2752static void
2753ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2754{
2755 METHOD_TRACE("ips_putq_scb_head", 1);
2756
2757 if (!item)
2758 return;
2759
2760 item->q_next = queue->head;
2761 queue->head = item;
2762
2763 if (!queue->tail)
2764 queue->tail = item;
2765
2766 queue->count++;
2767}
2768
2769/****************************************************************************/
2770/* */
2771/* Routine Name: ips_removeq_scb_head */
2772/* */
2773/* Routine Description: */
2774/* */
2775/* Remove the head of the queue */
2776/* */
2777/* ASSUMED to be called from within the HA lock */
2778/* */
2779/****************************************************************************/
2780static ips_scb_t *
2781ips_removeq_scb_head(ips_scb_queue_t * queue)
2782{
2783 ips_scb_t *item;
2784
2785 METHOD_TRACE("ips_removeq_scb_head", 1);
2786
2787 item = queue->head;
2788
2789 if (!item) {
2790 return (NULL);
2791 }
2792
2793 queue->head = item->q_next;
2794 item->q_next = NULL;
2795
2796 if (queue->tail == item)
2797 queue->tail = NULL;
2798
2799 queue->count--;
2800
2801 return (item);
2802}
2803
2804/****************************************************************************/
2805/* */
2806/* Routine Name: ips_removeq_scb */
2807/* */
2808/* Routine Description: */
2809/* */
2810/* Remove an item from a queue */
2811/* */
2812/* ASSUMED to be called from within the HA lock */
2813/* */
2814/****************************************************************************/
2815static ips_scb_t *
2816ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2817{
2818 ips_scb_t *p;
2819
2820 METHOD_TRACE("ips_removeq_scb", 1);
2821
2822 if (!item)
2823 return (NULL);
2824
2825 if (item == queue->head) {
2826 return (ips_removeq_scb_head(queue));
2827 }
2828
2829 p = queue->head;
2830
2831 while ((p) && (item != p->q_next))
2832 p = p->q_next;
2833
2834 if (p) {
2835 /* found a match */
2836 p->q_next = item->q_next;
2837
2838 if (!item->q_next)
2839 queue->tail = p;
2840
2841 item->q_next = NULL;
2842 queue->count--;
2843
2844 return (item);
2845 }
2846
2847 return (NULL);
2848}
2849
2850/****************************************************************************/
2851/* */
2852/* Routine Name: ips_putq_wait_tail */
2853/* */
2854/* Routine Description: */
2855/* */
2856/* Add an item to the tail of the queue */
2857/* */
2858/* ASSUMED to be called from within the HA lock */
2859/* */
2860/****************************************************************************/
2861static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
2862{
2863 METHOD_TRACE("ips_putq_wait_tail", 1);
2864
2865 if (!item)
2866 return;
2867
2868 item->host_scribble = NULL;
2869
2870 if (queue->tail)
2871 queue->tail->host_scribble = (char *) item;
2872
2873 queue->tail = item;
2874
2875 if (!queue->head)
2876 queue->head = item;
2877
2878 queue->count++;
2879}
2880
2881/****************************************************************************/
2882/* */
2883/* Routine Name: ips_removeq_wait_head */
2884/* */
2885/* Routine Description: */
2886/* */
2887/* Remove the head of the queue */
2888/* */
2889/* ASSUMED to be called from within the HA lock */
2890/* */
2891/****************************************************************************/
2892static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
2893{
2894 struct scsi_cmnd *item;
2895
2896 METHOD_TRACE("ips_removeq_wait_head", 1);
2897
2898 item = queue->head;
2899
2900 if (!item) {
2901 return (NULL);
2902 }
2903
2904 queue->head = (struct scsi_cmnd *) item->host_scribble;
2905 item->host_scribble = NULL;
2906
2907 if (queue->tail == item)
2908 queue->tail = NULL;
2909
2910 queue->count--;
2911
2912 return (item);
2913}
2914
2915/****************************************************************************/
2916/* */
2917/* Routine Name: ips_removeq_wait */
2918/* */
2919/* Routine Description: */
2920/* */
2921/* Remove an item from a queue */
2922/* */
2923/* ASSUMED to be called from within the HA lock */
2924/* */
2925/****************************************************************************/
2926static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
2927 struct scsi_cmnd *item)
2928{
2929 struct scsi_cmnd *p;
2930
2931 METHOD_TRACE("ips_removeq_wait", 1);
2932
2933 if (!item)
2934 return (NULL);
2935
2936 if (item == queue->head) {
2937 return (ips_removeq_wait_head(queue));
2938 }
2939
2940 p = queue->head;
2941
2942 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2943 p = (struct scsi_cmnd *) p->host_scribble;
2944
2945 if (p) {
2946 /* found a match */
2947 p->host_scribble = item->host_scribble;
2948
2949 if (!item->host_scribble)
2950 queue->tail = p;
2951
2952 item->host_scribble = NULL;
2953 queue->count--;
2954
2955 return (item);
2956 }
2957
2958 return (NULL);
2959}
2960
2961/****************************************************************************/
2962/* */
2963/* Routine Name: ips_putq_copp_tail */
2964/* */
2965/* Routine Description: */
2966/* */
2967/* Add an item to the tail of the queue */
2968/* */
2969/* ASSUMED to be called from within the HA lock */
2970/* */
2971/****************************************************************************/
2972static void
2973ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2974{
2975 METHOD_TRACE("ips_putq_copp_tail", 1);
2976
2977 if (!item)
2978 return;
2979
2980 item->next = NULL;
2981
2982 if (queue->tail)
2983 queue->tail->next = item;
2984
2985 queue->tail = item;
2986
2987 if (!queue->head)
2988 queue->head = item;
2989
2990 queue->count++;
2991}
2992
2993/****************************************************************************/
2994/* */
2995/* Routine Name: ips_removeq_copp_head */
2996/* */
2997/* Routine Description: */
2998/* */
2999/* Remove the head of the queue */
3000/* */
3001/* ASSUMED to be called from within the HA lock */
3002/* */
3003/****************************************************************************/
3004static ips_copp_wait_item_t *
3005ips_removeq_copp_head(ips_copp_queue_t * queue)
3006{
3007 ips_copp_wait_item_t *item;
3008
3009 METHOD_TRACE("ips_removeq_copp_head", 1);
3010
3011 item = queue->head;
3012
3013 if (!item) {
3014 return (NULL);
3015 }
3016
3017 queue->head = item->next;
3018 item->next = NULL;
3019
3020 if (queue->tail == item)
3021 queue->tail = NULL;
3022
3023 queue->count--;
3024
3025 return (item);
3026}
3027
3028/****************************************************************************/
3029/* */
3030/* Routine Name: ips_removeq_copp */
3031/* */
3032/* Routine Description: */
3033/* */
3034/* Remove an item from a queue */
3035/* */
3036/* ASSUMED to be called from within the HA lock */
3037/* */
3038/****************************************************************************/
3039static ips_copp_wait_item_t *
3040ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3041{
3042 ips_copp_wait_item_t *p;
3043
3044 METHOD_TRACE("ips_removeq_copp", 1);
3045
3046 if (!item)
3047 return (NULL);
3048
3049 if (item == queue->head) {
3050 return (ips_removeq_copp_head(queue));
3051 }
3052
3053 p = queue->head;
3054
3055 while ((p) && (item != p->next))
3056 p = p->next;
3057
3058 if (p) {
3059 /* found a match */
3060 p->next = item->next;
3061
3062 if (!item->next)
3063 queue->tail = p;
3064
3065 item->next = NULL;
3066 queue->count--;
3067
3068 return (item);
3069 }
3070
3071 return (NULL);
3072}
3073
3074/****************************************************************************/
3075/* */
3076/* Routine Name: ipsintr_blocking */
3077/* */
3078/* Routine Description: */
3079/* */
3080/* Finalize an interrupt for internal commands */
3081/* */
3082/****************************************************************************/
3083static void
3084ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3085{
3086 METHOD_TRACE("ipsintr_blocking", 2);
3087
3088 ips_freescb(ha, scb);
3089 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3090 ha->waitflag = FALSE;
3091
3092 return;
3093 }
3094}
3095
3096/****************************************************************************/
3097/* */
3098/* Routine Name: ipsintr_done */
3099/* */
3100/* Routine Description: */
3101/* */
3102/* Finalize an interrupt for non-internal commands */
3103/* */
3104/****************************************************************************/
3105static void
3106ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3107{
3108 METHOD_TRACE("ipsintr_done", 2);
3109
3110 if (!scb) {
3111 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3112 "Spurious interrupt; scb NULL.\n");
3113
3114 return;
3115 }
3116
3117 if (scb->scsi_cmd == NULL) {
3118 /* unexpected interrupt */
3119 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3120 "Spurious interrupt; scsi_cmd not set.\n");
3121
3122 return;
3123 }
3124
3125 ips_done(ha, scb);
3126}
3127
3128/****************************************************************************/
3129/* */
3130/* Routine Name: ips_done */
3131/* */
3132/* Routine Description: */
3133/* */
3134/* Do housekeeping on completed commands */
3135/* ASSUMED to be called form within the request lock */
3136/****************************************************************************/
3137static void
3138ips_done(ips_ha_t * ha, ips_scb_t * scb)
3139{
3140 int ret;
3141
3142 METHOD_TRACE("ips_done", 1);
3143
3144 if (!scb)
3145 return;
3146
3147 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3148 ips_cleanup_passthru(ha, scb);
3149 ha->num_ioctl--;
3150 } else {
3151 /*
3152 * Check to see if this command had too much
3153 * data and had to be broke up. If so, queue
3154 * the rest of the data and continue.
3155 */
3156 if ((scb->breakup) || (scb->sg_break)) {
3157 struct scatterlist *sg;
3158 int i, sg_dma_index, ips_sg_index = 0;
3159
3160 /* we had a data breakup */
3161 scb->data_len = 0;
3162
3163 sg = scsi_sglist(scb->scsi_cmd);
3164
3165 /* Spin forward to last dma chunk */
3166 sg_dma_index = scb->breakup;
3167 for (i = 0; i < scb->breakup; i++)
3168 sg = sg_next(sg);
3169
3170 /* Take care of possible partial on last chunk */
3171 ips_fill_scb_sg_single(ha,
3172 sg_dma_address(sg),
3173 scb, ips_sg_index++,
3174 sg_dma_len(sg));
3175
3176 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3177 sg_dma_index++, sg = sg_next(sg)) {
3178 if (ips_fill_scb_sg_single
3179 (ha,
3180 sg_dma_address(sg),
3181 scb, ips_sg_index++,
3182 sg_dma_len(sg)) < 0)
3183 break;
3184 }
3185
3186 scb->dcdb.transfer_length = scb->data_len;
3187 scb->dcdb.cmd_attribute |=
3188 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3189
3190 if (!(scb->dcdb.cmd_attribute & 0x3))
3191 scb->dcdb.transfer_length = 0;
3192
3193 if (scb->data_len >= IPS_MAX_XFER) {
3194 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3195 scb->dcdb.transfer_length = 0;
3196 }
3197
3198 ret = ips_send_cmd(ha, scb);
3199
3200 switch (ret) {
3201 case IPS_FAILURE:
3202 if (scb->scsi_cmd) {
3203 scb->scsi_cmd->result = DID_ERROR << 16;
3204 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3205 }
3206
3207 ips_freescb(ha, scb);
3208 break;
3209 case IPS_SUCCESS_IMM:
3210 if (scb->scsi_cmd) {
3211 scb->scsi_cmd->result = DID_ERROR << 16;
3212 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3213 }
3214
3215 ips_freescb(ha, scb);
3216 break;
3217 default:
3218 break;
3219 } /* end case */
3220
3221 return;
3222 }
3223 } /* end if passthru */
3224
3225 if (scb->bus) {
3226 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3227 }
3228
3229 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3230
3231 ips_freescb(ha, scb);
3232}
3233
3234/****************************************************************************/
3235/* */
3236/* Routine Name: ips_map_status */
3237/* */
3238/* Routine Description: */
3239/* */
3240/* Map Controller Error codes to Linux Error Codes */
3241/* */
3242/****************************************************************************/
3243static int
3244ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3245{
3246 int errcode;
3247 int device_error;
3248 uint32_t transfer_len;
3249 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3250 IPS_SCSI_INQ_DATA inquiryData;
3251
3252 METHOD_TRACE("ips_map_status", 1);
3253
3254 if (scb->bus) {
3255 DEBUG_VAR(2,
3256 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3257 ips_name, ha->host_num,
3258 scb->scsi_cmd->device->channel,
3259 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3260 scb->basic_status, scb->extended_status,
3261 scb->extended_status ==
3262 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3263 scb->extended_status ==
3264 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3265 scb->extended_status ==
3266 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3267 }
3268
3269 /* default driver error */
3270 errcode = DID_ERROR;
3271 device_error = 0;
3272
3273 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3274 case IPS_CMD_TIMEOUT:
3275 errcode = DID_TIME_OUT;
3276 break;
3277
3278 case IPS_INVAL_OPCO:
3279 case IPS_INVAL_CMD_BLK:
3280 case IPS_INVAL_PARM_BLK:
3281 case IPS_LD_ERROR:
3282 case IPS_CMD_CMPLT_WERROR:
3283 break;
3284
3285 case IPS_PHYS_DRV_ERROR:
3286 switch (scb->extended_status) {
3287 case IPS_ERR_SEL_TO:
3288 if (scb->bus)
3289 errcode = DID_NO_CONNECT;
3290
3291 break;
3292
3293 case IPS_ERR_OU_RUN:
3294 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3295 (scb->cmd.dcdb.op_code ==
3296 IPS_CMD_EXTENDED_DCDB_SG)) {
3297 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3298 transfer_len = tapeDCDB->transfer_length;
3299 } else {
3300 transfer_len =
3301 (uint32_t) scb->dcdb.transfer_length;
3302 }
3303
3304 if ((scb->bus) && (transfer_len < scb->data_len)) {
3305 /* Underrun - set default to no error */
3306 errcode = DID_OK;
3307
3308 /* Restrict access to physical DASD */
3309 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3310 ips_scmd_buf_read(scb->scsi_cmd,
3311 &inquiryData, sizeof (inquiryData));
3312 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3313 errcode = DID_TIME_OUT;
3314 break;
3315 }
3316 }
3317 } else
3318 errcode = DID_ERROR;
3319
3320 break;
3321
3322 case IPS_ERR_RECOVERY:
3323 /* don't fail recovered errors */
3324 if (scb->bus)
3325 errcode = DID_OK;
3326
3327 break;
3328
3329 case IPS_ERR_HOST_RESET:
3330 case IPS_ERR_DEV_RESET:
3331 errcode = DID_RESET;
3332 break;
3333
3334 case IPS_ERR_CKCOND:
3335 if (scb->bus) {
3336 if ((scb->cmd.dcdb.op_code ==
3337 IPS_CMD_EXTENDED_DCDB)
3338 || (scb->cmd.dcdb.op_code ==
3339 IPS_CMD_EXTENDED_DCDB_SG)) {
3340 tapeDCDB =
3341 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3342 memcpy(scb->scsi_cmd->sense_buffer,
3343 tapeDCDB->sense_info,
3344 SCSI_SENSE_BUFFERSIZE);
3345 } else {
3346 memcpy(scb->scsi_cmd->sense_buffer,
3347 scb->dcdb.sense_info,
3348 SCSI_SENSE_BUFFERSIZE);
3349 }
3350 device_error = 2; /* check condition */
3351 }
3352
3353 errcode = DID_OK;
3354
3355 break;
3356
3357 default:
3358 errcode = DID_ERROR;
3359 break;
3360
3361 } /* end switch */
3362 } /* end switch */
3363
3364 scb->scsi_cmd->result = device_error | (errcode << 16);
3365
3366 return (1);
3367}
3368
3369/****************************************************************************/
3370/* */
3371/* Routine Name: ips_send_wait */
3372/* */
3373/* Routine Description: */
3374/* */
3375/* Send a command to the controller and wait for it to return */
3376/* */
3377/* The FFDC Time Stamp use this function for the callback, but doesn't */
3378/* actually need to wait. */
3379/****************************************************************************/
3380static int
3381ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3382{
3383 int ret;
3384
3385 METHOD_TRACE("ips_send_wait", 1);
3386
3387 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3388 ha->waitflag = TRUE;
3389 ha->cmd_in_progress = scb->cdb[0];
3390 }
3391 scb->callback = ipsintr_blocking;
3392 ret = ips_send_cmd(ha, scb);
3393
3394 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3395 return (ret);
3396
3397 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3398 ret = ips_wait(ha, timeout, intr);
3399
3400 return (ret);
3401}
3402
3403/****************************************************************************/
3404/* */
3405/* Routine Name: ips_scmd_buf_write */
3406/* */
3407/* Routine Description: */
3408/* Write data to struct scsi_cmnd request_buffer at proper offsets */
3409/****************************************************************************/
3410static void
3411ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3412{
3413 unsigned long flags;
3414
3415 local_irq_save(flags);
3416 scsi_sg_copy_from_buffer(scmd, data, count);
3417 local_irq_restore(flags);
3418}
3419
3420/****************************************************************************/
3421/* */
3422/* Routine Name: ips_scmd_buf_read */
3423/* */
3424/* Routine Description: */
3425/* Copy data from a struct scsi_cmnd to a new, linear buffer */
3426/****************************************************************************/
3427static void
3428ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3429{
3430 unsigned long flags;
3431
3432 local_irq_save(flags);
3433 scsi_sg_copy_to_buffer(scmd, data, count);
3434 local_irq_restore(flags);
3435}
3436
3437/****************************************************************************/
3438/* */
3439/* Routine Name: ips_send_cmd */
3440/* */
3441/* Routine Description: */
3442/* */
3443/* Map SCSI commands to ServeRAID commands for logical drives */
3444/* */
3445/****************************************************************************/
3446static int
3447ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3448{
3449 int ret;
3450 char *sp;
3451 int device_error;
3452 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3453 int TimeOut;
3454
3455 METHOD_TRACE("ips_send_cmd", 1);
3456
3457 ret = IPS_SUCCESS;
3458
3459 if (!scb->scsi_cmd) {
3460 /* internal command */
3461
3462 if (scb->bus > 0) {
3463 /* Controller commands can't be issued */
3464 /* to real devices -- fail them */
3465 if ((ha->waitflag == TRUE) &&
3466 (ha->cmd_in_progress == scb->cdb[0])) {
3467 ha->waitflag = FALSE;
3468 }
3469
3470 return (1);
3471 }
3472 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3473 /* command to logical bus -- interpret */
3474 ret = IPS_SUCCESS_IMM;
3475
3476 switch (scb->scsi_cmd->cmnd[0]) {
3477 case ALLOW_MEDIUM_REMOVAL:
3478 case REZERO_UNIT:
3479 case ERASE:
3480 case WRITE_FILEMARKS:
3481 case SPACE:
3482 scb->scsi_cmd->result = DID_ERROR << 16;
3483 break;
3484
3485 case START_STOP:
3486 scb->scsi_cmd->result = DID_OK << 16;
3487 break;
3488
3489 case TEST_UNIT_READY:
3490 case INQUIRY:
3491 if (scb->target_id == IPS_ADAPTER_ID) {
3492 /*
3493 * Either we have a TUR
3494 * or we have a SCSI inquiry
3495 */
3496 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3497 scb->scsi_cmd->result = DID_OK << 16;
3498
3499 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3500 IPS_SCSI_INQ_DATA inquiry;
3501
3502 memset(&inquiry, 0,
3503 sizeof (IPS_SCSI_INQ_DATA));
3504
3505 inquiry.DeviceType =
3506 IPS_SCSI_INQ_TYPE_PROCESSOR;
3507 inquiry.DeviceTypeQualifier =
3508 IPS_SCSI_INQ_LU_CONNECTED;
3509 inquiry.Version = IPS_SCSI_INQ_REV2;
3510 inquiry.ResponseDataFormat =
3511 IPS_SCSI_INQ_RD_REV2;
3512 inquiry.AdditionalLength = 31;
3513 inquiry.Flags[0] =
3514 IPS_SCSI_INQ_Address16;
3515 inquiry.Flags[1] =
3516 IPS_SCSI_INQ_WBus16 |
3517 IPS_SCSI_INQ_Sync;
3518 memcpy(inquiry.VendorId, "IBM ",
3519 8);
3520 memcpy(inquiry.ProductId,
3521 "SERVERAID ", 16);
3522 memcpy(inquiry.ProductRevisionLevel,
3523 "1.00", 4);
3524
3525 ips_scmd_buf_write(scb->scsi_cmd,
3526 &inquiry,
3527 sizeof (inquiry));
3528
3529 scb->scsi_cmd->result = DID_OK << 16;
3530 }
3531 } else {
3532 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3533 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3534 scb->cmd.logical_info.reserved = 0;
3535 scb->cmd.logical_info.reserved2 = 0;
3536 scb->data_len = sizeof (IPS_LD_INFO);
3537 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3538 scb->flags = 0;
3539 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3540 ret = IPS_SUCCESS;
3541 }
3542
3543 break;
3544
3545 case REQUEST_SENSE:
3546 ips_reqsen(ha, scb);
3547 scb->scsi_cmd->result = DID_OK << 16;
3548 break;
3549
3550 case READ_6:
3551 case WRITE_6:
3552 if (!scb->sg_len) {
3553 scb->cmd.basic_io.op_code =
3554 (scb->scsi_cmd->cmnd[0] ==
3555 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3556 scb->cmd.basic_io.enhanced_sg = 0;
3557 scb->cmd.basic_io.sg_addr =
3558 cpu_to_le32(scb->data_busaddr);
3559 } else {
3560 scb->cmd.basic_io.op_code =
3561 (scb->scsi_cmd->cmnd[0] ==
3562 READ_6) ? IPS_CMD_READ_SG :
3563 IPS_CMD_WRITE_SG;
3564 scb->cmd.basic_io.enhanced_sg =
3565 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3566 scb->cmd.basic_io.sg_addr =
3567 cpu_to_le32(scb->sg_busaddr);
3568 }
3569
3570 scb->cmd.basic_io.segment_4G = 0;
3571 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3572 scb->cmd.basic_io.log_drv = scb->target_id;
3573 scb->cmd.basic_io.sg_count = scb->sg_len;
3574
3575 if (scb->cmd.basic_io.lba)
3576 le32_add_cpu(&scb->cmd.basic_io.lba,
3577 le16_to_cpu(scb->cmd.basic_io.
3578 sector_count));
3579 else
3580 scb->cmd.basic_io.lba =
3581 (((scb->scsi_cmd->
3582 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3583 cmnd[2] << 8) |
3584 (scb->scsi_cmd->cmnd[3]));
3585
3586 scb->cmd.basic_io.sector_count =
3587 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3588
3589 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3590 scb->cmd.basic_io.sector_count =
3591 cpu_to_le16(256);
3592
3593 ret = IPS_SUCCESS;
3594 break;
3595
3596 case READ_10:
3597 case WRITE_10:
3598 if (!scb->sg_len) {
3599 scb->cmd.basic_io.op_code =
3600 (scb->scsi_cmd->cmnd[0] ==
3601 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3602 scb->cmd.basic_io.enhanced_sg = 0;
3603 scb->cmd.basic_io.sg_addr =
3604 cpu_to_le32(scb->data_busaddr);
3605 } else {
3606 scb->cmd.basic_io.op_code =
3607 (scb->scsi_cmd->cmnd[0] ==
3608 READ_10) ? IPS_CMD_READ_SG :
3609 IPS_CMD_WRITE_SG;
3610 scb->cmd.basic_io.enhanced_sg =
3611 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3612 scb->cmd.basic_io.sg_addr =
3613 cpu_to_le32(scb->sg_busaddr);
3614 }
3615
3616 scb->cmd.basic_io.segment_4G = 0;
3617 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3618 scb->cmd.basic_io.log_drv = scb->target_id;
3619 scb->cmd.basic_io.sg_count = scb->sg_len;
3620
3621 if (scb->cmd.basic_io.lba)
3622 le32_add_cpu(&scb->cmd.basic_io.lba,
3623 le16_to_cpu(scb->cmd.basic_io.
3624 sector_count));
3625 else
3626 scb->cmd.basic_io.lba =
3627 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3628 scsi_cmd->
3629 cmnd[3]
3630 << 16) |
3631 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3632 scsi_cmd->cmnd[5]);
3633
3634 scb->cmd.basic_io.sector_count =
3635 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3636
3637 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3638 /*
3639 * This is a null condition
3640 * we don't have to do anything
3641 * so just return
3642 */
3643 scb->scsi_cmd->result = DID_OK << 16;
3644 } else
3645 ret = IPS_SUCCESS;
3646
3647 break;
3648
3649 case RESERVE:
3650 case RELEASE:
3651 scb->scsi_cmd->result = DID_OK << 16;
3652 break;
3653
3654 case MODE_SENSE:
3655 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3656 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3657 scb->cmd.basic_io.segment_4G = 0;
3658 scb->cmd.basic_io.enhanced_sg = 0;
3659 scb->data_len = sizeof (*ha->enq);
3660 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3661 ret = IPS_SUCCESS;
3662 break;
3663
3664 case READ_CAPACITY:
3665 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3666 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3667 scb->cmd.logical_info.reserved = 0;
3668 scb->cmd.logical_info.reserved2 = 0;
3669 scb->cmd.logical_info.reserved3 = 0;
3670 scb->data_len = sizeof (IPS_LD_INFO);
3671 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3672 scb->flags = 0;
3673 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3674 ret = IPS_SUCCESS;
3675 break;
3676
3677 case SEND_DIAGNOSTIC:
3678 case REASSIGN_BLOCKS:
3679 case FORMAT_UNIT:
3680 case SEEK_10:
3681 case VERIFY:
3682 case READ_DEFECT_DATA:
3683 case READ_BUFFER:
3684 case WRITE_BUFFER:
3685 scb->scsi_cmd->result = DID_OK << 16;
3686 break;
3687
3688 default:
3689 /* Set the Return Info to appear like the Command was */
3690 /* attempted, a Check Condition occurred, and Sense */
3691 /* Data indicating an Invalid CDB OpCode is returned. */
3692 sp = (char *) scb->scsi_cmd->sense_buffer;
3693
3694 sp[0] = 0x70; /* Error Code */
3695 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3696 sp[7] = 0x0A; /* Additional Sense Length */
3697 sp[12] = 0x20; /* ASC = Invalid OpCode */
3698 sp[13] = 0x00; /* ASCQ */
3699
3700 device_error = 2; /* Indicate Check Condition */
3701 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3702 break;
3703 } /* end switch */
3704 }
3705 /* end if */
3706 if (ret == IPS_SUCCESS_IMM)
3707 return (ret);
3708
3709 /* setup DCDB */
3710 if (scb->bus > 0) {
3711
3712 /* If we already know the Device is Not there, no need to attempt a Command */
3713 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3714 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3715 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3716 return (IPS_SUCCESS_IMM);
3717 }
3718
3719 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3720 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3721 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3722 (unsigned long) &scb->
3723 dcdb -
3724 (unsigned long) scb);
3725 scb->cmd.dcdb.reserved = 0;
3726 scb->cmd.dcdb.reserved2 = 0;
3727 scb->cmd.dcdb.reserved3 = 0;
3728 scb->cmd.dcdb.segment_4G = 0;
3729 scb->cmd.dcdb.enhanced_sg = 0;
3730
3731 TimeOut = scb->scsi_cmd->request->timeout;
3732
3733 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3734 if (!scb->sg_len) {
3735 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3736 } else {
3737 scb->cmd.dcdb.op_code =
3738 IPS_CMD_EXTENDED_DCDB_SG;
3739 scb->cmd.dcdb.enhanced_sg =
3740 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3741 }
3742
3743 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3744 tapeDCDB->device_address =
3745 ((scb->bus - 1) << 4) | scb->target_id;
3746 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3747 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3748
3749 if (TimeOut) {
3750 if (TimeOut < (10 * HZ))
3751 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3752 else if (TimeOut < (60 * HZ))
3753 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3754 else if (TimeOut < (1200 * HZ))
3755 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3756 }
3757
3758 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3759 tapeDCDB->reserved_for_LUN = 0;
3760 tapeDCDB->transfer_length = scb->data_len;
3761 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3762 tapeDCDB->buffer_pointer =
3763 cpu_to_le32(scb->sg_busaddr);
3764 else
3765 tapeDCDB->buffer_pointer =
3766 cpu_to_le32(scb->data_busaddr);
3767 tapeDCDB->sg_count = scb->sg_len;
3768 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3769 tapeDCDB->scsi_status = 0;
3770 tapeDCDB->reserved = 0;
3771 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3772 scb->scsi_cmd->cmd_len);
3773 } else {
3774 if (!scb->sg_len) {
3775 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3776 } else {
3777 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3778 scb->cmd.dcdb.enhanced_sg =
3779 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3780 }
3781
3782 scb->dcdb.device_address =
3783 ((scb->bus - 1) << 4) | scb->target_id;
3784 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3785
3786 if (TimeOut) {
3787 if (TimeOut < (10 * HZ))
3788 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3789 else if (TimeOut < (60 * HZ))
3790 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3791 else if (TimeOut < (1200 * HZ))
3792 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3793 }
3794
3795 scb->dcdb.transfer_length = scb->data_len;
3796 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3797 scb->dcdb.transfer_length = 0;
3798 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3799 scb->dcdb.buffer_pointer =
3800 cpu_to_le32(scb->sg_busaddr);
3801 else
3802 scb->dcdb.buffer_pointer =
3803 cpu_to_le32(scb->data_busaddr);
3804 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3805 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3806 scb->dcdb.sg_count = scb->sg_len;
3807 scb->dcdb.reserved = 0;
3808 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3809 scb->scsi_cmd->cmd_len);
3810 scb->dcdb.scsi_status = 0;
3811 scb->dcdb.reserved2[0] = 0;
3812 scb->dcdb.reserved2[1] = 0;
3813 scb->dcdb.reserved2[2] = 0;
3814 }
3815 }
3816
3817 return ((*ha->func.issue) (ha, scb));
3818}
3819
3820/****************************************************************************/
3821/* */
3822/* Routine Name: ips_chk_status */
3823/* */
3824/* Routine Description: */
3825/* */
3826/* Check the status of commands to logical drives */
3827/* Assumed to be called with the HA lock */
3828/****************************************************************************/
3829static void
3830ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3831{
3832 ips_scb_t *scb;
3833 ips_stat_t *sp;
3834 uint8_t basic_status;
3835 uint8_t ext_status;
3836 int errcode;
3837 IPS_SCSI_INQ_DATA inquiryData;
3838
3839 METHOD_TRACE("ips_chkstatus", 1);
3840
3841 scb = &ha->scbs[pstatus->fields.command_id];
3842 scb->basic_status = basic_status =
3843 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3844 scb->extended_status = ext_status = pstatus->fields.extended_status;
3845
3846 sp = &ha->sp;
3847 sp->residue_len = 0;
3848 sp->scb_addr = (void *) scb;
3849
3850 /* Remove the item from the active queue */
3851 ips_removeq_scb(&ha->scb_activelist, scb);
3852
3853 if (!scb->scsi_cmd)
3854 /* internal commands are handled in do_ipsintr */
3855 return;
3856
3857 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3858 ips_name,
3859 ha->host_num,
3860 scb->cdb[0],
3861 scb->cmd.basic_io.command_id,
3862 scb->bus, scb->target_id, scb->lun);
3863
3864 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3865 /* passthru - just returns the raw result */
3866 return;
3867
3868 errcode = DID_OK;
3869
3870 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3871 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3872
3873 if (scb->bus == 0) {
3874 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3875 IPS_CMD_RECOVERED_ERROR) {
3876 DEBUG_VAR(1,
3877 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3878 ips_name, ha->host_num,
3879 scb->cmd.basic_io.op_code,
3880 basic_status, ext_status);
3881 }
3882
3883 switch (scb->scsi_cmd->cmnd[0]) {
3884 case ALLOW_MEDIUM_REMOVAL:
3885 case REZERO_UNIT:
3886 case ERASE:
3887 case WRITE_FILEMARKS:
3888 case SPACE:
3889 errcode = DID_ERROR;
3890 break;
3891
3892 case START_STOP:
3893 break;
3894
3895 case TEST_UNIT_READY:
3896 if (!ips_online(ha, scb)) {
3897 errcode = DID_TIME_OUT;
3898 }
3899 break;
3900
3901 case INQUIRY:
3902 if (ips_online(ha, scb)) {
3903 ips_inquiry(ha, scb);
3904 } else {
3905 errcode = DID_TIME_OUT;
3906 }
3907 break;
3908
3909 case REQUEST_SENSE:
3910 ips_reqsen(ha, scb);
3911 break;
3912
3913 case READ_6:
3914 case WRITE_6:
3915 case READ_10:
3916 case WRITE_10:
3917 case RESERVE:
3918 case RELEASE:
3919 break;
3920
3921 case MODE_SENSE:
3922 if (!ips_online(ha, scb)
3923 || !ips_msense(ha, scb)) {
3924 errcode = DID_ERROR;
3925 }
3926 break;
3927
3928 case READ_CAPACITY:
3929 if (ips_online(ha, scb))
3930 ips_rdcap(ha, scb);
3931 else {
3932 errcode = DID_TIME_OUT;
3933 }
3934 break;
3935
3936 case SEND_DIAGNOSTIC:
3937 case REASSIGN_BLOCKS:
3938 break;
3939
3940 case FORMAT_UNIT:
3941 errcode = DID_ERROR;
3942 break;
3943
3944 case SEEK_10:
3945 case VERIFY:
3946 case READ_DEFECT_DATA:
3947 case READ_BUFFER:
3948 case WRITE_BUFFER:
3949 break;
3950
3951 default:
3952 errcode = DID_ERROR;
3953 } /* end switch */
3954
3955 scb->scsi_cmd->result = errcode << 16;
3956 } else { /* bus == 0 */
3957 /* restrict access to physical drives */
3958 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3959 ips_scmd_buf_read(scb->scsi_cmd,
3960 &inquiryData, sizeof (inquiryData));
3961 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3962 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3963 }
3964 } /* else */
3965 } else { /* recovered error / success */
3966 if (scb->bus == 0) {
3967 DEBUG_VAR(1,
3968 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3969 ips_name, ha->host_num,
3970 scb->cmd.basic_io.op_code, basic_status,
3971 ext_status);
3972 }
3973
3974 ips_map_status(ha, scb, sp);
3975 } /* else */
3976}
3977
3978/****************************************************************************/
3979/* */
3980/* Routine Name: ips_online */
3981/* */
3982/* Routine Description: */
3983/* */
3984/* Determine if a logical drive is online */
3985/* */
3986/****************************************************************************/
3987static int
3988ips_online(ips_ha_t * ha, ips_scb_t * scb)
3989{
3990 METHOD_TRACE("ips_online", 1);
3991
3992 if (scb->target_id >= IPS_MAX_LD)
3993 return (0);
3994
3995 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
3996 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
3997 return (0);
3998 }
3999
4000 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4001 IPS_LD_OFFLINE
4002 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4003 IPS_LD_FREE
4004 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4005 IPS_LD_CRS
4006 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4007 IPS_LD_SYS)
4008 return (1);
4009 else
4010 return (0);
4011}
4012
4013/****************************************************************************/
4014/* */
4015/* Routine Name: ips_inquiry */
4016/* */
4017/* Routine Description: */
4018/* */
4019/* Simulate an inquiry command to a logical drive */
4020/* */
4021/****************************************************************************/
4022static int
4023ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4024{
4025 IPS_SCSI_INQ_DATA inquiry;
4026
4027 METHOD_TRACE("ips_inquiry", 1);
4028
4029 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4030
4031 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4032 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4033 inquiry.Version = IPS_SCSI_INQ_REV2;
4034 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4035 inquiry.AdditionalLength = 31;
4036 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4037 inquiry.Flags[1] =
4038 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4039 memcpy(inquiry.VendorId, "IBM ", 8);
4040 memcpy(inquiry.ProductId, "SERVERAID ", 16);
4041 memcpy(inquiry.ProductRevisionLevel, "1.00", 4);
4042
4043 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4044
4045 return (1);
4046}
4047
4048/****************************************************************************/
4049/* */
4050/* Routine Name: ips_rdcap */
4051/* */
4052/* Routine Description: */
4053/* */
4054/* Simulate a read capacity command to a logical drive */
4055/* */
4056/****************************************************************************/
4057static int
4058ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4059{
4060 IPS_SCSI_CAPACITY cap;
4061
4062 METHOD_TRACE("ips_rdcap", 1);
4063
4064 if (scsi_bufflen(scb->scsi_cmd) < 8)
4065 return (0);
4066
4067 cap.lba =
4068 cpu_to_be32(le32_to_cpu
4069 (ha->logical_drive_info->
4070 drive_info[scb->target_id].sector_count) - 1);
4071 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4072
4073 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4074
4075 return (1);
4076}
4077
4078/****************************************************************************/
4079/* */
4080/* Routine Name: ips_msense */
4081/* */
4082/* Routine Description: */
4083/* */
4084/* Simulate a mode sense command to a logical drive */
4085/* */
4086/****************************************************************************/
4087static int
4088ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4089{
4090 uint16_t heads;
4091 uint16_t sectors;
4092 uint32_t cylinders;
4093 IPS_SCSI_MODE_PAGE_DATA mdata;
4094
4095 METHOD_TRACE("ips_msense", 1);
4096
4097 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4098 (ha->enq->ucMiscFlag & 0x8) == 0) {
4099 heads = IPS_NORM_HEADS;
4100 sectors = IPS_NORM_SECTORS;
4101 } else {
4102 heads = IPS_COMP_HEADS;
4103 sectors = IPS_COMP_SECTORS;
4104 }
4105
4106 cylinders =
4107 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4108 1) / (heads * sectors);
4109
4110 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4111
4112 mdata.hdr.BlockDescLength = 8;
4113
4114 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4115 case 0x03: /* page 3 */
4116 mdata.pdata.pg3.PageCode = 3;
4117 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4118 mdata.hdr.DataLength =
4119 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4120 mdata.pdata.pg3.TracksPerZone = 0;
4121 mdata.pdata.pg3.AltSectorsPerZone = 0;
4122 mdata.pdata.pg3.AltTracksPerZone = 0;
4123 mdata.pdata.pg3.AltTracksPerVolume = 0;
4124 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4125 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4126 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4127 mdata.pdata.pg3.TrackSkew = 0;
4128 mdata.pdata.pg3.CylinderSkew = 0;
4129 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4130 break;
4131
4132 case 0x4:
4133 mdata.pdata.pg4.PageCode = 4;
4134 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4135 mdata.hdr.DataLength =
4136 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4137 mdata.pdata.pg4.CylindersHigh =
4138 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4139 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4140 mdata.pdata.pg4.Heads = heads;
4141 mdata.pdata.pg4.WritePrecompHigh = 0;
4142 mdata.pdata.pg4.WritePrecompLow = 0;
4143 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4144 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4145 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4146 mdata.pdata.pg4.LandingZoneHigh = 0;
4147 mdata.pdata.pg4.LandingZoneLow = 0;
4148 mdata.pdata.pg4.flags = 0;
4149 mdata.pdata.pg4.RotationalOffset = 0;
4150 mdata.pdata.pg4.MediumRotationRate = 0;
4151 break;
4152 case 0x8:
4153 mdata.pdata.pg8.PageCode = 8;
4154 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4155 mdata.hdr.DataLength =
4156 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4157 /* everything else is left set to 0 */
4158 break;
4159
4160 default:
4161 return (0);
4162 } /* end switch */
4163
4164 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4165
4166 return (1);
4167}
4168
4169/****************************************************************************/
4170/* */
4171/* Routine Name: ips_reqsen */
4172/* */
4173/* Routine Description: */
4174/* */
4175/* Simulate a request sense command to a logical drive */
4176/* */
4177/****************************************************************************/
4178static int
4179ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4180{
4181 IPS_SCSI_REQSEN reqsen;
4182
4183 METHOD_TRACE("ips_reqsen", 1);
4184
4185 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4186
4187 reqsen.ResponseCode =
4188 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4189 reqsen.AdditionalLength = 10;
4190 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4191 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4192
4193 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4194
4195 return (1);
4196}
4197
4198/****************************************************************************/
4199/* */
4200/* Routine Name: ips_free */
4201/* */
4202/* Routine Description: */
4203/* */
4204/* Free any allocated space for this controller */
4205/* */
4206/****************************************************************************/
4207static void
4208ips_free(ips_ha_t * ha)
4209{
4210
4211 METHOD_TRACE("ips_free", 1);
4212
4213 if (ha) {
4214 if (ha->enq) {
4215 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ),
4216 ha->enq, ha->enq_busaddr);
4217 ha->enq = NULL;
4218 }
4219
4220 kfree(ha->conf);
4221 ha->conf = NULL;
4222
4223 if (ha->adapt) {
4224 dma_free_coherent(&ha->pcidev->dev,
4225 sizeof (IPS_ADAPTER) +
4226 sizeof (IPS_IO_CMD), ha->adapt,
4227 ha->adapt->hw_status_start);
4228 ha->adapt = NULL;
4229 }
4230
4231 if (ha->logical_drive_info) {
4232 dma_free_coherent(&ha->pcidev->dev,
4233 sizeof (IPS_LD_INFO),
4234 ha->logical_drive_info,
4235 ha->logical_drive_info_dma_addr);
4236 ha->logical_drive_info = NULL;
4237 }
4238
4239 kfree(ha->nvram);
4240 ha->nvram = NULL;
4241
4242 kfree(ha->subsys);
4243 ha->subsys = NULL;
4244
4245 if (ha->ioctl_data) {
4246 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
4247 ha->ioctl_data, ha->ioctl_busaddr);
4248 ha->ioctl_data = NULL;
4249 ha->ioctl_datasize = 0;
4250 ha->ioctl_len = 0;
4251 }
4252 ips_deallocatescbs(ha, ha->max_cmds);
4253
4254 /* free memory mapped (if applicable) */
4255 if (ha->mem_ptr) {
4256 iounmap(ha->ioremap_ptr);
4257 ha->ioremap_ptr = NULL;
4258 ha->mem_ptr = NULL;
4259 }
4260
4261 ha->mem_addr = 0;
4262
4263 }
4264}
4265
4266/****************************************************************************/
4267/* */
4268/* Routine Name: ips_deallocatescbs */
4269/* */
4270/* Routine Description: */
4271/* */
4272/* Free the command blocks */
4273/* */
4274/****************************************************************************/
4275static int
4276ips_deallocatescbs(ips_ha_t * ha, int cmds)
4277{
4278 if (ha->scbs) {
4279 dma_free_coherent(&ha->pcidev->dev,
4280 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4281 ha->scbs->sg_list.list,
4282 ha->scbs->sg_busaddr);
4283 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds,
4284 ha->scbs, ha->scbs->scb_busaddr);
4285 ha->scbs = NULL;
4286 } /* end if */
4287 return 1;
4288}
4289
4290/****************************************************************************/
4291/* */
4292/* Routine Name: ips_allocatescbs */
4293/* */
4294/* Routine Description: */
4295/* */
4296/* Allocate the command blocks */
4297/* */
4298/****************************************************************************/
4299static int
4300ips_allocatescbs(ips_ha_t * ha)
4301{
4302 ips_scb_t *scb_p;
4303 IPS_SG_LIST ips_sg;
4304 int i;
4305 dma_addr_t command_dma, sg_dma;
4306
4307 METHOD_TRACE("ips_allocatescbs", 1);
4308
4309 /* Allocate memory for the SCBs */
4310 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev,
4311 ha->max_cmds * sizeof (ips_scb_t),
4312 &command_dma, GFP_KERNEL);
4313 if (ha->scbs == NULL)
4314 return 0;
4315 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev,
4316 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds,
4317 &sg_dma, GFP_KERNEL);
4318 if (ips_sg.list == NULL) {
4319 dma_free_coherent(&ha->pcidev->dev,
4320 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4321 command_dma);
4322 return 0;
4323 }
4324
4325 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4326
4327 for (i = 0; i < ha->max_cmds; i++) {
4328 scb_p = &ha->scbs[i];
4329 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4330 /* set up S/G list */
4331 if (IPS_USE_ENH_SGLIST(ha)) {
4332 scb_p->sg_list.enh_list =
4333 ips_sg.enh_list + i * IPS_MAX_SG;
4334 scb_p->sg_busaddr =
4335 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4336 } else {
4337 scb_p->sg_list.std_list =
4338 ips_sg.std_list + i * IPS_MAX_SG;
4339 scb_p->sg_busaddr =
4340 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4341 }
4342
4343 /* add to the free list */
4344 if (i < ha->max_cmds - 1) {
4345 scb_p->q_next = ha->scb_freelist;
4346 ha->scb_freelist = scb_p;
4347 }
4348 }
4349
4350 /* success */
4351 return (1);
4352}
4353
4354/****************************************************************************/
4355/* */
4356/* Routine Name: ips_init_scb */
4357/* */
4358/* Routine Description: */
4359/* */
4360/* Initialize a CCB to default values */
4361/* */
4362/****************************************************************************/
4363static void
4364ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4365{
4366 IPS_SG_LIST sg_list;
4367 uint32_t cmd_busaddr, sg_busaddr;
4368 METHOD_TRACE("ips_init_scb", 1);
4369
4370 if (scb == NULL)
4371 return;
4372
4373 sg_list.list = scb->sg_list.list;
4374 cmd_busaddr = scb->scb_busaddr;
4375 sg_busaddr = scb->sg_busaddr;
4376 /* zero fill */
4377 memset(scb, 0, sizeof (ips_scb_t));
4378 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4379
4380 /* Initialize dummy command bucket */
4381 ha->dummy->op_code = 0xFF;
4382 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4383 + sizeof (IPS_ADAPTER));
4384 ha->dummy->command_id = IPS_MAX_CMDS;
4385
4386 /* set bus address of scb */
4387 scb->scb_busaddr = cmd_busaddr;
4388 scb->sg_busaddr = sg_busaddr;
4389 scb->sg_list.list = sg_list.list;
4390
4391 /* Neptune Fix */
4392 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4393 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4394 + sizeof (IPS_ADAPTER));
4395}
4396
4397/****************************************************************************/
4398/* */
4399/* Routine Name: ips_get_scb */
4400/* */
4401/* Routine Description: */
4402/* */
4403/* Initialize a CCB to default values */
4404/* */
4405/* ASSUMED to be called from within a lock */
4406/* */
4407/****************************************************************************/
4408static ips_scb_t *
4409ips_getscb(ips_ha_t * ha)
4410{
4411 ips_scb_t *scb;
4412
4413 METHOD_TRACE("ips_getscb", 1);
4414
4415 if ((scb = ha->scb_freelist) == NULL) {
4416
4417 return (NULL);
4418 }
4419
4420 ha->scb_freelist = scb->q_next;
4421 scb->flags = 0;
4422 scb->q_next = NULL;
4423
4424 ips_init_scb(ha, scb);
4425
4426 return (scb);
4427}
4428
4429/****************************************************************************/
4430/* */
4431/* Routine Name: ips_free_scb */
4432/* */
4433/* Routine Description: */
4434/* */
4435/* Return an unused CCB back to the free list */
4436/* */
4437/* ASSUMED to be called from within a lock */
4438/* */
4439/****************************************************************************/
4440static void
4441ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4442{
4443
4444 METHOD_TRACE("ips_freescb", 1);
4445 if (scb->flags & IPS_SCB_MAP_SG)
4446 scsi_dma_unmap(scb->scsi_cmd);
4447 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4448 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr,
4449 scb->data_len, IPS_DMA_DIR(scb));
4450
4451 /* check to make sure this is not our "special" scb */
4452 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4453 scb->q_next = ha->scb_freelist;
4454 ha->scb_freelist = scb;
4455 }
4456}
4457
4458/****************************************************************************/
4459/* */
4460/* Routine Name: ips_isinit_copperhead */
4461/* */
4462/* Routine Description: */
4463/* */
4464/* Is controller initialized ? */
4465/* */
4466/****************************************************************************/
4467static int
4468ips_isinit_copperhead(ips_ha_t * ha)
4469{
4470 uint8_t scpr;
4471 uint8_t isr;
4472
4473 METHOD_TRACE("ips_isinit_copperhead", 1);
4474
4475 isr = inb(ha->io_addr + IPS_REG_HISR);
4476 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4477
4478 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4479 return (0);
4480 else
4481 return (1);
4482}
4483
4484/****************************************************************************/
4485/* */
4486/* Routine Name: ips_isinit_copperhead_memio */
4487/* */
4488/* Routine Description: */
4489/* */
4490/* Is controller initialized ? */
4491/* */
4492/****************************************************************************/
4493static int
4494ips_isinit_copperhead_memio(ips_ha_t * ha)
4495{
4496 uint8_t isr = 0;
4497 uint8_t scpr;
4498
4499 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4500
4501 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4502 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4503
4504 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4505 return (0);
4506 else
4507 return (1);
4508}
4509
4510/****************************************************************************/
4511/* */
4512/* Routine Name: ips_isinit_morpheus */
4513/* */
4514/* Routine Description: */
4515/* */
4516/* Is controller initialized ? */
4517/* */
4518/****************************************************************************/
4519static int
4520ips_isinit_morpheus(ips_ha_t * ha)
4521{
4522 uint32_t post;
4523 uint32_t bits;
4524
4525 METHOD_TRACE("ips_is_init_morpheus", 1);
4526
4527 if (ips_isintr_morpheus(ha))
4528 ips_flush_and_reset(ha);
4529
4530 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4531 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4532
4533 if (post == 0)
4534 return (0);
4535 else if (bits & 0x3)
4536 return (0);
4537 else
4538 return (1);
4539}
4540
4541/****************************************************************************/
4542/* */
4543/* Routine Name: ips_flush_and_reset */
4544/* */
4545/* Routine Description: */
4546/* */
4547/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4548/* state ( was trying to INIT and an interrupt was already pending ) ... */
4549/* */
4550/****************************************************************************/
4551static void
4552ips_flush_and_reset(ips_ha_t *ha)
4553{
4554 ips_scb_t *scb;
4555 int ret;
4556 int time;
4557 int done;
4558 dma_addr_t command_dma;
4559
4560 /* Create a usuable SCB */
4561 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t),
4562 &command_dma, GFP_KERNEL);
4563 if (scb) {
4564 memset(scb, 0, sizeof(ips_scb_t));
4565 ips_init_scb(ha, scb);
4566 scb->scb_busaddr = command_dma;
4567
4568 scb->timeout = ips_cmd_timeout;
4569 scb->cdb[0] = IPS_CMD_FLUSH;
4570
4571 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4572 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4573 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4574 scb->cmd.flush_cache.reserved = 0;
4575 scb->cmd.flush_cache.reserved2 = 0;
4576 scb->cmd.flush_cache.reserved3 = 0;
4577 scb->cmd.flush_cache.reserved4 = 0;
4578
4579 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4580
4581 if (ret == IPS_SUCCESS) {
4582 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4583 done = 0;
4584
4585 while ((time > 0) && (!done)) {
4586 done = ips_poll_for_flush_complete(ha);
4587 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4588 udelay(1000);
4589 time--;
4590 }
4591 }
4592 }
4593
4594 /* Now RESET and INIT the adapter */
4595 (*ha->func.reset) (ha);
4596
4597 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma);
4598 return;
4599}
4600
4601/****************************************************************************/
4602/* */
4603/* Routine Name: ips_poll_for_flush_complete */
4604/* */
4605/* Routine Description: */
4606/* */
4607/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4608/* All other responses are just taken off the queue and ignored */
4609/* */
4610/****************************************************************************/
4611static int
4612ips_poll_for_flush_complete(ips_ha_t * ha)
4613{
4614 IPS_STATUS cstatus;
4615
4616 while (TRUE) {
4617 cstatus.value = (*ha->func.statupd) (ha);
4618
4619 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4620 break;
4621
4622 /* Success is when we see the Flush Command ID */
4623 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4624 return 1;
4625 }
4626
4627 return 0;
4628}
4629
4630/****************************************************************************/
4631/* */
4632/* Routine Name: ips_enable_int_copperhead */
4633/* */
4634/* Routine Description: */
4635/* Turn on interrupts */
4636/* */
4637/****************************************************************************/
4638static void
4639ips_enable_int_copperhead(ips_ha_t * ha)
4640{
4641 METHOD_TRACE("ips_enable_int_copperhead", 1);
4642
4643 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4644 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4645}
4646
4647/****************************************************************************/
4648/* */
4649/* Routine Name: ips_enable_int_copperhead_memio */
4650/* */
4651/* Routine Description: */
4652/* Turn on interrupts */
4653/* */
4654/****************************************************************************/
4655static void
4656ips_enable_int_copperhead_memio(ips_ha_t * ha)
4657{
4658 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4659
4660 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4661 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4662}
4663
4664/****************************************************************************/
4665/* */
4666/* Routine Name: ips_enable_int_morpheus */
4667/* */
4668/* Routine Description: */
4669/* Turn on interrupts */
4670/* */
4671/****************************************************************************/
4672static void
4673ips_enable_int_morpheus(ips_ha_t * ha)
4674{
4675 uint32_t Oimr;
4676
4677 METHOD_TRACE("ips_enable_int_morpheus", 1);
4678
4679 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4680 Oimr &= ~0x08;
4681 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4682 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4683}
4684
4685/****************************************************************************/
4686/* */
4687/* Routine Name: ips_init_copperhead */
4688/* */
4689/* Routine Description: */
4690/* */
4691/* Initialize a copperhead controller */
4692/* */
4693/****************************************************************************/
4694static int
4695ips_init_copperhead(ips_ha_t * ha)
4696{
4697 uint8_t Isr;
4698 uint8_t Cbsp;
4699 uint8_t PostByte[IPS_MAX_POST_BYTES];
4700 int i, j;
4701
4702 METHOD_TRACE("ips_init_copperhead", 1);
4703
4704 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4705 for (j = 0; j < 45; j++) {
4706 Isr = inb(ha->io_addr + IPS_REG_HISR);
4707 if (Isr & IPS_BIT_GHI)
4708 break;
4709
4710 /* Delay for 1 Second */
4711 MDELAY(IPS_ONE_SEC);
4712 }
4713
4714 if (j >= 45)
4715 /* error occurred */
4716 return (0);
4717
4718 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4719 outb(Isr, ha->io_addr + IPS_REG_HISR);
4720 }
4721
4722 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4723 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4724 "reset controller fails (post status %x %x).\n",
4725 PostByte[0], PostByte[1]);
4726
4727 return (0);
4728 }
4729
4730 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4731 for (j = 0; j < 240; j++) {
4732 Isr = inb(ha->io_addr + IPS_REG_HISR);
4733 if (Isr & IPS_BIT_GHI)
4734 break;
4735
4736 /* Delay for 1 Second */
4737 MDELAY(IPS_ONE_SEC);
4738 }
4739
4740 if (j >= 240)
4741 /* error occurred */
4742 return (0);
4743
4744 inb(ha->io_addr + IPS_REG_ISPR);
4745 outb(Isr, ha->io_addr + IPS_REG_HISR);
4746 }
4747
4748 for (i = 0; i < 240; i++) {
4749 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4750
4751 if ((Cbsp & IPS_BIT_OP) == 0)
4752 break;
4753
4754 /* Delay for 1 Second */
4755 MDELAY(IPS_ONE_SEC);
4756 }
4757
4758 if (i >= 240)
4759 /* reset failed */
4760 return (0);
4761
4762 /* setup CCCR */
4763 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4764
4765 /* Enable busmastering */
4766 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4767
4768 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4769 /* fix for anaconda64 */
4770 outl(0, ha->io_addr + IPS_REG_NDAE);
4771
4772 /* Enable interrupts */
4773 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4774
4775 return (1);
4776}
4777
4778/****************************************************************************/
4779/* */
4780/* Routine Name: ips_init_copperhead_memio */
4781/* */
4782/* Routine Description: */
4783/* */
4784/* Initialize a copperhead controller with memory mapped I/O */
4785/* */
4786/****************************************************************************/
4787static int
4788ips_init_copperhead_memio(ips_ha_t * ha)
4789{
4790 uint8_t Isr = 0;
4791 uint8_t Cbsp;
4792 uint8_t PostByte[IPS_MAX_POST_BYTES];
4793 int i, j;
4794
4795 METHOD_TRACE("ips_init_copperhead_memio", 1);
4796
4797 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4798 for (j = 0; j < 45; j++) {
4799 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4800 if (Isr & IPS_BIT_GHI)
4801 break;
4802
4803 /* Delay for 1 Second */
4804 MDELAY(IPS_ONE_SEC);
4805 }
4806
4807 if (j >= 45)
4808 /* error occurred */
4809 return (0);
4810
4811 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4812 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4813 }
4814
4815 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4816 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4817 "reset controller fails (post status %x %x).\n",
4818 PostByte[0], PostByte[1]);
4819
4820 return (0);
4821 }
4822
4823 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4824 for (j = 0; j < 240; j++) {
4825 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4826 if (Isr & IPS_BIT_GHI)
4827 break;
4828
4829 /* Delay for 1 Second */
4830 MDELAY(IPS_ONE_SEC);
4831 }
4832
4833 if (j >= 240)
4834 /* error occurred */
4835 return (0);
4836
4837 readb(ha->mem_ptr + IPS_REG_ISPR);
4838 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4839 }
4840
4841 for (i = 0; i < 240; i++) {
4842 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4843
4844 if ((Cbsp & IPS_BIT_OP) == 0)
4845 break;
4846
4847 /* Delay for 1 Second */
4848 MDELAY(IPS_ONE_SEC);
4849 }
4850
4851 if (i >= 240)
4852 /* error occurred */
4853 return (0);
4854
4855 /* setup CCCR */
4856 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4857
4858 /* Enable busmastering */
4859 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4860
4861 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4862 /* fix for anaconda64 */
4863 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4864
4865 /* Enable interrupts */
4866 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4867
4868 /* if we get here then everything went OK */
4869 return (1);
4870}
4871
4872/****************************************************************************/
4873/* */
4874/* Routine Name: ips_init_morpheus */
4875/* */
4876/* Routine Description: */
4877/* */
4878/* Initialize a morpheus controller */
4879/* */
4880/****************************************************************************/
4881static int
4882ips_init_morpheus(ips_ha_t * ha)
4883{
4884 uint32_t Post;
4885 uint32_t Config;
4886 uint32_t Isr;
4887 uint32_t Oimr;
4888 int i;
4889
4890 METHOD_TRACE("ips_init_morpheus", 1);
4891
4892 /* Wait up to 45 secs for Post */
4893 for (i = 0; i < 45; i++) {
4894 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4895
4896 if (Isr & IPS_BIT_I960_MSG0I)
4897 break;
4898
4899 /* Delay for 1 Second */
4900 MDELAY(IPS_ONE_SEC);
4901 }
4902
4903 if (i >= 45) {
4904 /* error occurred */
4905 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4906 "timeout waiting for post.\n");
4907
4908 return (0);
4909 }
4910
4911 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4912
4913 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
4914 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4915 "Flashing Battery PIC, Please wait ...\n");
4916
4917 /* Clear the interrupt bit */
4918 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4919 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4920
4921 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
4922 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4923 if (Post != 0x4F00)
4924 break;
4925 /* Delay for 1 Second */
4926 MDELAY(IPS_ONE_SEC);
4927 }
4928
4929 if (i >= 120) {
4930 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4931 "timeout waiting for Battery PIC Flash\n");
4932 return (0);
4933 }
4934
4935 }
4936
4937 /* Clear the interrupt bit */
4938 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4939 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4940
4941 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4942 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4943 "reset controller fails (post status %x).\n", Post);
4944
4945 return (0);
4946 }
4947
4948 /* Wait up to 240 secs for config bytes */
4949 for (i = 0; i < 240; i++) {
4950 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4951
4952 if (Isr & IPS_BIT_I960_MSG1I)
4953 break;
4954
4955 /* Delay for 1 Second */
4956 MDELAY(IPS_ONE_SEC);
4957 }
4958
4959 if (i >= 240) {
4960 /* error occurred */
4961 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4962 "timeout waiting for config.\n");
4963
4964 return (0);
4965 }
4966
4967 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4968
4969 /* Clear interrupt bit */
4970 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4971 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4972
4973 /* Turn on the interrupts */
4974 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4975 Oimr &= ~0x8;
4976 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4977
4978 /* if we get here then everything went OK */
4979
4980 /* Since we did a RESET, an EraseStripeLock may be needed */
4981 if (Post == 0xEF10) {
4982 if ((Config == 0x000F) || (Config == 0x0009))
4983 ha->requires_esl = 1;
4984 }
4985
4986 return (1);
4987}
4988
4989/****************************************************************************/
4990/* */
4991/* Routine Name: ips_reset_copperhead */
4992/* */
4993/* Routine Description: */
4994/* */
4995/* Reset the controller */
4996/* */
4997/****************************************************************************/
4998static int
4999ips_reset_copperhead(ips_ha_t * ha)
5000{
5001 int reset_counter;
5002
5003 METHOD_TRACE("ips_reset_copperhead", 1);
5004
5005 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5006 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5007
5008 reset_counter = 0;
5009
5010 while (reset_counter < 2) {
5011 reset_counter++;
5012
5013 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5014
5015 /* Delay for 1 Second */
5016 MDELAY(IPS_ONE_SEC);
5017
5018 outb(0, ha->io_addr + IPS_REG_SCPR);
5019
5020 /* Delay for 1 Second */
5021 MDELAY(IPS_ONE_SEC);
5022
5023 if ((*ha->func.init) (ha))
5024 break;
5025 else if (reset_counter >= 2) {
5026
5027 return (0);
5028 }
5029 }
5030
5031 return (1);
5032}
5033
5034/****************************************************************************/
5035/* */
5036/* Routine Name: ips_reset_copperhead_memio */
5037/* */
5038/* Routine Description: */
5039/* */
5040/* Reset the controller */
5041/* */
5042/****************************************************************************/
5043static int
5044ips_reset_copperhead_memio(ips_ha_t * ha)
5045{
5046 int reset_counter;
5047
5048 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5049
5050 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5051 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5052
5053 reset_counter = 0;
5054
5055 while (reset_counter < 2) {
5056 reset_counter++;
5057
5058 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5059
5060 /* Delay for 1 Second */
5061 MDELAY(IPS_ONE_SEC);
5062
5063 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5064
5065 /* Delay for 1 Second */
5066 MDELAY(IPS_ONE_SEC);
5067
5068 if ((*ha->func.init) (ha))
5069 break;
5070 else if (reset_counter >= 2) {
5071
5072 return (0);
5073 }
5074 }
5075
5076 return (1);
5077}
5078
5079/****************************************************************************/
5080/* */
5081/* Routine Name: ips_reset_morpheus */
5082/* */
5083/* Routine Description: */
5084/* */
5085/* Reset the controller */
5086/* */
5087/****************************************************************************/
5088static int
5089ips_reset_morpheus(ips_ha_t * ha)
5090{
5091 int reset_counter;
5092 uint8_t junk;
5093
5094 METHOD_TRACE("ips_reset_morpheus", 1);
5095
5096 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5097 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5098
5099 reset_counter = 0;
5100
5101 while (reset_counter < 2) {
5102 reset_counter++;
5103
5104 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5105
5106 /* Delay for 5 Seconds */
5107 MDELAY(5 * IPS_ONE_SEC);
5108
5109 /* Do a PCI config read to wait for adapter */
5110 pci_read_config_byte(ha->pcidev, 4, &junk);
5111
5112 if ((*ha->func.init) (ha))
5113 break;
5114 else if (reset_counter >= 2) {
5115
5116 return (0);
5117 }
5118 }
5119
5120 return (1);
5121}
5122
5123/****************************************************************************/
5124/* */
5125/* Routine Name: ips_statinit */
5126/* */
5127/* Routine Description: */
5128/* */
5129/* Initialize the status queues on the controller */
5130/* */
5131/****************************************************************************/
5132static void
5133ips_statinit(ips_ha_t * ha)
5134{
5135 uint32_t phys_status_start;
5136
5137 METHOD_TRACE("ips_statinit", 1);
5138
5139 ha->adapt->p_status_start = ha->adapt->status;
5140 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5141 ha->adapt->p_status_tail = ha->adapt->status;
5142
5143 phys_status_start = ha->adapt->hw_status_start;
5144 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5145 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5146 ha->io_addr + IPS_REG_SQER);
5147 outl(phys_status_start + IPS_STATUS_SIZE,
5148 ha->io_addr + IPS_REG_SQHR);
5149 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5150
5151 ha->adapt->hw_status_tail = phys_status_start;
5152}
5153
5154/****************************************************************************/
5155/* */
5156/* Routine Name: ips_statinit_memio */
5157/* */
5158/* Routine Description: */
5159/* */
5160/* Initialize the status queues on the controller */
5161/* */
5162/****************************************************************************/
5163static void
5164ips_statinit_memio(ips_ha_t * ha)
5165{
5166 uint32_t phys_status_start;
5167
5168 METHOD_TRACE("ips_statinit_memio", 1);
5169
5170 ha->adapt->p_status_start = ha->adapt->status;
5171 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5172 ha->adapt->p_status_tail = ha->adapt->status;
5173
5174 phys_status_start = ha->adapt->hw_status_start;
5175 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5176 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5177 ha->mem_ptr + IPS_REG_SQER);
5178 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5179 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5180
5181 ha->adapt->hw_status_tail = phys_status_start;
5182}
5183
5184/****************************************************************************/
5185/* */
5186/* Routine Name: ips_statupd_copperhead */
5187/* */
5188/* Routine Description: */
5189/* */
5190/* Remove an element from the status queue */
5191/* */
5192/****************************************************************************/
5193static uint32_t
5194ips_statupd_copperhead(ips_ha_t * ha)
5195{
5196 METHOD_TRACE("ips_statupd_copperhead", 1);
5197
5198 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5199 ha->adapt->p_status_tail++;
5200 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5201 } else {
5202 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5203 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5204 }
5205
5206 outl(ha->adapt->hw_status_tail,
5207 ha->io_addr + IPS_REG_SQTR);
5208
5209 return (ha->adapt->p_status_tail->value);
5210}
5211
5212/****************************************************************************/
5213/* */
5214/* Routine Name: ips_statupd_copperhead_memio */
5215/* */
5216/* Routine Description: */
5217/* */
5218/* Remove an element from the status queue */
5219/* */
5220/****************************************************************************/
5221static uint32_t
5222ips_statupd_copperhead_memio(ips_ha_t * ha)
5223{
5224 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5225
5226 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5227 ha->adapt->p_status_tail++;
5228 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5229 } else {
5230 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5231 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5232 }
5233
5234 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5235
5236 return (ha->adapt->p_status_tail->value);
5237}
5238
5239/****************************************************************************/
5240/* */
5241/* Routine Name: ips_statupd_morpheus */
5242/* */
5243/* Routine Description: */
5244/* */
5245/* Remove an element from the status queue */
5246/* */
5247/****************************************************************************/
5248static uint32_t
5249ips_statupd_morpheus(ips_ha_t * ha)
5250{
5251 uint32_t val;
5252
5253 METHOD_TRACE("ips_statupd_morpheus", 1);
5254
5255 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5256
5257 return (val);
5258}
5259
5260/****************************************************************************/
5261/* */
5262/* Routine Name: ips_issue_copperhead */
5263/* */
5264/* Routine Description: */
5265/* */
5266/* Send a command down to the controller */
5267/* */
5268/****************************************************************************/
5269static int
5270ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5271{
5272 uint32_t TimeOut;
5273 uint32_t val;
5274
5275 METHOD_TRACE("ips_issue_copperhead", 1);
5276
5277 if (scb->scsi_cmd) {
5278 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5279 ips_name,
5280 ha->host_num,
5281 scb->cdb[0],
5282 scb->cmd.basic_io.command_id,
5283 scb->bus, scb->target_id, scb->lun);
5284 } else {
5285 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5286 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5287 }
5288
5289 TimeOut = 0;
5290
5291 while ((val =
5292 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5293 udelay(1000);
5294
5295 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5296 if (!(val & IPS_BIT_START_STOP))
5297 break;
5298
5299 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5300 "ips_issue val [0x%x].\n", val);
5301 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5302 "ips_issue semaphore chk timeout.\n");
5303
5304 return (IPS_FAILURE);
5305 } /* end if */
5306 } /* end while */
5307
5308 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5309 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5310
5311 return (IPS_SUCCESS);
5312}
5313
5314/****************************************************************************/
5315/* */
5316/* Routine Name: ips_issue_copperhead_memio */
5317/* */
5318/* Routine Description: */
5319/* */
5320/* Send a command down to the controller */
5321/* */
5322/****************************************************************************/
5323static int
5324ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5325{
5326 uint32_t TimeOut;
5327 uint32_t val;
5328
5329 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5330
5331 if (scb->scsi_cmd) {
5332 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5333 ips_name,
5334 ha->host_num,
5335 scb->cdb[0],
5336 scb->cmd.basic_io.command_id,
5337 scb->bus, scb->target_id, scb->lun);
5338 } else {
5339 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5340 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5341 }
5342
5343 TimeOut = 0;
5344
5345 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5346 udelay(1000);
5347
5348 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5349 if (!(val & IPS_BIT_START_STOP))
5350 break;
5351
5352 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5353 "ips_issue val [0x%x].\n", val);
5354 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5355 "ips_issue semaphore chk timeout.\n");
5356
5357 return (IPS_FAILURE);
5358 } /* end if */
5359 } /* end while */
5360
5361 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5362 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5363
5364 return (IPS_SUCCESS);
5365}
5366
5367/****************************************************************************/
5368/* */
5369/* Routine Name: ips_issue_i2o */
5370/* */
5371/* Routine Description: */
5372/* */
5373/* Send a command down to the controller */
5374/* */
5375/****************************************************************************/
5376static int
5377ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5378{
5379
5380 METHOD_TRACE("ips_issue_i2o", 1);
5381
5382 if (scb->scsi_cmd) {
5383 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5384 ips_name,
5385 ha->host_num,
5386 scb->cdb[0],
5387 scb->cmd.basic_io.command_id,
5388 scb->bus, scb->target_id, scb->lun);
5389 } else {
5390 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5391 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5392 }
5393
5394 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5395
5396 return (IPS_SUCCESS);
5397}
5398
5399/****************************************************************************/
5400/* */
5401/* Routine Name: ips_issue_i2o_memio */
5402/* */
5403/* Routine Description: */
5404/* */
5405/* Send a command down to the controller */
5406/* */
5407/****************************************************************************/
5408static int
5409ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5410{
5411
5412 METHOD_TRACE("ips_issue_i2o_memio", 1);
5413
5414 if (scb->scsi_cmd) {
5415 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5416 ips_name,
5417 ha->host_num,
5418 scb->cdb[0],
5419 scb->cmd.basic_io.command_id,
5420 scb->bus, scb->target_id, scb->lun);
5421 } else {
5422 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5423 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5424 }
5425
5426 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5427
5428 return (IPS_SUCCESS);
5429}
5430
5431/****************************************************************************/
5432/* */
5433/* Routine Name: ips_isintr_copperhead */
5434/* */
5435/* Routine Description: */
5436/* */
5437/* Test to see if an interrupt is for us */
5438/* */
5439/****************************************************************************/
5440static int
5441ips_isintr_copperhead(ips_ha_t * ha)
5442{
5443 uint8_t Isr;
5444
5445 METHOD_TRACE("ips_isintr_copperhead", 2);
5446
5447 Isr = inb(ha->io_addr + IPS_REG_HISR);
5448
5449 if (Isr == 0xFF)
5450 /* ?!?! Nothing really there */
5451 return (0);
5452
5453 if (Isr & IPS_BIT_SCE)
5454 return (1);
5455 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5456 /* status queue overflow or GHI */
5457 /* just clear the interrupt */
5458 outb(Isr, ha->io_addr + IPS_REG_HISR);
5459 }
5460
5461 return (0);
5462}
5463
5464/****************************************************************************/
5465/* */
5466/* Routine Name: ips_isintr_copperhead_memio */
5467/* */
5468/* Routine Description: */
5469/* */
5470/* Test to see if an interrupt is for us */
5471/* */
5472/****************************************************************************/
5473static int
5474ips_isintr_copperhead_memio(ips_ha_t * ha)
5475{
5476 uint8_t Isr;
5477
5478 METHOD_TRACE("ips_isintr_memio", 2);
5479
5480 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5481
5482 if (Isr == 0xFF)
5483 /* ?!?! Nothing really there */
5484 return (0);
5485
5486 if (Isr & IPS_BIT_SCE)
5487 return (1);
5488 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5489 /* status queue overflow or GHI */
5490 /* just clear the interrupt */
5491 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5492 }
5493
5494 return (0);
5495}
5496
5497/****************************************************************************/
5498/* */
5499/* Routine Name: ips_isintr_morpheus */
5500/* */
5501/* Routine Description: */
5502/* */
5503/* Test to see if an interrupt is for us */
5504/* */
5505/****************************************************************************/
5506static int
5507ips_isintr_morpheus(ips_ha_t * ha)
5508{
5509 uint32_t Isr;
5510
5511 METHOD_TRACE("ips_isintr_morpheus", 2);
5512
5513 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5514
5515 if (Isr & IPS_BIT_I2O_OPQI)
5516 return (1);
5517 else
5518 return (0);
5519}
5520
5521/****************************************************************************/
5522/* */
5523/* Routine Name: ips_wait */
5524/* */
5525/* Routine Description: */
5526/* */
5527/* Wait for a command to complete */
5528/* */
5529/****************************************************************************/
5530static int
5531ips_wait(ips_ha_t * ha, int time, int intr)
5532{
5533 int ret;
5534 int done;
5535
5536 METHOD_TRACE("ips_wait", 1);
5537
5538 ret = IPS_FAILURE;
5539 done = FALSE;
5540
5541 time *= IPS_ONE_SEC; /* convert seconds */
5542
5543 while ((time > 0) && (!done)) {
5544 if (intr == IPS_INTR_ON) {
5545 if (ha->waitflag == FALSE) {
5546 ret = IPS_SUCCESS;
5547 done = TRUE;
5548 break;
5549 }
5550 } else if (intr == IPS_INTR_IORL) {
5551 if (ha->waitflag == FALSE) {
5552 /*
5553 * controller generated an interrupt to
5554 * acknowledge completion of the command
5555 * and ips_intr() has serviced the interrupt.
5556 */
5557 ret = IPS_SUCCESS;
5558 done = TRUE;
5559 break;
5560 }
5561
5562 /*
5563 * NOTE: we already have the io_request_lock so
5564 * even if we get an interrupt it won't get serviced
5565 * until after we finish.
5566 */
5567
5568 (*ha->func.intr) (ha);
5569 }
5570
5571 /* This looks like a very evil loop, but it only does this during start-up */
5572 udelay(1000);
5573 time--;
5574 }
5575
5576 return (ret);
5577}
5578
5579/****************************************************************************/
5580/* */
5581/* Routine Name: ips_write_driver_status */
5582/* */
5583/* Routine Description: */
5584/* */
5585/* Write OS/Driver version to Page 5 of the nvram on the controller */
5586/* */
5587/****************************************************************************/
5588static int
5589ips_write_driver_status(ips_ha_t * ha, int intr)
5590{
5591 METHOD_TRACE("ips_write_driver_status", 1);
5592
5593 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5594 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5595 "unable to read NVRAM page 5.\n");
5596
5597 return (0);
5598 }
5599
5600 /* check to make sure the page has a valid */
5601 /* signature */
5602 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5603 DEBUG_VAR(1,
5604 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5605 ips_name, ha->host_num, ha->nvram->signature);
5606 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5607 }
5608
5609 DEBUG_VAR(2,
5610 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5611 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5612 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5613 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5614 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5615 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5616 ha->nvram->bios_low[3]);
5617
5618 ips_get_bios_version(ha, intr);
5619
5620 /* change values (as needed) */
5621 ha->nvram->operating_system = IPS_OS_LINUX;
5622 ha->nvram->adapter_type = ha->ad_type;
5623 memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5624 memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5625 memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5626 memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5627
5628 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5629
5630 /* now update the page */
5631 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5632 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5633 "unable to write NVRAM page 5.\n");
5634
5635 return (0);
5636 }
5637
5638 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5639 ha->slot_num = ha->nvram->adapter_slot;
5640
5641 return (1);
5642}
5643
5644/****************************************************************************/
5645/* */
5646/* Routine Name: ips_read_adapter_status */
5647/* */
5648/* Routine Description: */
5649/* */
5650/* Do an Inquiry command to the adapter */
5651/* */
5652/****************************************************************************/
5653static int
5654ips_read_adapter_status(ips_ha_t * ha, int intr)
5655{
5656 ips_scb_t *scb;
5657 int ret;
5658
5659 METHOD_TRACE("ips_read_adapter_status", 1);
5660
5661 scb = &ha->scbs[ha->max_cmds - 1];
5662
5663 ips_init_scb(ha, scb);
5664
5665 scb->timeout = ips_cmd_timeout;
5666 scb->cdb[0] = IPS_CMD_ENQUIRY;
5667
5668 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5669 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5670 scb->cmd.basic_io.sg_count = 0;
5671 scb->cmd.basic_io.lba = 0;
5672 scb->cmd.basic_io.sector_count = 0;
5673 scb->cmd.basic_io.log_drv = 0;
5674 scb->data_len = sizeof (*ha->enq);
5675 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5676
5677 /* send command */
5678 if (((ret =
5679 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5680 || (ret == IPS_SUCCESS_IMM)
5681 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5682 return (0);
5683
5684 return (1);
5685}
5686
5687/****************************************************************************/
5688/* */
5689/* Routine Name: ips_read_subsystem_parameters */
5690/* */
5691/* Routine Description: */
5692/* */
5693/* Read subsystem parameters from the adapter */
5694/* */
5695/****************************************************************************/
5696static int
5697ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5698{
5699 ips_scb_t *scb;
5700 int ret;
5701
5702 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5703
5704 scb = &ha->scbs[ha->max_cmds - 1];
5705
5706 ips_init_scb(ha, scb);
5707
5708 scb->timeout = ips_cmd_timeout;
5709 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5710
5711 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5712 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5713 scb->cmd.basic_io.sg_count = 0;
5714 scb->cmd.basic_io.lba = 0;
5715 scb->cmd.basic_io.sector_count = 0;
5716 scb->cmd.basic_io.log_drv = 0;
5717 scb->data_len = sizeof (*ha->subsys);
5718 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5719
5720 /* send command */
5721 if (((ret =
5722 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5723 || (ret == IPS_SUCCESS_IMM)
5724 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5725 return (0);
5726
5727 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5728 return (1);
5729}
5730
5731/****************************************************************************/
5732/* */
5733/* Routine Name: ips_read_config */
5734/* */
5735/* Routine Description: */
5736/* */
5737/* Read the configuration on the adapter */
5738/* */
5739/****************************************************************************/
5740static int
5741ips_read_config(ips_ha_t * ha, int intr)
5742{
5743 ips_scb_t *scb;
5744 int i;
5745 int ret;
5746
5747 METHOD_TRACE("ips_read_config", 1);
5748
5749 /* set defaults for initiator IDs */
5750 for (i = 0; i < 4; i++)
5751 ha->conf->init_id[i] = 7;
5752
5753 scb = &ha->scbs[ha->max_cmds - 1];
5754
5755 ips_init_scb(ha, scb);
5756
5757 scb->timeout = ips_cmd_timeout;
5758 scb->cdb[0] = IPS_CMD_READ_CONF;
5759
5760 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5761 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5762 scb->data_len = sizeof (*ha->conf);
5763 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5764
5765 /* send command */
5766 if (((ret =
5767 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5768 || (ret == IPS_SUCCESS_IMM)
5769 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5770
5771 memset(ha->conf, 0, sizeof (IPS_CONF));
5772
5773 /* reset initiator IDs */
5774 for (i = 0; i < 4; i++)
5775 ha->conf->init_id[i] = 7;
5776
5777 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5778 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5779 IPS_CMD_CMPLT_WERROR)
5780 return (1);
5781
5782 return (0);
5783 }
5784
5785 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5786 return (1);
5787}
5788
5789/****************************************************************************/
5790/* */
5791/* Routine Name: ips_readwrite_page5 */
5792/* */
5793/* Routine Description: */
5794/* */
5795/* Read nvram page 5 from the adapter */
5796/* */
5797/****************************************************************************/
5798static int
5799ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5800{
5801 ips_scb_t *scb;
5802 int ret;
5803
5804 METHOD_TRACE("ips_readwrite_page5", 1);
5805
5806 scb = &ha->scbs[ha->max_cmds - 1];
5807
5808 ips_init_scb(ha, scb);
5809
5810 scb->timeout = ips_cmd_timeout;
5811 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5812
5813 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5814 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5815 scb->cmd.nvram.page = 5;
5816 scb->cmd.nvram.write = write;
5817 scb->cmd.nvram.reserved = 0;
5818 scb->cmd.nvram.reserved2 = 0;
5819 scb->data_len = sizeof (*ha->nvram);
5820 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5821 if (write)
5822 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5823
5824 /* issue the command */
5825 if (((ret =
5826 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5827 || (ret == IPS_SUCCESS_IMM)
5828 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5829
5830 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5831
5832 return (0);
5833 }
5834 if (!write)
5835 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5836 return (1);
5837}
5838
5839/****************************************************************************/
5840/* */
5841/* Routine Name: ips_clear_adapter */
5842/* */
5843/* Routine Description: */
5844/* */
5845/* Clear the stripe lock tables */
5846/* */
5847/****************************************************************************/
5848static int
5849ips_clear_adapter(ips_ha_t * ha, int intr)
5850{
5851 ips_scb_t *scb;
5852 int ret;
5853
5854 METHOD_TRACE("ips_clear_adapter", 1);
5855
5856 scb = &ha->scbs[ha->max_cmds - 1];
5857
5858 ips_init_scb(ha, scb);
5859
5860 scb->timeout = ips_reset_timeout;
5861 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5862
5863 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5864 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5865 scb->cmd.config_sync.channel = 0;
5866 scb->cmd.config_sync.source_target = IPS_POCL;
5867 scb->cmd.config_sync.reserved = 0;
5868 scb->cmd.config_sync.reserved2 = 0;
5869 scb->cmd.config_sync.reserved3 = 0;
5870
5871 /* issue command */
5872 if (((ret =
5873 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5874 || (ret == IPS_SUCCESS_IMM)
5875 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5876 return (0);
5877
5878 /* send unlock stripe command */
5879 ips_init_scb(ha, scb);
5880
5881 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5882 scb->timeout = ips_reset_timeout;
5883
5884 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5885 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5886 scb->cmd.unlock_stripe.log_drv = 0;
5887 scb->cmd.unlock_stripe.control = IPS_CSL;
5888 scb->cmd.unlock_stripe.reserved = 0;
5889 scb->cmd.unlock_stripe.reserved2 = 0;
5890 scb->cmd.unlock_stripe.reserved3 = 0;
5891
5892 /* issue command */
5893 if (((ret =
5894 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5895 || (ret == IPS_SUCCESS_IMM)
5896 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5897 return (0);
5898
5899 return (1);
5900}
5901
5902/****************************************************************************/
5903/* */
5904/* Routine Name: ips_ffdc_reset */
5905/* */
5906/* Routine Description: */
5907/* */
5908/* FFDC: write reset info */
5909/* */
5910/****************************************************************************/
5911static void
5912ips_ffdc_reset(ips_ha_t * ha, int intr)
5913{
5914 ips_scb_t *scb;
5915
5916 METHOD_TRACE("ips_ffdc_reset", 1);
5917
5918 scb = &ha->scbs[ha->max_cmds - 1];
5919
5920 ips_init_scb(ha, scb);
5921
5922 scb->timeout = ips_cmd_timeout;
5923 scb->cdb[0] = IPS_CMD_FFDC;
5924 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5925 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5926 scb->cmd.ffdc.reset_count = ha->reset_count;
5927 scb->cmd.ffdc.reset_type = 0x80;
5928
5929 /* convert time to what the card wants */
5930 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5931
5932 /* issue command */
5933 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5934}
5935
5936/****************************************************************************/
5937/* */
5938/* Routine Name: ips_ffdc_time */
5939/* */
5940/* Routine Description: */
5941/* */
5942/* FFDC: write time info */
5943/* */
5944/****************************************************************************/
5945static void
5946ips_ffdc_time(ips_ha_t * ha)
5947{
5948 ips_scb_t *scb;
5949
5950 METHOD_TRACE("ips_ffdc_time", 1);
5951
5952 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5953
5954 scb = &ha->scbs[ha->max_cmds - 1];
5955
5956 ips_init_scb(ha, scb);
5957
5958 scb->timeout = ips_cmd_timeout;
5959 scb->cdb[0] = IPS_CMD_FFDC;
5960 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5961 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5962 scb->cmd.ffdc.reset_count = 0;
5963 scb->cmd.ffdc.reset_type = 0;
5964
5965 /* convert time to what the card wants */
5966 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5967
5968 /* issue command */
5969 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5970}
5971
5972/****************************************************************************/
5973/* */
5974/* Routine Name: ips_fix_ffdc_time */
5975/* */
5976/* Routine Description: */
5977/* Adjust time_t to what the card wants */
5978/* */
5979/****************************************************************************/
5980static void
5981ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time)
5982{
5983 struct tm tm;
5984
5985 METHOD_TRACE("ips_fix_ffdc_time", 1);
5986
5987 time64_to_tm(current_time, 0, &tm);
5988
5989 scb->cmd.ffdc.hour = tm.tm_hour;
5990 scb->cmd.ffdc.minute = tm.tm_min;
5991 scb->cmd.ffdc.second = tm.tm_sec;
5992 scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100;
5993 scb->cmd.ffdc.yearL = tm.tm_year % 100;
5994 scb->cmd.ffdc.month = tm.tm_mon + 1;
5995 scb->cmd.ffdc.day = tm.tm_mday;
5996}
5997
5998/****************************************************************************
5999 * BIOS Flash Routines *
6000 ****************************************************************************/
6001
6002/****************************************************************************/
6003/* */
6004/* Routine Name: ips_erase_bios */
6005/* */
6006/* Routine Description: */
6007/* Erase the BIOS on the adapter */
6008/* */
6009/****************************************************************************/
6010static int
6011ips_erase_bios(ips_ha_t * ha)
6012{
6013 int timeout;
6014 uint8_t status = 0;
6015
6016 METHOD_TRACE("ips_erase_bios", 1);
6017
6018 status = 0;
6019
6020 /* Clear the status register */
6021 outl(0, ha->io_addr + IPS_REG_FLAP);
6022 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6023 udelay(25); /* 25 us */
6024
6025 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6026 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6027 udelay(25); /* 25 us */
6028
6029 /* Erase Setup */
6030 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6031 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6032 udelay(25); /* 25 us */
6033
6034 /* Erase Confirm */
6035 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6036 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6037 udelay(25); /* 25 us */
6038
6039 /* Erase Status */
6040 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6041 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6042 udelay(25); /* 25 us */
6043
6044 timeout = 80000; /* 80 seconds */
6045
6046 while (timeout > 0) {
6047 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6048 outl(0, ha->io_addr + IPS_REG_FLAP);
6049 udelay(25); /* 25 us */
6050 }
6051
6052 status = inb(ha->io_addr + IPS_REG_FLDP);
6053
6054 if (status & 0x80)
6055 break;
6056
6057 MDELAY(1);
6058 timeout--;
6059 }
6060
6061 /* check for timeout */
6062 if (timeout <= 0) {
6063 /* timeout */
6064
6065 /* try to suspend the erase */
6066 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6067 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6068 udelay(25); /* 25 us */
6069
6070 /* wait for 10 seconds */
6071 timeout = 10000;
6072 while (timeout > 0) {
6073 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6074 outl(0, ha->io_addr + IPS_REG_FLAP);
6075 udelay(25); /* 25 us */
6076 }
6077
6078 status = inb(ha->io_addr + IPS_REG_FLDP);
6079
6080 if (status & 0xC0)
6081 break;
6082
6083 MDELAY(1);
6084 timeout--;
6085 }
6086
6087 return (1);
6088 }
6089
6090 /* check for valid VPP */
6091 if (status & 0x08)
6092 /* VPP failure */
6093 return (1);
6094
6095 /* check for successful flash */
6096 if (status & 0x30)
6097 /* sequence error */
6098 return (1);
6099
6100 /* Otherwise, we were successful */
6101 /* clear status */
6102 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6103 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6104 udelay(25); /* 25 us */
6105
6106 /* enable reads */
6107 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6108 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6109 udelay(25); /* 25 us */
6110
6111 return (0);
6112}
6113
6114/****************************************************************************/
6115/* */
6116/* Routine Name: ips_erase_bios_memio */
6117/* */
6118/* Routine Description: */
6119/* Erase the BIOS on the adapter */
6120/* */
6121/****************************************************************************/
6122static int
6123ips_erase_bios_memio(ips_ha_t * ha)
6124{
6125 int timeout;
6126 uint8_t status;
6127
6128 METHOD_TRACE("ips_erase_bios_memio", 1);
6129
6130 status = 0;
6131
6132 /* Clear the status register */
6133 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6134 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6135 udelay(25); /* 25 us */
6136
6137 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6138 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6139 udelay(25); /* 25 us */
6140
6141 /* Erase Setup */
6142 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6143 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6144 udelay(25); /* 25 us */
6145
6146 /* Erase Confirm */
6147 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6148 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6149 udelay(25); /* 25 us */
6150
6151 /* Erase Status */
6152 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6153 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6154 udelay(25); /* 25 us */
6155
6156 timeout = 80000; /* 80 seconds */
6157
6158 while (timeout > 0) {
6159 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6160 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6161 udelay(25); /* 25 us */
6162 }
6163
6164 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6165
6166 if (status & 0x80)
6167 break;
6168
6169 MDELAY(1);
6170 timeout--;
6171 }
6172
6173 /* check for timeout */
6174 if (timeout <= 0) {
6175 /* timeout */
6176
6177 /* try to suspend the erase */
6178 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6179 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6180 udelay(25); /* 25 us */
6181
6182 /* wait for 10 seconds */
6183 timeout = 10000;
6184 while (timeout > 0) {
6185 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6186 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6187 udelay(25); /* 25 us */
6188 }
6189
6190 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6191
6192 if (status & 0xC0)
6193 break;
6194
6195 MDELAY(1);
6196 timeout--;
6197 }
6198
6199 return (1);
6200 }
6201
6202 /* check for valid VPP */
6203 if (status & 0x08)
6204 /* VPP failure */
6205 return (1);
6206
6207 /* check for successful flash */
6208 if (status & 0x30)
6209 /* sequence error */
6210 return (1);
6211
6212 /* Otherwise, we were successful */
6213 /* clear status */
6214 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6215 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6216 udelay(25); /* 25 us */
6217
6218 /* enable reads */
6219 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6220 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6221 udelay(25); /* 25 us */
6222
6223 return (0);
6224}
6225
6226/****************************************************************************/
6227/* */
6228/* Routine Name: ips_program_bios */
6229/* */
6230/* Routine Description: */
6231/* Program the BIOS on the adapter */
6232/* */
6233/****************************************************************************/
6234static int
6235ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6236 uint32_t offset)
6237{
6238 int i;
6239 int timeout;
6240 uint8_t status = 0;
6241
6242 METHOD_TRACE("ips_program_bios", 1);
6243
6244 status = 0;
6245
6246 for (i = 0; i < buffersize; i++) {
6247 /* write a byte */
6248 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6249 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6250 udelay(25); /* 25 us */
6251
6252 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6253 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6254 udelay(25); /* 25 us */
6255
6256 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6257 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6258 udelay(25); /* 25 us */
6259
6260 /* wait up to one second */
6261 timeout = 1000;
6262 while (timeout > 0) {
6263 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6264 outl(0, ha->io_addr + IPS_REG_FLAP);
6265 udelay(25); /* 25 us */
6266 }
6267
6268 status = inb(ha->io_addr + IPS_REG_FLDP);
6269
6270 if (status & 0x80)
6271 break;
6272
6273 MDELAY(1);
6274 timeout--;
6275 }
6276
6277 if (timeout == 0) {
6278 /* timeout error */
6279 outl(0, ha->io_addr + IPS_REG_FLAP);
6280 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6281 udelay(25); /* 25 us */
6282
6283 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6284 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6285 udelay(25); /* 25 us */
6286
6287 return (1);
6288 }
6289
6290 /* check the status */
6291 if (status & 0x18) {
6292 /* programming error */
6293 outl(0, ha->io_addr + IPS_REG_FLAP);
6294 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6295 udelay(25); /* 25 us */
6296
6297 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6298 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6299 udelay(25); /* 25 us */
6300
6301 return (1);
6302 }
6303 } /* end for */
6304
6305 /* Enable reading */
6306 outl(0, ha->io_addr + IPS_REG_FLAP);
6307 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6308 udelay(25); /* 25 us */
6309
6310 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6311 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6312 udelay(25); /* 25 us */
6313
6314 return (0);
6315}
6316
6317/****************************************************************************/
6318/* */
6319/* Routine Name: ips_program_bios_memio */
6320/* */
6321/* Routine Description: */
6322/* Program the BIOS on the adapter */
6323/* */
6324/****************************************************************************/
6325static int
6326ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6327 uint32_t offset)
6328{
6329 int i;
6330 int timeout;
6331 uint8_t status = 0;
6332
6333 METHOD_TRACE("ips_program_bios_memio", 1);
6334
6335 status = 0;
6336
6337 for (i = 0; i < buffersize; i++) {
6338 /* write a byte */
6339 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6340 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6341 udelay(25); /* 25 us */
6342
6343 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6344 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6345 udelay(25); /* 25 us */
6346
6347 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6348 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6349 udelay(25); /* 25 us */
6350
6351 /* wait up to one second */
6352 timeout = 1000;
6353 while (timeout > 0) {
6354 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6355 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6356 udelay(25); /* 25 us */
6357 }
6358
6359 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6360
6361 if (status & 0x80)
6362 break;
6363
6364 MDELAY(1);
6365 timeout--;
6366 }
6367
6368 if (timeout == 0) {
6369 /* timeout error */
6370 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6371 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6372 udelay(25); /* 25 us */
6373
6374 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6375 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6376 udelay(25); /* 25 us */
6377
6378 return (1);
6379 }
6380
6381 /* check the status */
6382 if (status & 0x18) {
6383 /* programming error */
6384 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6385 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6386 udelay(25); /* 25 us */
6387
6388 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6389 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6390 udelay(25); /* 25 us */
6391
6392 return (1);
6393 }
6394 } /* end for */
6395
6396 /* Enable reading */
6397 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6398 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6399 udelay(25); /* 25 us */
6400
6401 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6402 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6403 udelay(25); /* 25 us */
6404
6405 return (0);
6406}
6407
6408/****************************************************************************/
6409/* */
6410/* Routine Name: ips_verify_bios */
6411/* */
6412/* Routine Description: */
6413/* Verify the BIOS on the adapter */
6414/* */
6415/****************************************************************************/
6416static int
6417ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6418 uint32_t offset)
6419{
6420 uint8_t checksum;
6421 int i;
6422
6423 METHOD_TRACE("ips_verify_bios", 1);
6424
6425 /* test 1st byte */
6426 outl(0, ha->io_addr + IPS_REG_FLAP);
6427 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6428 udelay(25); /* 25 us */
6429
6430 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6431 return (1);
6432
6433 outl(1, ha->io_addr + IPS_REG_FLAP);
6434 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6435 udelay(25); /* 25 us */
6436 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6437 return (1);
6438
6439 checksum = 0xff;
6440 for (i = 2; i < buffersize; i++) {
6441
6442 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6443 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6444 udelay(25); /* 25 us */
6445
6446 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6447 }
6448
6449 if (checksum != 0)
6450 /* failure */
6451 return (1);
6452 else
6453 /* success */
6454 return (0);
6455}
6456
6457/****************************************************************************/
6458/* */
6459/* Routine Name: ips_verify_bios_memio */
6460/* */
6461/* Routine Description: */
6462/* Verify the BIOS on the adapter */
6463/* */
6464/****************************************************************************/
6465static int
6466ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6467 uint32_t offset)
6468{
6469 uint8_t checksum;
6470 int i;
6471
6472 METHOD_TRACE("ips_verify_bios_memio", 1);
6473
6474 /* test 1st byte */
6475 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6476 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6477 udelay(25); /* 25 us */
6478
6479 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6480 return (1);
6481
6482 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6483 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6484 udelay(25); /* 25 us */
6485 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6486 return (1);
6487
6488 checksum = 0xff;
6489 for (i = 2; i < buffersize; i++) {
6490
6491 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6492 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6493 udelay(25); /* 25 us */
6494
6495 checksum =
6496 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6497 }
6498
6499 if (checksum != 0)
6500 /* failure */
6501 return (1);
6502 else
6503 /* success */
6504 return (0);
6505}
6506
6507/****************************************************************************/
6508/* */
6509/* Routine Name: ips_abort_init */
6510/* */
6511/* Routine Description: */
6512/* cleanup routine for a failed adapter initialization */
6513/****************************************************************************/
6514static int
6515ips_abort_init(ips_ha_t * ha, int index)
6516{
6517 ha->active = 0;
6518 ips_free(ha);
6519 ips_ha[index] = NULL;
6520 ips_sh[index] = NULL;
6521 return -1;
6522}
6523
6524/****************************************************************************/
6525/* */
6526/* Routine Name: ips_shift_controllers */
6527/* */
6528/* Routine Description: */
6529/* helper function for ordering adapters */
6530/****************************************************************************/
6531static void
6532ips_shift_controllers(int lowindex, int highindex)
6533{
6534 ips_ha_t *ha_sav = ips_ha[highindex];
6535 struct Scsi_Host *sh_sav = ips_sh[highindex];
6536 int i;
6537
6538 for (i = highindex; i > lowindex; i--) {
6539 ips_ha[i] = ips_ha[i - 1];
6540 ips_sh[i] = ips_sh[i - 1];
6541 ips_ha[i]->host_num = i;
6542 }
6543 ha_sav->host_num = lowindex;
6544 ips_ha[lowindex] = ha_sav;
6545 ips_sh[lowindex] = sh_sav;
6546}
6547
6548/****************************************************************************/
6549/* */
6550/* Routine Name: ips_order_controllers */
6551/* */
6552/* Routine Description: */
6553/* place controllers is the "proper" boot order */
6554/****************************************************************************/
6555static void
6556ips_order_controllers(void)
6557{
6558 int i, j, tmp, position = 0;
6559 IPS_NVRAM_P5 *nvram;
6560 if (!ips_ha[0])
6561 return;
6562 nvram = ips_ha[0]->nvram;
6563
6564 if (nvram->adapter_order[0]) {
6565 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6566 for (j = position; j < ips_num_controllers; j++) {
6567 switch (ips_ha[j]->ad_type) {
6568 case IPS_ADTYPE_SERVERAID6M:
6569 case IPS_ADTYPE_SERVERAID7M:
6570 if (nvram->adapter_order[i] == 'M') {
6571 ips_shift_controllers(position,
6572 j);
6573 position++;
6574 }
6575 break;
6576 case IPS_ADTYPE_SERVERAID4L:
6577 case IPS_ADTYPE_SERVERAID4M:
6578 case IPS_ADTYPE_SERVERAID4MX:
6579 case IPS_ADTYPE_SERVERAID4LX:
6580 if (nvram->adapter_order[i] == 'N') {
6581 ips_shift_controllers(position,
6582 j);
6583 position++;
6584 }
6585 break;
6586 case IPS_ADTYPE_SERVERAID6I:
6587 case IPS_ADTYPE_SERVERAID5I2:
6588 case IPS_ADTYPE_SERVERAID5I1:
6589 case IPS_ADTYPE_SERVERAID7k:
6590 if (nvram->adapter_order[i] == 'S') {
6591 ips_shift_controllers(position,
6592 j);
6593 position++;
6594 }
6595 break;
6596 case IPS_ADTYPE_SERVERAID:
6597 case IPS_ADTYPE_SERVERAID2:
6598 case IPS_ADTYPE_NAVAJO:
6599 case IPS_ADTYPE_KIOWA:
6600 case IPS_ADTYPE_SERVERAID3L:
6601 case IPS_ADTYPE_SERVERAID3:
6602 case IPS_ADTYPE_SERVERAID4H:
6603 if (nvram->adapter_order[i] == 'A') {
6604 ips_shift_controllers(position,
6605 j);
6606 position++;
6607 }
6608 break;
6609 default:
6610 break;
6611 }
6612 }
6613 }
6614 /* if adapter_order[0], then ordering is complete */
6615 return;
6616 }
6617 /* old bios, use older ordering */
6618 tmp = 0;
6619 for (i = position; i < ips_num_controllers; i++) {
6620 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6621 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6622 ips_shift_controllers(position, i);
6623 position++;
6624 tmp = 1;
6625 }
6626 }
6627 /* if there were no 5I cards, then don't do any extra ordering */
6628 if (!tmp)
6629 return;
6630 for (i = position; i < ips_num_controllers; i++) {
6631 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6632 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6633 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6634 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6635 ips_shift_controllers(position, i);
6636 position++;
6637 }
6638 }
6639
6640 return;
6641}
6642
6643/****************************************************************************/
6644/* */
6645/* Routine Name: ips_register_scsi */
6646/* */
6647/* Routine Description: */
6648/* perform any registration and setup with the scsi layer */
6649/****************************************************************************/
6650static int
6651ips_register_scsi(int index)
6652{
6653 struct Scsi_Host *sh;
6654 ips_ha_t *ha, *oldha = ips_ha[index];
6655 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6656 if (!sh) {
6657 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6658 "Unable to register controller with SCSI subsystem\n");
6659 return -1;
6660 }
6661 ha = IPS_HA(sh);
6662 memcpy(ha, oldha, sizeof (ips_ha_t));
6663 free_irq(oldha->pcidev->irq, oldha);
6664 /* Install the interrupt handler with the new ha */
6665 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6666 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6667 "Unable to install interrupt handler\n");
6668 goto err_out_sh;
6669 }
6670
6671 kfree(oldha);
6672
6673 /* Store away needed values for later use */
6674 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6675 sh->sg_tablesize = sh->hostt->sg_tablesize;
6676 sh->can_queue = sh->hostt->can_queue;
6677 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6678 sh->max_sectors = 128;
6679
6680 sh->max_id = ha->ntargets;
6681 sh->max_lun = ha->nlun;
6682 sh->max_channel = ha->nbus - 1;
6683 sh->can_queue = ha->max_cmds - 1;
6684
6685 if (scsi_add_host(sh, &ha->pcidev->dev))
6686 goto err_out;
6687
6688 ips_sh[index] = sh;
6689 ips_ha[index] = ha;
6690
6691 scsi_scan_host(sh);
6692
6693 return 0;
6694
6695err_out:
6696 free_irq(ha->pcidev->irq, ha);
6697err_out_sh:
6698 scsi_host_put(sh);
6699 return -1;
6700}
6701
6702/*---------------------------------------------------------------------------*/
6703/* Routine Name: ips_remove_device */
6704/* */
6705/* Routine Description: */
6706/* Remove one Adapter ( Hot Plugging ) */
6707/*---------------------------------------------------------------------------*/
6708static void
6709ips_remove_device(struct pci_dev *pci_dev)
6710{
6711 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6712
6713 pci_set_drvdata(pci_dev, NULL);
6714
6715 ips_release(sh);
6716
6717 pci_release_regions(pci_dev);
6718 pci_disable_device(pci_dev);
6719}
6720
6721/****************************************************************************/
6722/* */
6723/* Routine Name: ips_module_init */
6724/* */
6725/* Routine Description: */
6726/* function called on module load */
6727/****************************************************************************/
6728static int __init
6729ips_module_init(void)
6730{
6731#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6732 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6733 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6734#endif
6735
6736 if (pci_register_driver(&ips_pci_driver) < 0)
6737 return -ENODEV;
6738 ips_driver_template.module = THIS_MODULE;
6739 ips_order_controllers();
6740 if (!ips_detect(&ips_driver_template)) {
6741 pci_unregister_driver(&ips_pci_driver);
6742 return -ENODEV;
6743 }
6744 register_reboot_notifier(&ips_notifier);
6745 return 0;
6746}
6747
6748/****************************************************************************/
6749/* */
6750/* Routine Name: ips_module_exit */
6751/* */
6752/* Routine Description: */
6753/* function called on module unload */
6754/****************************************************************************/
6755static void __exit
6756ips_module_exit(void)
6757{
6758 pci_unregister_driver(&ips_pci_driver);
6759 unregister_reboot_notifier(&ips_notifier);
6760}
6761
6762module_init(ips_module_init);
6763module_exit(ips_module_exit);
6764
6765/*---------------------------------------------------------------------------*/
6766/* Routine Name: ips_insert_device */
6767/* */
6768/* Routine Description: */
6769/* Add One Adapter ( Hot Plug ) */
6770/* */
6771/* Return Value: */
6772/* 0 if Successful, else non-zero */
6773/*---------------------------------------------------------------------------*/
6774static int
6775ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6776{
6777 int index = -1;
6778 int rc;
6779
6780 METHOD_TRACE("ips_insert_device", 1);
6781 rc = pci_enable_device(pci_dev);
6782 if (rc)
6783 return rc;
6784
6785 rc = pci_request_regions(pci_dev, "ips");
6786 if (rc)
6787 goto err_out;
6788
6789 rc = ips_init_phase1(pci_dev, &index);
6790 if (rc == SUCCESS)
6791 rc = ips_init_phase2(index);
6792
6793 if (ips_hotplug)
6794 if (ips_register_scsi(index)) {
6795 ips_free(ips_ha[index]);
6796 rc = -1;
6797 }
6798
6799 if (rc == SUCCESS)
6800 ips_num_controllers++;
6801
6802 ips_next_controller = ips_num_controllers;
6803
6804 if (rc < 0) {
6805 rc = -ENODEV;
6806 goto err_out_regions;
6807 }
6808
6809 pci_set_drvdata(pci_dev, ips_sh[index]);
6810 return 0;
6811
6812err_out_regions:
6813 pci_release_regions(pci_dev);
6814err_out:
6815 pci_disable_device(pci_dev);
6816 return rc;
6817}
6818
6819/*---------------------------------------------------------------------------*/
6820/* Routine Name: ips_init_phase1 */
6821/* */
6822/* Routine Description: */
6823/* Adapter Initialization */
6824/* */
6825/* Return Value: */
6826/* 0 if Successful, else non-zero */
6827/*---------------------------------------------------------------------------*/
6828static int
6829ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6830{
6831 ips_ha_t *ha;
6832 uint32_t io_addr;
6833 uint32_t mem_addr;
6834 uint32_t io_len;
6835 uint32_t mem_len;
6836 int j;
6837 int index;
6838 dma_addr_t dma_address;
6839 char __iomem *ioremap_ptr;
6840 char __iomem *mem_ptr;
6841 uint32_t IsDead;
6842
6843 METHOD_TRACE("ips_init_phase1", 1);
6844 index = IPS_MAX_ADAPTERS;
6845 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6846 if (ips_ha[j] == NULL) {
6847 index = j;
6848 break;
6849 }
6850 }
6851
6852 if (index >= IPS_MAX_ADAPTERS)
6853 return -1;
6854
6855 /* Init MEM/IO addresses to 0 */
6856 mem_addr = 0;
6857 io_addr = 0;
6858 mem_len = 0;
6859 io_len = 0;
6860
6861 for (j = 0; j < 2; j++) {
6862 if (!pci_resource_start(pci_dev, j))
6863 break;
6864
6865 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6866 io_addr = pci_resource_start(pci_dev, j);
6867 io_len = pci_resource_len(pci_dev, j);
6868 } else {
6869 mem_addr = pci_resource_start(pci_dev, j);
6870 mem_len = pci_resource_len(pci_dev, j);
6871 }
6872 }
6873
6874 /* setup memory mapped area (if applicable) */
6875 if (mem_addr) {
6876 uint32_t base;
6877 uint32_t offs;
6878
6879 base = mem_addr & PAGE_MASK;
6880 offs = mem_addr - base;
6881 ioremap_ptr = ioremap(base, PAGE_SIZE);
6882 if (!ioremap_ptr)
6883 return -1;
6884 mem_ptr = ioremap_ptr + offs;
6885 } else {
6886 ioremap_ptr = NULL;
6887 mem_ptr = NULL;
6888 }
6889
6890 /* found a controller */
6891 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6892 if (ha == NULL) {
6893 IPS_PRINTK(KERN_WARNING, pci_dev,
6894 "Unable to allocate temporary ha struct\n");
6895 return -1;
6896 }
6897
6898 ips_sh[index] = NULL;
6899 ips_ha[index] = ha;
6900 ha->active = 1;
6901
6902 /* Store info in HA structure */
6903 ha->io_addr = io_addr;
6904 ha->io_len = io_len;
6905 ha->mem_addr = mem_addr;
6906 ha->mem_len = mem_len;
6907 ha->mem_ptr = mem_ptr;
6908 ha->ioremap_ptr = ioremap_ptr;
6909 ha->host_num = (uint32_t) index;
6910 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6911 ha->pcidev = pci_dev;
6912
6913 /*
6914 * Set the pci_dev's dma_mask. Not all adapters support 64bit
6915 * addressing so don't enable it if the adapter can't support
6916 * it! Also, don't use 64bit addressing if dma addresses
6917 * are guaranteed to be < 4G.
6918 */
6919 if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) &&
6920 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) {
6921 (ha)->flags |= IPS_HA_ENH_SG;
6922 } else {
6923 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) {
6924 printk(KERN_WARNING "Unable to set DMA Mask\n");
6925 return ips_abort_init(ha, index);
6926 }
6927 }
6928 if(ips_cd_boot && !ips_FlashData){
6929 ips_FlashData = dma_alloc_coherent(&pci_dev->dev,
6930 PAGE_SIZE << 7, &ips_flashbusaddr, GFP_KERNEL);
6931 }
6932
6933 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ),
6934 &ha->enq_busaddr, GFP_KERNEL);
6935 if (!ha->enq) {
6936 IPS_PRINTK(KERN_WARNING, pci_dev,
6937 "Unable to allocate host inquiry structure\n");
6938 return ips_abort_init(ha, index);
6939 }
6940
6941 ha->adapt = dma_alloc_coherent(&pci_dev->dev,
6942 sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD),
6943 &dma_address, GFP_KERNEL);
6944 if (!ha->adapt) {
6945 IPS_PRINTK(KERN_WARNING, pci_dev,
6946 "Unable to allocate host adapt & dummy structures\n");
6947 return ips_abort_init(ha, index);
6948 }
6949 ha->adapt->hw_status_start = dma_address;
6950 ha->dummy = (void *) (ha->adapt + 1);
6951
6952
6953
6954 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev,
6955 sizeof (IPS_LD_INFO), &dma_address, GFP_KERNEL);
6956 if (!ha->logical_drive_info) {
6957 IPS_PRINTK(KERN_WARNING, pci_dev,
6958 "Unable to allocate logical drive info structure\n");
6959 return ips_abort_init(ha, index);
6960 }
6961 ha->logical_drive_info_dma_addr = dma_address;
6962
6963
6964 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
6965
6966 if (!ha->conf) {
6967 IPS_PRINTK(KERN_WARNING, pci_dev,
6968 "Unable to allocate host conf structure\n");
6969 return ips_abort_init(ha, index);
6970 }
6971
6972 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
6973
6974 if (!ha->nvram) {
6975 IPS_PRINTK(KERN_WARNING, pci_dev,
6976 "Unable to allocate host NVRAM structure\n");
6977 return ips_abort_init(ha, index);
6978 }
6979
6980 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
6981
6982 if (!ha->subsys) {
6983 IPS_PRINTK(KERN_WARNING, pci_dev,
6984 "Unable to allocate host subsystem structure\n");
6985 return ips_abort_init(ha, index);
6986 }
6987
6988 /* the ioctl buffer is now used during adapter initialization, so its
6989 * successful allocation is now required */
6990 if (ips_ioctlsize < PAGE_SIZE)
6991 ips_ioctlsize = PAGE_SIZE;
6992
6993 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize,
6994 &ha->ioctl_busaddr, GFP_KERNEL);
6995 ha->ioctl_len = ips_ioctlsize;
6996 if (!ha->ioctl_data) {
6997 IPS_PRINTK(KERN_WARNING, pci_dev,
6998 "Unable to allocate IOCTL data\n");
6999 return ips_abort_init(ha, index);
7000 }
7001
7002 /*
7003 * Setup Functions
7004 */
7005 ips_setup_funclist(ha);
7006
7007 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7008 /* If Morpheus appears dead, reset it */
7009 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7010 if (IsDead == 0xDEADBEEF) {
7011 ips_reset_morpheus(ha);
7012 }
7013 }
7014
7015 /*
7016 * Initialize the card if it isn't already
7017 */
7018
7019 if (!(*ha->func.isinit) (ha)) {
7020 if (!(*ha->func.init) (ha)) {
7021 /*
7022 * Initialization failed
7023 */
7024 IPS_PRINTK(KERN_WARNING, pci_dev,
7025 "Unable to initialize controller\n");
7026 return ips_abort_init(ha, index);
7027 }
7028 }
7029
7030 *indexPtr = index;
7031 return SUCCESS;
7032}
7033
7034/*---------------------------------------------------------------------------*/
7035/* Routine Name: ips_init_phase2 */
7036/* */
7037/* Routine Description: */
7038/* Adapter Initialization Phase 2 */
7039/* */
7040/* Return Value: */
7041/* 0 if Successful, else non-zero */
7042/*---------------------------------------------------------------------------*/
7043static int
7044ips_init_phase2(int index)
7045{
7046 ips_ha_t *ha;
7047
7048 ha = ips_ha[index];
7049
7050 METHOD_TRACE("ips_init_phase2", 1);
7051 if (!ha->active) {
7052 ips_ha[index] = NULL;
7053 return -1;
7054 }
7055
7056 /* Install the interrupt handler */
7057 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7058 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7059 "Unable to install interrupt handler\n");
7060 return ips_abort_init(ha, index);
7061 }
7062
7063 /*
7064 * Allocate a temporary SCB for initialization
7065 */
7066 ha->max_cmds = 1;
7067 if (!ips_allocatescbs(ha)) {
7068 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7069 "Unable to allocate a CCB\n");
7070 free_irq(ha->pcidev->irq, ha);
7071 return ips_abort_init(ha, index);
7072 }
7073
7074 if (!ips_hainit(ha)) {
7075 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7076 "Unable to initialize controller\n");
7077 free_irq(ha->pcidev->irq, ha);
7078 return ips_abort_init(ha, index);
7079 }
7080 /* Free the temporary SCB */
7081 ips_deallocatescbs(ha, 1);
7082
7083 /* allocate CCBs */
7084 if (!ips_allocatescbs(ha)) {
7085 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7086 "Unable to allocate CCBs\n");
7087 free_irq(ha->pcidev->irq, ha);
7088 return ips_abort_init(ha, index);
7089 }
7090
7091 return SUCCESS;
7092}
7093
7094MODULE_LICENSE("GPL");
7095MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7096MODULE_VERSION(IPS_VER_STRING);
7097
7098
7099/*
7100 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7101 * Emacs will notice this stuff at the end of the file and automatically
7102 * adjust the settings for this buffer only. This must remain at the end
7103 * of the file.
7104 * ---------------------------------------------------------------------------
7105 * Local variables:
7106 * c-indent-level: 2
7107 * c-brace-imaginary-offset: 0
7108 * c-brace-offset: -2
7109 * c-argdecl-indent: 2
7110 * c-label-offset: -2
7111 * c-continued-statement-offset: 2
7112 * c-continued-brace-offset: 0
7113 * indent-tabs-mode: nil
7114 * tab-width: 8
7115 * End:
7116 */