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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63#include <linux/types.h>
64#include <linux/slab.h>
65#include <linux/export.h>
66#include <linux/etherdevice.h>
67#include <linux/pci.h>
68#include <linux/firmware.h>
69
70#include "iwl-drv.h"
71#include "iwl-modparams.h"
72#include "iwl-nvm-parse.h"
73#include "iwl-prph.h"
74#include "iwl-io.h"
75#include "iwl-csr.h"
76#include "fw/acpi.h"
77#include "fw/api/nvm-reg.h"
78#include "fw/api/commands.h"
79#include "fw/api/cmdhdr.h"
80#include "fw/img.h"
81
82/* NVM offsets (in words) definitions */
83enum nvm_offsets {
84 /* NVM HW-Section offset (in words) definitions */
85 SUBSYSTEM_ID = 0x0A,
86 HW_ADDR = 0x15,
87
88 /* NVM SW-Section offset (in words) definitions */
89 NVM_SW_SECTION = 0x1C0,
90 NVM_VERSION = 0,
91 RADIO_CFG = 1,
92 SKU = 2,
93 N_HW_ADDRS = 3,
94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
95
96 /* NVM calibration section offset (in words) definitions */
97 NVM_CALIB_SECTION = 0x2B8,
98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
99
100 /* NVM REGULATORY -Section offset (in words) definitions */
101 NVM_CHANNELS_SDP = 0,
102};
103
104enum ext_nvm_offsets {
105 /* NVM HW-Section offset (in words) definitions */
106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
107
108 /* NVM SW-Section offset (in words) definitions */
109 NVM_VERSION_EXT_NVM = 0,
110 RADIO_CFG_FAMILY_EXT_NVM = 0,
111 SKU_FAMILY_8000 = 2,
112 N_HW_ADDRS_FAMILY_8000 = 3,
113
114 /* NVM REGULATORY -Section offset (in words) definitions */
115 NVM_CHANNELS_EXTENDED = 0,
116 NVM_LAR_OFFSET_OLD = 0x4C7,
117 NVM_LAR_OFFSET = 0x507,
118 NVM_LAR_ENABLED = 0x7,
119};
120
121/* SKU Capabilities (actual values from NVM definition) */
122enum nvm_sku_bits {
123 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
124 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
125 NVM_SKU_CAP_11N_ENABLE = BIT(2),
126 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
128};
129
130/*
131 * These are the channel numbers in the order that they are stored in the NVM
132 */
133static const u16 iwl_nvm_channels[] = {
134 /* 2.4 GHz */
135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
136 /* 5 GHz */
137 36, 40, 44 , 48, 52, 56, 60, 64,
138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
139 149, 153, 157, 161, 165
140};
141
142static const u16 iwl_ext_nvm_channels[] = {
143 /* 2.4 GHz */
144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
145 /* 5 GHz */
146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
148 149, 153, 157, 161, 165, 169, 173, 177, 181
149};
150
151static const u16 iwl_uhb_nvm_channels[] = {
152 /* 2.4 GHz */
153 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
154 /* 5 GHz */
155 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
156 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
157 149, 153, 157, 161, 165, 169, 173, 177, 181,
158 /* 6-7 GHz */
159 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
160 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
161 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
162 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
163};
164
165#define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
166#define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
167#define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
168#define NUM_2GHZ_CHANNELS 14
169#define FIRST_2GHZ_HT_MINUS 5
170#define LAST_2GHZ_HT_PLUS 9
171#define N_HW_ADDR_MASK 0xF
172
173/* rate data (static) */
174static struct ieee80211_rate iwl_cfg80211_rates[] = {
175 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
176 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
177 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
178 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
179 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
180 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
181 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
182 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
183 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
184 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
185 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
186 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
187 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
188 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
189 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
190};
191#define RATES_24_OFFS 0
192#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
193#define RATES_52_OFFS 4
194#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
195
196/**
197 * enum iwl_nvm_channel_flags - channel flags in NVM
198 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
199 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
200 * @NVM_CHANNEL_ACTIVE: active scanning allowed
201 * @NVM_CHANNEL_RADAR: radar detection required
202 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
203 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
204 * on same channel on 2.4 or same UNII band on 5.2
205 * @NVM_CHANNEL_UNIFORM: uniform spreading required
206 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
207 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
208 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
209 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
210 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
211 */
212enum iwl_nvm_channel_flags {
213 NVM_CHANNEL_VALID = BIT(0),
214 NVM_CHANNEL_IBSS = BIT(1),
215 NVM_CHANNEL_ACTIVE = BIT(3),
216 NVM_CHANNEL_RADAR = BIT(4),
217 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
218 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
219 NVM_CHANNEL_UNIFORM = BIT(7),
220 NVM_CHANNEL_20MHZ = BIT(8),
221 NVM_CHANNEL_40MHZ = BIT(9),
222 NVM_CHANNEL_80MHZ = BIT(10),
223 NVM_CHANNEL_160MHZ = BIT(11),
224 NVM_CHANNEL_DC_HIGH = BIT(12),
225};
226
227/**
228 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
229 * domain.
230 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
231 * 2.4Ghz band is allowed.
232 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
233 * 5Ghz band is allowed.
234 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
235 * for this regulatory domain (valid only in 5Ghz).
236 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
237 * for this regulatory domain (valid only in 5Ghz).
238 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
239 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
240 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
241 * for this regulatory domain (valid only in 5Ghz).
242 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
243 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
244 */
245enum iwl_reg_capa_flags {
246 REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
247 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
248 REG_CAPA_160MHZ_ALLOWED = BIT(2),
249 REG_CAPA_80MHZ_ALLOWED = BIT(3),
250 REG_CAPA_MCS_8_ALLOWED = BIT(4),
251 REG_CAPA_MCS_9_ALLOWED = BIT(5),
252 REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
253 REG_CAPA_DC_HIGH_ENABLED = BIT(9),
254 REG_CAPA_11AX_DISABLED = BIT(10),
255};
256
257static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
258 int chan, u32 flags)
259{
260#define CHECK_AND_PRINT_I(x) \
261 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
262
263 if (!(flags & NVM_CHANNEL_VALID)) {
264 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
265 chan, flags);
266 return;
267 }
268
269 /* Note: already can print up to 101 characters, 110 is the limit! */
270 IWL_DEBUG_DEV(dev, level,
271 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
272 chan, flags,
273 CHECK_AND_PRINT_I(VALID),
274 CHECK_AND_PRINT_I(IBSS),
275 CHECK_AND_PRINT_I(ACTIVE),
276 CHECK_AND_PRINT_I(RADAR),
277 CHECK_AND_PRINT_I(INDOOR_ONLY),
278 CHECK_AND_PRINT_I(GO_CONCURRENT),
279 CHECK_AND_PRINT_I(UNIFORM),
280 CHECK_AND_PRINT_I(20MHZ),
281 CHECK_AND_PRINT_I(40MHZ),
282 CHECK_AND_PRINT_I(80MHZ),
283 CHECK_AND_PRINT_I(160MHZ),
284 CHECK_AND_PRINT_I(DC_HIGH));
285#undef CHECK_AND_PRINT_I
286}
287
288static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
289 u32 nvm_flags, const struct iwl_cfg *cfg)
290{
291 u32 flags = IEEE80211_CHAN_NO_HT40;
292
293 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
294 if (ch_num <= LAST_2GHZ_HT_PLUS)
295 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
296 if (ch_num >= FIRST_2GHZ_HT_MINUS)
297 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
298 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
299 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
300 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
301 else
302 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
303 }
304 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
305 flags |= IEEE80211_CHAN_NO_80MHZ;
306 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
307 flags |= IEEE80211_CHAN_NO_160MHZ;
308
309 if (!(nvm_flags & NVM_CHANNEL_IBSS))
310 flags |= IEEE80211_CHAN_NO_IR;
311
312 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
313 flags |= IEEE80211_CHAN_NO_IR;
314
315 if (nvm_flags & NVM_CHANNEL_RADAR)
316 flags |= IEEE80211_CHAN_RADAR;
317
318 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
319 flags |= IEEE80211_CHAN_INDOOR_ONLY;
320
321 /* Set the GO concurrent flag only in case that NO_IR is set.
322 * Otherwise it is meaningless
323 */
324 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
325 (flags & IEEE80211_CHAN_NO_IR))
326 flags |= IEEE80211_CHAN_IR_CONCURRENT;
327
328 return flags;
329}
330
331static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
332{
333 if (ch_idx >= NUM_2GHZ_CHANNELS)
334 return NL80211_BAND_5GHZ;
335 return NL80211_BAND_2GHZ;
336}
337
338static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
339 struct iwl_nvm_data *data,
340 const void * const nvm_ch_flags,
341 u32 sbands_flags, bool v4)
342{
343 int ch_idx;
344 int n_channels = 0;
345 struct ieee80211_channel *channel;
346 u32 ch_flags;
347 int num_of_ch;
348 const u16 *nvm_chan;
349
350 if (cfg->uhb_supported) {
351 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
352 nvm_chan = iwl_uhb_nvm_channels;
353 } else if (cfg->nvm_type == IWL_NVM_EXT) {
354 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
355 nvm_chan = iwl_ext_nvm_channels;
356 } else {
357 num_of_ch = IWL_NVM_NUM_CHANNELS;
358 nvm_chan = iwl_nvm_channels;
359 }
360
361 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
362 enum nl80211_band band =
363 iwl_nl80211_band_from_channel_idx(ch_idx);
364
365 if (v4)
366 ch_flags =
367 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
368 else
369 ch_flags =
370 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
371
372 if (band == NL80211_BAND_5GHZ &&
373 !data->sku_cap_band_52ghz_enable)
374 continue;
375
376 /* workaround to disable wide channels in 5GHz */
377 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
378 band == NL80211_BAND_5GHZ) {
379 ch_flags &= ~(NVM_CHANNEL_40MHZ |
380 NVM_CHANNEL_80MHZ |
381 NVM_CHANNEL_160MHZ);
382 }
383
384 if (ch_flags & NVM_CHANNEL_160MHZ)
385 data->vht160_supported = true;
386
387 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
388 !(ch_flags & NVM_CHANNEL_VALID)) {
389 /*
390 * Channels might become valid later if lar is
391 * supported, hence we still want to add them to
392 * the list of supported channels to cfg80211.
393 */
394 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
395 nvm_chan[ch_idx], ch_flags);
396 continue;
397 }
398
399 channel = &data->channels[n_channels];
400 n_channels++;
401
402 channel->hw_value = nvm_chan[ch_idx];
403 channel->band = band;
404 channel->center_freq =
405 ieee80211_channel_to_frequency(
406 channel->hw_value, channel->band);
407
408 /* Initialize regulatory-based run-time data */
409
410 /*
411 * Default value - highest tx power value. max_power
412 * is not used in mvm, and is used for backwards compatibility
413 */
414 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
415
416 /* don't put limitations in case we're using LAR */
417 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
418 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
419 ch_idx, band,
420 ch_flags, cfg);
421 else
422 channel->flags = 0;
423
424 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
425 channel->hw_value, ch_flags);
426 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
427 channel->hw_value, channel->max_power);
428 }
429
430 return n_channels;
431}
432
433static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
434 struct iwl_nvm_data *data,
435 struct ieee80211_sta_vht_cap *vht_cap,
436 u8 tx_chains, u8 rx_chains)
437{
438 const struct iwl_cfg *cfg = trans->cfg;
439 int num_rx_ants = num_of_ant(rx_chains);
440 int num_tx_ants = num_of_ant(tx_chains);
441 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
442 IEEE80211_VHT_MAX_AMPDU_1024K);
443
444 vht_cap->vht_supported = true;
445
446 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
447 IEEE80211_VHT_CAP_RXSTBC_1 |
448 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
449 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
450 max_ampdu_exponent <<
451 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
452
453 if (data->vht160_supported)
454 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
455 IEEE80211_VHT_CAP_SHORT_GI_160;
456
457 if (cfg->vht_mu_mimo_supported)
458 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
459
460 if (cfg->ht_params->ldpc)
461 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
462
463 if (data->sku_cap_mimo_disabled) {
464 num_rx_ants = 1;
465 num_tx_ants = 1;
466 }
467
468 if (num_tx_ants > 1)
469 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
470 else
471 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
472
473 switch (iwlwifi_mod_params.amsdu_size) {
474 case IWL_AMSDU_DEF:
475 if (trans->trans_cfg->mq_rx_supported)
476 vht_cap->cap |=
477 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
478 else
479 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
480 break;
481 case IWL_AMSDU_2K:
482 if (trans->trans_cfg->mq_rx_supported)
483 vht_cap->cap |=
484 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
485 else
486 WARN(1, "RB size of 2K is not supported by this device\n");
487 break;
488 case IWL_AMSDU_4K:
489 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
490 break;
491 case IWL_AMSDU_8K:
492 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
493 break;
494 case IWL_AMSDU_12K:
495 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
496 break;
497 default:
498 break;
499 }
500
501 vht_cap->vht_mcs.rx_mcs_map =
502 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
503 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
504 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
505 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
506 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
507 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
508 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
509 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
510
511 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
512 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
513 /* this works because NOT_SUPPORTED == 3 */
514 vht_cap->vht_mcs.rx_mcs_map |=
515 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
516 }
517
518 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
519
520 vht_cap->vht_mcs.tx_highest |=
521 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
522}
523
524static struct ieee80211_sband_iftype_data iwl_he_capa[] = {
525 {
526 .types_mask = BIT(NL80211_IFTYPE_STATION),
527 .he_cap = {
528 .has_he = true,
529 .he_cap_elem = {
530 .mac_cap_info[0] =
531 IEEE80211_HE_MAC_CAP0_HTC_HE |
532 IEEE80211_HE_MAC_CAP0_TWT_REQ,
533 .mac_cap_info[1] =
534 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
535 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
536 .mac_cap_info[2] =
537 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
538 .mac_cap_info[3] =
539 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
540 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
541 .mac_cap_info[4] =
542 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU |
543 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
544 .mac_cap_info[5] =
545 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
546 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
547 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
548 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
549 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
550 .phy_cap_info[0] =
551 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
552 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
553 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
554 .phy_cap_info[1] =
555 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
556 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
557 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
558 .phy_cap_info[2] =
559 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
560 .phy_cap_info[3] =
561 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
562 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
563 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
564 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
565 .phy_cap_info[4] =
566 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
567 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
568 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
569 .phy_cap_info[5] =
570 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
571 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
572 .phy_cap_info[6] =
573 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
574 .phy_cap_info[7] =
575 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
576 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
577 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
578 .phy_cap_info[8] =
579 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
580 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
581 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
582 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
583 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
584 .phy_cap_info[9] =
585 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
586 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
587 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
588 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
589 },
590 /*
591 * Set default Tx/Rx HE MCS NSS Support field.
592 * Indicate support for up to 2 spatial streams and all
593 * MCS, without any special cases
594 */
595 .he_mcs_nss_supp = {
596 .rx_mcs_80 = cpu_to_le16(0xfffa),
597 .tx_mcs_80 = cpu_to_le16(0xfffa),
598 .rx_mcs_160 = cpu_to_le16(0xfffa),
599 .tx_mcs_160 = cpu_to_le16(0xfffa),
600 .rx_mcs_80p80 = cpu_to_le16(0xffff),
601 .tx_mcs_80p80 = cpu_to_le16(0xffff),
602 },
603 /*
604 * Set default PPE thresholds, with PPET16 set to 0,
605 * PPET8 set to 7
606 */
607 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
608 },
609 },
610 {
611 .types_mask = BIT(NL80211_IFTYPE_AP),
612 .he_cap = {
613 .has_he = true,
614 .he_cap_elem = {
615 .mac_cap_info[0] =
616 IEEE80211_HE_MAC_CAP0_HTC_HE,
617 .mac_cap_info[1] =
618 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
619 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
620 .mac_cap_info[2] =
621 IEEE80211_HE_MAC_CAP2_BSR,
622 .mac_cap_info[3] =
623 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
624 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
625 .mac_cap_info[4] =
626 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
627 .mac_cap_info[5] =
628 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
629 .phy_cap_info[0] =
630 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
631 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
632 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
633 .phy_cap_info[1] =
634 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
635 .phy_cap_info[2] =
636 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
637 .phy_cap_info[3] =
638 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
639 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
640 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
641 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
642 .phy_cap_info[4] =
643 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
644 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
645 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
646 .phy_cap_info[5] =
647 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
648 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
649 .phy_cap_info[6] =
650 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
651 .phy_cap_info[7] =
652 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
653 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
654 .phy_cap_info[8] =
655 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
656 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
657 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
658 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
659 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
660 .phy_cap_info[9] =
661 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
662 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
663 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
664 },
665 /*
666 * Set default Tx/Rx HE MCS NSS Support field.
667 * Indicate support for up to 2 spatial streams and all
668 * MCS, without any special cases
669 */
670 .he_mcs_nss_supp = {
671 .rx_mcs_80 = cpu_to_le16(0xfffa),
672 .tx_mcs_80 = cpu_to_le16(0xfffa),
673 .rx_mcs_160 = cpu_to_le16(0xfffa),
674 .tx_mcs_160 = cpu_to_le16(0xfffa),
675 .rx_mcs_80p80 = cpu_to_le16(0xffff),
676 .tx_mcs_80p80 = cpu_to_le16(0xffff),
677 },
678 /*
679 * Set default PPE thresholds, with PPET16 set to 0,
680 * PPET8 set to 7
681 */
682 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
683 },
684 },
685};
686
687static void iwl_init_he_hw_capab(struct iwl_trans *trans,
688 struct iwl_nvm_data *data,
689 struct ieee80211_supported_band *sband,
690 u8 tx_chains, u8 rx_chains)
691{
692 sband->iftype_data = iwl_he_capa;
693 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
694
695 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
696 if ((tx_chains & rx_chains) != ANT_AB) {
697 int i;
698
699 for (i = 0; i < sband->n_iftype_data; i++) {
700 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &=
701 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
702 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &=
703 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
704 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &=
705 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
706 }
707 }
708}
709
710static void iwl_init_sbands(struct iwl_trans *trans,
711 struct iwl_nvm_data *data,
712 const void *nvm_ch_flags, u8 tx_chains,
713 u8 rx_chains, u32 sbands_flags, bool v4)
714{
715 struct device *dev = trans->dev;
716 const struct iwl_cfg *cfg = trans->cfg;
717 int n_channels;
718 int n_used = 0;
719 struct ieee80211_supported_band *sband;
720
721 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
722 sbands_flags, v4);
723 sband = &data->bands[NL80211_BAND_2GHZ];
724 sband->band = NL80211_BAND_2GHZ;
725 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
726 sband->n_bitrates = N_RATES_24;
727 n_used += iwl_init_sband_channels(data, sband, n_channels,
728 NL80211_BAND_2GHZ);
729 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
730 tx_chains, rx_chains);
731
732 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
733 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
734
735 sband = &data->bands[NL80211_BAND_5GHZ];
736 sband->band = NL80211_BAND_5GHZ;
737 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
738 sband->n_bitrates = N_RATES_52;
739 n_used += iwl_init_sband_channels(data, sband, n_channels,
740 NL80211_BAND_5GHZ);
741 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
742 tx_chains, rx_chains);
743 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
744 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
745 tx_chains, rx_chains);
746
747 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
748 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
749
750 if (n_channels != n_used)
751 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
752 n_used, n_channels);
753}
754
755static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
756 const __le16 *phy_sku)
757{
758 if (cfg->nvm_type != IWL_NVM_EXT)
759 return le16_to_cpup(nvm_sw + SKU);
760
761 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
762}
763
764static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
765{
766 if (cfg->nvm_type != IWL_NVM_EXT)
767 return le16_to_cpup(nvm_sw + NVM_VERSION);
768 else
769 return le32_to_cpup((__le32 *)(nvm_sw +
770 NVM_VERSION_EXT_NVM));
771}
772
773static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
774 const __le16 *phy_sku)
775{
776 if (cfg->nvm_type != IWL_NVM_EXT)
777 return le16_to_cpup(nvm_sw + RADIO_CFG);
778
779 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
780
781}
782
783static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
784{
785 int n_hw_addr;
786
787 if (cfg->nvm_type != IWL_NVM_EXT)
788 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
789
790 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
791
792 return n_hw_addr & N_HW_ADDR_MASK;
793}
794
795static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
796 struct iwl_nvm_data *data,
797 u32 radio_cfg)
798{
799 if (cfg->nvm_type != IWL_NVM_EXT) {
800 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
801 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
802 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
803 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
804 return;
805 }
806
807 /* set the radio configuration for family 8000 */
808 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
809 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
810 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
811 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
812 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
813 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
814}
815
816static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
817{
818 const u8 *hw_addr;
819
820 hw_addr = (const u8 *)&mac_addr0;
821 dest[0] = hw_addr[3];
822 dest[1] = hw_addr[2];
823 dest[2] = hw_addr[1];
824 dest[3] = hw_addr[0];
825
826 hw_addr = (const u8 *)&mac_addr1;
827 dest[4] = hw_addr[1];
828 dest[5] = hw_addr[0];
829}
830
831static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
832 struct iwl_nvm_data *data)
833{
834 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
835 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
836
837 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
838 /*
839 * If the OEM fused a valid address, use it instead of the one in the
840 * OTP
841 */
842 if (is_valid_ether_addr(data->hw_addr))
843 return;
844
845 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
846 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
847
848 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
849}
850
851static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
852 const struct iwl_cfg *cfg,
853 struct iwl_nvm_data *data,
854 const __le16 *mac_override,
855 const __be16 *nvm_hw)
856{
857 const u8 *hw_addr;
858
859 if (mac_override) {
860 static const u8 reserved_mac[] = {
861 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
862 };
863
864 hw_addr = (const u8 *)(mac_override +
865 MAC_ADDRESS_OVERRIDE_EXT_NVM);
866
867 /*
868 * Store the MAC address from MAO section.
869 * No byte swapping is required in MAO section
870 */
871 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
872
873 /*
874 * Force the use of the OTP MAC address in case of reserved MAC
875 * address in the NVM, or if address is given but invalid.
876 */
877 if (is_valid_ether_addr(data->hw_addr) &&
878 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
879 return;
880
881 IWL_ERR(trans,
882 "mac address from nvm override section is not valid\n");
883 }
884
885 if (nvm_hw) {
886 /* read the mac address from WFMP registers */
887 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
888 WFMP_MAC_ADDR_0));
889 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
890 WFMP_MAC_ADDR_1));
891
892 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
893
894 return;
895 }
896
897 IWL_ERR(trans, "mac address is not found\n");
898}
899
900static int iwl_set_hw_address(struct iwl_trans *trans,
901 const struct iwl_cfg *cfg,
902 struct iwl_nvm_data *data, const __be16 *nvm_hw,
903 const __le16 *mac_override)
904{
905 if (cfg->mac_addr_from_csr) {
906 iwl_set_hw_address_from_csr(trans, data);
907 } else if (cfg->nvm_type != IWL_NVM_EXT) {
908 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
909
910 /* The byte order is little endian 16 bit, meaning 214365 */
911 data->hw_addr[0] = hw_addr[1];
912 data->hw_addr[1] = hw_addr[0];
913 data->hw_addr[2] = hw_addr[3];
914 data->hw_addr[3] = hw_addr[2];
915 data->hw_addr[4] = hw_addr[5];
916 data->hw_addr[5] = hw_addr[4];
917 } else {
918 iwl_set_hw_address_family_8000(trans, cfg, data,
919 mac_override, nvm_hw);
920 }
921
922 if (!is_valid_ether_addr(data->hw_addr)) {
923 IWL_ERR(trans, "no valid mac address was found\n");
924 return -EINVAL;
925 }
926
927 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
928
929 return 0;
930}
931
932static bool
933iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
934 const __be16 *nvm_hw)
935{
936 /*
937 * Workaround a bug in Indonesia SKUs where the regulatory in
938 * some 7000-family OTPs erroneously allow wide channels in
939 * 5GHz. To check for Indonesia, we take the SKU value from
940 * bits 1-4 in the subsystem ID and check if it is either 5 or
941 * 9. In those cases, we need to force-disable wide channels
942 * in 5GHz otherwise the FW will throw a sysassert when we try
943 * to use them.
944 */
945 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
946 /*
947 * Unlike the other sections in the NVM, the hw
948 * section uses big-endian.
949 */
950 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
951 u8 sku = (subsystem_id & 0x1e) >> 1;
952
953 if (sku == 5 || sku == 9) {
954 IWL_DEBUG_EEPROM(trans->dev,
955 "disabling wide channels in 5GHz (0x%0x %d)\n",
956 subsystem_id, sku);
957 return true;
958 }
959 }
960
961 return false;
962}
963
964struct iwl_nvm_data *
965iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
966 const struct iwl_fw *fw,
967 const __be16 *nvm_hw, const __le16 *nvm_sw,
968 const __le16 *nvm_calib, const __le16 *regulatory,
969 const __le16 *mac_override, const __le16 *phy_sku,
970 u8 tx_chains, u8 rx_chains)
971{
972 struct iwl_nvm_data *data;
973 bool lar_enabled;
974 u32 sku, radio_cfg;
975 u32 sbands_flags = 0;
976 u16 lar_config;
977 const __le16 *ch_section;
978
979 if (cfg->uhb_supported)
980 data = kzalloc(struct_size(data, channels,
981 IWL_NVM_NUM_CHANNELS_UHB),
982 GFP_KERNEL);
983 else if (cfg->nvm_type != IWL_NVM_EXT)
984 data = kzalloc(struct_size(data, channels,
985 IWL_NVM_NUM_CHANNELS),
986 GFP_KERNEL);
987 else
988 data = kzalloc(struct_size(data, channels,
989 IWL_NVM_NUM_CHANNELS_EXT),
990 GFP_KERNEL);
991 if (!data)
992 return NULL;
993
994 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
995
996 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
997 iwl_set_radio_cfg(cfg, data, radio_cfg);
998 if (data->valid_tx_ant)
999 tx_chains &= data->valid_tx_ant;
1000 if (data->valid_rx_ant)
1001 rx_chains &= data->valid_rx_ant;
1002
1003 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1004 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1005 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1006 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1007 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1008 data->sku_cap_11n_enable = false;
1009 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1010 (sku & NVM_SKU_CAP_11AC_ENABLE);
1011 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1012
1013 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1014
1015 if (cfg->nvm_type != IWL_NVM_EXT) {
1016 /* Checking for required sections */
1017 if (!nvm_calib) {
1018 IWL_ERR(trans,
1019 "Can't parse empty Calib NVM sections\n");
1020 kfree(data);
1021 return NULL;
1022 }
1023
1024 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1025 ®ulatory[NVM_CHANNELS_SDP] :
1026 &nvm_sw[NVM_CHANNELS];
1027
1028 /* in family 8000 Xtal calibration values moved to OTP */
1029 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1030 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1031 lar_enabled = true;
1032 } else {
1033 u16 lar_offset = data->nvm_version < 0xE39 ?
1034 NVM_LAR_OFFSET_OLD :
1035 NVM_LAR_OFFSET;
1036
1037 lar_config = le16_to_cpup(regulatory + lar_offset);
1038 data->lar_enabled = !!(lar_config &
1039 NVM_LAR_ENABLED);
1040 lar_enabled = data->lar_enabled;
1041 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
1042 }
1043
1044 /* If no valid mac address was found - bail out */
1045 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1046 kfree(data);
1047 return NULL;
1048 }
1049
1050 if (lar_enabled &&
1051 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1052 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1053
1054 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1055 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1056
1057 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1058 sbands_flags, false);
1059 data->calib_version = 255;
1060
1061 return data;
1062}
1063IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1064
1065static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1066 int ch_idx, u16 nvm_flags,
1067 u16 cap_flags,
1068 const struct iwl_cfg *cfg)
1069{
1070 u32 flags = NL80211_RRF_NO_HT40;
1071
1072 if (ch_idx < NUM_2GHZ_CHANNELS &&
1073 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1074 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1075 flags &= ~NL80211_RRF_NO_HT40PLUS;
1076 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1077 flags &= ~NL80211_RRF_NO_HT40MINUS;
1078 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1079 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1080 flags &= ~NL80211_RRF_NO_HT40PLUS;
1081 else
1082 flags &= ~NL80211_RRF_NO_HT40MINUS;
1083 }
1084
1085 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1086 flags |= NL80211_RRF_NO_80MHZ;
1087 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1088 flags |= NL80211_RRF_NO_160MHZ;
1089
1090 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1091 flags |= NL80211_RRF_NO_IR;
1092
1093 if (nvm_flags & NVM_CHANNEL_RADAR)
1094 flags |= NL80211_RRF_DFS;
1095
1096 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1097 flags |= NL80211_RRF_NO_OUTDOOR;
1098
1099 /* Set the GO concurrent flag only in case that NO_IR is set.
1100 * Otherwise it is meaningless
1101 */
1102 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1103 (flags & NL80211_RRF_NO_IR))
1104 flags |= NL80211_RRF_GO_CONCURRENT;
1105
1106 /*
1107 * cap_flags is per regulatory domain so apply it for every channel
1108 */
1109 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1110 if (cap_flags & REG_CAPA_40MHZ_FORBIDDEN)
1111 flags |= NL80211_RRF_NO_HT40;
1112
1113 if (!(cap_flags & REG_CAPA_80MHZ_ALLOWED))
1114 flags |= NL80211_RRF_NO_80MHZ;
1115
1116 if (!(cap_flags & REG_CAPA_160MHZ_ALLOWED))
1117 flags |= NL80211_RRF_NO_160MHZ;
1118 }
1119
1120 if (cap_flags & REG_CAPA_11AX_DISABLED)
1121 flags |= NL80211_RRF_NO_HE;
1122
1123 return flags;
1124}
1125
1126struct ieee80211_regdomain *
1127iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1128 int num_of_ch, __le32 *channels, u16 fw_mcc,
1129 u16 geo_info, u16 cap)
1130{
1131 int ch_idx;
1132 u16 ch_flags;
1133 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1134 const u16 *nvm_chan;
1135 struct ieee80211_regdomain *regd, *copy_rd;
1136 struct ieee80211_reg_rule *rule;
1137 enum nl80211_band band;
1138 int center_freq, prev_center_freq = 0;
1139 int valid_rules = 0;
1140 bool new_rule;
1141 int max_num_ch;
1142
1143 if (cfg->uhb_supported) {
1144 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1145 nvm_chan = iwl_uhb_nvm_channels;
1146 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1147 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1148 nvm_chan = iwl_ext_nvm_channels;
1149 } else {
1150 max_num_ch = IWL_NVM_NUM_CHANNELS;
1151 nvm_chan = iwl_nvm_channels;
1152 }
1153
1154 if (WARN_ON(num_of_ch > max_num_ch))
1155 num_of_ch = max_num_ch;
1156
1157 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1158 return ERR_PTR(-EINVAL);
1159
1160 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1161 num_of_ch);
1162
1163 /* build a regdomain rule for every valid channel */
1164 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1165 if (!regd)
1166 return ERR_PTR(-ENOMEM);
1167
1168 /* set alpha2 from FW. */
1169 regd->alpha2[0] = fw_mcc >> 8;
1170 regd->alpha2[1] = fw_mcc & 0xff;
1171
1172 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1173 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1174 band = iwl_nl80211_band_from_channel_idx(ch_idx);
1175 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1176 band);
1177 new_rule = false;
1178
1179 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1180 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1181 nvm_chan[ch_idx], ch_flags);
1182 continue;
1183 }
1184
1185 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1186 ch_flags, cap,
1187 cfg);
1188
1189 /* we can't continue the same rule */
1190 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1191 center_freq - prev_center_freq > 20) {
1192 valid_rules++;
1193 new_rule = true;
1194 }
1195
1196 rule = ®d->reg_rules[valid_rules - 1];
1197
1198 if (new_rule)
1199 rule->freq_range.start_freq_khz =
1200 MHZ_TO_KHZ(center_freq - 10);
1201
1202 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1203
1204 /* this doesn't matter - not used by FW */
1205 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1206 rule->power_rule.max_eirp =
1207 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1208
1209 rule->flags = reg_rule_flags;
1210
1211 /* rely on auto-calculation to merge BW of contiguous chans */
1212 rule->flags |= NL80211_RRF_AUTO_BW;
1213 rule->freq_range.max_bandwidth_khz = 0;
1214
1215 prev_center_freq = center_freq;
1216 prev_reg_rule_flags = reg_rule_flags;
1217
1218 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1219 nvm_chan[ch_idx], ch_flags);
1220
1221 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1222 band == NL80211_BAND_2GHZ)
1223 continue;
1224
1225 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1226 }
1227
1228 regd->n_reg_rules = valid_rules;
1229
1230 /*
1231 * Narrow down regdom for unused regulatory rules to prevent hole
1232 * between reg rules to wmm rules.
1233 */
1234 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1235 GFP_KERNEL);
1236 if (!copy_rd)
1237 copy_rd = ERR_PTR(-ENOMEM);
1238
1239 kfree(regd);
1240 return copy_rd;
1241}
1242IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1243
1244#define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1245#define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1246#define MAX_NVM_FILE_LEN 16384
1247
1248void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1249 unsigned int len)
1250{
1251#define IWL_4165_DEVICE_ID 0x5501
1252#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1253
1254 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1255 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1256 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1257 /* OTP 0x52 bug work around: it's a 1x1 device */
1258 data[3] = ANT_B | (ANT_B << 4);
1259}
1260IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1261
1262/*
1263 * Reads external NVM from a file into mvm->nvm_sections
1264 *
1265 * HOW TO CREATE THE NVM FILE FORMAT:
1266 * ------------------------------
1267 * 1. create hex file, format:
1268 * 3800 -> header
1269 * 0000 -> header
1270 * 5a40 -> data
1271 *
1272 * rev - 6 bit (word1)
1273 * len - 10 bit (word1)
1274 * id - 4 bit (word2)
1275 * rsv - 12 bit (word2)
1276 *
1277 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1278 *
1279 * 3. create binary file from the hex file
1280 *
1281 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1282 */
1283int iwl_read_external_nvm(struct iwl_trans *trans,
1284 const char *nvm_file_name,
1285 struct iwl_nvm_section *nvm_sections)
1286{
1287 int ret, section_size;
1288 u16 section_id;
1289 const struct firmware *fw_entry;
1290 const struct {
1291 __le16 word1;
1292 __le16 word2;
1293 u8 data[];
1294 } *file_sec;
1295 const u8 *eof;
1296 u8 *temp;
1297 int max_section_size;
1298 const __le32 *dword_buff;
1299
1300#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1301#define NVM_WORD2_ID(x) (x >> 12)
1302#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1303#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1304#define NVM_HEADER_0 (0x2A504C54)
1305#define NVM_HEADER_1 (0x4E564D2A)
1306#define NVM_HEADER_SIZE (4 * sizeof(u32))
1307
1308 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1309
1310 /* Maximal size depends on NVM version */
1311 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1312 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1313 else
1314 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1315
1316 /*
1317 * Obtain NVM image via request_firmware. Since we already used
1318 * request_firmware_nowait() for the firmware binary load and only
1319 * get here after that we assume the NVM request can be satisfied
1320 * synchronously.
1321 */
1322 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1323 if (ret) {
1324 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1325 nvm_file_name, ret);
1326 return ret;
1327 }
1328
1329 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1330 nvm_file_name, fw_entry->size);
1331
1332 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1333 IWL_ERR(trans, "NVM file too large\n");
1334 ret = -EINVAL;
1335 goto out;
1336 }
1337
1338 eof = fw_entry->data + fw_entry->size;
1339 dword_buff = (__le32 *)fw_entry->data;
1340
1341 /* some NVM file will contain a header.
1342 * The header is identified by 2 dwords header as follow:
1343 * dword[0] = 0x2A504C54
1344 * dword[1] = 0x4E564D2A
1345 *
1346 * This header must be skipped when providing the NVM data to the FW.
1347 */
1348 if (fw_entry->size > NVM_HEADER_SIZE &&
1349 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1350 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1351 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1352 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1353 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1354 le32_to_cpu(dword_buff[3]));
1355
1356 /* nvm file validation, dword_buff[2] holds the file version */
1357 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1358 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1359 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1360 ret = -EFAULT;
1361 goto out;
1362 }
1363 } else {
1364 file_sec = (void *)fw_entry->data;
1365 }
1366
1367 while (true) {
1368 if (file_sec->data > eof) {
1369 IWL_ERR(trans,
1370 "ERROR - NVM file too short for section header\n");
1371 ret = -EINVAL;
1372 break;
1373 }
1374
1375 /* check for EOF marker */
1376 if (!file_sec->word1 && !file_sec->word2) {
1377 ret = 0;
1378 break;
1379 }
1380
1381 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1382 section_size =
1383 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1384 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1385 } else {
1386 section_size = 2 * EXT_NVM_WORD2_LEN(
1387 le16_to_cpu(file_sec->word2));
1388 section_id = EXT_NVM_WORD1_ID(
1389 le16_to_cpu(file_sec->word1));
1390 }
1391
1392 if (section_size > max_section_size) {
1393 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1394 section_size);
1395 ret = -EINVAL;
1396 break;
1397 }
1398
1399 if (!section_size) {
1400 IWL_ERR(trans, "ERROR - section empty\n");
1401 ret = -EINVAL;
1402 break;
1403 }
1404
1405 if (file_sec->data + section_size > eof) {
1406 IWL_ERR(trans,
1407 "ERROR - NVM file too short for section (%d bytes)\n",
1408 section_size);
1409 ret = -EINVAL;
1410 break;
1411 }
1412
1413 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1414 "Invalid NVM section ID %d\n", section_id)) {
1415 ret = -EINVAL;
1416 break;
1417 }
1418
1419 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1420 if (!temp) {
1421 ret = -ENOMEM;
1422 break;
1423 }
1424
1425 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1426
1427 kfree(nvm_sections[section_id].data);
1428 nvm_sections[section_id].data = temp;
1429 nvm_sections[section_id].length = section_size;
1430
1431 /* advance to the next section */
1432 file_sec = (void *)(file_sec->data + section_size);
1433 }
1434out:
1435 release_firmware(fw_entry);
1436 return ret;
1437}
1438IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1439
1440struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1441 const struct iwl_fw *fw)
1442{
1443 struct iwl_nvm_get_info cmd = {};
1444 struct iwl_nvm_data *nvm;
1445 struct iwl_host_cmd hcmd = {
1446 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1447 .data = { &cmd, },
1448 .len = { sizeof(cmd) },
1449 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1450 };
1451 int ret;
1452 bool empty_otp;
1453 u32 mac_flags;
1454 u32 sbands_flags = 0;
1455 /*
1456 * All the values in iwl_nvm_get_info_rsp v4 are the same as
1457 * in v3, except for the channel profile part of the
1458 * regulatory. So we can just access the new struct, with the
1459 * exception of the latter.
1460 */
1461 struct iwl_nvm_get_info_rsp *rsp;
1462 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1463 bool v4 = fw_has_api(&fw->ucode_capa,
1464 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1465 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1466 void *channel_profile;
1467
1468 ret = iwl_trans_send_cmd(trans, &hcmd);
1469 if (ret)
1470 return ERR_PTR(ret);
1471
1472 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1473 "Invalid payload len in NVM response from FW %d",
1474 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1475 ret = -EINVAL;
1476 goto out;
1477 }
1478
1479 rsp = (void *)hcmd.resp_pkt->data;
1480 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1481 NVM_GENERAL_FLAGS_EMPTY_OTP);
1482 if (empty_otp)
1483 IWL_INFO(trans, "OTP is empty\n");
1484
1485 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1486 if (!nvm) {
1487 ret = -ENOMEM;
1488 goto out;
1489 }
1490
1491 iwl_set_hw_address_from_csr(trans, nvm);
1492 /* TODO: if platform NVM has MAC address - override it here */
1493
1494 if (!is_valid_ether_addr(nvm->hw_addr)) {
1495 IWL_ERR(trans, "no valid mac address was found\n");
1496 ret = -EINVAL;
1497 goto err_free;
1498 }
1499
1500 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1501
1502 /* Initialize general data */
1503 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1504 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1505 if (nvm->n_hw_addrs == 0)
1506 IWL_WARN(trans,
1507 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1508 empty_otp);
1509
1510 /* Initialize MAC sku data */
1511 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1512 nvm->sku_cap_11ac_enable =
1513 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1514 nvm->sku_cap_11n_enable =
1515 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1516 nvm->sku_cap_11ax_enable =
1517 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1518 nvm->sku_cap_band_24ghz_enable =
1519 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1520 nvm->sku_cap_band_52ghz_enable =
1521 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1522 nvm->sku_cap_mimo_disabled =
1523 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1524
1525 /* Initialize PHY sku data */
1526 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1527 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1528
1529 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1530 fw_has_capa(&fw->ucode_capa,
1531 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1532 nvm->lar_enabled = true;
1533 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1534 }
1535
1536 rsp_v3 = (void *)rsp;
1537 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1538 (void *)rsp_v3->regulatory.channel_profile;
1539
1540 iwl_init_sbands(trans, nvm,
1541 channel_profile,
1542 nvm->valid_tx_ant & fw->valid_tx_ant,
1543 nvm->valid_rx_ant & fw->valid_rx_ant,
1544 sbands_flags, v4);
1545
1546 iwl_free_resp(&hcmd);
1547 return nvm;
1548
1549err_free:
1550 kfree(nvm);
1551out:
1552 iwl_free_resp(&hcmd);
1553 return ERR_PTR(ret);
1554}
1555IWL_EXPORT_SYMBOL(iwl_get_nvm);