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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63#include <linux/types.h>
64#include <linux/slab.h>
65#include <linux/export.h>
66#include <linux/etherdevice.h>
67#include <linux/pci.h>
68#include <linux/firmware.h>
69
70#include "iwl-drv.h"
71#include "iwl-modparams.h"
72#include "iwl-nvm-parse.h"
73#include "iwl-prph.h"
74#include "iwl-io.h"
75#include "iwl-csr.h"
76#include "fw/acpi.h"
77#include "fw/api/nvm-reg.h"
78#include "fw/api/commands.h"
79#include "fw/api/cmdhdr.h"
80#include "fw/img.h"
81
82/* NVM offsets (in words) definitions */
83enum nvm_offsets {
84 /* NVM HW-Section offset (in words) definitions */
85 SUBSYSTEM_ID = 0x0A,
86 HW_ADDR = 0x15,
87
88 /* NVM SW-Section offset (in words) definitions */
89 NVM_SW_SECTION = 0x1C0,
90 NVM_VERSION = 0,
91 RADIO_CFG = 1,
92 SKU = 2,
93 N_HW_ADDRS = 3,
94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
95
96 /* NVM calibration section offset (in words) definitions */
97 NVM_CALIB_SECTION = 0x2B8,
98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
99
100 /* NVM REGULATORY -Section offset (in words) definitions */
101 NVM_CHANNELS_SDP = 0,
102};
103
104enum ext_nvm_offsets {
105 /* NVM HW-Section offset (in words) definitions */
106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
107
108 /* NVM SW-Section offset (in words) definitions */
109 NVM_VERSION_EXT_NVM = 0,
110 RADIO_CFG_FAMILY_EXT_NVM = 0,
111 SKU_FAMILY_8000 = 2,
112 N_HW_ADDRS_FAMILY_8000 = 3,
113
114 /* NVM REGULATORY -Section offset (in words) definitions */
115 NVM_CHANNELS_EXTENDED = 0,
116 NVM_LAR_OFFSET_OLD = 0x4C7,
117 NVM_LAR_OFFSET = 0x507,
118 NVM_LAR_ENABLED = 0x7,
119};
120
121/* SKU Capabilities (actual values from NVM definition) */
122enum nvm_sku_bits {
123 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
124 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
125 NVM_SKU_CAP_11N_ENABLE = BIT(2),
126 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
128};
129
130/*
131 * These are the channel numbers in the order that they are stored in the NVM
132 */
133static const u16 iwl_nvm_channels[] = {
134 /* 2.4 GHz */
135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
136 /* 5 GHz */
137 36, 40, 44 , 48, 52, 56, 60, 64,
138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
139 149, 153, 157, 161, 165
140};
141
142static const u16 iwl_ext_nvm_channels[] = {
143 /* 2.4 GHz */
144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
145 /* 5 GHz */
146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
148 149, 153, 157, 161, 165, 169, 173, 177, 181
149};
150
151static const u16 iwl_uhb_nvm_channels[] = {
152 /* 2.4 GHz */
153 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
154 /* 5 GHz */
155 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
156 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
157 149, 153, 157, 161, 165, 169, 173, 177, 181,
158 /* 6-7 GHz */
159 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241,
160 245, 249, 253, 257, 261, 265, 269, 273, 277, 281, 285, 289, 293, 297,
161 301, 305, 309, 313, 317, 321, 325, 329, 333, 337, 341, 345, 349, 353,
162 357, 361, 365, 369, 373, 377, 381, 385, 389, 393, 397, 401, 405, 409,
163 413, 417, 421
164};
165
166#define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
167#define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
168#define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
169#define NUM_2GHZ_CHANNELS 14
170#define FIRST_2GHZ_HT_MINUS 5
171#define LAST_2GHZ_HT_PLUS 9
172#define N_HW_ADDR_MASK 0xF
173
174/* rate data (static) */
175static struct ieee80211_rate iwl_cfg80211_rates[] = {
176 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
177 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
178 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
179 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
180 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
181 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
182 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
183 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
184 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
185 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
186 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
187 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
188 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
189 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
190 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
191};
192#define RATES_24_OFFS 0
193#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
194#define RATES_52_OFFS 4
195#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
196
197/**
198 * enum iwl_nvm_channel_flags - channel flags in NVM
199 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
200 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
201 * @NVM_CHANNEL_ACTIVE: active scanning allowed
202 * @NVM_CHANNEL_RADAR: radar detection required
203 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
204 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
205 * on same channel on 2.4 or same UNII band on 5.2
206 * @NVM_CHANNEL_UNIFORM: uniform spreading required
207 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
208 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
209 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
210 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
211 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
212 */
213enum iwl_nvm_channel_flags {
214 NVM_CHANNEL_VALID = BIT(0),
215 NVM_CHANNEL_IBSS = BIT(1),
216 NVM_CHANNEL_ACTIVE = BIT(3),
217 NVM_CHANNEL_RADAR = BIT(4),
218 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
219 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
220 NVM_CHANNEL_UNIFORM = BIT(7),
221 NVM_CHANNEL_20MHZ = BIT(8),
222 NVM_CHANNEL_40MHZ = BIT(9),
223 NVM_CHANNEL_80MHZ = BIT(10),
224 NVM_CHANNEL_160MHZ = BIT(11),
225 NVM_CHANNEL_DC_HIGH = BIT(12),
226};
227
228static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
229 int chan, u32 flags)
230{
231#define CHECK_AND_PRINT_I(x) \
232 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
233
234 if (!(flags & NVM_CHANNEL_VALID)) {
235 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
236 chan, flags);
237 return;
238 }
239
240 /* Note: already can print up to 101 characters, 110 is the limit! */
241 IWL_DEBUG_DEV(dev, level,
242 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
243 chan, flags,
244 CHECK_AND_PRINT_I(VALID),
245 CHECK_AND_PRINT_I(IBSS),
246 CHECK_AND_PRINT_I(ACTIVE),
247 CHECK_AND_PRINT_I(RADAR),
248 CHECK_AND_PRINT_I(INDOOR_ONLY),
249 CHECK_AND_PRINT_I(GO_CONCURRENT),
250 CHECK_AND_PRINT_I(UNIFORM),
251 CHECK_AND_PRINT_I(20MHZ),
252 CHECK_AND_PRINT_I(40MHZ),
253 CHECK_AND_PRINT_I(80MHZ),
254 CHECK_AND_PRINT_I(160MHZ),
255 CHECK_AND_PRINT_I(DC_HIGH));
256#undef CHECK_AND_PRINT_I
257}
258
259static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
260 u32 nvm_flags, const struct iwl_cfg *cfg)
261{
262 u32 flags = IEEE80211_CHAN_NO_HT40;
263
264 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
265 if (ch_num <= LAST_2GHZ_HT_PLUS)
266 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
267 if (ch_num >= FIRST_2GHZ_HT_MINUS)
268 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
269 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
270 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
271 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
272 else
273 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
274 }
275 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
276 flags |= IEEE80211_CHAN_NO_80MHZ;
277 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
278 flags |= IEEE80211_CHAN_NO_160MHZ;
279
280 if (!(nvm_flags & NVM_CHANNEL_IBSS))
281 flags |= IEEE80211_CHAN_NO_IR;
282
283 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
284 flags |= IEEE80211_CHAN_NO_IR;
285
286 if (nvm_flags & NVM_CHANNEL_RADAR)
287 flags |= IEEE80211_CHAN_RADAR;
288
289 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
290 flags |= IEEE80211_CHAN_INDOOR_ONLY;
291
292 /* Set the GO concurrent flag only in case that NO_IR is set.
293 * Otherwise it is meaningless
294 */
295 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
296 (flags & IEEE80211_CHAN_NO_IR))
297 flags |= IEEE80211_CHAN_IR_CONCURRENT;
298
299 return flags;
300}
301
302static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
303 struct iwl_nvm_data *data,
304 const void * const nvm_ch_flags,
305 u32 sbands_flags, bool v4)
306{
307 int ch_idx;
308 int n_channels = 0;
309 struct ieee80211_channel *channel;
310 u32 ch_flags;
311 int num_of_ch, num_2ghz_channels = NUM_2GHZ_CHANNELS;
312 const u16 *nvm_chan;
313
314 if (cfg->uhb_supported) {
315 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
316 nvm_chan = iwl_uhb_nvm_channels;
317 } else if (cfg->nvm_type == IWL_NVM_EXT) {
318 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
319 nvm_chan = iwl_ext_nvm_channels;
320 } else {
321 num_of_ch = IWL_NVM_NUM_CHANNELS;
322 nvm_chan = iwl_nvm_channels;
323 }
324
325 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
326 bool is_5ghz = (ch_idx >= num_2ghz_channels);
327
328 if (v4)
329 ch_flags =
330 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
331 else
332 ch_flags =
333 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
334
335 if (is_5ghz && !data->sku_cap_band_52ghz_enable)
336 continue;
337
338 /* workaround to disable wide channels in 5GHz */
339 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
340 is_5ghz) {
341 ch_flags &= ~(NVM_CHANNEL_40MHZ |
342 NVM_CHANNEL_80MHZ |
343 NVM_CHANNEL_160MHZ);
344 }
345
346 if (ch_flags & NVM_CHANNEL_160MHZ)
347 data->vht160_supported = true;
348
349 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
350 !(ch_flags & NVM_CHANNEL_VALID)) {
351 /*
352 * Channels might become valid later if lar is
353 * supported, hence we still want to add them to
354 * the list of supported channels to cfg80211.
355 */
356 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
357 nvm_chan[ch_idx], ch_flags);
358 continue;
359 }
360
361 channel = &data->channels[n_channels];
362 n_channels++;
363
364 channel->hw_value = nvm_chan[ch_idx];
365 channel->band = is_5ghz ?
366 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
367 channel->center_freq =
368 ieee80211_channel_to_frequency(
369 channel->hw_value, channel->band);
370
371 /* Initialize regulatory-based run-time data */
372
373 /*
374 * Default value - highest tx power value. max_power
375 * is not used in mvm, and is used for backwards compatibility
376 */
377 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
378
379 /* don't put limitations in case we're using LAR */
380 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
381 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
382 ch_idx, is_5ghz,
383 ch_flags, cfg);
384 else
385 channel->flags = 0;
386
387 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
388 channel->hw_value, ch_flags);
389 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
390 channel->hw_value, channel->max_power);
391 }
392
393 return n_channels;
394}
395
396static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
397 struct iwl_nvm_data *data,
398 struct ieee80211_sta_vht_cap *vht_cap,
399 u8 tx_chains, u8 rx_chains)
400{
401 const struct iwl_cfg *cfg = trans->cfg;
402 int num_rx_ants = num_of_ant(rx_chains);
403 int num_tx_ants = num_of_ant(tx_chains);
404 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
405 IEEE80211_VHT_MAX_AMPDU_1024K);
406
407 vht_cap->vht_supported = true;
408
409 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
410 IEEE80211_VHT_CAP_RXSTBC_1 |
411 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
412 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
413 max_ampdu_exponent <<
414 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
415
416 if (data->vht160_supported)
417 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
418 IEEE80211_VHT_CAP_SHORT_GI_160;
419
420 if (cfg->vht_mu_mimo_supported)
421 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
422
423 if (cfg->ht_params->ldpc)
424 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
425
426 if (data->sku_cap_mimo_disabled) {
427 num_rx_ants = 1;
428 num_tx_ants = 1;
429 }
430
431 if (num_tx_ants > 1)
432 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
433 else
434 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
435
436 switch (iwlwifi_mod_params.amsdu_size) {
437 case IWL_AMSDU_DEF:
438 if (trans->trans_cfg->mq_rx_supported)
439 vht_cap->cap |=
440 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
441 else
442 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
443 break;
444 case IWL_AMSDU_2K:
445 if (trans->trans_cfg->mq_rx_supported)
446 vht_cap->cap |=
447 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
448 else
449 WARN(1, "RB size of 2K is not supported by this device\n");
450 break;
451 case IWL_AMSDU_4K:
452 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
453 break;
454 case IWL_AMSDU_8K:
455 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
456 break;
457 case IWL_AMSDU_12K:
458 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
459 break;
460 default:
461 break;
462 }
463
464 vht_cap->vht_mcs.rx_mcs_map =
465 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
466 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
467 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
468 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
469 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
470 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
471 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
472 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
473
474 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
475 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
476 /* this works because NOT_SUPPORTED == 3 */
477 vht_cap->vht_mcs.rx_mcs_map |=
478 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
479 }
480
481 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
482
483 vht_cap->vht_mcs.tx_highest |=
484 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
485}
486
487static struct ieee80211_sband_iftype_data iwl_he_capa[] = {
488 {
489 .types_mask = BIT(NL80211_IFTYPE_STATION),
490 .he_cap = {
491 .has_he = true,
492 .he_cap_elem = {
493 .mac_cap_info[0] =
494 IEEE80211_HE_MAC_CAP0_HTC_HE |
495 IEEE80211_HE_MAC_CAP0_TWT_REQ,
496 .mac_cap_info[1] =
497 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
498 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
499 .mac_cap_info[2] =
500 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP |
501 IEEE80211_HE_MAC_CAP2_ACK_EN,
502 .mac_cap_info[3] =
503 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
504 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
505 .mac_cap_info[4] =
506 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU |
507 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
508 .mac_cap_info[5] =
509 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
510 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
511 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
512 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
513 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
514 .phy_cap_info[0] =
515 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
516 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
517 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
518 .phy_cap_info[1] =
519 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
520 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
521 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
522 .phy_cap_info[2] =
523 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
524 .phy_cap_info[3] =
525 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
526 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
527 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
528 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
529 .phy_cap_info[4] =
530 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
531 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
532 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
533 .phy_cap_info[5] =
534 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
535 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
536 .phy_cap_info[6] =
537 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
538 .phy_cap_info[7] =
539 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
540 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
541 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
542 .phy_cap_info[8] =
543 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
544 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
545 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
546 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
547 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
548 .phy_cap_info[9] =
549 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
550 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
551 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
552 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
553 },
554 /*
555 * Set default Tx/Rx HE MCS NSS Support field.
556 * Indicate support for up to 2 spatial streams and all
557 * MCS, without any special cases
558 */
559 .he_mcs_nss_supp = {
560 .rx_mcs_80 = cpu_to_le16(0xfffa),
561 .tx_mcs_80 = cpu_to_le16(0xfffa),
562 .rx_mcs_160 = cpu_to_le16(0xfffa),
563 .tx_mcs_160 = cpu_to_le16(0xfffa),
564 .rx_mcs_80p80 = cpu_to_le16(0xffff),
565 .tx_mcs_80p80 = cpu_to_le16(0xffff),
566 },
567 /*
568 * Set default PPE thresholds, with PPET16 set to 0,
569 * PPET8 set to 7
570 */
571 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
572 },
573 },
574 {
575 .types_mask = BIT(NL80211_IFTYPE_AP),
576 .he_cap = {
577 .has_he = true,
578 .he_cap_elem = {
579 .mac_cap_info[0] =
580 IEEE80211_HE_MAC_CAP0_HTC_HE,
581 .mac_cap_info[1] =
582 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
583 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
584 .mac_cap_info[2] =
585 IEEE80211_HE_MAC_CAP2_BSR |
586 IEEE80211_HE_MAC_CAP2_ACK_EN,
587 .mac_cap_info[3] =
588 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
589 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
590 .mac_cap_info[4] =
591 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
592 .mac_cap_info[5] =
593 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
594 .phy_cap_info[0] =
595 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
596 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
597 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
598 .phy_cap_info[1] =
599 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
600 .phy_cap_info[2] =
601 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
602 .phy_cap_info[3] =
603 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
604 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
605 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
606 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
607 .phy_cap_info[4] =
608 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
609 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
610 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
611 .phy_cap_info[5] =
612 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
613 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
614 .phy_cap_info[6] =
615 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
616 .phy_cap_info[7] =
617 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
618 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
619 .phy_cap_info[8] =
620 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
621 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
622 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
623 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
624 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
625 .phy_cap_info[9] =
626 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
627 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
628 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
629 },
630 /*
631 * Set default Tx/Rx HE MCS NSS Support field.
632 * Indicate support for up to 2 spatial streams and all
633 * MCS, without any special cases
634 */
635 .he_mcs_nss_supp = {
636 .rx_mcs_80 = cpu_to_le16(0xfffa),
637 .tx_mcs_80 = cpu_to_le16(0xfffa),
638 .rx_mcs_160 = cpu_to_le16(0xfffa),
639 .tx_mcs_160 = cpu_to_le16(0xfffa),
640 .rx_mcs_80p80 = cpu_to_le16(0xffff),
641 .tx_mcs_80p80 = cpu_to_le16(0xffff),
642 },
643 /*
644 * Set default PPE thresholds, with PPET16 set to 0,
645 * PPET8 set to 7
646 */
647 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
648 },
649 },
650};
651
652static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband,
653 u8 tx_chains, u8 rx_chains)
654{
655 sband->iftype_data = iwl_he_capa;
656 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
657
658 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
659 if ((tx_chains & rx_chains) != ANT_AB) {
660 int i;
661
662 for (i = 0; i < sband->n_iftype_data; i++) {
663 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &=
664 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
665 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &=
666 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
667 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &=
668 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
669 }
670 }
671}
672
673static void iwl_init_sbands(struct iwl_trans *trans,
674 struct iwl_nvm_data *data,
675 const void *nvm_ch_flags, u8 tx_chains,
676 u8 rx_chains, u32 sbands_flags, bool v4)
677{
678 struct device *dev = trans->dev;
679 const struct iwl_cfg *cfg = trans->cfg;
680 int n_channels;
681 int n_used = 0;
682 struct ieee80211_supported_band *sband;
683
684 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
685 sbands_flags, v4);
686 sband = &data->bands[NL80211_BAND_2GHZ];
687 sband->band = NL80211_BAND_2GHZ;
688 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
689 sband->n_bitrates = N_RATES_24;
690 n_used += iwl_init_sband_channels(data, sband, n_channels,
691 NL80211_BAND_2GHZ);
692 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
693 tx_chains, rx_chains);
694
695 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
696 iwl_init_he_hw_capab(sband, tx_chains, rx_chains);
697
698 sband = &data->bands[NL80211_BAND_5GHZ];
699 sband->band = NL80211_BAND_5GHZ;
700 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
701 sband->n_bitrates = N_RATES_52;
702 n_used += iwl_init_sband_channels(data, sband, n_channels,
703 NL80211_BAND_5GHZ);
704 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
705 tx_chains, rx_chains);
706 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
707 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
708 tx_chains, rx_chains);
709
710 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
711 iwl_init_he_hw_capab(sband, tx_chains, rx_chains);
712
713 if (n_channels != n_used)
714 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
715 n_used, n_channels);
716}
717
718static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
719 const __le16 *phy_sku)
720{
721 if (cfg->nvm_type != IWL_NVM_EXT)
722 return le16_to_cpup(nvm_sw + SKU);
723
724 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
725}
726
727static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
728{
729 if (cfg->nvm_type != IWL_NVM_EXT)
730 return le16_to_cpup(nvm_sw + NVM_VERSION);
731 else
732 return le32_to_cpup((__le32 *)(nvm_sw +
733 NVM_VERSION_EXT_NVM));
734}
735
736static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
737 const __le16 *phy_sku)
738{
739 if (cfg->nvm_type != IWL_NVM_EXT)
740 return le16_to_cpup(nvm_sw + RADIO_CFG);
741
742 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
743
744}
745
746static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
747{
748 int n_hw_addr;
749
750 if (cfg->nvm_type != IWL_NVM_EXT)
751 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
752
753 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
754
755 return n_hw_addr & N_HW_ADDR_MASK;
756}
757
758static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
759 struct iwl_nvm_data *data,
760 u32 radio_cfg)
761{
762 if (cfg->nvm_type != IWL_NVM_EXT) {
763 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
764 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
765 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
766 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
767 return;
768 }
769
770 /* set the radio configuration for family 8000 */
771 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
772 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
773 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
774 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
775 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
776 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
777}
778
779static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
780{
781 const u8 *hw_addr;
782
783 hw_addr = (const u8 *)&mac_addr0;
784 dest[0] = hw_addr[3];
785 dest[1] = hw_addr[2];
786 dest[2] = hw_addr[1];
787 dest[3] = hw_addr[0];
788
789 hw_addr = (const u8 *)&mac_addr1;
790 dest[4] = hw_addr[1];
791 dest[5] = hw_addr[0];
792}
793
794static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
795 struct iwl_nvm_data *data)
796{
797 __le32 mac_addr0 =
798 cpu_to_le32(iwl_read32(trans,
799 trans->trans_cfg->csr->mac_addr0_strap));
800 __le32 mac_addr1 =
801 cpu_to_le32(iwl_read32(trans,
802 trans->trans_cfg->csr->mac_addr1_strap));
803
804 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
805 /*
806 * If the OEM fused a valid address, use it instead of the one in the
807 * OTP
808 */
809 if (is_valid_ether_addr(data->hw_addr))
810 return;
811
812 mac_addr0 = cpu_to_le32(iwl_read32(trans,
813 trans->trans_cfg->csr->mac_addr0_otp));
814 mac_addr1 = cpu_to_le32(iwl_read32(trans,
815 trans->trans_cfg->csr->mac_addr1_otp));
816
817 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
818}
819
820static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
821 const struct iwl_cfg *cfg,
822 struct iwl_nvm_data *data,
823 const __le16 *mac_override,
824 const __be16 *nvm_hw)
825{
826 const u8 *hw_addr;
827
828 if (mac_override) {
829 static const u8 reserved_mac[] = {
830 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
831 };
832
833 hw_addr = (const u8 *)(mac_override +
834 MAC_ADDRESS_OVERRIDE_EXT_NVM);
835
836 /*
837 * Store the MAC address from MAO section.
838 * No byte swapping is required in MAO section
839 */
840 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
841
842 /*
843 * Force the use of the OTP MAC address in case of reserved MAC
844 * address in the NVM, or if address is given but invalid.
845 */
846 if (is_valid_ether_addr(data->hw_addr) &&
847 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
848 return;
849
850 IWL_ERR(trans,
851 "mac address from nvm override section is not valid\n");
852 }
853
854 if (nvm_hw) {
855 /* read the mac address from WFMP registers */
856 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
857 WFMP_MAC_ADDR_0));
858 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
859 WFMP_MAC_ADDR_1));
860
861 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
862
863 return;
864 }
865
866 IWL_ERR(trans, "mac address is not found\n");
867}
868
869static int iwl_set_hw_address(struct iwl_trans *trans,
870 const struct iwl_cfg *cfg,
871 struct iwl_nvm_data *data, const __be16 *nvm_hw,
872 const __le16 *mac_override)
873{
874 if (cfg->mac_addr_from_csr) {
875 iwl_set_hw_address_from_csr(trans, data);
876 } else if (cfg->nvm_type != IWL_NVM_EXT) {
877 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
878
879 /* The byte order is little endian 16 bit, meaning 214365 */
880 data->hw_addr[0] = hw_addr[1];
881 data->hw_addr[1] = hw_addr[0];
882 data->hw_addr[2] = hw_addr[3];
883 data->hw_addr[3] = hw_addr[2];
884 data->hw_addr[4] = hw_addr[5];
885 data->hw_addr[5] = hw_addr[4];
886 } else {
887 iwl_set_hw_address_family_8000(trans, cfg, data,
888 mac_override, nvm_hw);
889 }
890
891 if (!is_valid_ether_addr(data->hw_addr)) {
892 IWL_ERR(trans, "no valid mac address was found\n");
893 return -EINVAL;
894 }
895
896 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
897
898 return 0;
899}
900
901static bool
902iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
903 const __be16 *nvm_hw)
904{
905 /*
906 * Workaround a bug in Indonesia SKUs where the regulatory in
907 * some 7000-family OTPs erroneously allow wide channels in
908 * 5GHz. To check for Indonesia, we take the SKU value from
909 * bits 1-4 in the subsystem ID and check if it is either 5 or
910 * 9. In those cases, we need to force-disable wide channels
911 * in 5GHz otherwise the FW will throw a sysassert when we try
912 * to use them.
913 */
914 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
915 /*
916 * Unlike the other sections in the NVM, the hw
917 * section uses big-endian.
918 */
919 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
920 u8 sku = (subsystem_id & 0x1e) >> 1;
921
922 if (sku == 5 || sku == 9) {
923 IWL_DEBUG_EEPROM(trans->dev,
924 "disabling wide channels in 5GHz (0x%0x %d)\n",
925 subsystem_id, sku);
926 return true;
927 }
928 }
929
930 return false;
931}
932
933struct iwl_nvm_data *
934iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
935 const __be16 *nvm_hw, const __le16 *nvm_sw,
936 const __le16 *nvm_calib, const __le16 *regulatory,
937 const __le16 *mac_override, const __le16 *phy_sku,
938 u8 tx_chains, u8 rx_chains, bool lar_fw_supported)
939{
940 struct iwl_nvm_data *data;
941 bool lar_enabled;
942 u32 sku, radio_cfg;
943 u32 sbands_flags = 0;
944 u16 lar_config;
945 const __le16 *ch_section;
946
947 if (cfg->uhb_supported)
948 data = kzalloc(struct_size(data, channels,
949 IWL_NVM_NUM_CHANNELS_UHB),
950 GFP_KERNEL);
951 else if (cfg->nvm_type != IWL_NVM_EXT)
952 data = kzalloc(struct_size(data, channels,
953 IWL_NVM_NUM_CHANNELS),
954 GFP_KERNEL);
955 else
956 data = kzalloc(struct_size(data, channels,
957 IWL_NVM_NUM_CHANNELS_EXT),
958 GFP_KERNEL);
959 if (!data)
960 return NULL;
961
962 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
963
964 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
965 iwl_set_radio_cfg(cfg, data, radio_cfg);
966 if (data->valid_tx_ant)
967 tx_chains &= data->valid_tx_ant;
968 if (data->valid_rx_ant)
969 rx_chains &= data->valid_rx_ant;
970
971 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
972 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
973 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
974 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
975 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
976 data->sku_cap_11n_enable = false;
977 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
978 (sku & NVM_SKU_CAP_11AC_ENABLE);
979 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
980
981 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
982
983 if (cfg->nvm_type != IWL_NVM_EXT) {
984 /* Checking for required sections */
985 if (!nvm_calib) {
986 IWL_ERR(trans,
987 "Can't parse empty Calib NVM sections\n");
988 kfree(data);
989 return NULL;
990 }
991
992 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
993 ®ulatory[NVM_CHANNELS_SDP] :
994 &nvm_sw[NVM_CHANNELS];
995
996 /* in family 8000 Xtal calibration values moved to OTP */
997 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
998 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
999 lar_enabled = true;
1000 } else {
1001 u16 lar_offset = data->nvm_version < 0xE39 ?
1002 NVM_LAR_OFFSET_OLD :
1003 NVM_LAR_OFFSET;
1004
1005 lar_config = le16_to_cpup(regulatory + lar_offset);
1006 data->lar_enabled = !!(lar_config &
1007 NVM_LAR_ENABLED);
1008 lar_enabled = data->lar_enabled;
1009 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
1010 }
1011
1012 /* If no valid mac address was found - bail out */
1013 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1014 kfree(data);
1015 return NULL;
1016 }
1017
1018 if (lar_fw_supported && lar_enabled)
1019 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1020
1021 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1022 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1023
1024 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1025 sbands_flags, false);
1026 data->calib_version = 255;
1027
1028 return data;
1029}
1030IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1031
1032static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1033 int ch_idx, u16 nvm_flags,
1034 const struct iwl_cfg *cfg)
1035{
1036 u32 flags = NL80211_RRF_NO_HT40;
1037
1038 if (ch_idx < NUM_2GHZ_CHANNELS &&
1039 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1040 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1041 flags &= ~NL80211_RRF_NO_HT40PLUS;
1042 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1043 flags &= ~NL80211_RRF_NO_HT40MINUS;
1044 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1045 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1046 flags &= ~NL80211_RRF_NO_HT40PLUS;
1047 else
1048 flags &= ~NL80211_RRF_NO_HT40MINUS;
1049 }
1050
1051 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1052 flags |= NL80211_RRF_NO_80MHZ;
1053 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1054 flags |= NL80211_RRF_NO_160MHZ;
1055
1056 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1057 flags |= NL80211_RRF_NO_IR;
1058
1059 if (nvm_flags & NVM_CHANNEL_RADAR)
1060 flags |= NL80211_RRF_DFS;
1061
1062 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1063 flags |= NL80211_RRF_NO_OUTDOOR;
1064
1065 /* Set the GO concurrent flag only in case that NO_IR is set.
1066 * Otherwise it is meaningless
1067 */
1068 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1069 (flags & NL80211_RRF_NO_IR))
1070 flags |= NL80211_RRF_GO_CONCURRENT;
1071
1072 return flags;
1073}
1074
1075struct ieee80211_regdomain *
1076iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1077 int num_of_ch, __le32 *channels, u16 fw_mcc,
1078 u16 geo_info)
1079{
1080 int ch_idx;
1081 u16 ch_flags;
1082 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1083 const u16 *nvm_chan;
1084 struct ieee80211_regdomain *regd, *copy_rd;
1085 struct ieee80211_reg_rule *rule;
1086 enum nl80211_band band;
1087 int center_freq, prev_center_freq = 0;
1088 int valid_rules = 0;
1089 bool new_rule;
1090 int max_num_ch;
1091
1092 if (cfg->uhb_supported) {
1093 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1094 nvm_chan = iwl_uhb_nvm_channels;
1095 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1096 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1097 nvm_chan = iwl_ext_nvm_channels;
1098 } else {
1099 max_num_ch = IWL_NVM_NUM_CHANNELS;
1100 nvm_chan = iwl_nvm_channels;
1101 }
1102
1103 if (WARN_ON(num_of_ch > max_num_ch))
1104 num_of_ch = max_num_ch;
1105
1106 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1107 return ERR_PTR(-EINVAL);
1108
1109 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1110 num_of_ch);
1111
1112 /* build a regdomain rule for every valid channel */
1113 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1114 if (!regd)
1115 return ERR_PTR(-ENOMEM);
1116
1117 /* set alpha2 from FW. */
1118 regd->alpha2[0] = fw_mcc >> 8;
1119 regd->alpha2[1] = fw_mcc & 0xff;
1120
1121 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1122 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1123 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
1124 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1125 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1126 band);
1127 new_rule = false;
1128
1129 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1130 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1131 nvm_chan[ch_idx], ch_flags);
1132 continue;
1133 }
1134
1135 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1136 ch_flags, cfg);
1137
1138 /* we can't continue the same rule */
1139 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1140 center_freq - prev_center_freq > 20) {
1141 valid_rules++;
1142 new_rule = true;
1143 }
1144
1145 rule = ®d->reg_rules[valid_rules - 1];
1146
1147 if (new_rule)
1148 rule->freq_range.start_freq_khz =
1149 MHZ_TO_KHZ(center_freq - 10);
1150
1151 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1152
1153 /* this doesn't matter - not used by FW */
1154 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1155 rule->power_rule.max_eirp =
1156 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1157
1158 rule->flags = reg_rule_flags;
1159
1160 /* rely on auto-calculation to merge BW of contiguous chans */
1161 rule->flags |= NL80211_RRF_AUTO_BW;
1162 rule->freq_range.max_bandwidth_khz = 0;
1163
1164 prev_center_freq = center_freq;
1165 prev_reg_rule_flags = reg_rule_flags;
1166
1167 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1168 nvm_chan[ch_idx], ch_flags);
1169
1170 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1171 band == NL80211_BAND_2GHZ)
1172 continue;
1173
1174 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1175 }
1176
1177 regd->n_reg_rules = valid_rules;
1178
1179 /*
1180 * Narrow down regdom for unused regulatory rules to prevent hole
1181 * between reg rules to wmm rules.
1182 */
1183 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1184 GFP_KERNEL);
1185 if (!copy_rd)
1186 copy_rd = ERR_PTR(-ENOMEM);
1187
1188 kfree(regd);
1189 return copy_rd;
1190}
1191IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1192
1193#define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1194#define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1195#define MAX_NVM_FILE_LEN 16384
1196
1197void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1198 unsigned int len)
1199{
1200#define IWL_4165_DEVICE_ID 0x5501
1201#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1202
1203 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1204 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1205 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1206 /* OTP 0x52 bug work around: it's a 1x1 device */
1207 data[3] = ANT_B | (ANT_B << 4);
1208}
1209IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1210
1211/*
1212 * Reads external NVM from a file into mvm->nvm_sections
1213 *
1214 * HOW TO CREATE THE NVM FILE FORMAT:
1215 * ------------------------------
1216 * 1. create hex file, format:
1217 * 3800 -> header
1218 * 0000 -> header
1219 * 5a40 -> data
1220 *
1221 * rev - 6 bit (word1)
1222 * len - 10 bit (word1)
1223 * id - 4 bit (word2)
1224 * rsv - 12 bit (word2)
1225 *
1226 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1227 *
1228 * 3. create binary file from the hex file
1229 *
1230 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1231 */
1232int iwl_read_external_nvm(struct iwl_trans *trans,
1233 const char *nvm_file_name,
1234 struct iwl_nvm_section *nvm_sections)
1235{
1236 int ret, section_size;
1237 u16 section_id;
1238 const struct firmware *fw_entry;
1239 const struct {
1240 __le16 word1;
1241 __le16 word2;
1242 u8 data[];
1243 } *file_sec;
1244 const u8 *eof;
1245 u8 *temp;
1246 int max_section_size;
1247 const __le32 *dword_buff;
1248
1249#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1250#define NVM_WORD2_ID(x) (x >> 12)
1251#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1252#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1253#define NVM_HEADER_0 (0x2A504C54)
1254#define NVM_HEADER_1 (0x4E564D2A)
1255#define NVM_HEADER_SIZE (4 * sizeof(u32))
1256
1257 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1258
1259 /* Maximal size depends on NVM version */
1260 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1261 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1262 else
1263 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1264
1265 /*
1266 * Obtain NVM image via request_firmware. Since we already used
1267 * request_firmware_nowait() for the firmware binary load and only
1268 * get here after that we assume the NVM request can be satisfied
1269 * synchronously.
1270 */
1271 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1272 if (ret) {
1273 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1274 nvm_file_name, ret);
1275 return ret;
1276 }
1277
1278 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1279 nvm_file_name, fw_entry->size);
1280
1281 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1282 IWL_ERR(trans, "NVM file too large\n");
1283 ret = -EINVAL;
1284 goto out;
1285 }
1286
1287 eof = fw_entry->data + fw_entry->size;
1288 dword_buff = (__le32 *)fw_entry->data;
1289
1290 /* some NVM file will contain a header.
1291 * The header is identified by 2 dwords header as follow:
1292 * dword[0] = 0x2A504C54
1293 * dword[1] = 0x4E564D2A
1294 *
1295 * This header must be skipped when providing the NVM data to the FW.
1296 */
1297 if (fw_entry->size > NVM_HEADER_SIZE &&
1298 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1299 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1300 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1301 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1302 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1303 le32_to_cpu(dword_buff[3]));
1304
1305 /* nvm file validation, dword_buff[2] holds the file version */
1306 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1307 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1308 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1309 ret = -EFAULT;
1310 goto out;
1311 }
1312 } else {
1313 file_sec = (void *)fw_entry->data;
1314 }
1315
1316 while (true) {
1317 if (file_sec->data > eof) {
1318 IWL_ERR(trans,
1319 "ERROR - NVM file too short for section header\n");
1320 ret = -EINVAL;
1321 break;
1322 }
1323
1324 /* check for EOF marker */
1325 if (!file_sec->word1 && !file_sec->word2) {
1326 ret = 0;
1327 break;
1328 }
1329
1330 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1331 section_size =
1332 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1333 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1334 } else {
1335 section_size = 2 * EXT_NVM_WORD2_LEN(
1336 le16_to_cpu(file_sec->word2));
1337 section_id = EXT_NVM_WORD1_ID(
1338 le16_to_cpu(file_sec->word1));
1339 }
1340
1341 if (section_size > max_section_size) {
1342 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1343 section_size);
1344 ret = -EINVAL;
1345 break;
1346 }
1347
1348 if (!section_size) {
1349 IWL_ERR(trans, "ERROR - section empty\n");
1350 ret = -EINVAL;
1351 break;
1352 }
1353
1354 if (file_sec->data + section_size > eof) {
1355 IWL_ERR(trans,
1356 "ERROR - NVM file too short for section (%d bytes)\n",
1357 section_size);
1358 ret = -EINVAL;
1359 break;
1360 }
1361
1362 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1363 "Invalid NVM section ID %d\n", section_id)) {
1364 ret = -EINVAL;
1365 break;
1366 }
1367
1368 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1369 if (!temp) {
1370 ret = -ENOMEM;
1371 break;
1372 }
1373
1374 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1375
1376 kfree(nvm_sections[section_id].data);
1377 nvm_sections[section_id].data = temp;
1378 nvm_sections[section_id].length = section_size;
1379
1380 /* advance to the next section */
1381 file_sec = (void *)(file_sec->data + section_size);
1382 }
1383out:
1384 release_firmware(fw_entry);
1385 return ret;
1386}
1387IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1388
1389struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1390 const struct iwl_fw *fw)
1391{
1392 struct iwl_nvm_get_info cmd = {};
1393 struct iwl_nvm_data *nvm;
1394 struct iwl_host_cmd hcmd = {
1395 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1396 .data = { &cmd, },
1397 .len = { sizeof(cmd) },
1398 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1399 };
1400 int ret;
1401 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable &&
1402 fw_has_capa(&fw->ucode_capa,
1403 IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
1404 bool empty_otp;
1405 u32 mac_flags;
1406 u32 sbands_flags = 0;
1407 /*
1408 * All the values in iwl_nvm_get_info_rsp v4 are the same as
1409 * in v3, except for the channel profile part of the
1410 * regulatory. So we can just access the new struct, with the
1411 * exception of the latter.
1412 */
1413 struct iwl_nvm_get_info_rsp *rsp;
1414 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1415 bool v4 = fw_has_api(&fw->ucode_capa,
1416 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1417 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1418 void *channel_profile;
1419
1420 ret = iwl_trans_send_cmd(trans, &hcmd);
1421 if (ret)
1422 return ERR_PTR(ret);
1423
1424 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1425 "Invalid payload len in NVM response from FW %d",
1426 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1427 ret = -EINVAL;
1428 goto out;
1429 }
1430
1431 rsp = (void *)hcmd.resp_pkt->data;
1432 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1433 NVM_GENERAL_FLAGS_EMPTY_OTP);
1434 if (empty_otp)
1435 IWL_INFO(trans, "OTP is empty\n");
1436
1437 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1438 if (!nvm) {
1439 ret = -ENOMEM;
1440 goto out;
1441 }
1442
1443 iwl_set_hw_address_from_csr(trans, nvm);
1444 /* TODO: if platform NVM has MAC address - override it here */
1445
1446 if (!is_valid_ether_addr(nvm->hw_addr)) {
1447 IWL_ERR(trans, "no valid mac address was found\n");
1448 ret = -EINVAL;
1449 goto err_free;
1450 }
1451
1452 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1453
1454 /* Initialize general data */
1455 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1456 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1457 if (nvm->n_hw_addrs == 0)
1458 IWL_WARN(trans,
1459 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1460 empty_otp);
1461
1462 /* Initialize MAC sku data */
1463 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1464 nvm->sku_cap_11ac_enable =
1465 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1466 nvm->sku_cap_11n_enable =
1467 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1468 nvm->sku_cap_11ax_enable =
1469 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1470 nvm->sku_cap_band_24ghz_enable =
1471 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1472 nvm->sku_cap_band_52ghz_enable =
1473 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1474 nvm->sku_cap_mimo_disabled =
1475 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1476
1477 /* Initialize PHY sku data */
1478 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1479 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1480
1481 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) {
1482 nvm->lar_enabled = true;
1483 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1484 }
1485
1486 rsp_v3 = (void *)rsp;
1487 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1488 (void *)rsp_v3->regulatory.channel_profile;
1489
1490 iwl_init_sbands(trans, nvm,
1491 channel_profile,
1492 nvm->valid_tx_ant & fw->valid_tx_ant,
1493 nvm->valid_rx_ant & fw->valid_rx_ant,
1494 sbands_flags, v4);
1495
1496 iwl_free_resp(&hcmd);
1497 return nvm;
1498
1499err_free:
1500 kfree(nvm);
1501out:
1502 iwl_free_resp(&hcmd);
1503 return ERR_PTR(ret);
1504}
1505IWL_EXPORT_SYMBOL(iwl_get_nvm);