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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <drm/drm_fourcc.h>
7
8#include <linux/clk.h>
9#include <linux/component.h>
10#include <linux/module.h>
11#include <linux/of_device.h>
12#include <linux/of_irq.h>
13#include <linux/platform_device.h>
14#include <linux/soc/mediatek/mtk-cmdq.h>
15
16#include "mtk_drm_crtc.h"
17#include "mtk_drm_ddp_comp.h"
18
19#define DISP_REG_OVL_INTEN 0x0004
20#define OVL_FME_CPL_INT BIT(1)
21#define DISP_REG_OVL_INTSTA 0x0008
22#define DISP_REG_OVL_EN 0x000c
23#define DISP_REG_OVL_RST 0x0014
24#define DISP_REG_OVL_ROI_SIZE 0x0020
25#define DISP_REG_OVL_DATAPATH_CON 0x0024
26#define OVL_BGCLR_SEL_IN BIT(2)
27#define DISP_REG_OVL_ROI_BGCLR 0x0028
28#define DISP_REG_OVL_SRC_CON 0x002c
29#define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
30#define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
31#define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
32#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
33#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
34#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
35#define DISP_REG_OVL_ADDR_MT2701 0x0040
36#define DISP_REG_OVL_ADDR_MT8173 0x0f40
37#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
38
39#define GMC_THRESHOLD_BITS 16
40#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
41#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
42
43#define OVL_CON_BYTE_SWAP BIT(24)
44#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
45#define OVL_CON_CLRFMT_RGB (1 << 12)
46#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
47#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
48#define OVL_CON_CLRFMT_UYVY (4 << 12)
49#define OVL_CON_CLRFMT_YUYV (5 << 12)
50#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
51 0 : OVL_CON_CLRFMT_RGB)
52#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
53 OVL_CON_CLRFMT_RGB : 0)
54#define OVL_CON_AEN BIT(8)
55#define OVL_CON_ALPHA 0xff
56#define OVL_CON_VIRT_FLIP BIT(9)
57#define OVL_CON_HORZ_FLIP BIT(10)
58
59struct mtk_disp_ovl_data {
60 unsigned int addr;
61 unsigned int gmc_bits;
62 unsigned int layer_nr;
63 bool fmt_rgb565_is_0;
64};
65
66/**
67 * struct mtk_disp_ovl - DISP_OVL driver structure
68 * @ddp_comp - structure containing type enum and hardware resources
69 * @crtc - associated crtc to report vblank events to
70 */
71struct mtk_disp_ovl {
72 struct mtk_ddp_comp ddp_comp;
73 struct drm_crtc *crtc;
74 const struct mtk_disp_ovl_data *data;
75};
76
77static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp)
78{
79 return container_of(comp, struct mtk_disp_ovl, ddp_comp);
80}
81
82static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
83{
84 struct mtk_disp_ovl *priv = dev_id;
85 struct mtk_ddp_comp *ovl = &priv->ddp_comp;
86
87 /* Clear frame completion interrupt */
88 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
89
90 if (!priv->crtc)
91 return IRQ_NONE;
92
93 mtk_crtc_ddp_irq(priv->crtc, ovl);
94
95 return IRQ_HANDLED;
96}
97
98static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
99 struct drm_crtc *crtc)
100{
101 struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
102
103 ovl->crtc = crtc;
104 writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
105 writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
106}
107
108static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
109{
110 struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
111
112 ovl->crtc = NULL;
113 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
114}
115
116static void mtk_ovl_start(struct mtk_ddp_comp *comp)
117{
118 writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
119}
120
121static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
122{
123 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
124}
125
126static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
127 unsigned int h, unsigned int vrefresh,
128 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
129{
130 if (w != 0 && h != 0)
131 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
132 DISP_REG_OVL_ROI_SIZE);
133 mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
134
135 mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
136 mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
137}
138
139static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
140{
141 struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
142
143 return ovl->data->layer_nr;
144}
145
146static unsigned int mtk_ovl_supported_rotations(struct mtk_ddp_comp *comp)
147{
148 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
149 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
150}
151
152static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx,
153 struct mtk_plane_state *mtk_state)
154{
155 struct drm_plane_state *state = &mtk_state->base;
156 unsigned int rotation = 0;
157
158 rotation = drm_rotation_simplify(state->rotation,
159 DRM_MODE_ROTATE_0 |
160 DRM_MODE_REFLECT_X |
161 DRM_MODE_REFLECT_Y);
162 rotation &= ~DRM_MODE_ROTATE_0;
163
164 /* We can only do reflection, not rotation */
165 if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
166 return -EINVAL;
167
168 /*
169 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
170 * Only RGB[AX] variants are supported.
171 */
172 if (state->fb->format->is_yuv && rotation != 0)
173 return -EINVAL;
174
175 state->rotation = rotation;
176
177 return 0;
178}
179
180static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
181 struct cmdq_pkt *cmdq_pkt)
182{
183 unsigned int gmc_thrshd_l;
184 unsigned int gmc_thrshd_h;
185 unsigned int gmc_value;
186 struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
187
188 mtk_ddp_write(cmdq_pkt, 0x1, comp,
189 DISP_REG_OVL_RDMA_CTRL(idx));
190 gmc_thrshd_l = GMC_THRESHOLD_LOW >>
191 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
192 gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
193 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
194 if (ovl->data->gmc_bits == 10)
195 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
196 else
197 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
198 gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
199 mtk_ddp_write(cmdq_pkt, gmc_value,
200 comp, DISP_REG_OVL_RDMA_GMC(idx));
201 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
202 DISP_REG_OVL_SRC_CON, BIT(idx));
203}
204
205static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
206 struct cmdq_pkt *cmdq_pkt)
207{
208 mtk_ddp_write_mask(cmdq_pkt, 0, comp,
209 DISP_REG_OVL_SRC_CON, BIT(idx));
210 mtk_ddp_write(cmdq_pkt, 0, comp,
211 DISP_REG_OVL_RDMA_CTRL(idx));
212}
213
214static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
215{
216 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
217 * is defined in mediatek HW data sheet.
218 * The alphabet order in XXX is no relation to data
219 * arrangement in memory.
220 */
221 switch (fmt) {
222 default:
223 case DRM_FORMAT_RGB565:
224 return OVL_CON_CLRFMT_RGB565(ovl);
225 case DRM_FORMAT_BGR565:
226 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
227 case DRM_FORMAT_RGB888:
228 return OVL_CON_CLRFMT_RGB888(ovl);
229 case DRM_FORMAT_BGR888:
230 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
231 case DRM_FORMAT_RGBX8888:
232 case DRM_FORMAT_RGBA8888:
233 return OVL_CON_CLRFMT_ARGB8888;
234 case DRM_FORMAT_BGRX8888:
235 case DRM_FORMAT_BGRA8888:
236 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
237 case DRM_FORMAT_XRGB8888:
238 case DRM_FORMAT_ARGB8888:
239 return OVL_CON_CLRFMT_RGBA8888;
240 case DRM_FORMAT_XBGR8888:
241 case DRM_FORMAT_ABGR8888:
242 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
243 case DRM_FORMAT_UYVY:
244 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
245 case DRM_FORMAT_YUYV:
246 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
247 }
248}
249
250static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
251 struct mtk_plane_state *state,
252 struct cmdq_pkt *cmdq_pkt)
253{
254 struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
255 struct mtk_plane_pending_state *pending = &state->pending;
256 unsigned int addr = pending->addr;
257 unsigned int pitch = pending->pitch & 0xffff;
258 unsigned int fmt = pending->format;
259 unsigned int offset = (pending->y << 16) | pending->x;
260 unsigned int src_size = (pending->height << 16) | pending->width;
261 unsigned int con;
262
263 if (!pending->enable) {
264 mtk_ovl_layer_off(comp, idx, cmdq_pkt);
265 return;
266 }
267
268 con = ovl_fmt_convert(ovl, fmt);
269 if (state->base.fb->format->has_alpha)
270 con |= OVL_CON_AEN | OVL_CON_ALPHA;
271
272 if (pending->rotation & DRM_MODE_REFLECT_Y) {
273 con |= OVL_CON_VIRT_FLIP;
274 addr += (pending->height - 1) * pending->pitch;
275 }
276
277 if (pending->rotation & DRM_MODE_REFLECT_X) {
278 con |= OVL_CON_HORZ_FLIP;
279 addr += pending->pitch - 1;
280 }
281
282 mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
283 DISP_REG_OVL_CON(idx));
284 mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
285 DISP_REG_OVL_PITCH(idx));
286 mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
287 DISP_REG_OVL_SRC_SIZE(idx));
288 mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
289 DISP_REG_OVL_OFFSET(idx));
290 mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
291 DISP_REG_OVL_ADDR(ovl, idx));
292
293 mtk_ovl_layer_on(comp, idx, cmdq_pkt);
294}
295
296static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
297{
298 unsigned int reg;
299
300 reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
301 reg = reg | OVL_BGCLR_SEL_IN;
302 writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
303}
304
305static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
306{
307 unsigned int reg;
308
309 reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
310 reg = reg & ~OVL_BGCLR_SEL_IN;
311 writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
312}
313
314static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
315 .config = mtk_ovl_config,
316 .start = mtk_ovl_start,
317 .stop = mtk_ovl_stop,
318 .enable_vblank = mtk_ovl_enable_vblank,
319 .disable_vblank = mtk_ovl_disable_vblank,
320 .supported_rotations = mtk_ovl_supported_rotations,
321 .layer_nr = mtk_ovl_layer_nr,
322 .layer_check = mtk_ovl_layer_check,
323 .layer_config = mtk_ovl_layer_config,
324 .bgclr_in_on = mtk_ovl_bgclr_in_on,
325 .bgclr_in_off = mtk_ovl_bgclr_in_off,
326};
327
328static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
329 void *data)
330{
331 struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
332 struct drm_device *drm_dev = data;
333 int ret;
334
335 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
336 if (ret < 0) {
337 dev_err(dev, "Failed to register component %pOF: %d\n",
338 dev->of_node, ret);
339 return ret;
340 }
341
342 return 0;
343}
344
345static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
346 void *data)
347{
348 struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
349 struct drm_device *drm_dev = data;
350
351 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
352}
353
354static const struct component_ops mtk_disp_ovl_component_ops = {
355 .bind = mtk_disp_ovl_bind,
356 .unbind = mtk_disp_ovl_unbind,
357};
358
359static int mtk_disp_ovl_probe(struct platform_device *pdev)
360{
361 struct device *dev = &pdev->dev;
362 struct mtk_disp_ovl *priv;
363 int comp_id;
364 int irq;
365 int ret;
366
367 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
368 if (!priv)
369 return -ENOMEM;
370
371 irq = platform_get_irq(pdev, 0);
372 if (irq < 0)
373 return irq;
374
375 priv->data = of_device_get_match_data(dev);
376
377 comp_id = mtk_ddp_comp_get_id(dev->of_node,
378 priv->data->layer_nr == 4 ?
379 MTK_DISP_OVL :
380 MTK_DISP_OVL_2L);
381 if (comp_id < 0) {
382 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
383 return comp_id;
384 }
385
386 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
387 &mtk_disp_ovl_funcs);
388 if (ret) {
389 if (ret != -EPROBE_DEFER)
390 dev_err(dev, "Failed to initialize component: %d\n",
391 ret);
392
393 return ret;
394 }
395
396 platform_set_drvdata(pdev, priv);
397
398 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
399 IRQF_TRIGGER_NONE, dev_name(dev), priv);
400 if (ret < 0) {
401 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
402 return ret;
403 }
404
405 ret = component_add(dev, &mtk_disp_ovl_component_ops);
406 if (ret)
407 dev_err(dev, "Failed to add component: %d\n", ret);
408
409 return ret;
410}
411
412static int mtk_disp_ovl_remove(struct platform_device *pdev)
413{
414 component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
415
416 return 0;
417}
418
419static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
420 .addr = DISP_REG_OVL_ADDR_MT2701,
421 .gmc_bits = 8,
422 .layer_nr = 4,
423 .fmt_rgb565_is_0 = false,
424};
425
426static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
427 .addr = DISP_REG_OVL_ADDR_MT8173,
428 .gmc_bits = 8,
429 .layer_nr = 4,
430 .fmt_rgb565_is_0 = true,
431};
432
433static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
434 { .compatible = "mediatek,mt2701-disp-ovl",
435 .data = &mt2701_ovl_driver_data},
436 { .compatible = "mediatek,mt8173-disp-ovl",
437 .data = &mt8173_ovl_driver_data},
438 {},
439};
440MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
441
442struct platform_driver mtk_disp_ovl_driver = {
443 .probe = mtk_disp_ovl_probe,
444 .remove = mtk_disp_ovl_remove,
445 .driver = {
446 .name = "mediatek-disp-ovl",
447 .owner = THIS_MODULE,
448 .of_match_table = mtk_disp_ovl_driver_dt_match,
449 },
450};