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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <drm/intel-gtt.h>
39#include <linux/backlight.h>
40
41/* General customization:
42 */
43
44#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45
46#define DRIVER_NAME "i915"
47#define DRIVER_DESC "Intel Graphics"
48#define DRIVER_DATE "20080730"
49
50enum pipe {
51 PIPE_A = 0,
52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
55};
56#define pipe_name(p) ((p) + 'A')
57
58enum plane {
59 PLANE_A = 0,
60 PLANE_B,
61 PLANE_C,
62};
63#define plane_name(p) ((p) + 'A')
64
65#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66
67#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
69/* Interface history:
70 *
71 * 1.1: Original.
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
78 */
79#define DRIVER_MAJOR 1
80#define DRIVER_MINOR 6
81#define DRIVER_PATCHLEVEL 0
82
83#define WATCH_COHERENCY 0
84#define WATCH_LISTS 0
85
86#define I915_GEM_PHYS_CURSOR_0 1
87#define I915_GEM_PHYS_CURSOR_1 2
88#define I915_GEM_PHYS_OVERLAY_REGS 3
89#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90
91struct drm_i915_gem_phys_object {
92 int id;
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
96};
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
104};
105
106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110
111struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 void *vbt;
117 u32 __iomem *lid_state;
118};
119#define OPREGION_SIZE (8*1024)
120
121struct intel_overlay;
122struct intel_overlay_error_state;
123
124struct drm_i915_master_private {
125 drm_local_map_t *sarea;
126 struct _drm_i915_sarea *sarea_priv;
127};
128#define I915_FENCE_REG_NONE -1
129
130struct drm_i915_fence_reg {
131 struct list_head lru_list;
132 struct drm_i915_gem_object *obj;
133 uint32_t setup_seqno;
134};
135
136struct sdvo_device_mapping {
137 u8 initialized;
138 u8 dvo_port;
139 u8 slave_addr;
140 u8 dvo_wiring;
141 u8 i2c_pin;
142 u8 i2c_speed;
143 u8 ddc_pin;
144};
145
146struct intel_display_error_state;
147
148struct drm_i915_error_state {
149 u32 eir;
150 u32 pgtbl_er;
151 u32 pipestat[I915_MAX_PIPES];
152 u32 ipeir;
153 u32 ipehr;
154 u32 instdone;
155 u32 acthd;
156 u32 error; /* gen6+ */
157 u32 bcs_acthd; /* gen6+ blt engine */
158 u32 bcs_ipehr;
159 u32 bcs_ipeir;
160 u32 bcs_instdone;
161 u32 bcs_seqno;
162 u32 vcs_acthd; /* gen6+ bsd engine */
163 u32 vcs_ipehr;
164 u32 vcs_ipeir;
165 u32 vcs_instdone;
166 u32 vcs_seqno;
167 u32 instpm;
168 u32 instps;
169 u32 instdone1;
170 u32 seqno;
171 u64 bbaddr;
172 u64 fence[16];
173 struct timeval time;
174 struct drm_i915_error_object {
175 int page_count;
176 u32 gtt_offset;
177 u32 *pages[0];
178 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
179 struct drm_i915_error_buffer {
180 u32 size;
181 u32 name;
182 u32 seqno;
183 u32 gtt_offset;
184 u32 read_domains;
185 u32 write_domain;
186 s32 fence_reg:5;
187 s32 pinned:2;
188 u32 tiling:2;
189 u32 dirty:1;
190 u32 purgeable:1;
191 u32 ring:4;
192 u32 cache_level:2;
193 } *active_bo, *pinned_bo;
194 u32 active_bo_count, pinned_bo_count;
195 struct intel_overlay_error_state *overlay;
196 struct intel_display_error_state *display;
197};
198
199struct drm_i915_display_funcs {
200 void (*dpms)(struct drm_crtc *crtc, int mode);
201 bool (*fbc_enabled)(struct drm_device *dev);
202 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
203 void (*disable_fbc)(struct drm_device *dev);
204 int (*get_display_clock_speed)(struct drm_device *dev);
205 int (*get_fifo_size)(struct drm_device *dev, int plane);
206 void (*update_wm)(struct drm_device *dev);
207 int (*crtc_mode_set)(struct drm_crtc *crtc,
208 struct drm_display_mode *mode,
209 struct drm_display_mode *adjusted_mode,
210 int x, int y,
211 struct drm_framebuffer *old_fb);
212 void (*fdi_link_train)(struct drm_crtc *crtc);
213 void (*init_clock_gating)(struct drm_device *dev);
214 void (*init_pch_clock_gating)(struct drm_device *dev);
215 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
216 struct drm_framebuffer *fb,
217 struct drm_i915_gem_object *obj);
218 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
219 int x, int y);
220 /* clock updates for mode set */
221 /* cursor updates */
222 /* render clock increase/decrease */
223 /* display clock increase/decrease */
224 /* pll clock increase/decrease */
225};
226
227struct intel_device_info {
228 u8 gen;
229 u8 is_mobile : 1;
230 u8 is_i85x : 1;
231 u8 is_i915g : 1;
232 u8 is_i945gm : 1;
233 u8 is_g33 : 1;
234 u8 need_gfx_hws : 1;
235 u8 is_g4x : 1;
236 u8 is_pineview : 1;
237 u8 is_broadwater : 1;
238 u8 is_crestline : 1;
239 u8 is_ivybridge : 1;
240 u8 has_fbc : 1;
241 u8 has_pipe_cxsr : 1;
242 u8 has_hotplug : 1;
243 u8 cursor_needs_physical : 1;
244 u8 has_overlay : 1;
245 u8 overlay_needs_physical : 1;
246 u8 supports_tv : 1;
247 u8 has_bsd_ring : 1;
248 u8 has_blt_ring : 1;
249};
250
251enum no_fbc_reason {
252 FBC_NO_OUTPUT, /* no outputs enabled to compress */
253 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
254 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
255 FBC_MODE_TOO_LARGE, /* mode too large for compression */
256 FBC_BAD_PLANE, /* fbc not supported on plane */
257 FBC_NOT_TILED, /* buffer not tiled */
258 FBC_MULTIPLE_PIPES, /* more than one pipe active */
259 FBC_MODULE_PARAM,
260};
261
262enum intel_pch {
263 PCH_IBX, /* Ibexpeak PCH */
264 PCH_CPT, /* Cougarpoint PCH */
265};
266
267#define QUIRK_PIPEA_FORCE (1<<0)
268#define QUIRK_LVDS_SSC_DISABLE (1<<1)
269
270struct intel_fbdev;
271struct intel_fbc_work;
272
273typedef struct drm_i915_private {
274 struct drm_device *dev;
275
276 const struct intel_device_info *info;
277
278 int has_gem;
279 int relative_constants_mode;
280
281 void __iomem *regs;
282 u32 gt_fifo_count;
283
284 struct intel_gmbus {
285 struct i2c_adapter adapter;
286 struct i2c_adapter *force_bit;
287 u32 reg0;
288 } *gmbus;
289
290 struct pci_dev *bridge_dev;
291 struct intel_ring_buffer ring[I915_NUM_RINGS];
292 uint32_t next_seqno;
293
294 drm_dma_handle_t *status_page_dmah;
295 uint32_t counter;
296 drm_local_map_t hws_map;
297 struct drm_i915_gem_object *pwrctx;
298 struct drm_i915_gem_object *renderctx;
299
300 struct resource mch_res;
301
302 unsigned int cpp;
303 int back_offset;
304 int front_offset;
305 int current_page;
306 int page_flipping;
307
308 atomic_t irq_received;
309
310 /* protects the irq masks */
311 spinlock_t irq_lock;
312 /** Cached value of IMR to avoid reads in updating the bitfield */
313 u32 pipestat[2];
314 u32 irq_mask;
315 u32 gt_irq_mask;
316 u32 pch_irq_mask;
317
318 u32 hotplug_supported_mask;
319 struct work_struct hotplug_work;
320
321 int tex_lru_log_granularity;
322 int allow_batchbuffer;
323 struct mem_block *agp_heap;
324 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
325 int vblank_pipe;
326 int num_pipe;
327
328 /* For hangcheck timer */
329#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
330 struct timer_list hangcheck_timer;
331 int hangcheck_count;
332 uint32_t last_acthd;
333 uint32_t last_instdone;
334 uint32_t last_instdone1;
335
336 unsigned long cfb_size;
337 unsigned int cfb_fb;
338 enum plane cfb_plane;
339 int cfb_y;
340 struct intel_fbc_work *fbc_work;
341
342 struct intel_opregion opregion;
343
344 /* overlay */
345 struct intel_overlay *overlay;
346
347 /* LVDS info */
348 int backlight_level; /* restore backlight to this value */
349 bool backlight_enabled;
350 struct drm_display_mode *panel_fixed_mode;
351 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
352 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
353
354 /* Feature bits from the VBIOS */
355 unsigned int int_tv_support:1;
356 unsigned int lvds_dither:1;
357 unsigned int lvds_vbt:1;
358 unsigned int int_crt_support:1;
359 unsigned int lvds_use_ssc:1;
360 int lvds_ssc_freq;
361 struct {
362 int rate;
363 int lanes;
364 int preemphasis;
365 int vswing;
366
367 bool initialized;
368 bool support;
369 int bpp;
370 struct edp_power_seq pps;
371 } edp;
372 bool no_aux_handshake;
373
374 struct notifier_block lid_notifier;
375
376 int crt_ddc_pin;
377 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
378 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
379 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
380
381 unsigned int fsb_freq, mem_freq, is_ddr3;
382
383 spinlock_t error_lock;
384 struct drm_i915_error_state *first_error;
385 struct work_struct error_work;
386 struct completion error_completion;
387 struct workqueue_struct *wq;
388
389 /* Display functions */
390 struct drm_i915_display_funcs display;
391
392 /* PCH chipset type */
393 enum intel_pch pch_type;
394
395 unsigned long quirks;
396
397 /* Register state */
398 bool modeset_on_lid;
399 u8 saveLBB;
400 u32 saveDSPACNTR;
401 u32 saveDSPBCNTR;
402 u32 saveDSPARB;
403 u32 saveHWS;
404 u32 savePIPEACONF;
405 u32 savePIPEBCONF;
406 u32 savePIPEASRC;
407 u32 savePIPEBSRC;
408 u32 saveFPA0;
409 u32 saveFPA1;
410 u32 saveDPLL_A;
411 u32 saveDPLL_A_MD;
412 u32 saveHTOTAL_A;
413 u32 saveHBLANK_A;
414 u32 saveHSYNC_A;
415 u32 saveVTOTAL_A;
416 u32 saveVBLANK_A;
417 u32 saveVSYNC_A;
418 u32 saveBCLRPAT_A;
419 u32 saveTRANSACONF;
420 u32 saveTRANS_HTOTAL_A;
421 u32 saveTRANS_HBLANK_A;
422 u32 saveTRANS_HSYNC_A;
423 u32 saveTRANS_VTOTAL_A;
424 u32 saveTRANS_VBLANK_A;
425 u32 saveTRANS_VSYNC_A;
426 u32 savePIPEASTAT;
427 u32 saveDSPASTRIDE;
428 u32 saveDSPASIZE;
429 u32 saveDSPAPOS;
430 u32 saveDSPAADDR;
431 u32 saveDSPASURF;
432 u32 saveDSPATILEOFF;
433 u32 savePFIT_PGM_RATIOS;
434 u32 saveBLC_HIST_CTL;
435 u32 saveBLC_PWM_CTL;
436 u32 saveBLC_PWM_CTL2;
437 u32 saveBLC_CPU_PWM_CTL;
438 u32 saveBLC_CPU_PWM_CTL2;
439 u32 saveFPB0;
440 u32 saveFPB1;
441 u32 saveDPLL_B;
442 u32 saveDPLL_B_MD;
443 u32 saveHTOTAL_B;
444 u32 saveHBLANK_B;
445 u32 saveHSYNC_B;
446 u32 saveVTOTAL_B;
447 u32 saveVBLANK_B;
448 u32 saveVSYNC_B;
449 u32 saveBCLRPAT_B;
450 u32 saveTRANSBCONF;
451 u32 saveTRANS_HTOTAL_B;
452 u32 saveTRANS_HBLANK_B;
453 u32 saveTRANS_HSYNC_B;
454 u32 saveTRANS_VTOTAL_B;
455 u32 saveTRANS_VBLANK_B;
456 u32 saveTRANS_VSYNC_B;
457 u32 savePIPEBSTAT;
458 u32 saveDSPBSTRIDE;
459 u32 saveDSPBSIZE;
460 u32 saveDSPBPOS;
461 u32 saveDSPBADDR;
462 u32 saveDSPBSURF;
463 u32 saveDSPBTILEOFF;
464 u32 saveVGA0;
465 u32 saveVGA1;
466 u32 saveVGA_PD;
467 u32 saveVGACNTRL;
468 u32 saveADPA;
469 u32 saveLVDS;
470 u32 savePP_ON_DELAYS;
471 u32 savePP_OFF_DELAYS;
472 u32 saveDVOA;
473 u32 saveDVOB;
474 u32 saveDVOC;
475 u32 savePP_ON;
476 u32 savePP_OFF;
477 u32 savePP_CONTROL;
478 u32 savePP_DIVISOR;
479 u32 savePFIT_CONTROL;
480 u32 save_palette_a[256];
481 u32 save_palette_b[256];
482 u32 saveDPFC_CB_BASE;
483 u32 saveFBC_CFB_BASE;
484 u32 saveFBC_LL_BASE;
485 u32 saveFBC_CONTROL;
486 u32 saveFBC_CONTROL2;
487 u32 saveIER;
488 u32 saveIIR;
489 u32 saveIMR;
490 u32 saveDEIER;
491 u32 saveDEIMR;
492 u32 saveGTIER;
493 u32 saveGTIMR;
494 u32 saveFDI_RXA_IMR;
495 u32 saveFDI_RXB_IMR;
496 u32 saveCACHE_MODE_0;
497 u32 saveMI_ARB_STATE;
498 u32 saveSWF0[16];
499 u32 saveSWF1[16];
500 u32 saveSWF2[3];
501 u8 saveMSR;
502 u8 saveSR[8];
503 u8 saveGR[25];
504 u8 saveAR_INDEX;
505 u8 saveAR[21];
506 u8 saveDACMASK;
507 u8 saveCR[37];
508 uint64_t saveFENCE[16];
509 u32 saveCURACNTR;
510 u32 saveCURAPOS;
511 u32 saveCURABASE;
512 u32 saveCURBCNTR;
513 u32 saveCURBPOS;
514 u32 saveCURBBASE;
515 u32 saveCURSIZE;
516 u32 saveDP_B;
517 u32 saveDP_C;
518 u32 saveDP_D;
519 u32 savePIPEA_GMCH_DATA_M;
520 u32 savePIPEB_GMCH_DATA_M;
521 u32 savePIPEA_GMCH_DATA_N;
522 u32 savePIPEB_GMCH_DATA_N;
523 u32 savePIPEA_DP_LINK_M;
524 u32 savePIPEB_DP_LINK_M;
525 u32 savePIPEA_DP_LINK_N;
526 u32 savePIPEB_DP_LINK_N;
527 u32 saveFDI_RXA_CTL;
528 u32 saveFDI_TXA_CTL;
529 u32 saveFDI_RXB_CTL;
530 u32 saveFDI_TXB_CTL;
531 u32 savePFA_CTL_1;
532 u32 savePFB_CTL_1;
533 u32 savePFA_WIN_SZ;
534 u32 savePFB_WIN_SZ;
535 u32 savePFA_WIN_POS;
536 u32 savePFB_WIN_POS;
537 u32 savePCH_DREF_CONTROL;
538 u32 saveDISP_ARB_CTL;
539 u32 savePIPEA_DATA_M1;
540 u32 savePIPEA_DATA_N1;
541 u32 savePIPEA_LINK_M1;
542 u32 savePIPEA_LINK_N1;
543 u32 savePIPEB_DATA_M1;
544 u32 savePIPEB_DATA_N1;
545 u32 savePIPEB_LINK_M1;
546 u32 savePIPEB_LINK_N1;
547 u32 saveMCHBAR_RENDER_STANDBY;
548 u32 savePCH_PORT_HOTPLUG;
549
550 struct {
551 /** Bridge to intel-gtt-ko */
552 const struct intel_gtt *gtt;
553 /** Memory allocator for GTT stolen memory */
554 struct drm_mm stolen;
555 /** Memory allocator for GTT */
556 struct drm_mm gtt_space;
557 /** List of all objects in gtt_space. Used to restore gtt
558 * mappings on resume */
559 struct list_head gtt_list;
560
561 /** Usable portion of the GTT for GEM */
562 unsigned long gtt_start;
563 unsigned long gtt_mappable_end;
564 unsigned long gtt_end;
565
566 struct io_mapping *gtt_mapping;
567 int gtt_mtrr;
568
569 struct shrinker inactive_shrinker;
570
571 /**
572 * List of objects currently involved in rendering.
573 *
574 * Includes buffers having the contents of their GPU caches
575 * flushed, not necessarily primitives. last_rendering_seqno
576 * represents when the rendering involved will be completed.
577 *
578 * A reference is held on the buffer while on this list.
579 */
580 struct list_head active_list;
581
582 /**
583 * List of objects which are not in the ringbuffer but which
584 * still have a write_domain which needs to be flushed before
585 * unbinding.
586 *
587 * last_rendering_seqno is 0 while an object is in this list.
588 *
589 * A reference is held on the buffer while on this list.
590 */
591 struct list_head flushing_list;
592
593 /**
594 * LRU list of objects which are not in the ringbuffer and
595 * are ready to unbind, but are still in the GTT.
596 *
597 * last_rendering_seqno is 0 while an object is in this list.
598 *
599 * A reference is not held on the buffer while on this list,
600 * as merely being GTT-bound shouldn't prevent its being
601 * freed, and we'll pull it off the list in the free path.
602 */
603 struct list_head inactive_list;
604
605 /**
606 * LRU list of objects which are not in the ringbuffer but
607 * are still pinned in the GTT.
608 */
609 struct list_head pinned_list;
610
611 /** LRU list of objects with fence regs on them. */
612 struct list_head fence_list;
613
614 /**
615 * List of objects currently pending being freed.
616 *
617 * These objects are no longer in use, but due to a signal
618 * we were prevented from freeing them at the appointed time.
619 */
620 struct list_head deferred_free_list;
621
622 /**
623 * We leave the user IRQ off as much as possible,
624 * but this means that requests will finish and never
625 * be retired once the system goes idle. Set a timer to
626 * fire periodically while the ring is running. When it
627 * fires, go retire requests.
628 */
629 struct delayed_work retire_work;
630
631 /**
632 * Are we in a non-interruptible section of code like
633 * modesetting?
634 */
635 bool interruptible;
636
637 /**
638 * Flag if the X Server, and thus DRM, is not currently in
639 * control of the device.
640 *
641 * This is set between LeaveVT and EnterVT. It needs to be
642 * replaced with a semaphore. It also needs to be
643 * transitioned away from for kernel modesetting.
644 */
645 int suspended;
646
647 /**
648 * Flag if the hardware appears to be wedged.
649 *
650 * This is set when attempts to idle the device timeout.
651 * It prevents command submission from occurring and makes
652 * every pending request fail
653 */
654 atomic_t wedged;
655
656 /** Bit 6 swizzling required for X tiling */
657 uint32_t bit_6_swizzle_x;
658 /** Bit 6 swizzling required for Y tiling */
659 uint32_t bit_6_swizzle_y;
660
661 /* storage for physical objects */
662 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
663
664 /* accounting, useful for userland debugging */
665 size_t gtt_total;
666 size_t mappable_gtt_total;
667 size_t object_memory;
668 u32 object_count;
669 } mm;
670 struct sdvo_device_mapping sdvo_mappings[2];
671 /* indicate whether the LVDS_BORDER should be enabled or not */
672 unsigned int lvds_border_bits;
673 /* Panel fitter placement and size for Ironlake+ */
674 u32 pch_pf_pos, pch_pf_size;
675 int panel_t3, panel_t12;
676
677 struct drm_crtc *plane_to_crtc_mapping[2];
678 struct drm_crtc *pipe_to_crtc_mapping[2];
679 wait_queue_head_t pending_flip_queue;
680 bool flip_pending_is_done;
681
682 /* Reclocking support */
683 bool render_reclock_avail;
684 bool lvds_downclock_avail;
685 /* indicates the reduced downclock for LVDS*/
686 int lvds_downclock;
687 struct work_struct idle_work;
688 struct timer_list idle_timer;
689 bool busy;
690 u16 orig_clock;
691 int child_dev_num;
692 struct child_device_config *child_dev;
693 struct drm_connector *int_lvds_connector;
694 struct drm_connector *int_edp_connector;
695
696 bool mchbar_need_disable;
697
698 struct work_struct rps_work;
699 spinlock_t rps_lock;
700 u32 pm_iir;
701
702 u8 cur_delay;
703 u8 min_delay;
704 u8 max_delay;
705 u8 fmax;
706 u8 fstart;
707
708 u64 last_count1;
709 unsigned long last_time1;
710 u64 last_count2;
711 struct timespec last_time2;
712 unsigned long gfx_power;
713 int c_m;
714 int r_t;
715 u8 corr;
716 spinlock_t *mchdev_lock;
717
718 enum no_fbc_reason no_fbc_reason;
719
720 struct drm_mm_node *compressed_fb;
721 struct drm_mm_node *compressed_llb;
722
723 unsigned long last_gpu_reset;
724
725 /* list of fbdev register on this device */
726 struct intel_fbdev *fbdev;
727
728 struct backlight_device *backlight;
729
730 struct drm_property *broadcast_rgb_property;
731 struct drm_property *force_audio_property;
732
733 atomic_t forcewake_count;
734} drm_i915_private_t;
735
736enum i915_cache_level {
737 I915_CACHE_NONE,
738 I915_CACHE_LLC,
739 I915_CACHE_LLC_MLC, /* gen6+ */
740};
741
742struct drm_i915_gem_object {
743 struct drm_gem_object base;
744
745 /** Current space allocated to this object in the GTT, if any. */
746 struct drm_mm_node *gtt_space;
747 struct list_head gtt_list;
748
749 /** This object's place on the active/flushing/inactive lists */
750 struct list_head ring_list;
751 struct list_head mm_list;
752 /** This object's place on GPU write list */
753 struct list_head gpu_write_list;
754 /** This object's place in the batchbuffer or on the eviction list */
755 struct list_head exec_list;
756
757 /**
758 * This is set if the object is on the active or flushing lists
759 * (has pending rendering), and is not set if it's on inactive (ready
760 * to be unbound).
761 */
762 unsigned int active : 1;
763
764 /**
765 * This is set if the object has been written to since last bound
766 * to the GTT
767 */
768 unsigned int dirty : 1;
769
770 /**
771 * This is set if the object has been written to since the last
772 * GPU flush.
773 */
774 unsigned int pending_gpu_write : 1;
775
776 /**
777 * Fence register bits (if any) for this object. Will be set
778 * as needed when mapped into the GTT.
779 * Protected by dev->struct_mutex.
780 *
781 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
782 */
783 signed int fence_reg : 5;
784
785 /**
786 * Advice: are the backing pages purgeable?
787 */
788 unsigned int madv : 2;
789
790 /**
791 * Current tiling mode for the object.
792 */
793 unsigned int tiling_mode : 2;
794 unsigned int tiling_changed : 1;
795
796 /** How many users have pinned this object in GTT space. The following
797 * users can each hold at most one reference: pwrite/pread, pin_ioctl
798 * (via user_pin_count), execbuffer (objects are not allowed multiple
799 * times for the same batchbuffer), and the framebuffer code. When
800 * switching/pageflipping, the framebuffer code has at most two buffers
801 * pinned per crtc.
802 *
803 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
804 * bits with absolutely no headroom. So use 4 bits. */
805 unsigned int pin_count : 4;
806#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
807
808 /**
809 * Is the object at the current location in the gtt mappable and
810 * fenceable? Used to avoid costly recalculations.
811 */
812 unsigned int map_and_fenceable : 1;
813
814 /**
815 * Whether the current gtt mapping needs to be mappable (and isn't just
816 * mappable by accident). Track pin and fault separate for a more
817 * accurate mappable working set.
818 */
819 unsigned int fault_mappable : 1;
820 unsigned int pin_mappable : 1;
821
822 /*
823 * Is the GPU currently using a fence to access this buffer,
824 */
825 unsigned int pending_fenced_gpu_access:1;
826 unsigned int fenced_gpu_access:1;
827
828 unsigned int cache_level:2;
829
830 struct page **pages;
831
832 /**
833 * DMAR support
834 */
835 struct scatterlist *sg_list;
836 int num_sg;
837
838 /**
839 * Used for performing relocations during execbuffer insertion.
840 */
841 struct hlist_node exec_node;
842 unsigned long exec_handle;
843 struct drm_i915_gem_exec_object2 *exec_entry;
844
845 /**
846 * Current offset of the object in GTT space.
847 *
848 * This is the same as gtt_space->start
849 */
850 uint32_t gtt_offset;
851
852 /** Breadcrumb of last rendering to the buffer. */
853 uint32_t last_rendering_seqno;
854 struct intel_ring_buffer *ring;
855
856 /** Breadcrumb of last fenced GPU access to the buffer. */
857 uint32_t last_fenced_seqno;
858 struct intel_ring_buffer *last_fenced_ring;
859
860 /** Current tiling stride for the object, if it's tiled. */
861 uint32_t stride;
862
863 /** Record of address bit 17 of each page at last unbind. */
864 unsigned long *bit_17;
865
866
867 /**
868 * If present, while GEM_DOMAIN_CPU is in the read domain this array
869 * flags which individual pages are valid.
870 */
871 uint8_t *page_cpu_valid;
872
873 /** User space pin count and filp owning the pin */
874 uint32_t user_pin_count;
875 struct drm_file *pin_filp;
876
877 /** for phy allocated objects */
878 struct drm_i915_gem_phys_object *phys_obj;
879
880 /**
881 * Number of crtcs where this object is currently the fb, but
882 * will be page flipped away on the next vblank. When it
883 * reaches 0, dev_priv->pending_flip_queue will be woken up.
884 */
885 atomic_t pending_flip;
886};
887
888#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
889
890/**
891 * Request queue structure.
892 *
893 * The request queue allows us to note sequence numbers that have been emitted
894 * and may be associated with active buffers to be retired.
895 *
896 * By keeping this list, we can avoid having to do questionable
897 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
898 * an emission time with seqnos for tracking how far ahead of the GPU we are.
899 */
900struct drm_i915_gem_request {
901 /** On Which ring this request was generated */
902 struct intel_ring_buffer *ring;
903
904 /** GEM sequence number associated with this request. */
905 uint32_t seqno;
906
907 /** Time at which this request was emitted, in jiffies. */
908 unsigned long emitted_jiffies;
909
910 /** global list entry for this request */
911 struct list_head list;
912
913 struct drm_i915_file_private *file_priv;
914 /** file_priv list entry for this request */
915 struct list_head client_list;
916};
917
918struct drm_i915_file_private {
919 struct {
920 struct spinlock lock;
921 struct list_head request_list;
922 } mm;
923};
924
925#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
926
927#define IS_I830(dev) ((dev)->pci_device == 0x3577)
928#define IS_845G(dev) ((dev)->pci_device == 0x2562)
929#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
930#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
931#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
932#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
933#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
934#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
935#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
936#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
937#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
938#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
939#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
940#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
941#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
942#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
943#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
944#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
945#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
946#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
947
948/*
949 * The genX designation typically refers to the render engine, so render
950 * capability related checks should use IS_GEN, while display and other checks
951 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
952 * chips, etc.).
953 */
954#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
955#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
956#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
957#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
958#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
959#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
960
961#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
962#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
963#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
964
965#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
966#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
967
968/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
969 * rows, which changed the alignment requirements and fence programming.
970 */
971#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
972 IS_I915GM(dev)))
973#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
974#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
975#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
976#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
977#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
978#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
979/* dsparb controlled by hw only */
980#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
981
982#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
983#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
984#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
985
986#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
987#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
988
989#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
990#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
991#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
992
993#include "i915_trace.h"
994
995extern struct drm_ioctl_desc i915_ioctls[];
996extern int i915_max_ioctl;
997extern unsigned int i915_fbpercrtc __always_unused;
998extern int i915_panel_ignore_lid __read_mostly;
999extern unsigned int i915_powersave __read_mostly;
1000extern unsigned int i915_semaphores __read_mostly;
1001extern unsigned int i915_lvds_downclock __read_mostly;
1002extern unsigned int i915_panel_use_ssc __read_mostly;
1003extern int i915_vbt_sdvo_panel_type __read_mostly;
1004extern unsigned int i915_enable_rc6 __read_mostly;
1005extern unsigned int i915_enable_fbc __read_mostly;
1006extern bool i915_enable_hangcheck __read_mostly;
1007
1008extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1009extern int i915_resume(struct drm_device *dev);
1010extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1011extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1012
1013 /* i915_dma.c */
1014extern void i915_kernel_lost_context(struct drm_device * dev);
1015extern int i915_driver_load(struct drm_device *, unsigned long flags);
1016extern int i915_driver_unload(struct drm_device *);
1017extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1018extern void i915_driver_lastclose(struct drm_device * dev);
1019extern void i915_driver_preclose(struct drm_device *dev,
1020 struct drm_file *file_priv);
1021extern void i915_driver_postclose(struct drm_device *dev,
1022 struct drm_file *file_priv);
1023extern int i915_driver_device_is_agp(struct drm_device * dev);
1024extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1025 unsigned long arg);
1026extern int i915_emit_box(struct drm_device *dev,
1027 struct drm_clip_rect *box,
1028 int DR1, int DR4);
1029extern int i915_reset(struct drm_device *dev, u8 flags);
1030extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1031extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1032extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1033extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1034
1035
1036/* i915_irq.c */
1037void i915_hangcheck_elapsed(unsigned long data);
1038void i915_handle_error(struct drm_device *dev, bool wedged);
1039extern int i915_irq_emit(struct drm_device *dev, void *data,
1040 struct drm_file *file_priv);
1041extern int i915_irq_wait(struct drm_device *dev, void *data,
1042 struct drm_file *file_priv);
1043
1044extern void intel_irq_init(struct drm_device *dev);
1045
1046extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1048extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv);
1050extern int i915_vblank_swap(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv);
1052
1053void
1054i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1055
1056void
1057i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1058
1059void intel_enable_asle (struct drm_device *dev);
1060
1061#ifdef CONFIG_DEBUG_FS
1062extern void i915_destroy_error_state(struct drm_device *dev);
1063#else
1064#define i915_destroy_error_state(x)
1065#endif
1066
1067
1068/* i915_mem.c */
1069extern int i915_mem_alloc(struct drm_device *dev, void *data,
1070 struct drm_file *file_priv);
1071extern int i915_mem_free(struct drm_device *dev, void *data,
1072 struct drm_file *file_priv);
1073extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1074 struct drm_file *file_priv);
1075extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv);
1077extern void i915_mem_takedown(struct mem_block **heap);
1078extern void i915_mem_release(struct drm_device * dev,
1079 struct drm_file *file_priv, struct mem_block *heap);
1080/* i915_gem.c */
1081int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1082 struct drm_file *file_priv);
1083int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1084 struct drm_file *file_priv);
1085int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1086 struct drm_file *file_priv);
1087int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1088 struct drm_file *file_priv);
1089int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv);
1091int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv);
1093int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv);
1095int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1096 struct drm_file *file_priv);
1097int i915_gem_execbuffer(struct drm_device *dev, void *data,
1098 struct drm_file *file_priv);
1099int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1100 struct drm_file *file_priv);
1101int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1102 struct drm_file *file_priv);
1103int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1104 struct drm_file *file_priv);
1105int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1106 struct drm_file *file_priv);
1107int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1108 struct drm_file *file_priv);
1109int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv);
1111int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1112 struct drm_file *file_priv);
1113int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1114 struct drm_file *file_priv);
1115int i915_gem_set_tiling(struct drm_device *dev, void *data,
1116 struct drm_file *file_priv);
1117int i915_gem_get_tiling(struct drm_device *dev, void *data,
1118 struct drm_file *file_priv);
1119int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv);
1121void i915_gem_load(struct drm_device *dev);
1122int i915_gem_init_object(struct drm_gem_object *obj);
1123int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1124 uint32_t invalidate_domains,
1125 uint32_t flush_domains);
1126struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1127 size_t size);
1128void i915_gem_free_object(struct drm_gem_object *obj);
1129int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1130 uint32_t alignment,
1131 bool map_and_fenceable);
1132void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1133int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1134void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1135void i915_gem_lastclose(struct drm_device *dev);
1136
1137int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1138int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1139void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1140 struct intel_ring_buffer *ring,
1141 u32 seqno);
1142
1143int i915_gem_dumb_create(struct drm_file *file_priv,
1144 struct drm_device *dev,
1145 struct drm_mode_create_dumb *args);
1146int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1147 uint32_t handle, uint64_t *offset);
1148int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1149 uint32_t handle);
1150/**
1151 * Returns true if seq1 is later than seq2.
1152 */
1153static inline bool
1154i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1155{
1156 return (int32_t)(seq1 - seq2) >= 0;
1157}
1158
1159static inline u32
1160i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1161{
1162 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1163 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1164}
1165
1166int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1167 struct intel_ring_buffer *pipelined);
1168int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1169
1170void i915_gem_retire_requests(struct drm_device *dev);
1171void i915_gem_reset(struct drm_device *dev);
1172void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1173int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1174 uint32_t read_domains,
1175 uint32_t write_domain);
1176int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1177int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1178void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1179void i915_gem_do_init(struct drm_device *dev,
1180 unsigned long start,
1181 unsigned long mappable_end,
1182 unsigned long end);
1183int __must_check i915_gpu_idle(struct drm_device *dev);
1184int __must_check i915_gem_idle(struct drm_device *dev);
1185int __must_check i915_add_request(struct intel_ring_buffer *ring,
1186 struct drm_file *file,
1187 struct drm_i915_gem_request *request);
1188int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1189 uint32_t seqno);
1190int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1191int __must_check
1192i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1193 bool write);
1194int __must_check
1195i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1196 u32 alignment,
1197 struct intel_ring_buffer *pipelined);
1198int i915_gem_attach_phys_object(struct drm_device *dev,
1199 struct drm_i915_gem_object *obj,
1200 int id,
1201 int align);
1202void i915_gem_detach_phys_object(struct drm_device *dev,
1203 struct drm_i915_gem_object *obj);
1204void i915_gem_free_all_phys_object(struct drm_device *dev);
1205void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1206
1207uint32_t
1208i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1209 uint32_t size,
1210 int tiling_mode);
1211
1212int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1213 enum i915_cache_level cache_level);
1214
1215/* i915_gem_gtt.c */
1216void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1217int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1218void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1219 enum i915_cache_level cache_level);
1220void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1221
1222/* i915_gem_evict.c */
1223int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1224 unsigned alignment, bool mappable);
1225int __must_check i915_gem_evict_everything(struct drm_device *dev,
1226 bool purgeable_only);
1227int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1228 bool purgeable_only);
1229
1230/* i915_gem_tiling.c */
1231void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1232void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1233void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1234
1235/* i915_gem_debug.c */
1236void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1237 const char *where, uint32_t mark);
1238#if WATCH_LISTS
1239int i915_verify_lists(struct drm_device *dev);
1240#else
1241#define i915_verify_lists(dev) 0
1242#endif
1243void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1244 int handle);
1245void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1246 const char *where, uint32_t mark);
1247
1248/* i915_debugfs.c */
1249int i915_debugfs_init(struct drm_minor *minor);
1250void i915_debugfs_cleanup(struct drm_minor *minor);
1251
1252/* i915_suspend.c */
1253extern int i915_save_state(struct drm_device *dev);
1254extern int i915_restore_state(struct drm_device *dev);
1255
1256/* i915_suspend.c */
1257extern int i915_save_state(struct drm_device *dev);
1258extern int i915_restore_state(struct drm_device *dev);
1259
1260/* intel_i2c.c */
1261extern int intel_setup_gmbus(struct drm_device *dev);
1262extern void intel_teardown_gmbus(struct drm_device *dev);
1263extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1264extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1265extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1266{
1267 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1268}
1269extern void intel_i2c_reset(struct drm_device *dev);
1270
1271/* intel_opregion.c */
1272extern int intel_opregion_setup(struct drm_device *dev);
1273#ifdef CONFIG_ACPI
1274extern void intel_opregion_init(struct drm_device *dev);
1275extern void intel_opregion_fini(struct drm_device *dev);
1276extern void intel_opregion_asle_intr(struct drm_device *dev);
1277extern void intel_opregion_gse_intr(struct drm_device *dev);
1278extern void intel_opregion_enable_asle(struct drm_device *dev);
1279#else
1280static inline void intel_opregion_init(struct drm_device *dev) { return; }
1281static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1282static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1283static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1284static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1285#endif
1286
1287/* intel_acpi.c */
1288#ifdef CONFIG_ACPI
1289extern void intel_register_dsm_handler(void);
1290extern void intel_unregister_dsm_handler(void);
1291#else
1292static inline void intel_register_dsm_handler(void) { return; }
1293static inline void intel_unregister_dsm_handler(void) { return; }
1294#endif /* CONFIG_ACPI */
1295
1296/* modesetting */
1297extern void intel_modeset_init(struct drm_device *dev);
1298extern void intel_modeset_gem_init(struct drm_device *dev);
1299extern void intel_modeset_cleanup(struct drm_device *dev);
1300extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1301extern bool intel_fbc_enabled(struct drm_device *dev);
1302extern void intel_disable_fbc(struct drm_device *dev);
1303extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1304extern void ironlake_enable_rc6(struct drm_device *dev);
1305extern void gen6_set_rps(struct drm_device *dev, u8 val);
1306extern void intel_detect_pch (struct drm_device *dev);
1307extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1308
1309/* overlay */
1310#ifdef CONFIG_DEBUG_FS
1311extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1312extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1313
1314extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1315extern void intel_display_print_error_state(struct seq_file *m,
1316 struct drm_device *dev,
1317 struct intel_display_error_state *error);
1318#endif
1319
1320#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1321
1322#define BEGIN_LP_RING(n) \
1323 intel_ring_begin(LP_RING(dev_priv), (n))
1324
1325#define OUT_RING(x) \
1326 intel_ring_emit(LP_RING(dev_priv), x)
1327
1328#define ADVANCE_LP_RING() \
1329 intel_ring_advance(LP_RING(dev_priv))
1330
1331/**
1332 * Lock test for when it's just for synchronization of ring access.
1333 *
1334 * In that case, we don't need to do it when GEM is initialized as nobody else
1335 * has access to the ring.
1336 */
1337#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1338 if (LP_RING(dev->dev_private)->obj == NULL) \
1339 LOCK_TEST_WITH_RETURN(dev, file); \
1340} while (0)
1341
1342/* On SNB platform, before reading ring registers forcewake bit
1343 * must be set to prevent GT core from power down and stale values being
1344 * returned.
1345 */
1346void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1347void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1348void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1349
1350/* We give fast paths for the really cool registers */
1351#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1352 (((dev_priv)->info->gen >= 6) && \
1353 ((reg) < 0x40000) && \
1354 ((reg) != FORCEWAKE))
1355
1356#define __i915_read(x, y) \
1357static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1358 u##x val = 0; \
1359 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1360 gen6_gt_force_wake_get(dev_priv); \
1361 val = read##y(dev_priv->regs + reg); \
1362 gen6_gt_force_wake_put(dev_priv); \
1363 } else { \
1364 val = read##y(dev_priv->regs + reg); \
1365 } \
1366 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1367 return val; \
1368}
1369
1370__i915_read(8, b)
1371__i915_read(16, w)
1372__i915_read(32, l)
1373__i915_read(64, q)
1374#undef __i915_read
1375
1376#define __i915_write(x, y) \
1377static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1378 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1379 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1380 __gen6_gt_wait_for_fifo(dev_priv); \
1381 } \
1382 write##y(val, dev_priv->regs + reg); \
1383}
1384__i915_write(8, b)
1385__i915_write(16, w)
1386__i915_write(32, l)
1387__i915_write(64, q)
1388#undef __i915_write
1389
1390#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1391#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1392
1393#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1394#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1395#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1396#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1397
1398#define I915_READ(reg) i915_read32(dev_priv, (reg))
1399#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1400#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1401#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1402
1403#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1404#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1405
1406#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1407#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1408
1409
1410#endif
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <linux/backlight.h>
40#include <linux/hash.h>
41#include <linux/intel-iommu.h>
42#include <linux/kref.h>
43#include <linux/mm_types.h>
44#include <linux/perf_event.h>
45#include <linux/pm_qos.h>
46#include <linux/dma-resv.h>
47#include <linux/shmem_fs.h>
48#include <linux/stackdepot.h>
49#include <linux/xarray.h>
50
51#include <drm/intel-gtt.h>
52#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
53#include <drm/drm_gem.h>
54#include <drm/drm_auth.h>
55#include <drm/drm_cache.h>
56#include <drm/drm_util.h>
57#include <drm/drm_dsc.h>
58#include <drm/drm_atomic.h>
59#include <drm/drm_connector.h>
60#include <drm/i915_mei_hdcp_interface.h>
61
62#include "i915_params.h"
63#include "i915_reg.h"
64#include "i915_utils.h"
65
66#include "display/intel_bios.h"
67#include "display/intel_display.h"
68#include "display/intel_display_power.h"
69#include "display/intel_dpll_mgr.h"
70#include "display/intel_dsb.h"
71#include "display/intel_frontbuffer.h"
72#include "display/intel_global_state.h"
73#include "display/intel_gmbus.h"
74#include "display/intel_opregion.h"
75
76#include "gem/i915_gem_context_types.h"
77#include "gem/i915_gem_shrinker.h"
78#include "gem/i915_gem_stolen.h"
79
80#include "gt/intel_lrc.h"
81#include "gt/intel_engine.h"
82#include "gt/intel_gt_types.h"
83#include "gt/intel_workarounds.h"
84#include "gt/uc/intel_uc.h"
85
86#include "intel_device_info.h"
87#include "intel_pch.h"
88#include "intel_runtime_pm.h"
89#include "intel_memory_region.h"
90#include "intel_uncore.h"
91#include "intel_wakeref.h"
92#include "intel_wopcm.h"
93
94#include "i915_gem.h"
95#include "i915_gem_gtt.h"
96#include "i915_gpu_error.h"
97#include "i915_perf_types.h"
98#include "i915_request.h"
99#include "i915_scheduler.h"
100#include "gt/intel_timeline.h"
101#include "i915_vma.h"
102#include "i915_irq.h"
103
104#include "intel_region_lmem.h"
105
106/* General customization:
107 */
108
109#define DRIVER_NAME "i915"
110#define DRIVER_DESC "Intel Graphics"
111#define DRIVER_DATE "20200715"
112#define DRIVER_TIMESTAMP 1594811881
113
114struct drm_i915_gem_object;
115
116/*
117 * The code assumes that the hpd_pins below have consecutive values and
118 * starting with HPD_PORT_A, the HPD pin associated with any port can be
119 * retrieved by adding the corresponding port (or phy) enum value to
120 * HPD_PORT_A in most cases. For example:
121 * HPD_PORT_C = HPD_PORT_A + PHY_C - PHY_A
122 */
123enum hpd_pin {
124 HPD_NONE = 0,
125 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
126 HPD_CRT,
127 HPD_SDVO_B,
128 HPD_SDVO_C,
129 HPD_PORT_A,
130 HPD_PORT_B,
131 HPD_PORT_C,
132 HPD_PORT_D,
133 HPD_PORT_E,
134 HPD_PORT_F,
135 HPD_PORT_G,
136 HPD_PORT_H,
137 HPD_PORT_I,
138
139 HPD_NUM_PINS
140};
141
142#define for_each_hpd_pin(__pin) \
143 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
144
145/* Threshold == 5 for long IRQs, 50 for short */
146#define HPD_STORM_DEFAULT_THRESHOLD 50
147
148struct i915_hotplug {
149 struct delayed_work hotplug_work;
150
151 const u32 *hpd, *pch_hpd;
152
153 struct {
154 unsigned long last_jiffies;
155 int count;
156 enum {
157 HPD_ENABLED = 0,
158 HPD_DISABLED = 1,
159 HPD_MARK_DISABLED = 2
160 } state;
161 } stats[HPD_NUM_PINS];
162 u32 event_bits;
163 u32 retry_bits;
164 struct delayed_work reenable_work;
165
166 u32 long_port_mask;
167 u32 short_port_mask;
168 struct work_struct dig_port_work;
169
170 struct work_struct poll_init_work;
171 bool poll_enabled;
172
173 unsigned int hpd_storm_threshold;
174 /* Whether or not to count short HPD IRQs in HPD storms */
175 u8 hpd_short_storm_enabled;
176
177 /*
178 * if we get a HPD irq from DP and a HPD irq from non-DP
179 * the non-DP HPD could block the workqueue on a mode config
180 * mutex getting, that userspace may have taken. However
181 * userspace is waiting on the DP workqueue to run which is
182 * blocked behind the non-DP one.
183 */
184 struct workqueue_struct *dp_wq;
185};
186
187#define I915_GEM_GPU_DOMAINS \
188 (I915_GEM_DOMAIN_RENDER | \
189 I915_GEM_DOMAIN_SAMPLER | \
190 I915_GEM_DOMAIN_COMMAND | \
191 I915_GEM_DOMAIN_INSTRUCTION | \
192 I915_GEM_DOMAIN_VERTEX)
193
194struct drm_i915_private;
195struct i915_mm_struct;
196struct i915_mmu_object;
197
198struct drm_i915_file_private {
199 struct drm_i915_private *dev_priv;
200
201 union {
202 struct drm_file *file;
203 struct rcu_head rcu;
204 };
205
206 struct {
207 spinlock_t lock;
208 struct list_head request_list;
209 } mm;
210
211 struct xarray context_xa;
212 struct xarray vm_xa;
213
214 unsigned int bsd_engine;
215
216/*
217 * Every context ban increments per client ban score. Also
218 * hangs in short succession increments ban score. If ban threshold
219 * is reached, client is considered banned and submitting more work
220 * will fail. This is a stop gap measure to limit the badly behaving
221 * clients access to gpu. Note that unbannable contexts never increment
222 * the client ban score.
223 */
224#define I915_CLIENT_SCORE_HANG_FAST 1
225#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
226#define I915_CLIENT_SCORE_CONTEXT_BAN 3
227#define I915_CLIENT_SCORE_BANNED 9
228 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
229 atomic_t ban_score;
230 unsigned long hang_timestamp;
231};
232
233/* Interface history:
234 *
235 * 1.1: Original.
236 * 1.2: Add Power Management
237 * 1.3: Add vblank support
238 * 1.4: Fix cmdbuffer path, add heap destroy
239 * 1.5: Add vblank pipe configuration
240 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
241 * - Support vertical blank on secondary display pipe
242 */
243#define DRIVER_MAJOR 1
244#define DRIVER_MINOR 6
245#define DRIVER_PATCHLEVEL 0
246
247struct intel_overlay;
248struct intel_overlay_error_state;
249
250struct sdvo_device_mapping {
251 u8 initialized;
252 u8 dvo_port;
253 u8 slave_addr;
254 u8 dvo_wiring;
255 u8 i2c_pin;
256 u8 ddc_pin;
257};
258
259struct intel_connector;
260struct intel_encoder;
261struct intel_atomic_state;
262struct intel_cdclk_config;
263struct intel_cdclk_state;
264struct intel_cdclk_vals;
265struct intel_initial_plane_config;
266struct intel_crtc;
267struct intel_limit;
268struct dpll;
269
270struct drm_i915_display_funcs {
271 void (*get_cdclk)(struct drm_i915_private *dev_priv,
272 struct intel_cdclk_config *cdclk_config);
273 void (*set_cdclk)(struct drm_i915_private *dev_priv,
274 const struct intel_cdclk_config *cdclk_config,
275 enum pipe pipe);
276 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
277 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
278 enum i9xx_plane_id i9xx_plane);
279 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
280 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
281 void (*initial_watermarks)(struct intel_atomic_state *state,
282 struct intel_crtc *crtc);
283 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
284 struct intel_crtc *crtc);
285 void (*optimize_watermarks)(struct intel_atomic_state *state,
286 struct intel_crtc *crtc);
287 int (*compute_global_watermarks)(struct intel_atomic_state *state);
288 void (*update_wm)(struct intel_crtc *crtc);
289 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
290 u8 (*calc_voltage_level)(int cdclk);
291 /* Returns the active state of the crtc, and if the crtc is active,
292 * fills out the pipe-config with the hw state. */
293 bool (*get_pipe_config)(struct intel_crtc *,
294 struct intel_crtc_state *);
295 void (*get_initial_plane_config)(struct intel_crtc *,
296 struct intel_initial_plane_config *);
297 int (*crtc_compute_clock)(struct intel_crtc *crtc,
298 struct intel_crtc_state *crtc_state);
299 void (*crtc_enable)(struct intel_atomic_state *state,
300 struct intel_crtc *crtc);
301 void (*crtc_disable)(struct intel_atomic_state *state,
302 struct intel_crtc *crtc);
303 void (*commit_modeset_enables)(struct intel_atomic_state *state);
304 void (*commit_modeset_disables)(struct intel_atomic_state *state);
305 void (*audio_codec_enable)(struct intel_encoder *encoder,
306 const struct intel_crtc_state *crtc_state,
307 const struct drm_connector_state *conn_state);
308 void (*audio_codec_disable)(struct intel_encoder *encoder,
309 const struct intel_crtc_state *old_crtc_state,
310 const struct drm_connector_state *old_conn_state);
311 void (*fdi_link_train)(struct intel_crtc *crtc,
312 const struct intel_crtc_state *crtc_state);
313 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
314 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
315 /* clock updates for mode set */
316 /* cursor updates */
317 /* render clock increase/decrease */
318 /* display clock increase/decrease */
319 /* pll clock increase/decrease */
320
321 int (*color_check)(struct intel_crtc_state *crtc_state);
322 /*
323 * Program double buffered color management registers during
324 * vblank evasion. The registers should then latch during the
325 * next vblank start, alongside any other double buffered registers
326 * involved with the same commit.
327 */
328 void (*color_commit)(const struct intel_crtc_state *crtc_state);
329 /*
330 * Load LUTs (and other single buffered color management
331 * registers). Will (hopefully) be called during the vblank
332 * following the latching of any double buffered registers
333 * involved with the same commit.
334 */
335 void (*load_luts)(const struct intel_crtc_state *crtc_state);
336 void (*read_luts)(struct intel_crtc_state *crtc_state);
337};
338
339struct intel_csr {
340 struct work_struct work;
341 const char *fw_path;
342 u32 required_version;
343 u32 max_fw_size; /* bytes */
344 u32 *dmc_payload;
345 u32 dmc_fw_size; /* dwords */
346 u32 version;
347 u32 mmio_count;
348 i915_reg_t mmioaddr[20];
349 u32 mmiodata[20];
350 u32 dc_state;
351 u32 target_dc_state;
352 u32 allowed_dc_mask;
353 intel_wakeref_t wakeref;
354};
355
356enum i915_cache_level {
357 I915_CACHE_NONE = 0,
358 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
359 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
360 caches, eg sampler/render caches, and the
361 large Last-Level-Cache. LLC is coherent with
362 the CPU, but L3 is only visible to the GPU. */
363 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
364};
365
366#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
367
368struct intel_fbc {
369 /* This is always the inner lock when overlapping with struct_mutex and
370 * it's the outer lock when overlapping with stolen_lock. */
371 struct mutex lock;
372 unsigned threshold;
373 unsigned int possible_framebuffer_bits;
374 unsigned int busy_bits;
375 struct intel_crtc *crtc;
376
377 struct drm_mm_node compressed_fb;
378 struct drm_mm_node *compressed_llb;
379
380 bool false_color;
381
382 bool active;
383 bool activated;
384 bool flip_pending;
385
386 bool underrun_detected;
387 struct work_struct underrun_work;
388
389 /*
390 * Due to the atomic rules we can't access some structures without the
391 * appropriate locking, so we cache information here in order to avoid
392 * these problems.
393 */
394 struct intel_fbc_state_cache {
395 struct {
396 unsigned int mode_flags;
397 u32 hsw_bdw_pixel_rate;
398 } crtc;
399
400 struct {
401 unsigned int rotation;
402 int src_w;
403 int src_h;
404 bool visible;
405 /*
406 * Display surface base address adjustement for
407 * pageflips. Note that on gen4+ this only adjusts up
408 * to a tile, offsets within a tile are handled in
409 * the hw itself (with the TILEOFF register).
410 */
411 int adjusted_x;
412 int adjusted_y;
413
414 u16 pixel_blend_mode;
415 } plane;
416
417 struct {
418 const struct drm_format_info *format;
419 unsigned int stride;
420 u64 modifier;
421 } fb;
422
423 unsigned int fence_y_offset;
424 u16 gen9_wa_cfb_stride;
425 u16 interval;
426 s8 fence_id;
427 } state_cache;
428
429 /*
430 * This structure contains everything that's relevant to program the
431 * hardware registers. When we want to figure out if we need to disable
432 * and re-enable FBC for a new configuration we just check if there's
433 * something different in the struct. The genx_fbc_activate functions
434 * are supposed to read from it in order to program the registers.
435 */
436 struct intel_fbc_reg_params {
437 struct {
438 enum pipe pipe;
439 enum i9xx_plane_id i9xx_plane;
440 } crtc;
441
442 struct {
443 const struct drm_format_info *format;
444 unsigned int stride;
445 u64 modifier;
446 } fb;
447
448 int cfb_size;
449 unsigned int fence_y_offset;
450 u16 gen9_wa_cfb_stride;
451 u16 interval;
452 s8 fence_id;
453 bool plane_visible;
454 } params;
455
456 const char *no_fbc_reason;
457};
458
459/*
460 * HIGH_RR is the highest eDP panel refresh rate read from EDID
461 * LOW_RR is the lowest eDP panel refresh rate found from EDID
462 * parsing for same resolution.
463 */
464enum drrs_refresh_rate_type {
465 DRRS_HIGH_RR,
466 DRRS_LOW_RR,
467 DRRS_MAX_RR, /* RR count */
468};
469
470enum drrs_support_type {
471 DRRS_NOT_SUPPORTED = 0,
472 STATIC_DRRS_SUPPORT = 1,
473 SEAMLESS_DRRS_SUPPORT = 2
474};
475
476struct intel_dp;
477struct i915_drrs {
478 struct mutex mutex;
479 struct delayed_work work;
480 struct intel_dp *dp;
481 unsigned busy_frontbuffer_bits;
482 enum drrs_refresh_rate_type refresh_rate_type;
483 enum drrs_support_type type;
484};
485
486struct i915_psr {
487 struct mutex lock;
488
489#define I915_PSR_DEBUG_MODE_MASK 0x0f
490#define I915_PSR_DEBUG_DEFAULT 0x00
491#define I915_PSR_DEBUG_DISABLE 0x01
492#define I915_PSR_DEBUG_ENABLE 0x02
493#define I915_PSR_DEBUG_FORCE_PSR1 0x03
494#define I915_PSR_DEBUG_IRQ 0x10
495
496 u32 debug;
497 bool sink_support;
498 bool enabled;
499 struct intel_dp *dp;
500 enum pipe pipe;
501 enum transcoder transcoder;
502 bool active;
503 struct work_struct work;
504 unsigned busy_frontbuffer_bits;
505 bool sink_psr2_support;
506 bool link_standby;
507 bool colorimetry_support;
508 bool psr2_enabled;
509 u8 sink_sync_latency;
510 ktime_t last_entry_attempt;
511 ktime_t last_exit;
512 bool sink_not_reliable;
513 bool irq_aux_error;
514 u16 su_x_granularity;
515 bool dc3co_enabled;
516 u32 dc3co_exit_delay;
517 struct delayed_work dc3co_work;
518 bool force_mode_changed;
519 struct drm_dp_vsc_sdp vsc;
520};
521
522#define QUIRK_LVDS_SSC_DISABLE (1<<1)
523#define QUIRK_INVERT_BRIGHTNESS (1<<2)
524#define QUIRK_BACKLIGHT_PRESENT (1<<3)
525#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
526#define QUIRK_INCREASE_T12_DELAY (1<<6)
527#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
528
529struct intel_fbdev;
530struct intel_fbc_work;
531
532struct intel_gmbus {
533 struct i2c_adapter adapter;
534#define GMBUS_FORCE_BIT_RETRY (1U << 31)
535 u32 force_bit;
536 u32 reg0;
537 i915_reg_t gpio_reg;
538 struct i2c_algo_bit_data bit_algo;
539 struct drm_i915_private *dev_priv;
540};
541
542struct i915_suspend_saved_registers {
543 u32 saveDSPARB;
544 u32 saveFBC_CONTROL;
545 u32 saveCACHE_MODE_0;
546 u32 saveMI_ARB_STATE;
547 u32 saveSWF0[16];
548 u32 saveSWF1[16];
549 u32 saveSWF3[3];
550 u32 savePCH_PORT_HOTPLUG;
551 u16 saveGCDGMBUS;
552};
553
554struct vlv_s0ix_state;
555
556#define MAX_L3_SLICES 2
557struct intel_l3_parity {
558 u32 *remap_info[MAX_L3_SLICES];
559 struct work_struct error_work;
560 int which_slice;
561};
562
563struct i915_gem_mm {
564 /** Memory allocator for GTT stolen memory */
565 struct drm_mm stolen;
566 /** Protects the usage of the GTT stolen memory allocator. This is
567 * always the inner lock when overlapping with struct_mutex. */
568 struct mutex stolen_lock;
569
570 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
571 spinlock_t obj_lock;
572
573 /**
574 * List of objects which are purgeable.
575 */
576 struct list_head purge_list;
577
578 /**
579 * List of objects which have allocated pages and are shrinkable.
580 */
581 struct list_head shrink_list;
582
583 /**
584 * List of objects which are pending destruction.
585 */
586 struct llist_head free_list;
587 struct work_struct free_work;
588 /**
589 * Count of objects pending destructions. Used to skip needlessly
590 * waiting on an RCU barrier if no objects are waiting to be freed.
591 */
592 atomic_t free_count;
593
594 /**
595 * Small stash of WC pages
596 */
597 struct pagestash wc_stash;
598
599 /**
600 * tmpfs instance used for shmem backed objects
601 */
602 struct vfsmount *gemfs;
603
604 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
605
606 struct notifier_block oom_notifier;
607 struct notifier_block vmap_notifier;
608 struct shrinker shrinker;
609
610 /**
611 * Workqueue to fault in userptr pages, flushed by the execbuf
612 * when required but otherwise left to userspace to try again
613 * on EAGAIN.
614 */
615 struct workqueue_struct *userptr_wq;
616
617 /* shrinker accounting, also useful for userland debugging */
618 u64 shrink_memory;
619 u32 shrink_count;
620};
621
622#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
623
624unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
625 u64 context);
626
627static inline unsigned long
628i915_fence_timeout(const struct drm_i915_private *i915)
629{
630 return i915_fence_context_timeout(i915, U64_MAX);
631}
632
633/* Amount of SAGV/QGV points, BSpec precisely defines this */
634#define I915_NUM_QGV_POINTS 8
635
636struct ddi_vbt_port_info {
637 /* Non-NULL if port present. */
638 const struct child_device_config *child;
639
640 int max_tmds_clock;
641
642 /* This is an index in the HDMI/DVI DDI buffer translation table. */
643 u8 hdmi_level_shift;
644 u8 hdmi_level_shift_set:1;
645
646 u8 supports_dvi:1;
647 u8 supports_hdmi:1;
648 u8 supports_dp:1;
649 u8 supports_edp:1;
650 u8 supports_typec_usb:1;
651 u8 supports_tbt:1;
652
653 u8 alternate_aux_channel;
654 u8 alternate_ddc_pin;
655
656 u8 dp_boost_level;
657 u8 hdmi_boost_level;
658 int dp_max_link_rate; /* 0 for not limited by VBT */
659};
660
661enum psr_lines_to_wait {
662 PSR_0_LINES_TO_WAIT = 0,
663 PSR_1_LINE_TO_WAIT,
664 PSR_4_LINES_TO_WAIT,
665 PSR_8_LINES_TO_WAIT
666};
667
668struct intel_vbt_data {
669 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
670 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
671
672 /* Feature bits */
673 unsigned int int_tv_support:1;
674 unsigned int lvds_dither:1;
675 unsigned int int_crt_support:1;
676 unsigned int lvds_use_ssc:1;
677 unsigned int int_lvds_support:1;
678 unsigned int display_clock_mode:1;
679 unsigned int fdi_rx_polarity_inverted:1;
680 unsigned int panel_type:4;
681 int lvds_ssc_freq;
682 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
683 enum drm_panel_orientation orientation;
684
685 enum drrs_support_type drrs_type;
686
687 struct {
688 int rate;
689 int lanes;
690 int preemphasis;
691 int vswing;
692 bool low_vswing;
693 bool initialized;
694 int bpp;
695 struct edp_power_seq pps;
696 bool hobl;
697 } edp;
698
699 struct {
700 bool enable;
701 bool full_link;
702 bool require_aux_wakeup;
703 int idle_frames;
704 enum psr_lines_to_wait lines_to_wait;
705 int tp1_wakeup_time_us;
706 int tp2_tp3_wakeup_time_us;
707 int psr2_tp2_tp3_wakeup_time_us;
708 } psr;
709
710 struct {
711 u16 pwm_freq_hz;
712 bool present;
713 bool active_low_pwm;
714 u8 min_brightness; /* min_brightness/255 of max */
715 u8 controller; /* brightness controller number */
716 enum intel_backlight_type type;
717 } backlight;
718
719 /* MIPI DSI */
720 struct {
721 u16 panel_id;
722 struct mipi_config *config;
723 struct mipi_pps_data *pps;
724 u16 bl_ports;
725 u16 cabc_ports;
726 u8 seq_version;
727 u32 size;
728 u8 *data;
729 const u8 *sequence[MIPI_SEQ_MAX];
730 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
731 enum drm_panel_orientation orientation;
732 } dsi;
733
734 int crt_ddc_pin;
735
736 struct list_head display_devices;
737
738 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
739 struct sdvo_device_mapping sdvo_mappings[2];
740};
741
742enum intel_ddb_partitioning {
743 INTEL_DDB_PART_1_2,
744 INTEL_DDB_PART_5_6, /* IVB+ */
745};
746
747struct ilk_wm_values {
748 u32 wm_pipe[3];
749 u32 wm_lp[3];
750 u32 wm_lp_spr[3];
751 bool enable_fbc_wm;
752 enum intel_ddb_partitioning partitioning;
753};
754
755struct g4x_pipe_wm {
756 u16 plane[I915_MAX_PLANES];
757 u16 fbc;
758};
759
760struct g4x_sr_wm {
761 u16 plane;
762 u16 cursor;
763 u16 fbc;
764};
765
766struct vlv_wm_ddl_values {
767 u8 plane[I915_MAX_PLANES];
768};
769
770struct vlv_wm_values {
771 struct g4x_pipe_wm pipe[3];
772 struct g4x_sr_wm sr;
773 struct vlv_wm_ddl_values ddl[3];
774 u8 level;
775 bool cxsr;
776};
777
778struct g4x_wm_values {
779 struct g4x_pipe_wm pipe[2];
780 struct g4x_sr_wm sr;
781 struct g4x_sr_wm hpll;
782 bool cxsr;
783 bool hpll_en;
784 bool fbc_en;
785};
786
787struct skl_ddb_entry {
788 u16 start, end; /* in number of blocks, 'end' is exclusive */
789};
790
791static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
792{
793 return entry->end - entry->start;
794}
795
796static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
797 const struct skl_ddb_entry *e2)
798{
799 if (e1->start == e2->start && e1->end == e2->end)
800 return true;
801
802 return false;
803}
804
805struct i915_frontbuffer_tracking {
806 spinlock_t lock;
807
808 /*
809 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
810 * scheduled flips.
811 */
812 unsigned busy_bits;
813 unsigned flip_bits;
814};
815
816struct i915_virtual_gpu {
817 struct mutex lock; /* serialises sending of g2v_notify command pkts */
818 bool active;
819 u32 caps;
820};
821
822struct intel_cdclk_config {
823 unsigned int cdclk, vco, ref, bypass;
824 u8 voltage_level;
825};
826
827struct i915_selftest_stash {
828 atomic_t counter;
829};
830
831struct drm_i915_private {
832 struct drm_device drm;
833
834 /* FIXME: Device release actions should all be moved to drmm_ */
835 bool do_release;
836
837 /* i915 device parameters */
838 struct i915_params params;
839
840 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
841 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
842 struct intel_driver_caps caps;
843
844 /**
845 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
846 * end of stolen which we can optionally use to create GEM objects
847 * backed by stolen memory. Note that stolen_usable_size tells us
848 * exactly how much of this we are actually allowed to use, given that
849 * some portion of it is in fact reserved for use by hardware functions.
850 */
851 struct resource dsm;
852 /**
853 * Reseved portion of Data Stolen Memory
854 */
855 struct resource dsm_reserved;
856
857 /*
858 * Stolen memory is segmented in hardware with different portions
859 * offlimits to certain functions.
860 *
861 * The drm_mm is initialised to the total accessible range, as found
862 * from the PCI config. On Broadwell+, this is further restricted to
863 * avoid the first page! The upper end of stolen memory is reserved for
864 * hardware functions and similarly removed from the accessible range.
865 */
866 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
867
868 struct intel_uncore uncore;
869 struct intel_uncore_mmio_debug mmio_debug;
870
871 struct i915_virtual_gpu vgpu;
872
873 struct intel_gvt *gvt;
874
875 struct intel_wopcm wopcm;
876
877 struct intel_csr csr;
878
879 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
880
881 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
882 * controller on different i2c buses. */
883 struct mutex gmbus_mutex;
884
885 /**
886 * Base address of where the gmbus and gpio blocks are located (either
887 * on PCH or on SoC for platforms without PCH).
888 */
889 u32 gpio_mmio_base;
890
891 u32 hsw_psr_mmio_adjust;
892
893 /* MMIO base address for MIPI regs */
894 u32 mipi_mmio_base;
895
896 u32 pps_mmio_base;
897
898 wait_queue_head_t gmbus_wait_queue;
899
900 struct pci_dev *bridge_dev;
901
902 struct rb_root uabi_engines;
903
904 struct resource mch_res;
905
906 /* protects the irq masks */
907 spinlock_t irq_lock;
908
909 bool display_irqs_enabled;
910
911 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
912 struct pm_qos_request pm_qos;
913
914 /* Sideband mailbox protection */
915 struct mutex sb_lock;
916 struct pm_qos_request sb_qos;
917
918 /** Cached value of IMR to avoid reads in updating the bitfield */
919 union {
920 u32 irq_mask;
921 u32 de_irq_mask[I915_MAX_PIPES];
922 };
923 u32 pipestat_irq_mask[I915_MAX_PIPES];
924
925 struct i915_hotplug hotplug;
926 struct intel_fbc fbc;
927 struct i915_drrs drrs;
928 struct intel_opregion opregion;
929 struct intel_vbt_data vbt;
930
931 bool preserve_bios_swizzle;
932
933 /* overlay */
934 struct intel_overlay *overlay;
935
936 /* backlight registers and fields in struct intel_panel */
937 struct mutex backlight_lock;
938
939 /* protects panel power sequencer state */
940 struct mutex pps_mutex;
941
942 unsigned int fsb_freq, mem_freq, is_ddr3;
943 unsigned int skl_preferred_vco_freq;
944 unsigned int max_cdclk_freq;
945
946 unsigned int max_dotclk_freq;
947 unsigned int hpll_freq;
948 unsigned int fdi_pll_freq;
949 unsigned int czclk_freq;
950
951 struct {
952 /* The current hardware cdclk configuration */
953 struct intel_cdclk_config hw;
954
955 /* cdclk, divider, and ratio table from bspec */
956 const struct intel_cdclk_vals *table;
957
958 struct intel_global_obj obj;
959 } cdclk;
960
961 struct {
962 /* The current hardware dbuf configuration */
963 u8 enabled_slices;
964
965 struct intel_global_obj obj;
966 } dbuf;
967
968 /**
969 * wq - Driver workqueue for GEM.
970 *
971 * NOTE: Work items scheduled here are not allowed to grab any modeset
972 * locks, for otherwise the flushing done in the pageflip code will
973 * result in deadlocks.
974 */
975 struct workqueue_struct *wq;
976
977 /* ordered wq for modesets */
978 struct workqueue_struct *modeset_wq;
979 /* unbound hipri wq for page flips/plane updates */
980 struct workqueue_struct *flip_wq;
981
982 /* Display functions */
983 struct drm_i915_display_funcs display;
984
985 /* PCH chipset type */
986 enum intel_pch pch_type;
987 unsigned short pch_id;
988
989 unsigned long quirks;
990
991 struct drm_atomic_state *modeset_restore_state;
992 struct drm_modeset_acquire_ctx reset_ctx;
993
994 struct i915_ggtt ggtt; /* VM representing the global address space */
995
996 struct i915_gem_mm mm;
997 DECLARE_HASHTABLE(mm_structs, 7);
998 spinlock_t mm_lock;
999
1000 /* Kernel Modesetting */
1001
1002 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1003 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1004
1005 /**
1006 * dpll and cdclk state is protected by connection_mutex
1007 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
1008 * Must be global rather than per dpll, because on some platforms plls
1009 * share registers.
1010 */
1011 struct {
1012 struct mutex lock;
1013
1014 int num_shared_dpll;
1015 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1016 const struct intel_dpll_mgr *mgr;
1017
1018 struct {
1019 int nssc;
1020 int ssc;
1021 } ref_clks;
1022 } dpll;
1023
1024 struct list_head global_obj_list;
1025
1026 /*
1027 * For reading active_pipes holding any crtc lock is
1028 * sufficient, for writing must hold all of them.
1029 */
1030 u8 active_pipes;
1031
1032 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1033
1034 struct i915_wa_list gt_wa_list;
1035
1036 struct i915_frontbuffer_tracking fb_tracking;
1037
1038 struct intel_atomic_helper {
1039 struct llist_head free_list;
1040 struct work_struct free_work;
1041 } atomic_helper;
1042
1043 bool mchbar_need_disable;
1044
1045 struct intel_l3_parity l3_parity;
1046
1047 /*
1048 * edram size in MB.
1049 * Cannot be determined by PCIID. You must always read a register.
1050 */
1051 u32 edram_size_mb;
1052
1053 struct i915_power_domains power_domains;
1054
1055 struct i915_psr psr;
1056
1057 struct i915_gpu_error gpu_error;
1058
1059 struct drm_i915_gem_object *vlv_pctx;
1060
1061 /* list of fbdev register on this device */
1062 struct intel_fbdev *fbdev;
1063 struct work_struct fbdev_suspend_work;
1064
1065 struct drm_property *broadcast_rgb_property;
1066 struct drm_property *force_audio_property;
1067
1068 /* hda/i915 audio component */
1069 struct i915_audio_component *audio_component;
1070 bool audio_component_registered;
1071 /**
1072 * av_mutex - mutex for audio/video sync
1073 *
1074 */
1075 struct mutex av_mutex;
1076 int audio_power_refcount;
1077 u32 audio_freq_cntrl;
1078
1079 u32 fdi_rx_config;
1080
1081 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1082 u32 chv_phy_control;
1083 /*
1084 * Shadows for CHV DPLL_MD regs to keep the state
1085 * checker somewhat working in the presence hardware
1086 * crappiness (can't read out DPLL_MD for pipes B & C).
1087 */
1088 u32 chv_dpll_md[I915_MAX_PIPES];
1089 u32 bxt_phy_grc;
1090
1091 u32 suspend_count;
1092 bool power_domains_suspended;
1093 struct i915_suspend_saved_registers regfile;
1094 struct vlv_s0ix_state *vlv_s0ix_state;
1095
1096 enum {
1097 I915_SAGV_UNKNOWN = 0,
1098 I915_SAGV_DISABLED,
1099 I915_SAGV_ENABLED,
1100 I915_SAGV_NOT_CONTROLLED
1101 } sagv_status;
1102
1103 u32 sagv_block_time_us;
1104
1105 struct {
1106 /*
1107 * Raw watermark latency values:
1108 * in 0.1us units for WM0,
1109 * in 0.5us units for WM1+.
1110 */
1111 /* primary */
1112 u16 pri_latency[5];
1113 /* sprite */
1114 u16 spr_latency[5];
1115 /* cursor */
1116 u16 cur_latency[5];
1117 /*
1118 * Raw watermark memory latency values
1119 * for SKL for all 8 levels
1120 * in 1us units.
1121 */
1122 u16 skl_latency[8];
1123
1124 /* current hardware state */
1125 union {
1126 struct ilk_wm_values hw;
1127 struct vlv_wm_values vlv;
1128 struct g4x_wm_values g4x;
1129 };
1130
1131 u8 max_level;
1132
1133 /*
1134 * Should be held around atomic WM register writing; also
1135 * protects * intel_crtc->wm.active and
1136 * crtc_state->wm.need_postvbl_update.
1137 */
1138 struct mutex wm_mutex;
1139
1140 /*
1141 * Set during HW readout of watermarks/DDB. Some platforms
1142 * need to know when we're still using BIOS-provided values
1143 * (which we don't fully trust).
1144 *
1145 * FIXME get rid of this.
1146 */
1147 bool distrust_bios_wm;
1148 } wm;
1149
1150 struct dram_info {
1151 bool valid;
1152 bool is_16gb_dimm;
1153 u8 num_channels;
1154 u8 ranks;
1155 u32 bandwidth_kbps;
1156 bool symmetric_memory;
1157 enum intel_dram_type {
1158 INTEL_DRAM_UNKNOWN,
1159 INTEL_DRAM_DDR3,
1160 INTEL_DRAM_DDR4,
1161 INTEL_DRAM_LPDDR3,
1162 INTEL_DRAM_LPDDR4
1163 } type;
1164 } dram_info;
1165
1166 struct intel_bw_info {
1167 /* for each QGV point */
1168 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1169 u8 num_qgv_points;
1170 u8 num_planes;
1171 } max_bw[6];
1172
1173 struct intel_global_obj bw_obj;
1174
1175 struct intel_runtime_pm runtime_pm;
1176
1177 struct i915_perf perf;
1178
1179 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1180 struct intel_gt gt;
1181
1182 struct {
1183 struct i915_gem_contexts {
1184 spinlock_t lock; /* locks list */
1185 struct list_head list;
1186
1187 struct llist_head free_list;
1188 struct work_struct free_work;
1189 } contexts;
1190
1191 /*
1192 * We replace the local file with a global mappings as the
1193 * backing storage for the mmap is on the device and not
1194 * on the struct file, and we do not want to prolong the
1195 * lifetime of the local fd. To minimise the number of
1196 * anonymous inodes we create, we use a global singleton to
1197 * share the global mapping.
1198 */
1199 struct file *mmap_singleton;
1200 } gem;
1201
1202 u8 pch_ssc_use;
1203
1204 /* For i915gm/i945gm vblank irq workaround */
1205 u8 vblank_enabled;
1206
1207 /* perform PHY state sanity checks? */
1208 bool chv_phy_assert[2];
1209
1210 bool ipc_enabled;
1211
1212 /* Used to save the pipe-to-encoder mapping for audio */
1213 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1214
1215 /* necessary resource sharing with HDMI LPE audio driver. */
1216 struct {
1217 struct platform_device *platdev;
1218 int irq;
1219 } lpe_audio;
1220
1221 struct i915_pmu pmu;
1222
1223 struct i915_hdcp_comp_master *hdcp_master;
1224 bool hdcp_comp_added;
1225
1226 /* Mutex to protect the above hdcp component related values. */
1227 struct mutex hdcp_comp_mutex;
1228
1229 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1230
1231 /*
1232 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1233 * will be rejected. Instead look for a better place.
1234 */
1235};
1236
1237static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1238{
1239 return container_of(dev, struct drm_i915_private, drm);
1240}
1241
1242static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1243{
1244 return dev_get_drvdata(kdev);
1245}
1246
1247static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1248{
1249 return pci_get_drvdata(pdev);
1250}
1251
1252/* Simple iterator over all initialised engines */
1253#define for_each_engine(engine__, dev_priv__, id__) \
1254 for ((id__) = 0; \
1255 (id__) < I915_NUM_ENGINES; \
1256 (id__)++) \
1257 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1258
1259/* Iterator over subset of engines selected by mask */
1260#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1261 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1262 (tmp__) ? \
1263 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1264 0;)
1265
1266#define rb_to_uabi_engine(rb) \
1267 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1268
1269#define for_each_uabi_engine(engine__, i915__) \
1270 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1271 (engine__); \
1272 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1273
1274#define for_each_uabi_class_engine(engine__, class__, i915__) \
1275 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1276 (engine__) && (engine__)->uabi_class == (class__); \
1277 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1278
1279#define I915_GTT_OFFSET_NONE ((u32)-1)
1280
1281/*
1282 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1283 * considered to be the frontbuffer for the given plane interface-wise. This
1284 * doesn't mean that the hw necessarily already scans it out, but that any
1285 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1286 *
1287 * We have one bit per pipe and per scanout plane type.
1288 */
1289#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1290#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1291 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1292 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1293 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1294})
1295#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1296 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1297#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1298 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1299 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1300
1301#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1302#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1303#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1304
1305#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1306#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1307
1308#define REVID_FOREVER 0xff
1309#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1310
1311#define INTEL_GEN_MASK(s, e) ( \
1312 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1313 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1314 GENMASK((e) - 1, (s) - 1))
1315
1316/* Returns true if Gen is in inclusive range [Start, End] */
1317#define IS_GEN_RANGE(dev_priv, s, e) \
1318 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1319
1320#define IS_GEN(dev_priv, n) \
1321 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1322 INTEL_INFO(dev_priv)->gen == (n))
1323
1324#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1325
1326/*
1327 * Return true if revision is in range [since,until] inclusive.
1328 *
1329 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1330 */
1331#define IS_REVID(p, since, until) \
1332 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1333
1334static __always_inline unsigned int
1335__platform_mask_index(const struct intel_runtime_info *info,
1336 enum intel_platform p)
1337{
1338 const unsigned int pbits =
1339 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1340
1341 /* Expand the platform_mask array if this fails. */
1342 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1343 pbits * ARRAY_SIZE(info->platform_mask));
1344
1345 return p / pbits;
1346}
1347
1348static __always_inline unsigned int
1349__platform_mask_bit(const struct intel_runtime_info *info,
1350 enum intel_platform p)
1351{
1352 const unsigned int pbits =
1353 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1354
1355 return p % pbits + INTEL_SUBPLATFORM_BITS;
1356}
1357
1358static inline u32
1359intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1360{
1361 const unsigned int pi = __platform_mask_index(info, p);
1362
1363 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1364}
1365
1366static __always_inline bool
1367IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1368{
1369 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1370 const unsigned int pi = __platform_mask_index(info, p);
1371 const unsigned int pb = __platform_mask_bit(info, p);
1372
1373 BUILD_BUG_ON(!__builtin_constant_p(p));
1374
1375 return info->platform_mask[pi] & BIT(pb);
1376}
1377
1378static __always_inline bool
1379IS_SUBPLATFORM(const struct drm_i915_private *i915,
1380 enum intel_platform p, unsigned int s)
1381{
1382 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1383 const unsigned int pi = __platform_mask_index(info, p);
1384 const unsigned int pb = __platform_mask_bit(info, p);
1385 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1386 const u32 mask = info->platform_mask[pi];
1387
1388 BUILD_BUG_ON(!__builtin_constant_p(p));
1389 BUILD_BUG_ON(!__builtin_constant_p(s));
1390 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1391
1392 /* Shift and test on the MSB position so sign flag can be used. */
1393 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1394}
1395
1396#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1397#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1398
1399#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1400#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1401#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1402#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1403#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1404#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1405#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1406#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1407#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1408#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1409#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1410#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1411#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1412#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1413#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1414#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1415#define IS_IRONLAKE_M(dev_priv) \
1416 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1417#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1418#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1419 INTEL_INFO(dev_priv)->gt == 1)
1420#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1421#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1422#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1423#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1424#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1425#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1426#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1427#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1428#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1429#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1430#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1431#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1432#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1433#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1434#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1435#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
1436#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1437 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1438#define IS_BDW_ULT(dev_priv) \
1439 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1440#define IS_BDW_ULX(dev_priv) \
1441 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1442#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1443 INTEL_INFO(dev_priv)->gt == 3)
1444#define IS_HSW_ULT(dev_priv) \
1445 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1446#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1447 INTEL_INFO(dev_priv)->gt == 3)
1448#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1449 INTEL_INFO(dev_priv)->gt == 1)
1450/* ULX machines are also considered ULT. */
1451#define IS_HSW_ULX(dev_priv) \
1452 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1453#define IS_SKL_ULT(dev_priv) \
1454 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1455#define IS_SKL_ULX(dev_priv) \
1456 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1457#define IS_KBL_ULT(dev_priv) \
1458 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1459#define IS_KBL_ULX(dev_priv) \
1460 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1461#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1462 INTEL_INFO(dev_priv)->gt == 2)
1463#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1464 INTEL_INFO(dev_priv)->gt == 3)
1465#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1466 INTEL_INFO(dev_priv)->gt == 4)
1467#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1468 INTEL_INFO(dev_priv)->gt == 2)
1469#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1470 INTEL_INFO(dev_priv)->gt == 3)
1471#define IS_CFL_ULT(dev_priv) \
1472 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1473#define IS_CFL_ULX(dev_priv) \
1474 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1475#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1476 INTEL_INFO(dev_priv)->gt == 2)
1477#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1478 INTEL_INFO(dev_priv)->gt == 3)
1479
1480#define IS_CML_ULT(dev_priv) \
1481 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1482#define IS_CML_ULX(dev_priv) \
1483 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1484#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
1485 INTEL_INFO(dev_priv)->gt == 2)
1486
1487#define IS_CNL_WITH_PORT_F(dev_priv) \
1488 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1489#define IS_ICL_WITH_PORT_F(dev_priv) \
1490 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1491
1492#define SKL_REVID_A0 0x0
1493#define SKL_REVID_B0 0x1
1494#define SKL_REVID_C0 0x2
1495#define SKL_REVID_D0 0x3
1496#define SKL_REVID_E0 0x4
1497#define SKL_REVID_F0 0x5
1498#define SKL_REVID_G0 0x6
1499#define SKL_REVID_H0 0x7
1500
1501#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1502
1503#define BXT_REVID_A0 0x0
1504#define BXT_REVID_A1 0x1
1505#define BXT_REVID_B0 0x3
1506#define BXT_REVID_B_LAST 0x8
1507#define BXT_REVID_C0 0x9
1508
1509#define IS_BXT_REVID(dev_priv, since, until) \
1510 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1511
1512#define KBL_REVID_A0 0x0
1513#define KBL_REVID_B0 0x1
1514#define KBL_REVID_C0 0x2
1515#define KBL_REVID_D0 0x3
1516#define KBL_REVID_E0 0x4
1517
1518#define IS_KBL_REVID(dev_priv, since, until) \
1519 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1520
1521#define GLK_REVID_A0 0x0
1522#define GLK_REVID_A1 0x1
1523#define GLK_REVID_A2 0x2
1524#define GLK_REVID_B0 0x3
1525
1526#define IS_GLK_REVID(dev_priv, since, until) \
1527 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1528
1529#define CNL_REVID_A0 0x0
1530#define CNL_REVID_B0 0x1
1531#define CNL_REVID_C0 0x2
1532
1533#define IS_CNL_REVID(p, since, until) \
1534 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1535
1536#define ICL_REVID_A0 0x0
1537#define ICL_REVID_A2 0x1
1538#define ICL_REVID_B0 0x3
1539#define ICL_REVID_B2 0x4
1540#define ICL_REVID_C0 0x5
1541
1542#define IS_ICL_REVID(p, since, until) \
1543 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1544
1545#define EHL_REVID_A0 0x0
1546
1547#define IS_EHL_REVID(p, since, until) \
1548 (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
1549
1550#define TGL_REVID_A0 0x0
1551#define TGL_REVID_B0 0x1
1552#define TGL_REVID_C0 0x2
1553
1554#define IS_TGL_REVID(p, since, until) \
1555 (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1556
1557#define RKL_REVID_A0 0x0
1558#define RKL_REVID_B0 0x1
1559#define RKL_REVID_C0 0x4
1560
1561#define IS_RKL_REVID(p, since, until) \
1562 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1563
1564#define DG1_REVID_A0 0x0
1565#define DG1_REVID_B0 0x1
1566
1567#define IS_DG1_REVID(p, since, until) \
1568 (IS_DG1(p) && IS_REVID(p, since, until))
1569
1570#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1571#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1572#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1573
1574#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1575#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1576
1577#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
1578 unsigned int first__ = (first); \
1579 unsigned int count__ = (count); \
1580 ((gt)->info.engine_mask & \
1581 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1582})
1583#define VDBOX_MASK(gt) \
1584 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1585#define VEBOX_MASK(gt) \
1586 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1587
1588/*
1589 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1590 * All later gens can run the final buffer from the ppgtt
1591 */
1592#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1593
1594#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1595#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1596#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1597#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1598#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
1599 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1600
1601#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1602
1603#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1604 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1605#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1606 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1607#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1608 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1609
1610#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1611
1612#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1613
1614#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1615#define HAS_PPGTT(dev_priv) \
1616 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1617#define HAS_FULL_PPGTT(dev_priv) \
1618 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1619
1620#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1621 GEM_BUG_ON((sizes) == 0); \
1622 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1623})
1624
1625#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1626#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1627 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1628
1629/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1630#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1631
1632#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1633 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1634
1635/* WaRsDisableCoarsePowerGating:skl,cnl */
1636#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1637 (IS_CANNONLAKE(dev_priv) || \
1638 IS_SKL_GT3(dev_priv) || \
1639 IS_SKL_GT4(dev_priv))
1640
1641#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1642#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1643 IS_GEMINILAKE(dev_priv) || \
1644 IS_KABYLAKE(dev_priv))
1645
1646/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1647 * rows, which changed the alignment requirements and fence programming.
1648 */
1649#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1650 !(IS_I915G(dev_priv) || \
1651 IS_I915GM(dev_priv)))
1652#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1653#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1654
1655#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1656#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1657#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1658
1659#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1660
1661#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1662
1663#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1664#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1665#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1666#define HAS_PSR_HW_TRACKING(dev_priv) \
1667 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1668#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1669
1670#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1671#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1672#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1673
1674#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1675
1676#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1677
1678#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1679#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1680
1681#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1682
1683#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1684#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1685
1686#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1687
1688#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1689
1690#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1691
1692
1693#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1694
1695#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1696
1697/* DPF == dynamic parity feature */
1698#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1699#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1700 2 : HAS_L3_DPF(dev_priv))
1701
1702#define GT_FREQUENCY_MULTIPLIER 50
1703#define GEN9_FREQ_SCALER 3
1704
1705#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1706
1707#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1708
1709/* Only valid when HAS_DISPLAY() is true */
1710#define INTEL_DISPLAY_ENABLED(dev_priv) \
1711 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1712
1713static inline bool intel_vtd_active(void)
1714{
1715#ifdef CONFIG_INTEL_IOMMU
1716 if (intel_iommu_gfx_mapped)
1717 return true;
1718#endif
1719 return false;
1720}
1721
1722static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1723{
1724 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1725}
1726
1727static inline bool
1728intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1729{
1730 return IS_BROXTON(dev_priv) && intel_vtd_active();
1731}
1732
1733/* i915_drv.c */
1734extern const struct dev_pm_ops i915_pm_ops;
1735
1736int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1737void i915_driver_remove(struct drm_i915_private *i915);
1738
1739int i915_resume_switcheroo(struct drm_i915_private *i915);
1740int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1741
1742int i915_getparam_ioctl(struct drm_device *dev, void *data,
1743 struct drm_file *file_priv);
1744
1745/* i915_gem.c */
1746int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1747void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1748void i915_gem_init_early(struct drm_i915_private *dev_priv);
1749void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1750int i915_gem_freeze(struct drm_i915_private *dev_priv);
1751int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1752
1753struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1754
1755static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1756{
1757 /*
1758 * A single pass should suffice to release all the freed objects (along
1759 * most call paths) , but be a little more paranoid in that freeing
1760 * the objects does take a little amount of time, during which the rcu
1761 * callbacks could have added new objects into the freed list, and
1762 * armed the work again.
1763 */
1764 while (atomic_read(&i915->mm.free_count)) {
1765 flush_work(&i915->mm.free_work);
1766 rcu_barrier();
1767 }
1768}
1769
1770static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1771{
1772 /*
1773 * Similar to objects above (see i915_gem_drain_freed-objects), in
1774 * general we have workers that are armed by RCU and then rearm
1775 * themselves in their callbacks. To be paranoid, we need to
1776 * drain the workqueue a second time after waiting for the RCU
1777 * grace period so that we catch work queued via RCU from the first
1778 * pass. As neither drain_workqueue() nor flush_workqueue() report
1779 * a result, we make an assumption that we only don't require more
1780 * than 3 passes to catch all _recursive_ RCU delayed work.
1781 *
1782 */
1783 int pass = 3;
1784 do {
1785 flush_workqueue(i915->wq);
1786 rcu_barrier();
1787 i915_gem_drain_freed_objects(i915);
1788 } while (--pass);
1789 drain_workqueue(i915->wq);
1790}
1791
1792struct i915_vma * __must_check
1793i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1794 const struct i915_ggtt_view *view,
1795 u64 size,
1796 u64 alignment,
1797 u64 flags);
1798
1799int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1800 unsigned long flags);
1801#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1802#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1803#define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1804
1805void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1806
1807int i915_gem_dumb_create(struct drm_file *file_priv,
1808 struct drm_device *dev,
1809 struct drm_mode_create_dumb *args);
1810
1811int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1812
1813static inline u32 i915_reset_count(struct i915_gpu_error *error)
1814{
1815 return atomic_read(&error->reset_count);
1816}
1817
1818static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1819 const struct intel_engine_cs *engine)
1820{
1821 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1822}
1823
1824int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1825void i915_gem_driver_register(struct drm_i915_private *i915);
1826void i915_gem_driver_unregister(struct drm_i915_private *i915);
1827void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1828void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1829void i915_gem_suspend(struct drm_i915_private *dev_priv);
1830void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1831void i915_gem_resume(struct drm_i915_private *dev_priv);
1832
1833int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1834void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1835
1836int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1837 enum i915_cache_level cache_level);
1838
1839struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1840 struct dma_buf *dma_buf);
1841
1842struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1843
1844static inline struct i915_gem_context *
1845__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1846{
1847 return xa_load(&file_priv->context_xa, id);
1848}
1849
1850static inline struct i915_gem_context *
1851i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1852{
1853 struct i915_gem_context *ctx;
1854
1855 rcu_read_lock();
1856 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1857 if (ctx && !kref_get_unless_zero(&ctx->ref))
1858 ctx = NULL;
1859 rcu_read_unlock();
1860
1861 return ctx;
1862}
1863
1864/* i915_gem_evict.c */
1865int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1866 u64 min_size, u64 alignment,
1867 unsigned long color,
1868 u64 start, u64 end,
1869 unsigned flags);
1870int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1871 struct drm_mm_node *node,
1872 unsigned int flags);
1873int i915_gem_evict_vm(struct i915_address_space *vm);
1874
1875/* i915_gem_internal.c */
1876struct drm_i915_gem_object *
1877i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1878 phys_addr_t size);
1879
1880/* i915_gem_tiling.c */
1881static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1882{
1883 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1884
1885 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1886 i915_gem_object_is_tiled(obj);
1887}
1888
1889u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1890 unsigned int tiling, unsigned int stride);
1891u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1892 unsigned int tiling, unsigned int stride);
1893
1894const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1895
1896/* i915_cmd_parser.c */
1897int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1898void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1899void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1900int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1901 struct i915_vma *batch,
1902 u32 batch_offset,
1903 u32 batch_length,
1904 struct i915_vma *shadow,
1905 bool trampoline);
1906#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1907
1908/* intel_device_info.c */
1909static inline struct intel_device_info *
1910mkwrite_device_info(struct drm_i915_private *dev_priv)
1911{
1912 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1913}
1914
1915int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1916 struct drm_file *file);
1917
1918#define __I915_REG_OP(op__, dev_priv__, ...) \
1919 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1920
1921#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
1922#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1923
1924#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
1925
1926/* These are untraced mmio-accessors that are only valid to be used inside
1927 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1928 * controlled.
1929 *
1930 * Think twice, and think again, before using these.
1931 *
1932 * As an example, these accessors can possibly be used between:
1933 *
1934 * spin_lock_irq(&dev_priv->uncore.lock);
1935 * intel_uncore_forcewake_get__locked();
1936 *
1937 * and
1938 *
1939 * intel_uncore_forcewake_put__locked();
1940 * spin_unlock_irq(&dev_priv->uncore.lock);
1941 *
1942 *
1943 * Note: some registers may not need forcewake held, so
1944 * intel_uncore_forcewake_{get,put} can be omitted, see
1945 * intel_uncore_forcewake_for_reg().
1946 *
1947 * Certain architectures will die if the same cacheline is concurrently accessed
1948 * by different clients (e.g. on Ivybridge). Access to registers should
1949 * therefore generally be serialised, by either the dev_priv->uncore.lock or
1950 * a more localised lock guarding all access to that bank of registers.
1951 */
1952#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
1953#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
1954
1955/* i915_mm.c */
1956int remap_io_mapping(struct vm_area_struct *vma,
1957 unsigned long addr, unsigned long pfn, unsigned long size,
1958 struct io_mapping *iomap);
1959int remap_io_sg(struct vm_area_struct *vma,
1960 unsigned long addr, unsigned long size,
1961 struct scatterlist *sgl, resource_size_t iobase);
1962
1963static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1964{
1965 if (INTEL_GEN(i915) >= 10)
1966 return CNL_HWS_CSB_WRITE_INDEX;
1967 else
1968 return I915_HWS_CSB_WRITE_INDEX;
1969}
1970
1971static inline enum i915_map_type
1972i915_coherent_map_type(struct drm_i915_private *i915)
1973{
1974 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1975}
1976
1977static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)
1978{
1979 return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
1980 1000000000);
1981}
1982
1983static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)
1984{
1985 return div_u64(val * 1000000000,
1986 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
1987}
1988
1989#endif