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1#ifndef DW_SPI_HEADER_H
2#define DW_SPI_HEADER_H
3
4#include <linux/io.h>
5#include <linux/scatterlist.h>
6
7/* Bit fields in CTRLR0 */
8#define SPI_DFS_OFFSET 0
9
10#define SPI_FRF_OFFSET 4
11#define SPI_FRF_SPI 0x0
12#define SPI_FRF_SSP 0x1
13#define SPI_FRF_MICROWIRE 0x2
14#define SPI_FRF_RESV 0x3
15
16#define SPI_MODE_OFFSET 6
17#define SPI_SCPH_OFFSET 6
18#define SPI_SCOL_OFFSET 7
19
20#define SPI_TMOD_OFFSET 8
21#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
22#define SPI_TMOD_TR 0x0 /* xmit & recv */
23#define SPI_TMOD_TO 0x1 /* xmit only */
24#define SPI_TMOD_RO 0x2 /* recv only */
25#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
26
27#define SPI_SLVOE_OFFSET 10
28#define SPI_SRL_OFFSET 11
29#define SPI_CFS_OFFSET 12
30
31/* Bit fields in SR, 7 bits */
32#define SR_MASK 0x7f /* cover 7 bits */
33#define SR_BUSY (1 << 0)
34#define SR_TF_NOT_FULL (1 << 1)
35#define SR_TF_EMPT (1 << 2)
36#define SR_RF_NOT_EMPT (1 << 3)
37#define SR_RF_FULL (1 << 4)
38#define SR_TX_ERR (1 << 5)
39#define SR_DCOL (1 << 6)
40
41/* Bit fields in ISR, IMR, RISR, 7 bits */
42#define SPI_INT_TXEI (1 << 0)
43#define SPI_INT_TXOI (1 << 1)
44#define SPI_INT_RXUI (1 << 2)
45#define SPI_INT_RXOI (1 << 3)
46#define SPI_INT_RXFI (1 << 4)
47#define SPI_INT_MSTI (1 << 5)
48
49/* TX RX interrupt level threshold, max can be 256 */
50#define SPI_INT_THRESHOLD 32
51
52enum dw_ssi_type {
53 SSI_MOTO_SPI = 0,
54 SSI_TI_SSP,
55 SSI_NS_MICROWIRE,
56};
57
58struct dw_spi_reg {
59 u32 ctrl0;
60 u32 ctrl1;
61 u32 ssienr;
62 u32 mwcr;
63 u32 ser;
64 u32 baudr;
65 u32 txfltr;
66 u32 rxfltr;
67 u32 txflr;
68 u32 rxflr;
69 u32 sr;
70 u32 imr;
71 u32 isr;
72 u32 risr;
73 u32 txoicr;
74 u32 rxoicr;
75 u32 rxuicr;
76 u32 msticr;
77 u32 icr;
78 u32 dmacr;
79 u32 dmatdlr;
80 u32 dmardlr;
81 u32 idr;
82 u32 version;
83 u32 dr; /* Currently oper as 32 bits,
84 though only low 16 bits matters */
85} __packed;
86
87struct dw_spi;
88struct dw_spi_dma_ops {
89 int (*dma_init)(struct dw_spi *dws);
90 void (*dma_exit)(struct dw_spi *dws);
91 int (*dma_transfer)(struct dw_spi *dws, int cs_change);
92};
93
94struct dw_spi {
95 struct spi_master *master;
96 struct spi_device *cur_dev;
97 struct device *parent_dev;
98 enum dw_ssi_type type;
99 char name[16];
100
101 void __iomem *regs;
102 unsigned long paddr;
103 u32 iolen;
104 int irq;
105 u32 fifo_len; /* depth of the FIFO buffer */
106 u32 max_freq; /* max bus freq supported */
107
108 u16 bus_num;
109 u16 num_cs; /* supported slave numbers */
110
111 /* Driver message queue */
112 struct workqueue_struct *workqueue;
113 struct work_struct pump_messages;
114 spinlock_t lock;
115 struct list_head queue;
116 int busy;
117 int run;
118
119 /* Message Transfer pump */
120 struct tasklet_struct pump_transfers;
121
122 /* Current message transfer state info */
123 struct spi_message *cur_msg;
124 struct spi_transfer *cur_transfer;
125 struct chip_data *cur_chip;
126 struct chip_data *prev_chip;
127 size_t len;
128 void *tx;
129 void *tx_end;
130 void *rx;
131 void *rx_end;
132 int dma_mapped;
133 dma_addr_t rx_dma;
134 dma_addr_t tx_dma;
135 size_t rx_map_len;
136 size_t tx_map_len;
137 u8 n_bytes; /* current is a 1/2 bytes op */
138 u8 max_bits_per_word; /* maxim is 16b */
139 u32 dma_width;
140 int cs_change;
141 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
142 void (*cs_control)(u32 command);
143
144 /* Dma info */
145 int dma_inited;
146 struct dma_chan *txchan;
147 struct scatterlist tx_sgl;
148 struct dma_chan *rxchan;
149 struct scatterlist rx_sgl;
150 int dma_chan_done;
151 struct device *dma_dev;
152 dma_addr_t dma_addr; /* phy address of the Data register */
153 struct dw_spi_dma_ops *dma_ops;
154 void *dma_priv; /* platform relate info */
155 struct pci_dev *dmac;
156
157 /* Bus interface info */
158 void *priv;
159#ifdef CONFIG_DEBUG_FS
160 struct dentry *debugfs;
161#endif
162};
163
164#define dw_readl(dw, name) \
165 __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
166#define dw_writel(dw, name, val) \
167 __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
168#define dw_readw(dw, name) \
169 __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
170#define dw_writew(dw, name, val) \
171 __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
172
173static inline void spi_enable_chip(struct dw_spi *dws, int enable)
174{
175 dw_writel(dws, ssienr, (enable ? 1 : 0));
176}
177
178static inline void spi_set_clk(struct dw_spi *dws, u16 div)
179{
180 dw_writel(dws, baudr, div);
181}
182
183static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
184{
185 if (cs > dws->num_cs)
186 return;
187
188 if (dws->cs_control)
189 dws->cs_control(1);
190
191 dw_writel(dws, ser, 1 << cs);
192}
193
194/* Disable IRQ bits */
195static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
196{
197 u32 new_mask;
198
199 new_mask = dw_readl(dws, imr) & ~mask;
200 dw_writel(dws, imr, new_mask);
201}
202
203/* Enable IRQ bits */
204static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
205{
206 u32 new_mask;
207
208 new_mask = dw_readl(dws, imr) | mask;
209 dw_writel(dws, imr, new_mask);
210}
211
212/*
213 * Each SPI slave device to work with dw_api controller should
214 * has such a structure claiming its working mode (PIO/DMA etc),
215 * which can be save in the "controller_data" member of the
216 * struct spi_device
217 */
218struct dw_spi_chip {
219 u8 poll_mode; /* 0 for contoller polling mode */
220 u8 type; /* SPI/SSP/Micrwire */
221 u8 enable_dma;
222 void (*cs_control)(u32 command);
223};
224
225extern int dw_spi_add_host(struct dw_spi *dws);
226extern void dw_spi_remove_host(struct dw_spi *dws);
227extern int dw_spi_suspend_host(struct dw_spi *dws);
228extern int dw_spi_resume_host(struct dw_spi *dws);
229extern void dw_spi_xfer_done(struct dw_spi *dws);
230
231/* platform related setup */
232extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
233#endif /* DW_SPI_HEADER_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DW_SPI_HEADER_H
3#define DW_SPI_HEADER_H
4
5#include <linux/completion.h>
6#include <linux/debugfs.h>
7#include <linux/irqreturn.h>
8#include <linux/io.h>
9#include <linux/scatterlist.h>
10
11/* Register offsets */
12#define DW_SPI_CTRLR0 0x00
13#define DW_SPI_CTRLR1 0x04
14#define DW_SPI_SSIENR 0x08
15#define DW_SPI_MWCR 0x0c
16#define DW_SPI_SER 0x10
17#define DW_SPI_BAUDR 0x14
18#define DW_SPI_TXFTLR 0x18
19#define DW_SPI_RXFTLR 0x1c
20#define DW_SPI_TXFLR 0x20
21#define DW_SPI_RXFLR 0x24
22#define DW_SPI_SR 0x28
23#define DW_SPI_IMR 0x2c
24#define DW_SPI_ISR 0x30
25#define DW_SPI_RISR 0x34
26#define DW_SPI_TXOICR 0x38
27#define DW_SPI_RXOICR 0x3c
28#define DW_SPI_RXUICR 0x40
29#define DW_SPI_MSTICR 0x44
30#define DW_SPI_ICR 0x48
31#define DW_SPI_DMACR 0x4c
32#define DW_SPI_DMATDLR 0x50
33#define DW_SPI_DMARDLR 0x54
34#define DW_SPI_IDR 0x58
35#define DW_SPI_VERSION 0x5c
36#define DW_SPI_DR 0x60
37#define DW_SPI_CS_OVERRIDE 0xf4
38
39/* Bit fields in CTRLR0 */
40#define SPI_DFS_OFFSET 0
41
42#define SPI_FRF_OFFSET 4
43#define SPI_FRF_SPI 0x0
44#define SPI_FRF_SSP 0x1
45#define SPI_FRF_MICROWIRE 0x2
46#define SPI_FRF_RESV 0x3
47
48#define SPI_MODE_OFFSET 6
49#define SPI_SCPH_OFFSET 6
50#define SPI_SCOL_OFFSET 7
51
52#define SPI_TMOD_OFFSET 8
53#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
54#define SPI_TMOD_TR 0x0 /* xmit & recv */
55#define SPI_TMOD_TO 0x1 /* xmit only */
56#define SPI_TMOD_RO 0x2 /* recv only */
57#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
58
59#define SPI_SLVOE_OFFSET 10
60#define SPI_SRL_OFFSET 11
61#define SPI_CFS_OFFSET 12
62
63/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
64#define DWC_SSI_CTRLR0_SRL_OFFSET 13
65#define DWC_SSI_CTRLR0_TMOD_OFFSET 10
66#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
67#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
68#define DWC_SSI_CTRLR0_SCPH_OFFSET 8
69#define DWC_SSI_CTRLR0_FRF_OFFSET 6
70#define DWC_SSI_CTRLR0_DFS_OFFSET 0
71
72/* Bit fields in SR, 7 bits */
73#define SR_MASK 0x7f /* cover 7 bits */
74#define SR_BUSY (1 << 0)
75#define SR_TF_NOT_FULL (1 << 1)
76#define SR_TF_EMPT (1 << 2)
77#define SR_RF_NOT_EMPT (1 << 3)
78#define SR_RF_FULL (1 << 4)
79#define SR_TX_ERR (1 << 5)
80#define SR_DCOL (1 << 6)
81
82/* Bit fields in ISR, IMR, RISR, 7 bits */
83#define SPI_INT_TXEI (1 << 0)
84#define SPI_INT_TXOI (1 << 1)
85#define SPI_INT_RXUI (1 << 2)
86#define SPI_INT_RXOI (1 << 3)
87#define SPI_INT_RXFI (1 << 4)
88#define SPI_INT_MSTI (1 << 5)
89
90/* Bit fields in DMACR */
91#define SPI_DMA_RDMAE (1 << 0)
92#define SPI_DMA_TDMAE (1 << 1)
93
94/* TX RX interrupt level threshold, max can be 256 */
95#define SPI_INT_THRESHOLD 32
96
97enum dw_ssi_type {
98 SSI_MOTO_SPI = 0,
99 SSI_TI_SSP,
100 SSI_NS_MICROWIRE,
101};
102
103struct dw_spi;
104struct dw_spi_dma_ops {
105 int (*dma_init)(struct device *dev, struct dw_spi *dws);
106 void (*dma_exit)(struct dw_spi *dws);
107 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
108 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
109 struct spi_transfer *xfer);
110 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
111 void (*dma_stop)(struct dw_spi *dws);
112};
113
114struct dw_spi {
115 struct spi_controller *master;
116 enum dw_ssi_type type;
117
118 void __iomem *regs;
119 unsigned long paddr;
120 int irq;
121 u32 fifo_len; /* depth of the FIFO buffer */
122 u32 max_freq; /* max bus freq supported */
123
124 int cs_override;
125 u32 reg_io_width; /* DR I/O width in bytes */
126 u16 bus_num;
127 u16 num_cs; /* supported slave numbers */
128 void (*set_cs)(struct spi_device *spi, bool enable);
129 u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi,
130 struct spi_transfer *transfer);
131
132 /* Current message transfer state info */
133 size_t len;
134 void *tx;
135 void *tx_end;
136 spinlock_t buf_lock;
137 void *rx;
138 void *rx_end;
139 int dma_mapped;
140 u8 n_bytes; /* current is a 1/2 bytes op */
141 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
142 u32 current_freq; /* frequency in hz */
143
144 /* DMA info */
145 struct dma_chan *txchan;
146 u32 txburst;
147 struct dma_chan *rxchan;
148 u32 rxburst;
149 unsigned long dma_chan_busy;
150 dma_addr_t dma_addr; /* phy address of the Data register */
151 const struct dw_spi_dma_ops *dma_ops;
152 struct completion dma_completion;
153
154#ifdef CONFIG_DEBUG_FS
155 struct dentry *debugfs;
156 struct debugfs_regset32 regset;
157#endif
158};
159
160static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
161{
162 return __raw_readl(dws->regs + offset);
163}
164
165static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
166{
167 return __raw_readw(dws->regs + offset);
168}
169
170static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
171{
172 __raw_writel(val, dws->regs + offset);
173}
174
175static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
176{
177 __raw_writew(val, dws->regs + offset);
178}
179
180static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
181{
182 switch (dws->reg_io_width) {
183 case 2:
184 return dw_readw(dws, offset);
185 case 4:
186 default:
187 return dw_readl(dws, offset);
188 }
189}
190
191static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
192{
193 switch (dws->reg_io_width) {
194 case 2:
195 dw_writew(dws, offset, val);
196 break;
197 case 4:
198 default:
199 dw_writel(dws, offset, val);
200 break;
201 }
202}
203
204static inline void spi_enable_chip(struct dw_spi *dws, int enable)
205{
206 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
207}
208
209static inline void spi_set_clk(struct dw_spi *dws, u16 div)
210{
211 dw_writel(dws, DW_SPI_BAUDR, div);
212}
213
214/* Disable IRQ bits */
215static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
216{
217 u32 new_mask;
218
219 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
220 dw_writel(dws, DW_SPI_IMR, new_mask);
221}
222
223/* Enable IRQ bits */
224static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
225{
226 u32 new_mask;
227
228 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
229 dw_writel(dws, DW_SPI_IMR, new_mask);
230}
231
232/*
233 * This does disable the SPI controller, interrupts, and re-enable the
234 * controller back. Transmit and receive FIFO buffers are cleared when the
235 * device is disabled.
236 */
237static inline void spi_reset_chip(struct dw_spi *dws)
238{
239 spi_enable_chip(dws, 0);
240 spi_mask_intr(dws, 0xff);
241 spi_enable_chip(dws, 1);
242}
243
244static inline void spi_shutdown_chip(struct dw_spi *dws)
245{
246 spi_enable_chip(dws, 0);
247 spi_set_clk(dws, 0);
248}
249
250extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
251extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
252extern void dw_spi_remove_host(struct dw_spi *dws);
253extern int dw_spi_suspend_host(struct dw_spi *dws);
254extern int dw_spi_resume_host(struct dw_spi *dws);
255extern u32 dw_spi_update_cr0(struct spi_controller *master,
256 struct spi_device *spi,
257 struct spi_transfer *transfer);
258extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
259 struct spi_device *spi,
260 struct spi_transfer *transfer);
261
262#ifdef CONFIG_SPI_DW_DMA
263
264extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
265extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
266
267#else
268
269static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
270static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
271
272#endif /* !CONFIG_SPI_DW_DMA */
273
274#endif /* DW_SPI_HEADER_H */