Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright 2019 NXP Semiconductors
3 *
4 * This is an umbrella module for all network switches that are
5 * register-compatible with Ocelot and that perform I/O to their host CPU
6 * through an NPI (Node Processor Interface) Ethernet port.
7 */
8#include <uapi/linux/if_bridge.h>
9#include <soc/mscc/ocelot_vcap.h>
10#include <soc/mscc/ocelot_qsys.h>
11#include <soc/mscc/ocelot_sys.h>
12#include <soc/mscc/ocelot_dev.h>
13#include <soc/mscc/ocelot_ana.h>
14#include <soc/mscc/ocelot_ptp.h>
15#include <soc/mscc/ocelot.h>
16#include <linux/platform_device.h>
17#include <linux/packing.h>
18#include <linux/module.h>
19#include <linux/of_net.h>
20#include <linux/pci.h>
21#include <linux/of.h>
22#include <net/pkt_sched.h>
23#include <net/dsa.h>
24#include "felix.h"
25
26static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
27 int port,
28 enum dsa_tag_protocol mp)
29{
30 return DSA_TAG_PROTO_OCELOT;
31}
32
33static int felix_set_ageing_time(struct dsa_switch *ds,
34 unsigned int ageing_time)
35{
36 struct ocelot *ocelot = ds->priv;
37
38 ocelot_set_ageing_time(ocelot, ageing_time);
39
40 return 0;
41}
42
43static int felix_fdb_dump(struct dsa_switch *ds, int port,
44 dsa_fdb_dump_cb_t *cb, void *data)
45{
46 struct ocelot *ocelot = ds->priv;
47
48 return ocelot_fdb_dump(ocelot, port, cb, data);
49}
50
51static int felix_fdb_add(struct dsa_switch *ds, int port,
52 const unsigned char *addr, u16 vid)
53{
54 struct ocelot *ocelot = ds->priv;
55
56 return ocelot_fdb_add(ocelot, port, addr, vid);
57}
58
59static int felix_fdb_del(struct dsa_switch *ds, int port,
60 const unsigned char *addr, u16 vid)
61{
62 struct ocelot *ocelot = ds->priv;
63
64 return ocelot_fdb_del(ocelot, port, addr, vid);
65}
66
67/* This callback needs to be present */
68static int felix_mdb_prepare(struct dsa_switch *ds, int port,
69 const struct switchdev_obj_port_mdb *mdb)
70{
71 return 0;
72}
73
74static void felix_mdb_add(struct dsa_switch *ds, int port,
75 const struct switchdev_obj_port_mdb *mdb)
76{
77 struct ocelot *ocelot = ds->priv;
78
79 ocelot_port_mdb_add(ocelot, port, mdb);
80}
81
82static int felix_mdb_del(struct dsa_switch *ds, int port,
83 const struct switchdev_obj_port_mdb *mdb)
84{
85 struct ocelot *ocelot = ds->priv;
86
87 return ocelot_port_mdb_del(ocelot, port, mdb);
88}
89
90static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port,
91 u8 state)
92{
93 struct ocelot *ocelot = ds->priv;
94
95 return ocelot_bridge_stp_state_set(ocelot, port, state);
96}
97
98static int felix_bridge_join(struct dsa_switch *ds, int port,
99 struct net_device *br)
100{
101 struct ocelot *ocelot = ds->priv;
102
103 return ocelot_port_bridge_join(ocelot, port, br);
104}
105
106static void felix_bridge_leave(struct dsa_switch *ds, int port,
107 struct net_device *br)
108{
109 struct ocelot *ocelot = ds->priv;
110
111 ocelot_port_bridge_leave(ocelot, port, br);
112}
113
114/* This callback needs to be present */
115static int felix_vlan_prepare(struct dsa_switch *ds, int port,
116 const struct switchdev_obj_port_vlan *vlan)
117{
118 return 0;
119}
120
121static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled)
122{
123 struct ocelot *ocelot = ds->priv;
124
125 ocelot_port_vlan_filtering(ocelot, port, enabled);
126
127 return 0;
128}
129
130static void felix_vlan_add(struct dsa_switch *ds, int port,
131 const struct switchdev_obj_port_vlan *vlan)
132{
133 struct ocelot *ocelot = ds->priv;
134 u16 flags = vlan->flags;
135 u16 vid;
136 int err;
137
138 if (dsa_is_cpu_port(ds, port))
139 flags &= ~BRIDGE_VLAN_INFO_UNTAGGED;
140
141 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
142 err = ocelot_vlan_add(ocelot, port, vid,
143 flags & BRIDGE_VLAN_INFO_PVID,
144 flags & BRIDGE_VLAN_INFO_UNTAGGED);
145 if (err) {
146 dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n",
147 vid, port, err);
148 return;
149 }
150 }
151}
152
153static int felix_vlan_del(struct dsa_switch *ds, int port,
154 const struct switchdev_obj_port_vlan *vlan)
155{
156 struct ocelot *ocelot = ds->priv;
157 u16 vid;
158 int err;
159
160 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
161 err = ocelot_vlan_del(ocelot, port, vid);
162 if (err) {
163 dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n",
164 vid, port, err);
165 return err;
166 }
167 }
168 return 0;
169}
170
171static int felix_port_enable(struct dsa_switch *ds, int port,
172 struct phy_device *phy)
173{
174 struct ocelot *ocelot = ds->priv;
175
176 ocelot_port_enable(ocelot, port, phy);
177
178 return 0;
179}
180
181static void felix_port_disable(struct dsa_switch *ds, int port)
182{
183 struct ocelot *ocelot = ds->priv;
184
185 return ocelot_port_disable(ocelot, port);
186}
187
188static void felix_phylink_validate(struct dsa_switch *ds, int port,
189 unsigned long *supported,
190 struct phylink_link_state *state)
191{
192 struct ocelot *ocelot = ds->priv;
193 struct felix *felix = ocelot_to_felix(ocelot);
194
195 if (felix->info->phylink_validate)
196 felix->info->phylink_validate(ocelot, port, supported, state);
197}
198
199static int felix_phylink_mac_pcs_get_state(struct dsa_switch *ds, int port,
200 struct phylink_link_state *state)
201{
202 struct ocelot *ocelot = ds->priv;
203 struct felix *felix = ocelot_to_felix(ocelot);
204
205 if (felix->info->pcs_link_state)
206 felix->info->pcs_link_state(ocelot, port, state);
207
208 return 0;
209}
210
211static void felix_phylink_mac_config(struct dsa_switch *ds, int port,
212 unsigned int link_an_mode,
213 const struct phylink_link_state *state)
214{
215 struct ocelot *ocelot = ds->priv;
216 struct felix *felix = ocelot_to_felix(ocelot);
217
218 if (felix->info->pcs_config)
219 felix->info->pcs_config(ocelot, port, link_an_mode, state);
220}
221
222static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port,
223 unsigned int link_an_mode,
224 phy_interface_t interface)
225{
226 struct ocelot *ocelot = ds->priv;
227 struct ocelot_port *ocelot_port = ocelot->ports[port];
228
229 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
230 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
231}
232
233static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
234 unsigned int link_an_mode,
235 phy_interface_t interface,
236 struct phy_device *phydev,
237 int speed, int duplex,
238 bool tx_pause, bool rx_pause)
239{
240 struct ocelot *ocelot = ds->priv;
241 struct ocelot_port *ocelot_port = ocelot->ports[port];
242 struct felix *felix = ocelot_to_felix(ocelot);
243 u32 mac_fc_cfg;
244
245 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
246 * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is
247 * integrated is that the MAC speed is fixed and it's the PCS who is
248 * performing the rate adaptation, so we have to write "1000Mbps" into
249 * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default
250 * value).
251 */
252 ocelot_port_writel(ocelot_port,
253 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
254 DEV_CLOCK_CFG);
255
256 switch (speed) {
257 case SPEED_10:
258 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);
259 break;
260 case SPEED_100:
261 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);
262 break;
263 case SPEED_1000:
264 case SPEED_2500:
265 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);
266 break;
267 default:
268 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
269 port, speed);
270 return;
271 }
272
273 /* handle Rx pause in all cases, with 2500base-X this is used for rate
274 * adaptation.
275 */
276 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
277
278 if (tx_pause)
279 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
280 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
281 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
282 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
283
284 /* Flow control. Link speed is only used here to evaluate the time
285 * specification in incoming pause frames.
286 */
287 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
288
289 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
290
291 /* Undo the effects of felix_phylink_mac_link_down:
292 * enable MAC module
293 */
294 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
295 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
296
297 /* Enable receiving frames on the port, and activate auto-learning of
298 * MAC addresses.
299 */
300 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
301 ANA_PORT_PORT_CFG_RECV_ENA |
302 ANA_PORT_PORT_CFG_PORTID_VAL(port),
303 ANA_PORT_PORT_CFG, port);
304
305 /* Core: Enable port for frame transfer */
306 ocelot_fields_write(ocelot, port,
307 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
308
309 if (felix->info->pcs_link_up)
310 felix->info->pcs_link_up(ocelot, port, link_an_mode, interface,
311 speed, duplex);
312
313 if (felix->info->port_sched_speed_set)
314 felix->info->port_sched_speed_set(ocelot, port, speed);
315}
316
317static void felix_port_qos_map_init(struct ocelot *ocelot, int port)
318{
319 int i;
320
321 ocelot_rmw_gix(ocelot,
322 ANA_PORT_QOS_CFG_QOS_PCP_ENA,
323 ANA_PORT_QOS_CFG_QOS_PCP_ENA,
324 ANA_PORT_QOS_CFG,
325 port);
326
327 for (i = 0; i < FELIX_NUM_TC * 2; i++) {
328 ocelot_rmw_ix(ocelot,
329 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) |
330 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i),
331 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL |
332 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M,
333 ANA_PORT_PCP_DEI_MAP,
334 port, i);
335 }
336}
337
338static void felix_get_strings(struct dsa_switch *ds, int port,
339 u32 stringset, u8 *data)
340{
341 struct ocelot *ocelot = ds->priv;
342
343 return ocelot_get_strings(ocelot, port, stringset, data);
344}
345
346static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
347{
348 struct ocelot *ocelot = ds->priv;
349
350 ocelot_get_ethtool_stats(ocelot, port, data);
351}
352
353static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset)
354{
355 struct ocelot *ocelot = ds->priv;
356
357 return ocelot_get_sset_count(ocelot, port, sset);
358}
359
360static int felix_get_ts_info(struct dsa_switch *ds, int port,
361 struct ethtool_ts_info *info)
362{
363 struct ocelot *ocelot = ds->priv;
364
365 return ocelot_get_ts_info(ocelot, port, info);
366}
367
368static int felix_parse_ports_node(struct felix *felix,
369 struct device_node *ports_node,
370 phy_interface_t *port_phy_modes)
371{
372 struct ocelot *ocelot = &felix->ocelot;
373 struct device *dev = felix->ocelot.dev;
374 struct device_node *child;
375
376 for_each_available_child_of_node(ports_node, child) {
377 phy_interface_t phy_mode;
378 u32 port;
379 int err;
380
381 /* Get switch port number from DT */
382 if (of_property_read_u32(child, "reg", &port) < 0) {
383 dev_err(dev, "Port number not defined in device tree "
384 "(property \"reg\")\n");
385 of_node_put(child);
386 return -ENODEV;
387 }
388
389 /* Get PHY mode from DT */
390 err = of_get_phy_mode(child, &phy_mode);
391 if (err) {
392 dev_err(dev, "Failed to read phy-mode or "
393 "phy-interface-type property for port %d\n",
394 port);
395 of_node_put(child);
396 return -ENODEV;
397 }
398
399 err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode);
400 if (err < 0) {
401 dev_err(dev, "Unsupported PHY mode %s on port %d\n",
402 phy_modes(phy_mode), port);
403 of_node_put(child);
404 return err;
405 }
406
407 port_phy_modes[port] = phy_mode;
408 }
409
410 return 0;
411}
412
413static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes)
414{
415 struct device *dev = felix->ocelot.dev;
416 struct device_node *switch_node;
417 struct device_node *ports_node;
418 int err;
419
420 switch_node = dev->of_node;
421
422 ports_node = of_get_child_by_name(switch_node, "ports");
423 if (!ports_node) {
424 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
425 return -ENODEV;
426 }
427
428 err = felix_parse_ports_node(felix, ports_node, port_phy_modes);
429 of_node_put(ports_node);
430
431 return err;
432}
433
434static int felix_init_structs(struct felix *felix, int num_phys_ports)
435{
436 struct ocelot *ocelot = &felix->ocelot;
437 phy_interface_t *port_phy_modes;
438 struct resource res;
439 int port, i, err;
440
441 ocelot->num_phys_ports = num_phys_ports;
442 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports,
443 sizeof(struct ocelot_port *), GFP_KERNEL);
444 if (!ocelot->ports)
445 return -ENOMEM;
446
447 ocelot->map = felix->info->map;
448 ocelot->stats_layout = felix->info->stats_layout;
449 ocelot->num_stats = felix->info->num_stats;
450 ocelot->shared_queue_sz = felix->info->shared_queue_sz;
451 ocelot->num_mact_rows = felix->info->num_mact_rows;
452 ocelot->vcap_is2_keys = felix->info->vcap_is2_keys;
453 ocelot->vcap_is2_actions= felix->info->vcap_is2_actions;
454 ocelot->vcap = felix->info->vcap;
455 ocelot->ops = felix->info->ops;
456
457 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t),
458 GFP_KERNEL);
459 if (!port_phy_modes)
460 return -ENOMEM;
461
462 err = felix_parse_dt(felix, port_phy_modes);
463 if (err) {
464 kfree(port_phy_modes);
465 return err;
466 }
467
468 for (i = 0; i < TARGET_MAX; i++) {
469 struct regmap *target;
470
471 if (!felix->info->target_io_res[i].name)
472 continue;
473
474 memcpy(&res, &felix->info->target_io_res[i], sizeof(res));
475 res.flags = IORESOURCE_MEM;
476 res.start += felix->switch_base;
477 res.end += felix->switch_base;
478
479 target = ocelot_regmap_init(ocelot, &res);
480 if (IS_ERR(target)) {
481 dev_err(ocelot->dev,
482 "Failed to map device memory space\n");
483 kfree(port_phy_modes);
484 return PTR_ERR(target);
485 }
486
487 ocelot->targets[i] = target;
488 }
489
490 err = ocelot_regfields_init(ocelot, felix->info->regfields);
491 if (err) {
492 dev_err(ocelot->dev, "failed to init reg fields map\n");
493 kfree(port_phy_modes);
494 return err;
495 }
496
497 for (port = 0; port < num_phys_ports; port++) {
498 struct ocelot_port *ocelot_port;
499 struct regmap *target;
500 u8 *template;
501
502 ocelot_port = devm_kzalloc(ocelot->dev,
503 sizeof(struct ocelot_port),
504 GFP_KERNEL);
505 if (!ocelot_port) {
506 dev_err(ocelot->dev,
507 "failed to allocate port memory\n");
508 kfree(port_phy_modes);
509 return -ENOMEM;
510 }
511
512 memcpy(&res, &felix->info->port_io_res[port], sizeof(res));
513 res.flags = IORESOURCE_MEM;
514 res.start += felix->switch_base;
515 res.end += felix->switch_base;
516
517 target = ocelot_regmap_init(ocelot, &res);
518 if (IS_ERR(target)) {
519 dev_err(ocelot->dev,
520 "Failed to map memory space for port %d\n",
521 port);
522 kfree(port_phy_modes);
523 return PTR_ERR(target);
524 }
525
526 template = devm_kzalloc(ocelot->dev, OCELOT_TAG_LEN,
527 GFP_KERNEL);
528 if (!template) {
529 dev_err(ocelot->dev,
530 "Failed to allocate memory for DSA tag\n");
531 kfree(port_phy_modes);
532 return -ENOMEM;
533 }
534
535 ocelot_port->phy_mode = port_phy_modes[port];
536 ocelot_port->ocelot = ocelot;
537 ocelot_port->target = target;
538 ocelot_port->xmit_template = template;
539 ocelot->ports[port] = ocelot_port;
540
541 felix->info->xmit_template_populate(ocelot, port);
542 }
543
544 kfree(port_phy_modes);
545
546 if (felix->info->mdio_bus_alloc) {
547 err = felix->info->mdio_bus_alloc(ocelot);
548 if (err < 0)
549 return err;
550 }
551
552 return 0;
553}
554
555static struct ptp_clock_info ocelot_ptp_clock_info = {
556 .owner = THIS_MODULE,
557 .name = "felix ptp",
558 .max_adj = 0x7fffffff,
559 .n_alarm = 0,
560 .n_ext_ts = 0,
561 .n_per_out = OCELOT_PTP_PINS_NUM,
562 .n_pins = OCELOT_PTP_PINS_NUM,
563 .pps = 0,
564 .gettime64 = ocelot_ptp_gettime64,
565 .settime64 = ocelot_ptp_settime64,
566 .adjtime = ocelot_ptp_adjtime,
567 .adjfine = ocelot_ptp_adjfine,
568 .verify = ocelot_ptp_verify,
569 .enable = ocelot_ptp_enable,
570};
571
572/* Hardware initialization done here so that we can allocate structures with
573 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing
574 * us to allocate structures twice (leak memory) and map PCI memory twice
575 * (which will not work).
576 */
577static int felix_setup(struct dsa_switch *ds)
578{
579 struct ocelot *ocelot = ds->priv;
580 struct felix *felix = ocelot_to_felix(ocelot);
581 int port, err;
582 int tc;
583
584 err = felix_init_structs(felix, ds->num_ports);
585 if (err)
586 return err;
587
588 err = ocelot_init(ocelot);
589 if (err)
590 return err;
591
592 if (ocelot->ptp) {
593 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info);
594 if (err) {
595 dev_err(ocelot->dev,
596 "Timestamp initialization failed\n");
597 ocelot->ptp = 0;
598 }
599 }
600
601 for (port = 0; port < ds->num_ports; port++) {
602 ocelot_init_port(ocelot, port);
603
604 /* Bring up the CPU port module and configure the NPI port */
605 if (dsa_is_cpu_port(ds, port))
606 ocelot_configure_cpu(ocelot, port,
607 OCELOT_TAG_PREFIX_NONE,
608 OCELOT_TAG_PREFIX_LONG);
609
610 /* Set the default QoS Classification based on PCP and DEI
611 * bits of vlan tag.
612 */
613 felix_port_qos_map_init(ocelot, port);
614 }
615
616 /* Include the CPU port module in the forwarding mask for unknown
617 * unicast - the hardware default value for ANA_FLOODING_FLD_UNICAST
618 * excludes BIT(ocelot->num_phys_ports), and so does ocelot_init, since
619 * Ocelot relies on whitelisting MAC addresses towards PGID_CPU.
620 */
621 ocelot_write_rix(ocelot,
622 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
623 ANA_PGID_PGID, PGID_UC);
624 /* Setup the per-traffic class flooding PGIDs */
625 for (tc = 0; tc < FELIX_NUM_TC; tc++)
626 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
627 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
628 ANA_FLOODING_FLD_UNICAST(PGID_UC),
629 ANA_FLOODING, tc);
630
631 ds->mtu_enforcement_ingress = true;
632 ds->configure_vlan_while_not_filtering = true;
633 /* It looks like the MAC/PCS interrupt register - PM0_IEVENT (0x8040)
634 * isn't instantiated for the Felix PF.
635 * In-band AN may take a few ms to complete, so we need to poll.
636 */
637 ds->pcs_poll = true;
638
639 return 0;
640}
641
642static void felix_teardown(struct dsa_switch *ds)
643{
644 struct ocelot *ocelot = ds->priv;
645 struct felix *felix = ocelot_to_felix(ocelot);
646 int port;
647
648 if (felix->info->mdio_bus_free)
649 felix->info->mdio_bus_free(ocelot);
650
651 for (port = 0; port < ocelot->num_phys_ports; port++)
652 ocelot_deinit_port(ocelot, port);
653 ocelot_deinit_timestamp(ocelot);
654 /* stop workqueue thread */
655 ocelot_deinit(ocelot);
656}
657
658static int felix_hwtstamp_get(struct dsa_switch *ds, int port,
659 struct ifreq *ifr)
660{
661 struct ocelot *ocelot = ds->priv;
662
663 return ocelot_hwstamp_get(ocelot, port, ifr);
664}
665
666static int felix_hwtstamp_set(struct dsa_switch *ds, int port,
667 struct ifreq *ifr)
668{
669 struct ocelot *ocelot = ds->priv;
670
671 return ocelot_hwstamp_set(ocelot, port, ifr);
672}
673
674static bool felix_rxtstamp(struct dsa_switch *ds, int port,
675 struct sk_buff *skb, unsigned int type)
676{
677 struct skb_shared_hwtstamps *shhwtstamps;
678 struct ocelot *ocelot = ds->priv;
679 u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN;
680 u32 tstamp_lo, tstamp_hi;
681 struct timespec64 ts;
682 u64 tstamp, val;
683
684 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
685 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
686
687 packing(extraction, &val, 116, 85, OCELOT_TAG_LEN, UNPACK, 0);
688 tstamp_lo = (u32)val;
689
690 tstamp_hi = tstamp >> 32;
691 if ((tstamp & 0xffffffff) < tstamp_lo)
692 tstamp_hi--;
693
694 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo;
695
696 shhwtstamps = skb_hwtstamps(skb);
697 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
698 shhwtstamps->hwtstamp = tstamp;
699 return false;
700}
701
702static bool felix_txtstamp(struct dsa_switch *ds, int port,
703 struct sk_buff *clone, unsigned int type)
704{
705 struct ocelot *ocelot = ds->priv;
706 struct ocelot_port *ocelot_port = ocelot->ports[port];
707
708 if (!ocelot_port_add_txtstamp_skb(ocelot_port, clone))
709 return true;
710
711 return false;
712}
713
714static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
715{
716 struct ocelot *ocelot = ds->priv;
717
718 ocelot_port_set_maxlen(ocelot, port, new_mtu);
719
720 return 0;
721}
722
723static int felix_get_max_mtu(struct dsa_switch *ds, int port)
724{
725 struct ocelot *ocelot = ds->priv;
726
727 return ocelot_get_max_mtu(ocelot, port);
728}
729
730static int felix_cls_flower_add(struct dsa_switch *ds, int port,
731 struct flow_cls_offload *cls, bool ingress)
732{
733 struct ocelot *ocelot = ds->priv;
734
735 return ocelot_cls_flower_replace(ocelot, port, cls, ingress);
736}
737
738static int felix_cls_flower_del(struct dsa_switch *ds, int port,
739 struct flow_cls_offload *cls, bool ingress)
740{
741 struct ocelot *ocelot = ds->priv;
742
743 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress);
744}
745
746static int felix_cls_flower_stats(struct dsa_switch *ds, int port,
747 struct flow_cls_offload *cls, bool ingress)
748{
749 struct ocelot *ocelot = ds->priv;
750
751 return ocelot_cls_flower_stats(ocelot, port, cls, ingress);
752}
753
754static int felix_port_policer_add(struct dsa_switch *ds, int port,
755 struct dsa_mall_policer_tc_entry *policer)
756{
757 struct ocelot *ocelot = ds->priv;
758 struct ocelot_policer pol = {
759 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8,
760 .burst = policer->burst,
761 };
762
763 return ocelot_port_policer_add(ocelot, port, &pol);
764}
765
766static void felix_port_policer_del(struct dsa_switch *ds, int port)
767{
768 struct ocelot *ocelot = ds->priv;
769
770 ocelot_port_policer_del(ocelot, port);
771}
772
773static int felix_port_setup_tc(struct dsa_switch *ds, int port,
774 enum tc_setup_type type,
775 void *type_data)
776{
777 struct ocelot *ocelot = ds->priv;
778 struct felix *felix = ocelot_to_felix(ocelot);
779
780 if (felix->info->port_setup_tc)
781 return felix->info->port_setup_tc(ds, port, type, type_data);
782 else
783 return -EOPNOTSUPP;
784}
785
786const struct dsa_switch_ops felix_switch_ops = {
787 .get_tag_protocol = felix_get_tag_protocol,
788 .setup = felix_setup,
789 .teardown = felix_teardown,
790 .set_ageing_time = felix_set_ageing_time,
791 .get_strings = felix_get_strings,
792 .get_ethtool_stats = felix_get_ethtool_stats,
793 .get_sset_count = felix_get_sset_count,
794 .get_ts_info = felix_get_ts_info,
795 .phylink_validate = felix_phylink_validate,
796 .phylink_mac_link_state = felix_phylink_mac_pcs_get_state,
797 .phylink_mac_config = felix_phylink_mac_config,
798 .phylink_mac_link_down = felix_phylink_mac_link_down,
799 .phylink_mac_link_up = felix_phylink_mac_link_up,
800 .port_enable = felix_port_enable,
801 .port_disable = felix_port_disable,
802 .port_fdb_dump = felix_fdb_dump,
803 .port_fdb_add = felix_fdb_add,
804 .port_fdb_del = felix_fdb_del,
805 .port_mdb_prepare = felix_mdb_prepare,
806 .port_mdb_add = felix_mdb_add,
807 .port_mdb_del = felix_mdb_del,
808 .port_bridge_join = felix_bridge_join,
809 .port_bridge_leave = felix_bridge_leave,
810 .port_stp_state_set = felix_bridge_stp_state_set,
811 .port_vlan_prepare = felix_vlan_prepare,
812 .port_vlan_filtering = felix_vlan_filtering,
813 .port_vlan_add = felix_vlan_add,
814 .port_vlan_del = felix_vlan_del,
815 .port_hwtstamp_get = felix_hwtstamp_get,
816 .port_hwtstamp_set = felix_hwtstamp_set,
817 .port_rxtstamp = felix_rxtstamp,
818 .port_txtstamp = felix_txtstamp,
819 .port_change_mtu = felix_change_mtu,
820 .port_max_mtu = felix_get_max_mtu,
821 .port_policer_add = felix_port_policer_add,
822 .port_policer_del = felix_port_policer_del,
823 .cls_flower_add = felix_cls_flower_add,
824 .cls_flower_del = felix_cls_flower_del,
825 .cls_flower_stats = felix_cls_flower_stats,
826 .port_setup_tc = felix_port_setup_tc,
827};
828
829static int __init felix_init(void)
830{
831 int err;
832
833 err = pci_register_driver(&felix_vsc9959_pci_driver);
834 if (err)
835 return err;
836
837 err = platform_driver_register(&seville_vsc9953_driver);
838 if (err)
839 return err;
840
841 return 0;
842}
843module_init(felix_init);
844
845static void __exit felix_exit(void)
846{
847 pci_unregister_driver(&felix_vsc9959_pci_driver);
848 platform_driver_unregister(&seville_vsc9953_driver);
849}
850module_exit(felix_exit);
851
852MODULE_DESCRIPTION("Felix Switch driver");
853MODULE_LICENSE("GPL v2");