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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright 2019-2021 NXP Semiconductors
3 *
4 * This is an umbrella module for all network switches that are
5 * register-compatible with Ocelot and that perform I/O to their host CPU
6 * through an NPI (Node Processor Interface) Ethernet port.
7 */
8#include <uapi/linux/if_bridge.h>
9#include <soc/mscc/ocelot_vcap.h>
10#include <soc/mscc/ocelot_qsys.h>
11#include <soc/mscc/ocelot_sys.h>
12#include <soc/mscc/ocelot_dev.h>
13#include <soc/mscc/ocelot_ana.h>
14#include <soc/mscc/ocelot_ptp.h>
15#include <soc/mscc/ocelot.h>
16#include <linux/dsa/8021q.h>
17#include <linux/dsa/ocelot.h>
18#include <linux/platform_device.h>
19#include <linux/ptp_classify.h>
20#include <linux/module.h>
21#include <linux/of_net.h>
22#include <linux/pci.h>
23#include <linux/of.h>
24#include <linux/pcs-lynx.h>
25#include <net/pkt_sched.h>
26#include <net/dsa.h>
27#include "felix.h"
28
29static int felix_tag_8021q_rxvlan_add(struct felix *felix, int port, u16 vid,
30 bool pvid, bool untagged)
31{
32 struct ocelot_vcap_filter *outer_tagging_rule;
33 struct ocelot *ocelot = &felix->ocelot;
34 struct dsa_switch *ds = felix->ds;
35 int key_length, upstream, err;
36
37 /* We don't need to install the rxvlan into the other ports' filtering
38 * tables, because we're just pushing the rxvlan when sending towards
39 * the CPU
40 */
41 if (!pvid)
42 return 0;
43
44 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length;
45 upstream = dsa_upstream_port(ds, port);
46
47 outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter),
48 GFP_KERNEL);
49 if (!outer_tagging_rule)
50 return -ENOMEM;
51
52 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY;
53 outer_tagging_rule->prio = 1;
54 outer_tagging_rule->id.cookie = port;
55 outer_tagging_rule->id.tc_offload = false;
56 outer_tagging_rule->block_id = VCAP_ES0;
57 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
58 outer_tagging_rule->lookup = 0;
59 outer_tagging_rule->ingress_port.value = port;
60 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0);
61 outer_tagging_rule->egress_port.value = upstream;
62 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0);
63 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG;
64 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD;
65 outer_tagging_rule->action.tag_a_vid_sel = 1;
66 outer_tagging_rule->action.vid_a_val = vid;
67
68 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL);
69 if (err)
70 kfree(outer_tagging_rule);
71
72 return err;
73}
74
75static int felix_tag_8021q_txvlan_add(struct felix *felix, int port, u16 vid,
76 bool pvid, bool untagged)
77{
78 struct ocelot_vcap_filter *untagging_rule, *redirect_rule;
79 struct ocelot *ocelot = &felix->ocelot;
80 struct dsa_switch *ds = felix->ds;
81 int upstream, err;
82
83 /* tag_8021q.c assumes we are implementing this via port VLAN
84 * membership, which we aren't. So we don't need to add any VCAP filter
85 * for the CPU port.
86 */
87 if (ocelot->ports[port]->is_dsa_8021q_cpu)
88 return 0;
89
90 untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL);
91 if (!untagging_rule)
92 return -ENOMEM;
93
94 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL);
95 if (!redirect_rule) {
96 kfree(untagging_rule);
97 return -ENOMEM;
98 }
99
100 upstream = dsa_upstream_port(ds, port);
101
102 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY;
103 untagging_rule->ingress_port_mask = BIT(upstream);
104 untagging_rule->vlan.vid.value = vid;
105 untagging_rule->vlan.vid.mask = VLAN_VID_MASK;
106 untagging_rule->prio = 1;
107 untagging_rule->id.cookie = port;
108 untagging_rule->id.tc_offload = false;
109 untagging_rule->block_id = VCAP_IS1;
110 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
111 untagging_rule->lookup = 0;
112 untagging_rule->action.vlan_pop_cnt_ena = true;
113 untagging_rule->action.vlan_pop_cnt = 1;
114 untagging_rule->action.pag_override_mask = 0xff;
115 untagging_rule->action.pag_val = port;
116
117 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL);
118 if (err) {
119 kfree(untagging_rule);
120 kfree(redirect_rule);
121 return err;
122 }
123
124 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY;
125 redirect_rule->ingress_port_mask = BIT(upstream);
126 redirect_rule->pag = port;
127 redirect_rule->prio = 1;
128 redirect_rule->id.cookie = port;
129 redirect_rule->id.tc_offload = false;
130 redirect_rule->block_id = VCAP_IS2;
131 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
132 redirect_rule->lookup = 0;
133 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT;
134 redirect_rule->action.port_mask = BIT(port);
135
136 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL);
137 if (err) {
138 ocelot_vcap_filter_del(ocelot, untagging_rule);
139 kfree(redirect_rule);
140 return err;
141 }
142
143 return 0;
144}
145
146static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
147 u16 flags)
148{
149 bool untagged = flags & BRIDGE_VLAN_INFO_UNTAGGED;
150 bool pvid = flags & BRIDGE_VLAN_INFO_PVID;
151 struct ocelot *ocelot = ds->priv;
152
153 if (vid_is_dsa_8021q_rxvlan(vid))
154 return felix_tag_8021q_rxvlan_add(ocelot_to_felix(ocelot),
155 port, vid, pvid, untagged);
156
157 if (vid_is_dsa_8021q_txvlan(vid))
158 return felix_tag_8021q_txvlan_add(ocelot_to_felix(ocelot),
159 port, vid, pvid, untagged);
160
161 return 0;
162}
163
164static int felix_tag_8021q_rxvlan_del(struct felix *felix, int port, u16 vid)
165{
166 struct ocelot_vcap_filter *outer_tagging_rule;
167 struct ocelot_vcap_block *block_vcap_es0;
168 struct ocelot *ocelot = &felix->ocelot;
169
170 block_vcap_es0 = &ocelot->block[VCAP_ES0];
171
172 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0,
173 port, false);
174 /* In rxvlan_add, we had the "if (!pvid) return 0" logic to avoid
175 * installing outer tagging ES0 rules where they weren't needed.
176 * But in rxvlan_del, the API doesn't give us the "flags" anymore,
177 * so that forces us to be slightly sloppy here, and just assume that
178 * if we didn't find an outer_tagging_rule it means that there was
179 * none in the first place, i.e. rxvlan_del is called on a non-pvid
180 * port. This is most probably true though.
181 */
182 if (!outer_tagging_rule)
183 return 0;
184
185 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule);
186}
187
188static int felix_tag_8021q_txvlan_del(struct felix *felix, int port, u16 vid)
189{
190 struct ocelot_vcap_filter *untagging_rule, *redirect_rule;
191 struct ocelot_vcap_block *block_vcap_is1;
192 struct ocelot_vcap_block *block_vcap_is2;
193 struct ocelot *ocelot = &felix->ocelot;
194 int err;
195
196 if (ocelot->ports[port]->is_dsa_8021q_cpu)
197 return 0;
198
199 block_vcap_is1 = &ocelot->block[VCAP_IS1];
200 block_vcap_is2 = &ocelot->block[VCAP_IS2];
201
202 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1,
203 port, false);
204 if (!untagging_rule)
205 return 0;
206
207 err = ocelot_vcap_filter_del(ocelot, untagging_rule);
208 if (err)
209 return err;
210
211 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2,
212 port, false);
213 if (!redirect_rule)
214 return 0;
215
216 return ocelot_vcap_filter_del(ocelot, redirect_rule);
217}
218
219static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
220{
221 struct ocelot *ocelot = ds->priv;
222
223 if (vid_is_dsa_8021q_rxvlan(vid))
224 return felix_tag_8021q_rxvlan_del(ocelot_to_felix(ocelot),
225 port, vid);
226
227 if (vid_is_dsa_8021q_txvlan(vid))
228 return felix_tag_8021q_txvlan_del(ocelot_to_felix(ocelot),
229 port, vid);
230
231 return 0;
232}
233
234static const struct dsa_8021q_ops felix_tag_8021q_ops = {
235 .vlan_add = felix_tag_8021q_vlan_add,
236 .vlan_del = felix_tag_8021q_vlan_del,
237};
238
239/* Alternatively to using the NPI functionality, that same hardware MAC
240 * connected internally to the enetc or fman DSA master can be configured to
241 * use the software-defined tag_8021q frame format. As far as the hardware is
242 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port
243 * module are now disconnected from it, but can still be accessed through
244 * register-based MMIO.
245 */
246static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port)
247{
248 ocelot->ports[port]->is_dsa_8021q_cpu = true;
249 ocelot->npi = -1;
250
251 /* Overwrite PGID_CPU with the non-tagging port */
252 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, PGID_CPU);
253
254 ocelot_apply_bridge_fwd_mask(ocelot);
255}
256
257static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port)
258{
259 ocelot->ports[port]->is_dsa_8021q_cpu = false;
260
261 /* Restore PGID_CPU */
262 ocelot_write_rix(ocelot, BIT(ocelot->num_phys_ports), ANA_PGID_PGID,
263 PGID_CPU);
264
265 ocelot_apply_bridge_fwd_mask(ocelot);
266}
267
268/* Set up a VCAP IS2 rule for delivering PTP frames to the CPU port module.
269 * If the quirk_no_xtr_irq is in place, then also copy those PTP frames to the
270 * tag_8021q CPU port.
271 */
272static int felix_setup_mmio_filtering(struct felix *felix)
273{
274 unsigned long user_ports = dsa_user_ports(felix->ds);
275 struct ocelot_vcap_filter *redirect_rule;
276 struct ocelot_vcap_filter *tagging_rule;
277 struct ocelot *ocelot = &felix->ocelot;
278 struct dsa_switch *ds = felix->ds;
279 int cpu = -1, port, ret;
280
281 tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL);
282 if (!tagging_rule)
283 return -ENOMEM;
284
285 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL);
286 if (!redirect_rule) {
287 kfree(tagging_rule);
288 return -ENOMEM;
289 }
290
291 for (port = 0; port < ocelot->num_phys_ports; port++) {
292 if (dsa_is_cpu_port(ds, port)) {
293 cpu = port;
294 break;
295 }
296 }
297
298 if (cpu < 0)
299 return -EINVAL;
300
301 tagging_rule->key_type = OCELOT_VCAP_KEY_ETYPE;
302 *(__be16 *)tagging_rule->key.etype.etype.value = htons(ETH_P_1588);
303 *(__be16 *)tagging_rule->key.etype.etype.mask = htons(0xffff);
304 tagging_rule->ingress_port_mask = user_ports;
305 tagging_rule->prio = 1;
306 tagging_rule->id.cookie = ocelot->num_phys_ports;
307 tagging_rule->id.tc_offload = false;
308 tagging_rule->block_id = VCAP_IS1;
309 tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
310 tagging_rule->lookup = 0;
311 tagging_rule->action.pag_override_mask = 0xff;
312 tagging_rule->action.pag_val = ocelot->num_phys_ports;
313
314 ret = ocelot_vcap_filter_add(ocelot, tagging_rule, NULL);
315 if (ret) {
316 kfree(tagging_rule);
317 kfree(redirect_rule);
318 return ret;
319 }
320
321 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY;
322 redirect_rule->ingress_port_mask = user_ports;
323 redirect_rule->pag = ocelot->num_phys_ports;
324 redirect_rule->prio = 1;
325 redirect_rule->id.cookie = ocelot->num_phys_ports;
326 redirect_rule->id.tc_offload = false;
327 redirect_rule->block_id = VCAP_IS2;
328 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
329 redirect_rule->lookup = 0;
330 redirect_rule->action.cpu_copy_ena = true;
331 if (felix->info->quirk_no_xtr_irq) {
332 /* Redirect to the tag_8021q CPU but also copy PTP packets to
333 * the CPU port module
334 */
335 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT;
336 redirect_rule->action.port_mask = BIT(cpu);
337 } else {
338 /* Trap PTP packets only to the CPU port module (which is
339 * redirected to the NPI port)
340 */
341 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
342 redirect_rule->action.port_mask = 0;
343 }
344
345 ret = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL);
346 if (ret) {
347 ocelot_vcap_filter_del(ocelot, tagging_rule);
348 kfree(redirect_rule);
349 return ret;
350 }
351
352 /* The ownership of the CPU port module's queues might have just been
353 * transferred to the tag_8021q tagger from the NPI-based tagger.
354 * So there might still be all sorts of crap in the queues. On the
355 * other hand, the MMIO-based matching of PTP frames is very brittle,
356 * so we need to be careful that there are no extra frames to be
357 * dequeued over MMIO, since we would never know to discard them.
358 */
359 ocelot_drain_cpu_queue(ocelot, 0);
360
361 return 0;
362}
363
364static int felix_teardown_mmio_filtering(struct felix *felix)
365{
366 struct ocelot_vcap_filter *tagging_rule, *redirect_rule;
367 struct ocelot_vcap_block *block_vcap_is1;
368 struct ocelot_vcap_block *block_vcap_is2;
369 struct ocelot *ocelot = &felix->ocelot;
370 int err;
371
372 block_vcap_is1 = &ocelot->block[VCAP_IS1];
373 block_vcap_is2 = &ocelot->block[VCAP_IS2];
374
375 tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1,
376 ocelot->num_phys_ports,
377 false);
378 if (!tagging_rule)
379 return -ENOENT;
380
381 err = ocelot_vcap_filter_del(ocelot, tagging_rule);
382 if (err)
383 return err;
384
385 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2,
386 ocelot->num_phys_ports,
387 false);
388 if (!redirect_rule)
389 return -ENOENT;
390
391 return ocelot_vcap_filter_del(ocelot, redirect_rule);
392}
393
394static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu)
395{
396 struct ocelot *ocelot = ds->priv;
397 struct felix *felix = ocelot_to_felix(ocelot);
398 unsigned long cpu_flood;
399 int port, err;
400
401 felix_8021q_cpu_port_init(ocelot, cpu);
402
403 for (port = 0; port < ds->num_ports; port++) {
404 if (dsa_is_unused_port(ds, port))
405 continue;
406
407 /* This overwrites ocelot_init():
408 * Do not forward BPDU frames to the CPU port module,
409 * for 2 reasons:
410 * - When these packets are injected from the tag_8021q
411 * CPU port, we want them to go out, not loop back
412 * into the system.
413 * - STP traffic ingressing on a user port should go to
414 * the tag_8021q CPU port, not to the hardware CPU
415 * port module.
416 */
417 ocelot_write_gix(ocelot,
418 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0),
419 ANA_PORT_CPU_FWD_BPDU_CFG, port);
420 }
421
422 /* In tag_8021q mode, the CPU port module is unused, except for PTP
423 * frames. So we want to disable flooding of any kind to the CPU port
424 * module, since packets going there will end in a black hole.
425 */
426 cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports));
427 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_UC);
428 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_MC);
429 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_BC);
430
431 felix->dsa_8021q_ctx = kzalloc(sizeof(*felix->dsa_8021q_ctx),
432 GFP_KERNEL);
433 if (!felix->dsa_8021q_ctx)
434 return -ENOMEM;
435
436 felix->dsa_8021q_ctx->ops = &felix_tag_8021q_ops;
437 felix->dsa_8021q_ctx->proto = htons(ETH_P_8021AD);
438 felix->dsa_8021q_ctx->ds = ds;
439
440 err = dsa_8021q_setup(felix->dsa_8021q_ctx, true);
441 if (err)
442 goto out_free_dsa_8021_ctx;
443
444 err = felix_setup_mmio_filtering(felix);
445 if (err)
446 goto out_teardown_dsa_8021q;
447
448 return 0;
449
450out_teardown_dsa_8021q:
451 dsa_8021q_setup(felix->dsa_8021q_ctx, false);
452out_free_dsa_8021_ctx:
453 kfree(felix->dsa_8021q_ctx);
454 return err;
455}
456
457static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu)
458{
459 struct ocelot *ocelot = ds->priv;
460 struct felix *felix = ocelot_to_felix(ocelot);
461 int err, port;
462
463 err = felix_teardown_mmio_filtering(felix);
464 if (err)
465 dev_err(ds->dev, "felix_teardown_mmio_filtering returned %d",
466 err);
467
468 err = dsa_8021q_setup(felix->dsa_8021q_ctx, false);
469 if (err)
470 dev_err(ds->dev, "dsa_8021q_setup returned %d", err);
471
472 kfree(felix->dsa_8021q_ctx);
473
474 for (port = 0; port < ds->num_ports; port++) {
475 if (dsa_is_unused_port(ds, port))
476 continue;
477
478 /* Restore the logic from ocelot_init:
479 * do not forward BPDU frames to the front ports.
480 */
481 ocelot_write_gix(ocelot,
482 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
483 ANA_PORT_CPU_FWD_BPDU_CFG,
484 port);
485 }
486
487 felix_8021q_cpu_port_deinit(ocelot, cpu);
488}
489
490/* The CPU port module is connected to the Node Processor Interface (NPI). This
491 * is the mode through which frames can be injected from and extracted to an
492 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU
493 * running Linux, and this forms a DSA setup together with the enetc or fman
494 * DSA master.
495 */
496static void felix_npi_port_init(struct ocelot *ocelot, int port)
497{
498 ocelot->npi = port;
499
500 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
501 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port),
502 QSYS_EXT_CPU_CFG);
503
504 /* NPI port Injection/Extraction configuration */
505 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR,
506 ocelot->npi_xtr_prefix);
507 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR,
508 ocelot->npi_inj_prefix);
509
510 /* Disable transmission of pause frames */
511 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
512}
513
514static void felix_npi_port_deinit(struct ocelot *ocelot, int port)
515{
516 /* Restore hardware defaults */
517 int unused_port = ocelot->num_phys_ports + 2;
518
519 ocelot->npi = -1;
520
521 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port),
522 QSYS_EXT_CPU_CFG);
523
524 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR,
525 OCELOT_TAG_PREFIX_DISABLED);
526 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR,
527 OCELOT_TAG_PREFIX_DISABLED);
528
529 /* Enable transmission of pause frames */
530 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
531}
532
533static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu)
534{
535 struct ocelot *ocelot = ds->priv;
536 unsigned long cpu_flood;
537
538 felix_npi_port_init(ocelot, cpu);
539
540 /* Include the CPU port module (and indirectly, the NPI port)
541 * in the forwarding mask for unknown unicast - the hardware
542 * default value for ANA_FLOODING_FLD_UNICAST excludes
543 * BIT(ocelot->num_phys_ports), and so does ocelot_init,
544 * since Ocelot relies on whitelisting MAC addresses towards
545 * PGID_CPU.
546 * We do this because DSA does not yet perform RX filtering,
547 * and the NPI port does not perform source address learning,
548 * so traffic sent to Linux is effectively unknown from the
549 * switch's perspective.
550 */
551 cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports));
552 ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ANA_PGID_PGID, PGID_UC);
553 ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ANA_PGID_PGID, PGID_MC);
554 ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ANA_PGID_PGID, PGID_BC);
555
556 return 0;
557}
558
559static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu)
560{
561 struct ocelot *ocelot = ds->priv;
562
563 felix_npi_port_deinit(ocelot, cpu);
564}
565
566static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu,
567 enum dsa_tag_protocol proto)
568{
569 int err;
570
571 switch (proto) {
572 case DSA_TAG_PROTO_SEVILLE:
573 case DSA_TAG_PROTO_OCELOT:
574 err = felix_setup_tag_npi(ds, cpu);
575 break;
576 case DSA_TAG_PROTO_OCELOT_8021Q:
577 err = felix_setup_tag_8021q(ds, cpu);
578 break;
579 default:
580 err = -EPROTONOSUPPORT;
581 }
582
583 return err;
584}
585
586static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu,
587 enum dsa_tag_protocol proto)
588{
589 switch (proto) {
590 case DSA_TAG_PROTO_SEVILLE:
591 case DSA_TAG_PROTO_OCELOT:
592 felix_teardown_tag_npi(ds, cpu);
593 break;
594 case DSA_TAG_PROTO_OCELOT_8021Q:
595 felix_teardown_tag_8021q(ds, cpu);
596 break;
597 default:
598 break;
599 }
600}
601
602/* This always leaves the switch in a consistent state, because although the
603 * tag_8021q setup can fail, the NPI setup can't. So either the change is made,
604 * or the restoration is guaranteed to work.
605 */
606static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu,
607 enum dsa_tag_protocol proto)
608{
609 struct ocelot *ocelot = ds->priv;
610 struct felix *felix = ocelot_to_felix(ocelot);
611 enum dsa_tag_protocol old_proto = felix->tag_proto;
612 int err;
613
614 if (proto != DSA_TAG_PROTO_SEVILLE &&
615 proto != DSA_TAG_PROTO_OCELOT &&
616 proto != DSA_TAG_PROTO_OCELOT_8021Q)
617 return -EPROTONOSUPPORT;
618
619 felix_del_tag_protocol(ds, cpu, old_proto);
620
621 err = felix_set_tag_protocol(ds, cpu, proto);
622 if (err) {
623 felix_set_tag_protocol(ds, cpu, old_proto);
624 return err;
625 }
626
627 felix->tag_proto = proto;
628
629 return 0;
630}
631
632static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
633 int port,
634 enum dsa_tag_protocol mp)
635{
636 struct ocelot *ocelot = ds->priv;
637 struct felix *felix = ocelot_to_felix(ocelot);
638
639 return felix->tag_proto;
640}
641
642static int felix_set_ageing_time(struct dsa_switch *ds,
643 unsigned int ageing_time)
644{
645 struct ocelot *ocelot = ds->priv;
646
647 ocelot_set_ageing_time(ocelot, ageing_time);
648
649 return 0;
650}
651
652static int felix_fdb_dump(struct dsa_switch *ds, int port,
653 dsa_fdb_dump_cb_t *cb, void *data)
654{
655 struct ocelot *ocelot = ds->priv;
656
657 return ocelot_fdb_dump(ocelot, port, cb, data);
658}
659
660static int felix_fdb_add(struct dsa_switch *ds, int port,
661 const unsigned char *addr, u16 vid)
662{
663 struct ocelot *ocelot = ds->priv;
664
665 return ocelot_fdb_add(ocelot, port, addr, vid);
666}
667
668static int felix_fdb_del(struct dsa_switch *ds, int port,
669 const unsigned char *addr, u16 vid)
670{
671 struct ocelot *ocelot = ds->priv;
672
673 return ocelot_fdb_del(ocelot, port, addr, vid);
674}
675
676static int felix_mdb_add(struct dsa_switch *ds, int port,
677 const struct switchdev_obj_port_mdb *mdb)
678{
679 struct ocelot *ocelot = ds->priv;
680
681 return ocelot_port_mdb_add(ocelot, port, mdb);
682}
683
684static int felix_mdb_del(struct dsa_switch *ds, int port,
685 const struct switchdev_obj_port_mdb *mdb)
686{
687 struct ocelot *ocelot = ds->priv;
688
689 return ocelot_port_mdb_del(ocelot, port, mdb);
690}
691
692static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port,
693 u8 state)
694{
695 struct ocelot *ocelot = ds->priv;
696
697 return ocelot_bridge_stp_state_set(ocelot, port, state);
698}
699
700static int felix_pre_bridge_flags(struct dsa_switch *ds, int port,
701 struct switchdev_brport_flags val,
702 struct netlink_ext_ack *extack)
703{
704 struct ocelot *ocelot = ds->priv;
705
706 return ocelot_port_pre_bridge_flags(ocelot, port, val);
707}
708
709static int felix_bridge_flags(struct dsa_switch *ds, int port,
710 struct switchdev_brport_flags val,
711 struct netlink_ext_ack *extack)
712{
713 struct ocelot *ocelot = ds->priv;
714
715 ocelot_port_bridge_flags(ocelot, port, val);
716
717 return 0;
718}
719
720static int felix_bridge_join(struct dsa_switch *ds, int port,
721 struct net_device *br)
722{
723 struct ocelot *ocelot = ds->priv;
724
725 ocelot_port_bridge_join(ocelot, port, br);
726
727 return 0;
728}
729
730static void felix_bridge_leave(struct dsa_switch *ds, int port,
731 struct net_device *br)
732{
733 struct ocelot *ocelot = ds->priv;
734
735 ocelot_port_bridge_leave(ocelot, port, br);
736}
737
738static int felix_lag_join(struct dsa_switch *ds, int port,
739 struct net_device *bond,
740 struct netdev_lag_upper_info *info)
741{
742 struct ocelot *ocelot = ds->priv;
743
744 return ocelot_port_lag_join(ocelot, port, bond, info);
745}
746
747static int felix_lag_leave(struct dsa_switch *ds, int port,
748 struct net_device *bond)
749{
750 struct ocelot *ocelot = ds->priv;
751
752 ocelot_port_lag_leave(ocelot, port, bond);
753
754 return 0;
755}
756
757static int felix_lag_change(struct dsa_switch *ds, int port)
758{
759 struct dsa_port *dp = dsa_to_port(ds, port);
760 struct ocelot *ocelot = ds->priv;
761
762 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled);
763
764 return 0;
765}
766
767static int felix_vlan_prepare(struct dsa_switch *ds, int port,
768 const struct switchdev_obj_port_vlan *vlan)
769{
770 struct ocelot *ocelot = ds->priv;
771 u16 flags = vlan->flags;
772
773 /* Ocelot switches copy frames as-is to the CPU, so the flags:
774 * egress-untagged or not, pvid or not, make no difference. This
775 * behavior is already better than what DSA just tries to approximate
776 * when it installs the VLAN with the same flags on the CPU port.
777 * Just accept any configuration, and don't let ocelot deny installing
778 * multiple native VLANs on the NPI port, because the switch doesn't
779 * look at the port tag settings towards the NPI interface anyway.
780 */
781 if (port == ocelot->npi)
782 return 0;
783
784 return ocelot_vlan_prepare(ocelot, port, vlan->vid,
785 flags & BRIDGE_VLAN_INFO_PVID,
786 flags & BRIDGE_VLAN_INFO_UNTAGGED);
787}
788
789static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
790 struct netlink_ext_ack *extack)
791{
792 struct ocelot *ocelot = ds->priv;
793
794 return ocelot_port_vlan_filtering(ocelot, port, enabled);
795}
796
797static int felix_vlan_add(struct dsa_switch *ds, int port,
798 const struct switchdev_obj_port_vlan *vlan,
799 struct netlink_ext_ack *extack)
800{
801 struct ocelot *ocelot = ds->priv;
802 u16 flags = vlan->flags;
803 int err;
804
805 err = felix_vlan_prepare(ds, port, vlan);
806 if (err)
807 return err;
808
809 return ocelot_vlan_add(ocelot, port, vlan->vid,
810 flags & BRIDGE_VLAN_INFO_PVID,
811 flags & BRIDGE_VLAN_INFO_UNTAGGED);
812}
813
814static int felix_vlan_del(struct dsa_switch *ds, int port,
815 const struct switchdev_obj_port_vlan *vlan)
816{
817 struct ocelot *ocelot = ds->priv;
818
819 return ocelot_vlan_del(ocelot, port, vlan->vid);
820}
821
822static int felix_port_enable(struct dsa_switch *ds, int port,
823 struct phy_device *phy)
824{
825 struct ocelot *ocelot = ds->priv;
826
827 ocelot_port_enable(ocelot, port, phy);
828
829 return 0;
830}
831
832static void felix_port_disable(struct dsa_switch *ds, int port)
833{
834 struct ocelot *ocelot = ds->priv;
835
836 return ocelot_port_disable(ocelot, port);
837}
838
839static void felix_phylink_validate(struct dsa_switch *ds, int port,
840 unsigned long *supported,
841 struct phylink_link_state *state)
842{
843 struct ocelot *ocelot = ds->priv;
844 struct felix *felix = ocelot_to_felix(ocelot);
845
846 if (felix->info->phylink_validate)
847 felix->info->phylink_validate(ocelot, port, supported, state);
848}
849
850static void felix_phylink_mac_config(struct dsa_switch *ds, int port,
851 unsigned int link_an_mode,
852 const struct phylink_link_state *state)
853{
854 struct ocelot *ocelot = ds->priv;
855 struct felix *felix = ocelot_to_felix(ocelot);
856 struct dsa_port *dp = dsa_to_port(ds, port);
857
858 if (felix->pcs[port])
859 phylink_set_pcs(dp->pl, &felix->pcs[port]->pcs);
860}
861
862static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port,
863 unsigned int link_an_mode,
864 phy_interface_t interface)
865{
866 struct ocelot *ocelot = ds->priv;
867 struct ocelot_port *ocelot_port = ocelot->ports[port];
868 int err;
869
870 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
871 DEV_MAC_ENA_CFG);
872
873 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
874
875 err = ocelot_port_flush(ocelot, port);
876 if (err)
877 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
878 port, err);
879
880 /* Put the port in reset. */
881 ocelot_port_writel(ocelot_port,
882 DEV_CLOCK_CFG_MAC_TX_RST |
883 DEV_CLOCK_CFG_MAC_RX_RST |
884 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
885 DEV_CLOCK_CFG);
886}
887
888static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
889 unsigned int link_an_mode,
890 phy_interface_t interface,
891 struct phy_device *phydev,
892 int speed, int duplex,
893 bool tx_pause, bool rx_pause)
894{
895 struct ocelot *ocelot = ds->priv;
896 struct ocelot_port *ocelot_port = ocelot->ports[port];
897 struct felix *felix = ocelot_to_felix(ocelot);
898 u32 mac_fc_cfg;
899
900 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
901 * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is
902 * integrated is that the MAC speed is fixed and it's the PCS who is
903 * performing the rate adaptation, so we have to write "1000Mbps" into
904 * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default
905 * value).
906 */
907 ocelot_port_writel(ocelot_port,
908 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
909 DEV_CLOCK_CFG);
910
911 switch (speed) {
912 case SPEED_10:
913 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);
914 break;
915 case SPEED_100:
916 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);
917 break;
918 case SPEED_1000:
919 case SPEED_2500:
920 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);
921 break;
922 default:
923 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
924 port, speed);
925 return;
926 }
927
928 /* handle Rx pause in all cases, with 2500base-X this is used for rate
929 * adaptation.
930 */
931 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
932
933 if (tx_pause)
934 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
935 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
936 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
937 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
938
939 /* Flow control. Link speed is only used here to evaluate the time
940 * specification in incoming pause frames.
941 */
942 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
943
944 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
945
946 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause);
947
948 /* Undo the effects of felix_phylink_mac_link_down:
949 * enable MAC module
950 */
951 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
952 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
953
954 /* Enable receiving frames on the port, and activate auto-learning of
955 * MAC addresses.
956 */
957 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
958 ANA_PORT_PORT_CFG_RECV_ENA |
959 ANA_PORT_PORT_CFG_PORTID_VAL(port),
960 ANA_PORT_PORT_CFG, port);
961
962 /* Core: Enable port for frame transfer */
963 ocelot_fields_write(ocelot, port,
964 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
965
966 if (felix->info->port_sched_speed_set)
967 felix->info->port_sched_speed_set(ocelot, port, speed);
968}
969
970static void felix_port_qos_map_init(struct ocelot *ocelot, int port)
971{
972 int i;
973
974 ocelot_rmw_gix(ocelot,
975 ANA_PORT_QOS_CFG_QOS_PCP_ENA,
976 ANA_PORT_QOS_CFG_QOS_PCP_ENA,
977 ANA_PORT_QOS_CFG,
978 port);
979
980 for (i = 0; i < OCELOT_NUM_TC * 2; i++) {
981 ocelot_rmw_ix(ocelot,
982 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) |
983 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i),
984 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL |
985 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M,
986 ANA_PORT_PCP_DEI_MAP,
987 port, i);
988 }
989}
990
991static void felix_get_strings(struct dsa_switch *ds, int port,
992 u32 stringset, u8 *data)
993{
994 struct ocelot *ocelot = ds->priv;
995
996 return ocelot_get_strings(ocelot, port, stringset, data);
997}
998
999static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
1000{
1001 struct ocelot *ocelot = ds->priv;
1002
1003 ocelot_get_ethtool_stats(ocelot, port, data);
1004}
1005
1006static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset)
1007{
1008 struct ocelot *ocelot = ds->priv;
1009
1010 return ocelot_get_sset_count(ocelot, port, sset);
1011}
1012
1013static int felix_get_ts_info(struct dsa_switch *ds, int port,
1014 struct ethtool_ts_info *info)
1015{
1016 struct ocelot *ocelot = ds->priv;
1017
1018 return ocelot_get_ts_info(ocelot, port, info);
1019}
1020
1021static int felix_parse_ports_node(struct felix *felix,
1022 struct device_node *ports_node,
1023 phy_interface_t *port_phy_modes)
1024{
1025 struct ocelot *ocelot = &felix->ocelot;
1026 struct device *dev = felix->ocelot.dev;
1027 struct device_node *child;
1028
1029 for_each_available_child_of_node(ports_node, child) {
1030 phy_interface_t phy_mode;
1031 u32 port;
1032 int err;
1033
1034 /* Get switch port number from DT */
1035 if (of_property_read_u32(child, "reg", &port) < 0) {
1036 dev_err(dev, "Port number not defined in device tree "
1037 "(property \"reg\")\n");
1038 of_node_put(child);
1039 return -ENODEV;
1040 }
1041
1042 /* Get PHY mode from DT */
1043 err = of_get_phy_mode(child, &phy_mode);
1044 if (err) {
1045 dev_err(dev, "Failed to read phy-mode or "
1046 "phy-interface-type property for port %d\n",
1047 port);
1048 of_node_put(child);
1049 return -ENODEV;
1050 }
1051
1052 err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode);
1053 if (err < 0) {
1054 dev_err(dev, "Unsupported PHY mode %s on port %d\n",
1055 phy_modes(phy_mode), port);
1056 of_node_put(child);
1057 return err;
1058 }
1059
1060 port_phy_modes[port] = phy_mode;
1061 }
1062
1063 return 0;
1064}
1065
1066static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes)
1067{
1068 struct device *dev = felix->ocelot.dev;
1069 struct device_node *switch_node;
1070 struct device_node *ports_node;
1071 int err;
1072
1073 switch_node = dev->of_node;
1074
1075 ports_node = of_get_child_by_name(switch_node, "ports");
1076 if (!ports_node) {
1077 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1078 return -ENODEV;
1079 }
1080
1081 err = felix_parse_ports_node(felix, ports_node, port_phy_modes);
1082 of_node_put(ports_node);
1083
1084 return err;
1085}
1086
1087static int felix_init_structs(struct felix *felix, int num_phys_ports)
1088{
1089 struct ocelot *ocelot = &felix->ocelot;
1090 phy_interface_t *port_phy_modes;
1091 struct resource res;
1092 int port, i, err;
1093
1094 ocelot->num_phys_ports = num_phys_ports;
1095 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports,
1096 sizeof(struct ocelot_port *), GFP_KERNEL);
1097 if (!ocelot->ports)
1098 return -ENOMEM;
1099
1100 ocelot->map = felix->info->map;
1101 ocelot->stats_layout = felix->info->stats_layout;
1102 ocelot->num_stats = felix->info->num_stats;
1103 ocelot->num_mact_rows = felix->info->num_mact_rows;
1104 ocelot->vcap = felix->info->vcap;
1105 ocelot->ops = felix->info->ops;
1106 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT;
1107 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT;
1108 ocelot->devlink = felix->ds->devlink;
1109
1110 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t),
1111 GFP_KERNEL);
1112 if (!port_phy_modes)
1113 return -ENOMEM;
1114
1115 err = felix_parse_dt(felix, port_phy_modes);
1116 if (err) {
1117 kfree(port_phy_modes);
1118 return err;
1119 }
1120
1121 for (i = 0; i < TARGET_MAX; i++) {
1122 struct regmap *target;
1123
1124 if (!felix->info->target_io_res[i].name)
1125 continue;
1126
1127 memcpy(&res, &felix->info->target_io_res[i], sizeof(res));
1128 res.flags = IORESOURCE_MEM;
1129 res.start += felix->switch_base;
1130 res.end += felix->switch_base;
1131
1132 target = ocelot_regmap_init(ocelot, &res);
1133 if (IS_ERR(target)) {
1134 dev_err(ocelot->dev,
1135 "Failed to map device memory space\n");
1136 kfree(port_phy_modes);
1137 return PTR_ERR(target);
1138 }
1139
1140 ocelot->targets[i] = target;
1141 }
1142
1143 err = ocelot_regfields_init(ocelot, felix->info->regfields);
1144 if (err) {
1145 dev_err(ocelot->dev, "failed to init reg fields map\n");
1146 kfree(port_phy_modes);
1147 return err;
1148 }
1149
1150 for (port = 0; port < num_phys_ports; port++) {
1151 struct ocelot_port *ocelot_port;
1152 struct regmap *target;
1153
1154 ocelot_port = devm_kzalloc(ocelot->dev,
1155 sizeof(struct ocelot_port),
1156 GFP_KERNEL);
1157 if (!ocelot_port) {
1158 dev_err(ocelot->dev,
1159 "failed to allocate port memory\n");
1160 kfree(port_phy_modes);
1161 return -ENOMEM;
1162 }
1163
1164 memcpy(&res, &felix->info->port_io_res[port], sizeof(res));
1165 res.flags = IORESOURCE_MEM;
1166 res.start += felix->switch_base;
1167 res.end += felix->switch_base;
1168
1169 target = ocelot_regmap_init(ocelot, &res);
1170 if (IS_ERR(target)) {
1171 dev_err(ocelot->dev,
1172 "Failed to map memory space for port %d\n",
1173 port);
1174 kfree(port_phy_modes);
1175 return PTR_ERR(target);
1176 }
1177
1178 ocelot_port->phy_mode = port_phy_modes[port];
1179 ocelot_port->ocelot = ocelot;
1180 ocelot_port->target = target;
1181 ocelot->ports[port] = ocelot_port;
1182 }
1183
1184 kfree(port_phy_modes);
1185
1186 if (felix->info->mdio_bus_alloc) {
1187 err = felix->info->mdio_bus_alloc(ocelot);
1188 if (err < 0)
1189 return err;
1190 }
1191
1192 return 0;
1193}
1194
1195/* Hardware initialization done here so that we can allocate structures with
1196 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing
1197 * us to allocate structures twice (leak memory) and map PCI memory twice
1198 * (which will not work).
1199 */
1200static int felix_setup(struct dsa_switch *ds)
1201{
1202 struct ocelot *ocelot = ds->priv;
1203 struct felix *felix = ocelot_to_felix(ocelot);
1204 int port, err;
1205
1206 err = felix_init_structs(felix, ds->num_ports);
1207 if (err)
1208 return err;
1209
1210 err = ocelot_init(ocelot);
1211 if (err)
1212 goto out_mdiobus_free;
1213
1214 if (ocelot->ptp) {
1215 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps);
1216 if (err) {
1217 dev_err(ocelot->dev,
1218 "Timestamp initialization failed\n");
1219 ocelot->ptp = 0;
1220 }
1221 }
1222
1223 for (port = 0; port < ds->num_ports; port++) {
1224 if (dsa_is_unused_port(ds, port))
1225 continue;
1226
1227 ocelot_init_port(ocelot, port);
1228
1229 /* Set the default QoS Classification based on PCP and DEI
1230 * bits of vlan tag.
1231 */
1232 felix_port_qos_map_init(ocelot, port);
1233 }
1234
1235 err = ocelot_devlink_sb_register(ocelot);
1236 if (err)
1237 goto out_deinit_ports;
1238
1239 for (port = 0; port < ds->num_ports; port++) {
1240 if (!dsa_is_cpu_port(ds, port))
1241 continue;
1242
1243 /* The initial tag protocol is NPI which always returns 0, so
1244 * there's no real point in checking for errors.
1245 */
1246 felix_set_tag_protocol(ds, port, felix->tag_proto);
1247 break;
1248 }
1249
1250 ds->mtu_enforcement_ingress = true;
1251 ds->assisted_learning_on_cpu_port = true;
1252
1253 return 0;
1254
1255out_deinit_ports:
1256 for (port = 0; port < ocelot->num_phys_ports; port++) {
1257 if (dsa_is_unused_port(ds, port))
1258 continue;
1259
1260 ocelot_deinit_port(ocelot, port);
1261 }
1262
1263 ocelot_deinit_timestamp(ocelot);
1264 ocelot_deinit(ocelot);
1265
1266out_mdiobus_free:
1267 if (felix->info->mdio_bus_free)
1268 felix->info->mdio_bus_free(ocelot);
1269
1270 return err;
1271}
1272
1273static void felix_teardown(struct dsa_switch *ds)
1274{
1275 struct ocelot *ocelot = ds->priv;
1276 struct felix *felix = ocelot_to_felix(ocelot);
1277 int port;
1278
1279 for (port = 0; port < ds->num_ports; port++) {
1280 if (!dsa_is_cpu_port(ds, port))
1281 continue;
1282
1283 felix_del_tag_protocol(ds, port, felix->tag_proto);
1284 break;
1285 }
1286
1287 ocelot_devlink_sb_unregister(ocelot);
1288 ocelot_deinit_timestamp(ocelot);
1289 ocelot_deinit(ocelot);
1290
1291 for (port = 0; port < ocelot->num_phys_ports; port++) {
1292 if (dsa_is_unused_port(ds, port))
1293 continue;
1294
1295 ocelot_deinit_port(ocelot, port);
1296 }
1297
1298 if (felix->info->mdio_bus_free)
1299 felix->info->mdio_bus_free(ocelot);
1300}
1301
1302static int felix_hwtstamp_get(struct dsa_switch *ds, int port,
1303 struct ifreq *ifr)
1304{
1305 struct ocelot *ocelot = ds->priv;
1306
1307 return ocelot_hwstamp_get(ocelot, port, ifr);
1308}
1309
1310static int felix_hwtstamp_set(struct dsa_switch *ds, int port,
1311 struct ifreq *ifr)
1312{
1313 struct ocelot *ocelot = ds->priv;
1314
1315 return ocelot_hwstamp_set(ocelot, port, ifr);
1316}
1317
1318static bool felix_check_xtr_pkt(struct ocelot *ocelot, unsigned int ptp_type)
1319{
1320 struct felix *felix = ocelot_to_felix(ocelot);
1321 int err, grp = 0;
1322
1323 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q)
1324 return false;
1325
1326 if (!felix->info->quirk_no_xtr_irq)
1327 return false;
1328
1329 if (ptp_type == PTP_CLASS_NONE)
1330 return false;
1331
1332 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) {
1333 struct sk_buff *skb;
1334 unsigned int type;
1335
1336 err = ocelot_xtr_poll_frame(ocelot, grp, &skb);
1337 if (err)
1338 goto out;
1339
1340 /* We trap to the CPU port module all PTP frames, but
1341 * felix_rxtstamp() only gets called for event frames.
1342 * So we need to avoid sending duplicate general
1343 * message frames by running a second BPF classifier
1344 * here and dropping those.
1345 */
1346 __skb_push(skb, ETH_HLEN);
1347
1348 type = ptp_classify_raw(skb);
1349
1350 __skb_pull(skb, ETH_HLEN);
1351
1352 if (type == PTP_CLASS_NONE) {
1353 kfree_skb(skb);
1354 continue;
1355 }
1356
1357 netif_rx(skb);
1358 }
1359
1360out:
1361 if (err < 0)
1362 ocelot_drain_cpu_queue(ocelot, 0);
1363
1364 return true;
1365}
1366
1367static bool felix_rxtstamp(struct dsa_switch *ds, int port,
1368 struct sk_buff *skb, unsigned int type)
1369{
1370 u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN;
1371 struct skb_shared_hwtstamps *shhwtstamps;
1372 struct ocelot *ocelot = ds->priv;
1373 u32 tstamp_lo, tstamp_hi;
1374 struct timespec64 ts;
1375 u64 tstamp, val;
1376
1377 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb
1378 * for RX timestamping. Then free it, and poll for its copy through
1379 * MMIO in the CPU port module, and inject that into the stack from
1380 * ocelot_xtr_poll().
1381 */
1382 if (felix_check_xtr_pkt(ocelot, type)) {
1383 kfree_skb(skb);
1384 return true;
1385 }
1386
1387 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1388 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
1389
1390 ocelot_xfh_get_rew_val(extraction, &val);
1391 tstamp_lo = (u32)val;
1392
1393 tstamp_hi = tstamp >> 32;
1394 if ((tstamp & 0xffffffff) < tstamp_lo)
1395 tstamp_hi--;
1396
1397 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo;
1398
1399 shhwtstamps = skb_hwtstamps(skb);
1400 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1401 shhwtstamps->hwtstamp = tstamp;
1402 return false;
1403}
1404
1405static void felix_txtstamp(struct dsa_switch *ds, int port,
1406 struct sk_buff *skb)
1407{
1408 struct ocelot *ocelot = ds->priv;
1409 struct sk_buff *clone = NULL;
1410
1411 if (!ocelot->ptp)
1412 return;
1413
1414 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) {
1415 dev_err_ratelimited(ds->dev,
1416 "port %d delivering skb without TX timestamp\n",
1417 port);
1418 return;
1419 }
1420
1421 if (clone)
1422 OCELOT_SKB_CB(skb)->clone = clone;
1423}
1424
1425static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1426{
1427 struct ocelot *ocelot = ds->priv;
1428
1429 ocelot_port_set_maxlen(ocelot, port, new_mtu);
1430
1431 return 0;
1432}
1433
1434static int felix_get_max_mtu(struct dsa_switch *ds, int port)
1435{
1436 struct ocelot *ocelot = ds->priv;
1437
1438 return ocelot_get_max_mtu(ocelot, port);
1439}
1440
1441static int felix_cls_flower_add(struct dsa_switch *ds, int port,
1442 struct flow_cls_offload *cls, bool ingress)
1443{
1444 struct ocelot *ocelot = ds->priv;
1445
1446 return ocelot_cls_flower_replace(ocelot, port, cls, ingress);
1447}
1448
1449static int felix_cls_flower_del(struct dsa_switch *ds, int port,
1450 struct flow_cls_offload *cls, bool ingress)
1451{
1452 struct ocelot *ocelot = ds->priv;
1453
1454 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress);
1455}
1456
1457static int felix_cls_flower_stats(struct dsa_switch *ds, int port,
1458 struct flow_cls_offload *cls, bool ingress)
1459{
1460 struct ocelot *ocelot = ds->priv;
1461
1462 return ocelot_cls_flower_stats(ocelot, port, cls, ingress);
1463}
1464
1465static int felix_port_policer_add(struct dsa_switch *ds, int port,
1466 struct dsa_mall_policer_tc_entry *policer)
1467{
1468 struct ocelot *ocelot = ds->priv;
1469 struct ocelot_policer pol = {
1470 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8,
1471 .burst = policer->burst,
1472 };
1473
1474 return ocelot_port_policer_add(ocelot, port, &pol);
1475}
1476
1477static void felix_port_policer_del(struct dsa_switch *ds, int port)
1478{
1479 struct ocelot *ocelot = ds->priv;
1480
1481 ocelot_port_policer_del(ocelot, port);
1482}
1483
1484static int felix_port_setup_tc(struct dsa_switch *ds, int port,
1485 enum tc_setup_type type,
1486 void *type_data)
1487{
1488 struct ocelot *ocelot = ds->priv;
1489 struct felix *felix = ocelot_to_felix(ocelot);
1490
1491 if (felix->info->port_setup_tc)
1492 return felix->info->port_setup_tc(ds, port, type, type_data);
1493 else
1494 return -EOPNOTSUPP;
1495}
1496
1497static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index,
1498 u16 pool_index,
1499 struct devlink_sb_pool_info *pool_info)
1500{
1501 struct ocelot *ocelot = ds->priv;
1502
1503 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info);
1504}
1505
1506static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index,
1507 u16 pool_index, u32 size,
1508 enum devlink_sb_threshold_type threshold_type,
1509 struct netlink_ext_ack *extack)
1510{
1511 struct ocelot *ocelot = ds->priv;
1512
1513 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size,
1514 threshold_type, extack);
1515}
1516
1517static int felix_sb_port_pool_get(struct dsa_switch *ds, int port,
1518 unsigned int sb_index, u16 pool_index,
1519 u32 *p_threshold)
1520{
1521 struct ocelot *ocelot = ds->priv;
1522
1523 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index,
1524 p_threshold);
1525}
1526
1527static int felix_sb_port_pool_set(struct dsa_switch *ds, int port,
1528 unsigned int sb_index, u16 pool_index,
1529 u32 threshold, struct netlink_ext_ack *extack)
1530{
1531 struct ocelot *ocelot = ds->priv;
1532
1533 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index,
1534 threshold, extack);
1535}
1536
1537static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port,
1538 unsigned int sb_index, u16 tc_index,
1539 enum devlink_sb_pool_type pool_type,
1540 u16 *p_pool_index, u32 *p_threshold)
1541{
1542 struct ocelot *ocelot = ds->priv;
1543
1544 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index,
1545 pool_type, p_pool_index,
1546 p_threshold);
1547}
1548
1549static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port,
1550 unsigned int sb_index, u16 tc_index,
1551 enum devlink_sb_pool_type pool_type,
1552 u16 pool_index, u32 threshold,
1553 struct netlink_ext_ack *extack)
1554{
1555 struct ocelot *ocelot = ds->priv;
1556
1557 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index,
1558 pool_type, pool_index, threshold,
1559 extack);
1560}
1561
1562static int felix_sb_occ_snapshot(struct dsa_switch *ds,
1563 unsigned int sb_index)
1564{
1565 struct ocelot *ocelot = ds->priv;
1566
1567 return ocelot_sb_occ_snapshot(ocelot, sb_index);
1568}
1569
1570static int felix_sb_occ_max_clear(struct dsa_switch *ds,
1571 unsigned int sb_index)
1572{
1573 struct ocelot *ocelot = ds->priv;
1574
1575 return ocelot_sb_occ_max_clear(ocelot, sb_index);
1576}
1577
1578static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port,
1579 unsigned int sb_index, u16 pool_index,
1580 u32 *p_cur, u32 *p_max)
1581{
1582 struct ocelot *ocelot = ds->priv;
1583
1584 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index,
1585 p_cur, p_max);
1586}
1587
1588static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port,
1589 unsigned int sb_index, u16 tc_index,
1590 enum devlink_sb_pool_type pool_type,
1591 u32 *p_cur, u32 *p_max)
1592{
1593 struct ocelot *ocelot = ds->priv;
1594
1595 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index,
1596 pool_type, p_cur, p_max);
1597}
1598
1599static int felix_mrp_add(struct dsa_switch *ds, int port,
1600 const struct switchdev_obj_mrp *mrp)
1601{
1602 struct ocelot *ocelot = ds->priv;
1603
1604 return ocelot_mrp_add(ocelot, port, mrp);
1605}
1606
1607static int felix_mrp_del(struct dsa_switch *ds, int port,
1608 const struct switchdev_obj_mrp *mrp)
1609{
1610 struct ocelot *ocelot = ds->priv;
1611
1612 return ocelot_mrp_add(ocelot, port, mrp);
1613}
1614
1615static int
1616felix_mrp_add_ring_role(struct dsa_switch *ds, int port,
1617 const struct switchdev_obj_ring_role_mrp *mrp)
1618{
1619 struct ocelot *ocelot = ds->priv;
1620
1621 return ocelot_mrp_add_ring_role(ocelot, port, mrp);
1622}
1623
1624static int
1625felix_mrp_del_ring_role(struct dsa_switch *ds, int port,
1626 const struct switchdev_obj_ring_role_mrp *mrp)
1627{
1628 struct ocelot *ocelot = ds->priv;
1629
1630 return ocelot_mrp_del_ring_role(ocelot, port, mrp);
1631}
1632
1633const struct dsa_switch_ops felix_switch_ops = {
1634 .get_tag_protocol = felix_get_tag_protocol,
1635 .change_tag_protocol = felix_change_tag_protocol,
1636 .setup = felix_setup,
1637 .teardown = felix_teardown,
1638 .set_ageing_time = felix_set_ageing_time,
1639 .get_strings = felix_get_strings,
1640 .get_ethtool_stats = felix_get_ethtool_stats,
1641 .get_sset_count = felix_get_sset_count,
1642 .get_ts_info = felix_get_ts_info,
1643 .phylink_validate = felix_phylink_validate,
1644 .phylink_mac_config = felix_phylink_mac_config,
1645 .phylink_mac_link_down = felix_phylink_mac_link_down,
1646 .phylink_mac_link_up = felix_phylink_mac_link_up,
1647 .port_enable = felix_port_enable,
1648 .port_disable = felix_port_disable,
1649 .port_fdb_dump = felix_fdb_dump,
1650 .port_fdb_add = felix_fdb_add,
1651 .port_fdb_del = felix_fdb_del,
1652 .port_mdb_add = felix_mdb_add,
1653 .port_mdb_del = felix_mdb_del,
1654 .port_pre_bridge_flags = felix_pre_bridge_flags,
1655 .port_bridge_flags = felix_bridge_flags,
1656 .port_bridge_join = felix_bridge_join,
1657 .port_bridge_leave = felix_bridge_leave,
1658 .port_lag_join = felix_lag_join,
1659 .port_lag_leave = felix_lag_leave,
1660 .port_lag_change = felix_lag_change,
1661 .port_stp_state_set = felix_bridge_stp_state_set,
1662 .port_vlan_filtering = felix_vlan_filtering,
1663 .port_vlan_add = felix_vlan_add,
1664 .port_vlan_del = felix_vlan_del,
1665 .port_hwtstamp_get = felix_hwtstamp_get,
1666 .port_hwtstamp_set = felix_hwtstamp_set,
1667 .port_rxtstamp = felix_rxtstamp,
1668 .port_txtstamp = felix_txtstamp,
1669 .port_change_mtu = felix_change_mtu,
1670 .port_max_mtu = felix_get_max_mtu,
1671 .port_policer_add = felix_port_policer_add,
1672 .port_policer_del = felix_port_policer_del,
1673 .cls_flower_add = felix_cls_flower_add,
1674 .cls_flower_del = felix_cls_flower_del,
1675 .cls_flower_stats = felix_cls_flower_stats,
1676 .port_setup_tc = felix_port_setup_tc,
1677 .devlink_sb_pool_get = felix_sb_pool_get,
1678 .devlink_sb_pool_set = felix_sb_pool_set,
1679 .devlink_sb_port_pool_get = felix_sb_port_pool_get,
1680 .devlink_sb_port_pool_set = felix_sb_port_pool_set,
1681 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get,
1682 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set,
1683 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot,
1684 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear,
1685 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get,
1686 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get,
1687 .port_mrp_add = felix_mrp_add,
1688 .port_mrp_del = felix_mrp_del,
1689 .port_mrp_add_ring_role = felix_mrp_add_ring_role,
1690 .port_mrp_del_ring_role = felix_mrp_del_ring_role,
1691};
1692
1693struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port)
1694{
1695 struct felix *felix = ocelot_to_felix(ocelot);
1696 struct dsa_switch *ds = felix->ds;
1697
1698 if (!dsa_is_user_port(ds, port))
1699 return NULL;
1700
1701 return dsa_to_port(ds, port)->slave;
1702}
1703
1704int felix_netdev_to_port(struct net_device *dev)
1705{
1706 struct dsa_port *dp;
1707
1708 dp = dsa_port_from_netdev(dev);
1709 if (IS_ERR(dp))
1710 return -EINVAL;
1711
1712 return dp->index;
1713}