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1/*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36#include <linux/bitops.h>
37#include <linux/clk.h>
38#include <linux/err.h>
39#include <linux/gpio/driver.h>
40#include <linux/gpio/consumer.h>
41#include <linux/gpio/machine.h>
42#include <linux/init.h>
43#include <linux/io.h>
44#include <linux/irq.h>
45#include <linux/irqchip/chained_irq.h>
46#include <linux/irqdomain.h>
47#include <linux/mfd/syscon.h>
48#include <linux/of_device.h>
49#include <linux/pinctrl/consumer.h>
50#include <linux/platform_device.h>
51#include <linux/pwm.h>
52#include <linux/regmap.h>
53#include <linux/slab.h>
54
55/*
56 * GPIO unit register offsets.
57 */
58#define GPIO_OUT_OFF 0x0000
59#define GPIO_IO_CONF_OFF 0x0004
60#define GPIO_BLINK_EN_OFF 0x0008
61#define GPIO_IN_POL_OFF 0x000c
62#define GPIO_DATA_IN_OFF 0x0010
63#define GPIO_EDGE_CAUSE_OFF 0x0014
64#define GPIO_EDGE_MASK_OFF 0x0018
65#define GPIO_LEVEL_MASK_OFF 0x001c
66#define GPIO_BLINK_CNT_SELECT_OFF 0x0020
67
68/*
69 * PWM register offsets.
70 */
71#define PWM_BLINK_ON_DURATION_OFF 0x0
72#define PWM_BLINK_OFF_DURATION_OFF 0x4
73
74
75/* The MV78200 has per-CPU registers for edge mask and level mask */
76#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
77#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
78
79/*
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
81 * mask and interrupt level mask. Those are relative to the
82 * percpu_membase.
83 */
84#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
85#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
86#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
87
88#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
89#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
90#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
91#define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
92
93#define MVEBU_MAX_GPIO_PER_BANK 32
94
95struct mvebu_pwm {
96 void __iomem *membase;
97 unsigned long clk_rate;
98 struct gpio_desc *gpiod;
99 struct pwm_chip chip;
100 spinlock_t lock;
101 struct mvebu_gpio_chip *mvchip;
102
103 /* Used to preserve GPIO/PWM registers across suspend/resume */
104 u32 blink_select;
105 u32 blink_on_duration;
106 u32 blink_off_duration;
107};
108
109struct mvebu_gpio_chip {
110 struct gpio_chip chip;
111 struct regmap *regs;
112 u32 offset;
113 struct regmap *percpu_regs;
114 int irqbase;
115 struct irq_domain *domain;
116 int soc_variant;
117
118 /* Used for PWM support */
119 struct clk *clk;
120 struct mvebu_pwm *mvpwm;
121
122 /* Used to preserve GPIO registers across suspend/resume */
123 u32 out_reg;
124 u32 io_conf_reg;
125 u32 blink_en_reg;
126 u32 in_pol_reg;
127 u32 edge_mask_regs[4];
128 u32 level_mask_regs[4];
129};
130
131/*
132 * Functions returning addresses of individual registers for a given
133 * GPIO controller.
134 */
135
136static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
137 struct regmap **map, unsigned int *offset)
138{
139 int cpu;
140
141 switch (mvchip->soc_variant) {
142 case MVEBU_GPIO_SOC_VARIANT_ORION:
143 case MVEBU_GPIO_SOC_VARIANT_MV78200:
144 case MVEBU_GPIO_SOC_VARIANT_A8K:
145 *map = mvchip->regs;
146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
147 break;
148 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
149 cpu = smp_processor_id();
150 *map = mvchip->percpu_regs;
151 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
152 break;
153 default:
154 BUG();
155 }
156}
157
158static u32
159mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
160{
161 struct regmap *map;
162 unsigned int offset;
163 u32 val;
164
165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
166 regmap_read(map, offset, &val);
167
168 return val;
169}
170
171static void
172mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
173{
174 struct regmap *map;
175 unsigned int offset;
176
177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
178 regmap_write(map, offset, val);
179}
180
181static inline void
182mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
183 struct regmap **map, unsigned int *offset)
184{
185 int cpu;
186
187 switch (mvchip->soc_variant) {
188 case MVEBU_GPIO_SOC_VARIANT_ORION:
189 case MVEBU_GPIO_SOC_VARIANT_A8K:
190 *map = mvchip->regs;
191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
192 break;
193 case MVEBU_GPIO_SOC_VARIANT_MV78200:
194 cpu = smp_processor_id();
195 *map = mvchip->regs;
196 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
197 break;
198 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
199 cpu = smp_processor_id();
200 *map = mvchip->percpu_regs;
201 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
202 break;
203 default:
204 BUG();
205 }
206}
207
208static u32
209mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
210{
211 struct regmap *map;
212 unsigned int offset;
213 u32 val;
214
215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
216 regmap_read(map, offset, &val);
217
218 return val;
219}
220
221static void
222mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
223{
224 struct regmap *map;
225 unsigned int offset;
226
227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
228 regmap_write(map, offset, val);
229}
230
231static void
232mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
233 struct regmap **map, unsigned int *offset)
234{
235 int cpu;
236
237 switch (mvchip->soc_variant) {
238 case MVEBU_GPIO_SOC_VARIANT_ORION:
239 case MVEBU_GPIO_SOC_VARIANT_A8K:
240 *map = mvchip->regs;
241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
242 break;
243 case MVEBU_GPIO_SOC_VARIANT_MV78200:
244 cpu = smp_processor_id();
245 *map = mvchip->regs;
246 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
247 break;
248 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
249 cpu = smp_processor_id();
250 *map = mvchip->percpu_regs;
251 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
252 break;
253 default:
254 BUG();
255 }
256}
257
258static u32
259mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
260{
261 struct regmap *map;
262 unsigned int offset;
263 u32 val;
264
265 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
266 regmap_read(map, offset, &val);
267
268 return val;
269}
270
271static void
272mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
273{
274 struct regmap *map;
275 unsigned int offset;
276
277 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
278 regmap_write(map, offset, val);
279}
280
281/*
282 * Functions returning addresses of individual registers for a given
283 * PWM controller.
284 */
285static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
286{
287 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
288}
289
290static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
291{
292 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
293}
294
295/*
296 * Functions implementing the gpio_chip methods
297 */
298static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
299{
300 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
301
302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
303 BIT(pin), value ? BIT(pin) : 0);
304}
305
306static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
307{
308 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
309 u32 u;
310
311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
312
313 if (u & BIT(pin)) {
314 u32 data_in, in_pol;
315
316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
317 &data_in);
318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
319 &in_pol);
320 u = data_in ^ in_pol;
321 } else {
322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
323 }
324
325 return (u >> pin) & 1;
326}
327
328static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
329 int value)
330{
331 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
332
333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
334 BIT(pin), value ? BIT(pin) : 0);
335}
336
337static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
338{
339 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
340 int ret;
341
342 /*
343 * Check with the pinctrl driver whether this pin is usable as
344 * an input GPIO
345 */
346 ret = pinctrl_gpio_direction_input(chip->base + pin);
347 if (ret)
348 return ret;
349
350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
351 BIT(pin), BIT(pin));
352
353 return 0;
354}
355
356static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
357 int value)
358{
359 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
360 int ret;
361
362 /*
363 * Check with the pinctrl driver whether this pin is usable as
364 * an output GPIO
365 */
366 ret = pinctrl_gpio_direction_output(chip->base + pin);
367 if (ret)
368 return ret;
369
370 mvebu_gpio_blink(chip, pin, 0);
371 mvebu_gpio_set(chip, pin, value);
372
373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
374 BIT(pin), 0);
375
376 return 0;
377}
378
379static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
380{
381 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
382 u32 u;
383
384 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
385
386 if (u & BIT(pin))
387 return GPIO_LINE_DIRECTION_IN;
388
389 return GPIO_LINE_DIRECTION_OUT;
390}
391
392static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
393{
394 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
395
396 return irq_create_mapping(mvchip->domain, pin);
397}
398
399/*
400 * Functions implementing the irq_chip methods
401 */
402static void mvebu_gpio_irq_ack(struct irq_data *d)
403{
404 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
405 struct mvebu_gpio_chip *mvchip = gc->private;
406 u32 mask = d->mask;
407
408 irq_gc_lock(gc);
409 mvebu_gpio_write_edge_cause(mvchip, ~mask);
410 irq_gc_unlock(gc);
411}
412
413static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
414{
415 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
416 struct mvebu_gpio_chip *mvchip = gc->private;
417 struct irq_chip_type *ct = irq_data_get_chip_type(d);
418 u32 mask = d->mask;
419
420 irq_gc_lock(gc);
421 ct->mask_cache_priv &= ~mask;
422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
423 irq_gc_unlock(gc);
424}
425
426static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
427{
428 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
429 struct mvebu_gpio_chip *mvchip = gc->private;
430 struct irq_chip_type *ct = irq_data_get_chip_type(d);
431 u32 mask = d->mask;
432
433 irq_gc_lock(gc);
434 mvebu_gpio_write_edge_cause(mvchip, ~mask);
435 ct->mask_cache_priv |= mask;
436 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
437 irq_gc_unlock(gc);
438}
439
440static void mvebu_gpio_level_irq_mask(struct irq_data *d)
441{
442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
443 struct mvebu_gpio_chip *mvchip = gc->private;
444 struct irq_chip_type *ct = irq_data_get_chip_type(d);
445 u32 mask = d->mask;
446
447 irq_gc_lock(gc);
448 ct->mask_cache_priv &= ~mask;
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
450 irq_gc_unlock(gc);
451}
452
453static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
454{
455 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
456 struct mvebu_gpio_chip *mvchip = gc->private;
457 struct irq_chip_type *ct = irq_data_get_chip_type(d);
458 u32 mask = d->mask;
459
460 irq_gc_lock(gc);
461 ct->mask_cache_priv |= mask;
462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
463 irq_gc_unlock(gc);
464}
465
466/*****************************************************************************
467 * MVEBU GPIO IRQ
468 *
469 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
470 * value of the line or the opposite value.
471 *
472 * Level IRQ handlers: DATA_IN is used directly as cause register.
473 * Interrupt are masked by LEVEL_MASK registers.
474 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
475 * Interrupt are masked by EDGE_MASK registers.
476 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
477 * the polarity to catch the next line transaction.
478 * This is a race condition that might not perfectly
479 * work on some use cases.
480 *
481 * Every eight GPIO lines are grouped (OR'ed) before going up to main
482 * cause register.
483 *
484 * EDGE cause mask
485 * data-in /--------| |-----| |----\
486 * -----| |----- ---- to main cause reg
487 * X \----------------| |----/
488 * polarity LEVEL mask
489 *
490 ****************************************************************************/
491
492static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
493{
494 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
495 struct irq_chip_type *ct = irq_data_get_chip_type(d);
496 struct mvebu_gpio_chip *mvchip = gc->private;
497 int pin;
498 u32 u;
499
500 pin = d->hwirq;
501
502 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
503 if ((u & BIT(pin)) == 0)
504 return -EINVAL;
505
506 type &= IRQ_TYPE_SENSE_MASK;
507 if (type == IRQ_TYPE_NONE)
508 return -EINVAL;
509
510 /* Check if we need to change chip and handler */
511 if (!(ct->type & type))
512 if (irq_setup_alt_chip(d, type))
513 return -EINVAL;
514
515 /*
516 * Configure interrupt polarity.
517 */
518 switch (type) {
519 case IRQ_TYPE_EDGE_RISING:
520 case IRQ_TYPE_LEVEL_HIGH:
521 regmap_update_bits(mvchip->regs,
522 GPIO_IN_POL_OFF + mvchip->offset,
523 BIT(pin), 0);
524 break;
525 case IRQ_TYPE_EDGE_FALLING:
526 case IRQ_TYPE_LEVEL_LOW:
527 regmap_update_bits(mvchip->regs,
528 GPIO_IN_POL_OFF + mvchip->offset,
529 BIT(pin), BIT(pin));
530 break;
531 case IRQ_TYPE_EDGE_BOTH: {
532 u32 data_in, in_pol, val;
533
534 regmap_read(mvchip->regs,
535 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
536 regmap_read(mvchip->regs,
537 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
538
539 /*
540 * set initial polarity based on current input level
541 */
542 if ((data_in ^ in_pol) & BIT(pin))
543 val = BIT(pin); /* falling */
544 else
545 val = 0; /* raising */
546
547 regmap_update_bits(mvchip->regs,
548 GPIO_IN_POL_OFF + mvchip->offset,
549 BIT(pin), val);
550 break;
551 }
552 }
553 return 0;
554}
555
556static void mvebu_gpio_irq_handler(struct irq_desc *desc)
557{
558 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
559 struct irq_chip *chip = irq_desc_get_chip(desc);
560 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
561 int i;
562
563 if (mvchip == NULL)
564 return;
565
566 chained_irq_enter(chip, desc);
567
568 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
569 level_mask = mvebu_gpio_read_level_mask(mvchip);
570 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
571 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
572
573 cause = (data_in & level_mask) | (edge_cause & edge_mask);
574
575 for (i = 0; i < mvchip->chip.ngpio; i++) {
576 int irq;
577
578 irq = irq_find_mapping(mvchip->domain, i);
579
580 if (!(cause & BIT(i)))
581 continue;
582
583 type = irq_get_trigger_type(irq);
584 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
585 /* Swap polarity (race with GPIO line) */
586 u32 polarity;
587
588 regmap_read(mvchip->regs,
589 GPIO_IN_POL_OFF + mvchip->offset,
590 &polarity);
591 polarity ^= BIT(i);
592 regmap_write(mvchip->regs,
593 GPIO_IN_POL_OFF + mvchip->offset,
594 polarity);
595 }
596
597 generic_handle_irq(irq);
598 }
599
600 chained_irq_exit(chip, desc);
601}
602
603/*
604 * Functions implementing the pwm_chip methods
605 */
606static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
607{
608 return container_of(chip, struct mvebu_pwm, chip);
609}
610
611static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
612{
613 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
614 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
615 struct gpio_desc *desc;
616 unsigned long flags;
617 int ret = 0;
618
619 spin_lock_irqsave(&mvpwm->lock, flags);
620
621 if (mvpwm->gpiod) {
622 ret = -EBUSY;
623 } else {
624 desc = gpiochip_request_own_desc(&mvchip->chip,
625 pwm->hwpwm, "mvebu-pwm",
626 GPIO_ACTIVE_HIGH,
627 GPIOD_OUT_LOW);
628 if (IS_ERR(desc)) {
629 ret = PTR_ERR(desc);
630 goto out;
631 }
632
633 mvpwm->gpiod = desc;
634 }
635out:
636 spin_unlock_irqrestore(&mvpwm->lock, flags);
637 return ret;
638}
639
640static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
641{
642 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
643 unsigned long flags;
644
645 spin_lock_irqsave(&mvpwm->lock, flags);
646 gpiochip_free_own_desc(mvpwm->gpiod);
647 mvpwm->gpiod = NULL;
648 spin_unlock_irqrestore(&mvpwm->lock, flags);
649}
650
651static void mvebu_pwm_get_state(struct pwm_chip *chip,
652 struct pwm_device *pwm,
653 struct pwm_state *state) {
654
655 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
656 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
657 unsigned long long val;
658 unsigned long flags;
659 u32 u;
660
661 spin_lock_irqsave(&mvpwm->lock, flags);
662
663 val = (unsigned long long)
664 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
665 val *= NSEC_PER_SEC;
666 do_div(val, mvpwm->clk_rate);
667 if (val > UINT_MAX)
668 state->duty_cycle = UINT_MAX;
669 else if (val)
670 state->duty_cycle = val;
671 else
672 state->duty_cycle = 1;
673
674 val = (unsigned long long)
675 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
676 val *= NSEC_PER_SEC;
677 do_div(val, mvpwm->clk_rate);
678 if (val < state->duty_cycle) {
679 state->period = 1;
680 } else {
681 val -= state->duty_cycle;
682 if (val > UINT_MAX)
683 state->period = UINT_MAX;
684 else if (val)
685 state->period = val;
686 else
687 state->period = 1;
688 }
689
690 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
691 if (u)
692 state->enabled = true;
693 else
694 state->enabled = false;
695
696 spin_unlock_irqrestore(&mvpwm->lock, flags);
697}
698
699static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
700 const struct pwm_state *state)
701{
702 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
703 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
704 unsigned long long val;
705 unsigned long flags;
706 unsigned int on, off;
707
708 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
709 do_div(val, NSEC_PER_SEC);
710 if (val > UINT_MAX)
711 return -EINVAL;
712 if (val)
713 on = val;
714 else
715 on = 1;
716
717 val = (unsigned long long) mvpwm->clk_rate *
718 (state->period - state->duty_cycle);
719 do_div(val, NSEC_PER_SEC);
720 if (val > UINT_MAX)
721 return -EINVAL;
722 if (val)
723 off = val;
724 else
725 off = 1;
726
727 spin_lock_irqsave(&mvpwm->lock, flags);
728
729 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
730 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
731 if (state->enabled)
732 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
733 else
734 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
735
736 spin_unlock_irqrestore(&mvpwm->lock, flags);
737
738 return 0;
739}
740
741static const struct pwm_ops mvebu_pwm_ops = {
742 .request = mvebu_pwm_request,
743 .free = mvebu_pwm_free,
744 .get_state = mvebu_pwm_get_state,
745 .apply = mvebu_pwm_apply,
746 .owner = THIS_MODULE,
747};
748
749static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
750{
751 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
752
753 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
754 &mvpwm->blink_select);
755 mvpwm->blink_on_duration =
756 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
757 mvpwm->blink_off_duration =
758 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
759}
760
761static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
762{
763 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
764
765 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
766 mvpwm->blink_select);
767 writel_relaxed(mvpwm->blink_on_duration,
768 mvebu_pwmreg_blink_on_duration(mvpwm));
769 writel_relaxed(mvpwm->blink_off_duration,
770 mvebu_pwmreg_blink_off_duration(mvpwm));
771}
772
773static int mvebu_pwm_probe(struct platform_device *pdev,
774 struct mvebu_gpio_chip *mvchip,
775 int id)
776{
777 struct device *dev = &pdev->dev;
778 struct mvebu_pwm *mvpwm;
779 u32 set;
780
781 if (!of_device_is_compatible(mvchip->chip.of_node,
782 "marvell,armada-370-gpio"))
783 return 0;
784
785 /*
786 * There are only two sets of PWM configuration registers for
787 * all the GPIO lines on those SoCs which this driver reserves
788 * for the first two GPIO chips. So if the resource is missing
789 * we can't treat it as an error.
790 */
791 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
792 return 0;
793
794 if (IS_ERR(mvchip->clk))
795 return PTR_ERR(mvchip->clk);
796
797 /*
798 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
799 * with id 1. Don't allow further GPIO chips to be used for PWM.
800 */
801 if (id == 0)
802 set = 0;
803 else if (id == 1)
804 set = U32_MAX;
805 else
806 return -EINVAL;
807 regmap_write(mvchip->regs,
808 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
809
810 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
811 if (!mvpwm)
812 return -ENOMEM;
813 mvchip->mvpwm = mvpwm;
814 mvpwm->mvchip = mvchip;
815
816 mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
817 if (IS_ERR(mvpwm->membase))
818 return PTR_ERR(mvpwm->membase);
819
820 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
821 if (!mvpwm->clk_rate) {
822 dev_err(dev, "failed to get clock rate\n");
823 return -EINVAL;
824 }
825
826 mvpwm->chip.dev = dev;
827 mvpwm->chip.ops = &mvebu_pwm_ops;
828 mvpwm->chip.npwm = mvchip->chip.ngpio;
829 /*
830 * There may already be some PWM allocated, so we can't force
831 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
832 * So, we let pwmchip_add() do the numbering and take the next free
833 * region.
834 */
835 mvpwm->chip.base = -1;
836
837 spin_lock_init(&mvpwm->lock);
838
839 return pwmchip_add(&mvpwm->chip);
840}
841
842#ifdef CONFIG_DEBUG_FS
843#include <linux/seq_file.h>
844
845static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
846{
847 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
848 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
849 const char *label;
850 int i;
851
852 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
853 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
854 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
855 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
856 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
857 cause = mvebu_gpio_read_edge_cause(mvchip);
858 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
859 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
860
861 for_each_requested_gpio(chip, i, label) {
862 u32 msk;
863 bool is_out;
864
865 msk = BIT(i);
866 is_out = !(io_conf & msk);
867
868 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
869
870 if (is_out) {
871 seq_printf(s, " out %s %s\n",
872 out & msk ? "hi" : "lo",
873 blink & msk ? "(blink )" : "");
874 continue;
875 }
876
877 seq_printf(s, " in %s (act %s) - IRQ",
878 (data_in ^ in_pol) & msk ? "hi" : "lo",
879 in_pol & msk ? "lo" : "hi");
880 if (!((edg_msk | lvl_msk) & msk)) {
881 seq_puts(s, " disabled\n");
882 continue;
883 }
884 if (edg_msk & msk)
885 seq_puts(s, " edge ");
886 if (lvl_msk & msk)
887 seq_puts(s, " level");
888 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
889 }
890}
891#else
892#define mvebu_gpio_dbg_show NULL
893#endif
894
895static const struct of_device_id mvebu_gpio_of_match[] = {
896 {
897 .compatible = "marvell,orion-gpio",
898 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
899 },
900 {
901 .compatible = "marvell,mv78200-gpio",
902 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
903 },
904 {
905 .compatible = "marvell,armadaxp-gpio",
906 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
907 },
908 {
909 .compatible = "marvell,armada-370-gpio",
910 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
911 },
912 {
913 .compatible = "marvell,armada-8k-gpio",
914 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
915 },
916 {
917 /* sentinel */
918 },
919};
920
921static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
922{
923 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
924 int i;
925
926 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
927 &mvchip->out_reg);
928 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
929 &mvchip->io_conf_reg);
930 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
931 &mvchip->blink_en_reg);
932 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
933 &mvchip->in_pol_reg);
934
935 switch (mvchip->soc_variant) {
936 case MVEBU_GPIO_SOC_VARIANT_ORION:
937 case MVEBU_GPIO_SOC_VARIANT_A8K:
938 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
939 &mvchip->edge_mask_regs[0]);
940 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
941 &mvchip->level_mask_regs[0]);
942 break;
943 case MVEBU_GPIO_SOC_VARIANT_MV78200:
944 for (i = 0; i < 2; i++) {
945 regmap_read(mvchip->regs,
946 GPIO_EDGE_MASK_MV78200_OFF(i),
947 &mvchip->edge_mask_regs[i]);
948 regmap_read(mvchip->regs,
949 GPIO_LEVEL_MASK_MV78200_OFF(i),
950 &mvchip->level_mask_regs[i]);
951 }
952 break;
953 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
954 for (i = 0; i < 4; i++) {
955 regmap_read(mvchip->regs,
956 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
957 &mvchip->edge_mask_regs[i]);
958 regmap_read(mvchip->regs,
959 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
960 &mvchip->level_mask_regs[i]);
961 }
962 break;
963 default:
964 BUG();
965 }
966
967 if (IS_ENABLED(CONFIG_PWM))
968 mvebu_pwm_suspend(mvchip);
969
970 return 0;
971}
972
973static int mvebu_gpio_resume(struct platform_device *pdev)
974{
975 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
976 int i;
977
978 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
979 mvchip->out_reg);
980 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
981 mvchip->io_conf_reg);
982 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
983 mvchip->blink_en_reg);
984 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
985 mvchip->in_pol_reg);
986
987 switch (mvchip->soc_variant) {
988 case MVEBU_GPIO_SOC_VARIANT_ORION:
989 case MVEBU_GPIO_SOC_VARIANT_A8K:
990 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
991 mvchip->edge_mask_regs[0]);
992 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
993 mvchip->level_mask_regs[0]);
994 break;
995 case MVEBU_GPIO_SOC_VARIANT_MV78200:
996 for (i = 0; i < 2; i++) {
997 regmap_write(mvchip->regs,
998 GPIO_EDGE_MASK_MV78200_OFF(i),
999 mvchip->edge_mask_regs[i]);
1000 regmap_write(mvchip->regs,
1001 GPIO_LEVEL_MASK_MV78200_OFF(i),
1002 mvchip->level_mask_regs[i]);
1003 }
1004 break;
1005 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1006 for (i = 0; i < 4; i++) {
1007 regmap_write(mvchip->regs,
1008 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1009 mvchip->edge_mask_regs[i]);
1010 regmap_write(mvchip->regs,
1011 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1012 mvchip->level_mask_regs[i]);
1013 }
1014 break;
1015 default:
1016 BUG();
1017 }
1018
1019 if (IS_ENABLED(CONFIG_PWM))
1020 mvebu_pwm_resume(mvchip);
1021
1022 return 0;
1023}
1024
1025static const struct regmap_config mvebu_gpio_regmap_config = {
1026 .reg_bits = 32,
1027 .reg_stride = 4,
1028 .val_bits = 32,
1029 .fast_io = true,
1030};
1031
1032static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1033 struct mvebu_gpio_chip *mvchip)
1034{
1035 void __iomem *base;
1036
1037 base = devm_platform_ioremap_resource(pdev, 0);
1038 if (IS_ERR(base))
1039 return PTR_ERR(base);
1040
1041 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1042 &mvebu_gpio_regmap_config);
1043 if (IS_ERR(mvchip->regs))
1044 return PTR_ERR(mvchip->regs);
1045
1046 /*
1047 * For the legacy SoCs, the regmap directly maps to the GPIO
1048 * registers, so no offset is needed.
1049 */
1050 mvchip->offset = 0;
1051
1052 /*
1053 * The Armada XP has a second range of registers for the
1054 * per-CPU registers
1055 */
1056 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1057 base = devm_platform_ioremap_resource(pdev, 1);
1058 if (IS_ERR(base))
1059 return PTR_ERR(base);
1060
1061 mvchip->percpu_regs =
1062 devm_regmap_init_mmio(&pdev->dev, base,
1063 &mvebu_gpio_regmap_config);
1064 if (IS_ERR(mvchip->percpu_regs))
1065 return PTR_ERR(mvchip->percpu_regs);
1066 }
1067
1068 return 0;
1069}
1070
1071static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1072 struct mvebu_gpio_chip *mvchip)
1073{
1074 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1075 if (IS_ERR(mvchip->regs))
1076 return PTR_ERR(mvchip->regs);
1077
1078 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1079 return -EINVAL;
1080
1081 return 0;
1082}
1083
1084static int mvebu_gpio_probe(struct platform_device *pdev)
1085{
1086 struct mvebu_gpio_chip *mvchip;
1087 const struct of_device_id *match;
1088 struct device_node *np = pdev->dev.of_node;
1089 struct irq_chip_generic *gc;
1090 struct irq_chip_type *ct;
1091 unsigned int ngpios;
1092 bool have_irqs;
1093 int soc_variant;
1094 int i, cpu, id;
1095 int err;
1096
1097 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1098 if (match)
1099 soc_variant = (unsigned long) match->data;
1100 else
1101 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1102
1103 /* Some gpio controllers do not provide irq support */
1104 err = platform_irq_count(pdev);
1105 if (err < 0)
1106 return err;
1107
1108 have_irqs = err != 0;
1109
1110 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1111 GFP_KERNEL);
1112 if (!mvchip)
1113 return -ENOMEM;
1114
1115 platform_set_drvdata(pdev, mvchip);
1116
1117 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1118 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1119 return -ENODEV;
1120 }
1121
1122 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1123 if (id < 0) {
1124 dev_err(&pdev->dev, "Couldn't get OF id\n");
1125 return id;
1126 }
1127
1128 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1129 /* Not all SoCs require a clock.*/
1130 if (!IS_ERR(mvchip->clk))
1131 clk_prepare_enable(mvchip->clk);
1132
1133 mvchip->soc_variant = soc_variant;
1134 mvchip->chip.label = dev_name(&pdev->dev);
1135 mvchip->chip.parent = &pdev->dev;
1136 mvchip->chip.request = gpiochip_generic_request;
1137 mvchip->chip.free = gpiochip_generic_free;
1138 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1139 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1140 mvchip->chip.get = mvebu_gpio_get;
1141 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1142 mvchip->chip.set = mvebu_gpio_set;
1143 if (have_irqs)
1144 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1145 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1146 mvchip->chip.ngpio = ngpios;
1147 mvchip->chip.can_sleep = false;
1148 mvchip->chip.of_node = np;
1149 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1150
1151 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1152 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1153 else
1154 err = mvebu_gpio_probe_raw(pdev, mvchip);
1155
1156 if (err)
1157 return err;
1158
1159 /*
1160 * Mask and clear GPIO interrupts.
1161 */
1162 switch (soc_variant) {
1163 case MVEBU_GPIO_SOC_VARIANT_ORION:
1164 case MVEBU_GPIO_SOC_VARIANT_A8K:
1165 regmap_write(mvchip->regs,
1166 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1167 regmap_write(mvchip->regs,
1168 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1169 regmap_write(mvchip->regs,
1170 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1171 break;
1172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1173 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1174 for (cpu = 0; cpu < 2; cpu++) {
1175 regmap_write(mvchip->regs,
1176 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1177 regmap_write(mvchip->regs,
1178 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1179 }
1180 break;
1181 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1182 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1183 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1184 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1185 for (cpu = 0; cpu < 4; cpu++) {
1186 regmap_write(mvchip->percpu_regs,
1187 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1188 regmap_write(mvchip->percpu_regs,
1189 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1190 regmap_write(mvchip->percpu_regs,
1191 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1192 }
1193 break;
1194 default:
1195 BUG();
1196 }
1197
1198 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1199
1200 /* Some gpio controllers do not provide irq support */
1201 if (!have_irqs)
1202 return 0;
1203
1204 mvchip->domain =
1205 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1206 if (!mvchip->domain) {
1207 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1208 mvchip->chip.label);
1209 return -ENODEV;
1210 }
1211
1212 err = irq_alloc_domain_generic_chips(
1213 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1214 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1215 if (err) {
1216 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1217 mvchip->chip.label);
1218 goto err_domain;
1219 }
1220
1221 /*
1222 * NOTE: The common accessors cannot be used because of the percpu
1223 * access to the mask registers
1224 */
1225 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1226 gc->private = mvchip;
1227 ct = &gc->chip_types[0];
1228 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1229 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1230 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1231 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1232 ct->chip.name = mvchip->chip.label;
1233
1234 ct = &gc->chip_types[1];
1235 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1236 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1237 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1238 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1239 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1240 ct->handler = handle_edge_irq;
1241 ct->chip.name = mvchip->chip.label;
1242
1243 /*
1244 * Setup the interrupt handlers. Each chip can have up to 4
1245 * interrupt handlers, with each handler dealing with 8 GPIO
1246 * pins.
1247 */
1248 for (i = 0; i < 4; i++) {
1249 int irq = platform_get_irq_optional(pdev, i);
1250
1251 if (irq < 0)
1252 continue;
1253 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1254 mvchip);
1255 }
1256
1257 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1258 if (IS_ENABLED(CONFIG_PWM))
1259 return mvebu_pwm_probe(pdev, mvchip, id);
1260
1261 return 0;
1262
1263err_domain:
1264 irq_domain_remove(mvchip->domain);
1265
1266 return err;
1267}
1268
1269static struct platform_driver mvebu_gpio_driver = {
1270 .driver = {
1271 .name = "mvebu-gpio",
1272 .of_match_table = mvebu_gpio_of_match,
1273 },
1274 .probe = mvebu_gpio_probe,
1275 .suspend = mvebu_gpio_suspend,
1276 .resume = mvebu_gpio_resume,
1277};
1278builtin_platform_driver(mvebu_gpio_driver);