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1/*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36#include <linux/err.h>
37#include <linux/init.h>
38#include <linux/gpio.h>
39#include <linux/irq.h>
40#include <linux/slab.h>
41#include <linux/irqdomain.h>
42#include <linux/io.h>
43#include <linux/of_irq.h>
44#include <linux/of_device.h>
45#include <linux/clk.h>
46#include <linux/pinctrl/consumer.h>
47#include <linux/irqchip/chained_irq.h>
48
49/*
50 * GPIO unit register offsets.
51 */
52#define GPIO_OUT_OFF 0x0000
53#define GPIO_IO_CONF_OFF 0x0004
54#define GPIO_BLINK_EN_OFF 0x0008
55#define GPIO_IN_POL_OFF 0x000c
56#define GPIO_DATA_IN_OFF 0x0010
57#define GPIO_EDGE_CAUSE_OFF 0x0014
58#define GPIO_EDGE_MASK_OFF 0x0018
59#define GPIO_LEVEL_MASK_OFF 0x001c
60
61/* The MV78200 has per-CPU registers for edge mask and level mask */
62#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
63#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
64
65/* The Armada XP has per-CPU registers for interrupt cause, interrupt
66 * mask and interrupt level mask. Those are relative to the
67 * percpu_membase. */
68#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
69#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
70#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
71
72#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
73#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
74#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
75
76#define MVEBU_MAX_GPIO_PER_BANK 32
77
78struct mvebu_gpio_chip {
79 struct gpio_chip chip;
80 spinlock_t lock;
81 void __iomem *membase;
82 void __iomem *percpu_membase;
83 int irqbase;
84 struct irq_domain *domain;
85 int soc_variant;
86
87 /* Used to preserve GPIO registers across suspend/resume */
88 u32 out_reg;
89 u32 io_conf_reg;
90 u32 blink_en_reg;
91 u32 in_pol_reg;
92 u32 edge_mask_regs[4];
93 u32 level_mask_regs[4];
94};
95
96/*
97 * Functions returning addresses of individual registers for a given
98 * GPIO controller.
99 */
100static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
101{
102 return mvchip->membase + GPIO_OUT_OFF;
103}
104
105static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
106{
107 return mvchip->membase + GPIO_BLINK_EN_OFF;
108}
109
110static inline void __iomem *
111mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
112{
113 return mvchip->membase + GPIO_IO_CONF_OFF;
114}
115
116static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
117{
118 return mvchip->membase + GPIO_IN_POL_OFF;
119}
120
121static inline void __iomem *
122mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
123{
124 return mvchip->membase + GPIO_DATA_IN_OFF;
125}
126
127static inline void __iomem *
128mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
129{
130 int cpu;
131
132 switch (mvchip->soc_variant) {
133 case MVEBU_GPIO_SOC_VARIANT_ORION:
134 case MVEBU_GPIO_SOC_VARIANT_MV78200:
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
137 cpu = smp_processor_id();
138 return mvchip->percpu_membase +
139 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
140 default:
141 BUG();
142 }
143}
144
145static inline void __iomem *
146mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
147{
148 int cpu;
149
150 switch (mvchip->soc_variant) {
151 case MVEBU_GPIO_SOC_VARIANT_ORION:
152 return mvchip->membase + GPIO_EDGE_MASK_OFF;
153 case MVEBU_GPIO_SOC_VARIANT_MV78200:
154 cpu = smp_processor_id();
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
156 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
157 cpu = smp_processor_id();
158 return mvchip->percpu_membase +
159 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
160 default:
161 BUG();
162 }
163}
164
165static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
166{
167 int cpu;
168
169 switch (mvchip->soc_variant) {
170 case MVEBU_GPIO_SOC_VARIANT_ORION:
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF;
172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
173 cpu = smp_processor_id();
174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
176 cpu = smp_processor_id();
177 return mvchip->percpu_membase +
178 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
179 default:
180 BUG();
181 }
182}
183
184/*
185 * Functions implementing the gpio_chip methods
186 */
187
188static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
189{
190 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
191 unsigned long flags;
192 u32 u;
193
194 spin_lock_irqsave(&mvchip->lock, flags);
195 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
196 if (value)
197 u |= 1 << pin;
198 else
199 u &= ~(1 << pin);
200 writel_relaxed(u, mvebu_gpioreg_out(mvchip));
201 spin_unlock_irqrestore(&mvchip->lock, flags);
202}
203
204static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
205{
206 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
207 u32 u;
208
209 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
210 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
211 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
212 } else {
213 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
214 }
215
216 return (u >> pin) & 1;
217}
218
219static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
220{
221 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
222 unsigned long flags;
223 u32 u;
224
225 spin_lock_irqsave(&mvchip->lock, flags);
226 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
227 if (value)
228 u |= 1 << pin;
229 else
230 u &= ~(1 << pin);
231 writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
232 spin_unlock_irqrestore(&mvchip->lock, flags);
233}
234
235static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
236{
237 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
238 unsigned long flags;
239 int ret;
240 u32 u;
241
242 /* Check with the pinctrl driver whether this pin is usable as
243 * an input GPIO */
244 ret = pinctrl_gpio_direction_input(chip->base + pin);
245 if (ret)
246 return ret;
247
248 spin_lock_irqsave(&mvchip->lock, flags);
249 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
250 u |= 1 << pin;
251 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
252 spin_unlock_irqrestore(&mvchip->lock, flags);
253
254 return 0;
255}
256
257static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
258 int value)
259{
260 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
261 unsigned long flags;
262 int ret;
263 u32 u;
264
265 /* Check with the pinctrl driver whether this pin is usable as
266 * an output GPIO */
267 ret = pinctrl_gpio_direction_output(chip->base + pin);
268 if (ret)
269 return ret;
270
271 mvebu_gpio_blink(chip, pin, 0);
272 mvebu_gpio_set(chip, pin, value);
273
274 spin_lock_irqsave(&mvchip->lock, flags);
275 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
276 u &= ~(1 << pin);
277 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
278 spin_unlock_irqrestore(&mvchip->lock, flags);
279
280 return 0;
281}
282
283static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
284{
285 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
286 return irq_create_mapping(mvchip->domain, pin);
287}
288
289/*
290 * Functions implementing the irq_chip methods
291 */
292static void mvebu_gpio_irq_ack(struct irq_data *d)
293{
294 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
295 struct mvebu_gpio_chip *mvchip = gc->private;
296 u32 mask = d->mask;
297
298 irq_gc_lock(gc);
299 writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip));
300 irq_gc_unlock(gc);
301}
302
303static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
304{
305 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
306 struct mvebu_gpio_chip *mvchip = gc->private;
307 struct irq_chip_type *ct = irq_data_get_chip_type(d);
308 u32 mask = d->mask;
309
310 irq_gc_lock(gc);
311 ct->mask_cache_priv &= ~mask;
312
313 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
314 irq_gc_unlock(gc);
315}
316
317static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
318{
319 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
320 struct mvebu_gpio_chip *mvchip = gc->private;
321 struct irq_chip_type *ct = irq_data_get_chip_type(d);
322 u32 mask = d->mask;
323
324 irq_gc_lock(gc);
325 ct->mask_cache_priv |= mask;
326 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
327 irq_gc_unlock(gc);
328}
329
330static void mvebu_gpio_level_irq_mask(struct irq_data *d)
331{
332 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
333 struct mvebu_gpio_chip *mvchip = gc->private;
334 struct irq_chip_type *ct = irq_data_get_chip_type(d);
335 u32 mask = d->mask;
336
337 irq_gc_lock(gc);
338 ct->mask_cache_priv &= ~mask;
339 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
340 irq_gc_unlock(gc);
341}
342
343static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
344{
345 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
346 struct mvebu_gpio_chip *mvchip = gc->private;
347 struct irq_chip_type *ct = irq_data_get_chip_type(d);
348 u32 mask = d->mask;
349
350 irq_gc_lock(gc);
351 ct->mask_cache_priv |= mask;
352 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
353 irq_gc_unlock(gc);
354}
355
356/*****************************************************************************
357 * MVEBU GPIO IRQ
358 *
359 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
360 * value of the line or the opposite value.
361 *
362 * Level IRQ handlers: DATA_IN is used directly as cause register.
363 * Interrupt are masked by LEVEL_MASK registers.
364 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
365 * Interrupt are masked by EDGE_MASK registers.
366 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
367 * the polarity to catch the next line transaction.
368 * This is a race condition that might not perfectly
369 * work on some use cases.
370 *
371 * Every eight GPIO lines are grouped (OR'ed) before going up to main
372 * cause register.
373 *
374 * EDGE cause mask
375 * data-in /--------| |-----| |----\
376 * -----| |----- ---- to main cause reg
377 * X \----------------| |----/
378 * polarity LEVEL mask
379 *
380 ****************************************************************************/
381
382static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
383{
384 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
385 struct irq_chip_type *ct = irq_data_get_chip_type(d);
386 struct mvebu_gpio_chip *mvchip = gc->private;
387 int pin;
388 u32 u;
389
390 pin = d->hwirq;
391
392 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
393 if (!u)
394 return -EINVAL;
395
396 type &= IRQ_TYPE_SENSE_MASK;
397 if (type == IRQ_TYPE_NONE)
398 return -EINVAL;
399
400 /* Check if we need to change chip and handler */
401 if (!(ct->type & type))
402 if (irq_setup_alt_chip(d, type))
403 return -EINVAL;
404
405 /*
406 * Configure interrupt polarity.
407 */
408 switch (type) {
409 case IRQ_TYPE_EDGE_RISING:
410 case IRQ_TYPE_LEVEL_HIGH:
411 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
412 u &= ~(1 << pin);
413 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
414 break;
415 case IRQ_TYPE_EDGE_FALLING:
416 case IRQ_TYPE_LEVEL_LOW:
417 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
418 u |= 1 << pin;
419 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
420 break;
421 case IRQ_TYPE_EDGE_BOTH: {
422 u32 v;
423
424 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
425 readl_relaxed(mvebu_gpioreg_data_in(mvchip));
426
427 /*
428 * set initial polarity based on current input level
429 */
430 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
431 if (v & (1 << pin))
432 u |= 1 << pin; /* falling */
433 else
434 u &= ~(1 << pin); /* rising */
435 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
436 break;
437 }
438 }
439 return 0;
440}
441
442static void mvebu_gpio_irq_handler(struct irq_desc *desc)
443{
444 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
445 struct irq_chip *chip = irq_desc_get_chip(desc);
446 u32 cause, type;
447 int i;
448
449 if (mvchip == NULL)
450 return;
451
452 chained_irq_enter(chip, desc);
453
454 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
455 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
456 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
457 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
458
459 for (i = 0; i < mvchip->chip.ngpio; i++) {
460 int irq;
461
462 irq = irq_find_mapping(mvchip->domain, i);
463
464 if (!(cause & (1 << i)))
465 continue;
466
467 type = irq_get_trigger_type(irq);
468 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
469 /* Swap polarity (race with GPIO line) */
470 u32 polarity;
471
472 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
473 polarity ^= 1 << i;
474 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
475 }
476
477 generic_handle_irq(irq);
478 }
479
480 chained_irq_exit(chip, desc);
481}
482
483#ifdef CONFIG_DEBUG_FS
484#include <linux/seq_file.h>
485
486static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
487{
488 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
489 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
490 int i;
491
492 out = readl_relaxed(mvebu_gpioreg_out(mvchip));
493 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
494 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
495 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
496 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
497 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
498 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
499 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
500
501 for (i = 0; i < chip->ngpio; i++) {
502 const char *label;
503 u32 msk;
504 bool is_out;
505
506 label = gpiochip_is_requested(chip, i);
507 if (!label)
508 continue;
509
510 msk = 1 << i;
511 is_out = !(io_conf & msk);
512
513 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
514
515 if (is_out) {
516 seq_printf(s, " out %s %s\n",
517 out & msk ? "hi" : "lo",
518 blink & msk ? "(blink )" : "");
519 continue;
520 }
521
522 seq_printf(s, " in %s (act %s) - IRQ",
523 (data_in ^ in_pol) & msk ? "hi" : "lo",
524 in_pol & msk ? "lo" : "hi");
525 if (!((edg_msk | lvl_msk) & msk)) {
526 seq_puts(s, " disabled\n");
527 continue;
528 }
529 if (edg_msk & msk)
530 seq_puts(s, " edge ");
531 if (lvl_msk & msk)
532 seq_puts(s, " level");
533 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
534 }
535}
536#else
537#define mvebu_gpio_dbg_show NULL
538#endif
539
540static const struct of_device_id mvebu_gpio_of_match[] = {
541 {
542 .compatible = "marvell,orion-gpio",
543 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
544 },
545 {
546 .compatible = "marvell,mv78200-gpio",
547 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
548 },
549 {
550 .compatible = "marvell,armadaxp-gpio",
551 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
552 },
553 {
554 /* sentinel */
555 },
556};
557
558static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
559{
560 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
561 int i;
562
563 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
564 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
565 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
566 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
567
568 switch (mvchip->soc_variant) {
569 case MVEBU_GPIO_SOC_VARIANT_ORION:
570 mvchip->edge_mask_regs[0] =
571 readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
572 mvchip->level_mask_regs[0] =
573 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
574 break;
575 case MVEBU_GPIO_SOC_VARIANT_MV78200:
576 for (i = 0; i < 2; i++) {
577 mvchip->edge_mask_regs[i] =
578 readl(mvchip->membase +
579 GPIO_EDGE_MASK_MV78200_OFF(i));
580 mvchip->level_mask_regs[i] =
581 readl(mvchip->membase +
582 GPIO_LEVEL_MASK_MV78200_OFF(i));
583 }
584 break;
585 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
586 for (i = 0; i < 4; i++) {
587 mvchip->edge_mask_regs[i] =
588 readl(mvchip->membase +
589 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
590 mvchip->level_mask_regs[i] =
591 readl(mvchip->membase +
592 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
593 }
594 break;
595 default:
596 BUG();
597 }
598
599 return 0;
600}
601
602static int mvebu_gpio_resume(struct platform_device *pdev)
603{
604 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
605 int i;
606
607 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
608 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
609 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
610 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
611
612 switch (mvchip->soc_variant) {
613 case MVEBU_GPIO_SOC_VARIANT_ORION:
614 writel(mvchip->edge_mask_regs[0],
615 mvchip->membase + GPIO_EDGE_MASK_OFF);
616 writel(mvchip->level_mask_regs[0],
617 mvchip->membase + GPIO_LEVEL_MASK_OFF);
618 break;
619 case MVEBU_GPIO_SOC_VARIANT_MV78200:
620 for (i = 0; i < 2; i++) {
621 writel(mvchip->edge_mask_regs[i],
622 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
623 writel(mvchip->level_mask_regs[i],
624 mvchip->membase +
625 GPIO_LEVEL_MASK_MV78200_OFF(i));
626 }
627 break;
628 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
629 for (i = 0; i < 4; i++) {
630 writel(mvchip->edge_mask_regs[i],
631 mvchip->membase +
632 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
633 writel(mvchip->level_mask_regs[i],
634 mvchip->membase +
635 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
636 }
637 break;
638 default:
639 BUG();
640 }
641
642 return 0;
643}
644
645static int mvebu_gpio_probe(struct platform_device *pdev)
646{
647 struct mvebu_gpio_chip *mvchip;
648 const struct of_device_id *match;
649 struct device_node *np = pdev->dev.of_node;
650 struct resource *res;
651 struct irq_chip_generic *gc;
652 struct irq_chip_type *ct;
653 struct clk *clk;
654 unsigned int ngpios;
655 bool have_irqs;
656 int soc_variant;
657 int i, cpu, id;
658 int err;
659
660 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
661 if (match)
662 soc_variant = (int) match->data;
663 else
664 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
665
666 /* Some gpio controllers do not provide irq support */
667 have_irqs = of_irq_count(np) != 0;
668
669 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
670 GFP_KERNEL);
671 if (!mvchip)
672 return -ENOMEM;
673
674 platform_set_drvdata(pdev, mvchip);
675
676 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
677 dev_err(&pdev->dev, "Missing ngpios OF property\n");
678 return -ENODEV;
679 }
680
681 id = of_alias_get_id(pdev->dev.of_node, "gpio");
682 if (id < 0) {
683 dev_err(&pdev->dev, "Couldn't get OF id\n");
684 return id;
685 }
686
687 clk = devm_clk_get(&pdev->dev, NULL);
688 /* Not all SoCs require a clock.*/
689 if (!IS_ERR(clk))
690 clk_prepare_enable(clk);
691
692 mvchip->soc_variant = soc_variant;
693 mvchip->chip.label = dev_name(&pdev->dev);
694 mvchip->chip.parent = &pdev->dev;
695 mvchip->chip.request = gpiochip_generic_request;
696 mvchip->chip.free = gpiochip_generic_free;
697 mvchip->chip.direction_input = mvebu_gpio_direction_input;
698 mvchip->chip.get = mvebu_gpio_get;
699 mvchip->chip.direction_output = mvebu_gpio_direction_output;
700 mvchip->chip.set = mvebu_gpio_set;
701 if (have_irqs)
702 mvchip->chip.to_irq = mvebu_gpio_to_irq;
703 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
704 mvchip->chip.ngpio = ngpios;
705 mvchip->chip.can_sleep = false;
706 mvchip->chip.of_node = np;
707 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
708
709 spin_lock_init(&mvchip->lock);
710 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
712 if (IS_ERR(mvchip->membase))
713 return PTR_ERR(mvchip->membase);
714
715 /* The Armada XP has a second range of registers for the
716 * per-CPU registers */
717 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
718 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
719 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
720 res);
721 if (IS_ERR(mvchip->percpu_membase))
722 return PTR_ERR(mvchip->percpu_membase);
723 }
724
725 /*
726 * Mask and clear GPIO interrupts.
727 */
728 switch (soc_variant) {
729 case MVEBU_GPIO_SOC_VARIANT_ORION:
730 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
731 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
732 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
733 break;
734 case MVEBU_GPIO_SOC_VARIANT_MV78200:
735 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
736 for (cpu = 0; cpu < 2; cpu++) {
737 writel_relaxed(0, mvchip->membase +
738 GPIO_EDGE_MASK_MV78200_OFF(cpu));
739 writel_relaxed(0, mvchip->membase +
740 GPIO_LEVEL_MASK_MV78200_OFF(cpu));
741 }
742 break;
743 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
744 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
745 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
746 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
747 for (cpu = 0; cpu < 4; cpu++) {
748 writel_relaxed(0, mvchip->percpu_membase +
749 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
750 writel_relaxed(0, mvchip->percpu_membase +
751 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
752 writel_relaxed(0, mvchip->percpu_membase +
753 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
754 }
755 break;
756 default:
757 BUG();
758 }
759
760 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
761
762 /* Some gpio controllers do not provide irq support */
763 if (!have_irqs)
764 return 0;
765
766 mvchip->domain =
767 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
768 if (!mvchip->domain) {
769 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
770 mvchip->chip.label);
771 return -ENODEV;
772 }
773
774 err = irq_alloc_domain_generic_chips(
775 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
776 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
777 if (err) {
778 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
779 mvchip->chip.label);
780 goto err_domain;
781 }
782
783 /* NOTE: The common accessors cannot be used because of the percpu
784 * access to the mask registers
785 */
786 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
787 gc->private = mvchip;
788 ct = &gc->chip_types[0];
789 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
790 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
791 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
792 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
793 ct->chip.name = mvchip->chip.label;
794
795 ct = &gc->chip_types[1];
796 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
797 ct->chip.irq_ack = mvebu_gpio_irq_ack;
798 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
799 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
800 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
801 ct->handler = handle_edge_irq;
802 ct->chip.name = mvchip->chip.label;
803
804 /* Setup the interrupt handlers. Each chip can have up to 4
805 * interrupt handlers, with each handler dealing with 8 GPIO
806 * pins.
807 */
808 for (i = 0; i < 4; i++) {
809 int irq = platform_get_irq(pdev, i);
810
811 if (irq < 0)
812 continue;
813 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
814 mvchip);
815 }
816
817 return 0;
818
819err_domain:
820 irq_domain_remove(mvchip->domain);
821
822 return err;
823}
824
825static struct platform_driver mvebu_gpio_driver = {
826 .driver = {
827 .name = "mvebu-gpio",
828 .of_match_table = mvebu_gpio_of_match,
829 },
830 .probe = mvebu_gpio_probe,
831 .suspend = mvebu_gpio_suspend,
832 .resume = mvebu_gpio_resume,
833};
834builtin_platform_driver(mvebu_gpio_driver);