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1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h>
32#include <linux/slab.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/clk.h>
38#include <linux/serial_core.h>
39#include <linux/irq.h>
40
41#include <plat/dma.h>
42#include <plat/dmtimer.h>
43#include <plat/omap-serial.h>
44
45static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
46
47/* Forward declaration of functions */
48static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
49static void serial_omap_rx_timeout(unsigned long uart_no);
50static int serial_omap_start_rxdma(struct uart_omap_port *up);
51
52static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
53{
54 offset <<= up->port.regshift;
55 return readw(up->port.membase + offset);
56}
57
58static inline void serial_out(struct uart_omap_port *up, int offset, int value)
59{
60 offset <<= up->port.regshift;
61 writew(value, up->port.membase + offset);
62}
63
64static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
65{
66 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
67 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
68 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
69 serial_out(up, UART_FCR, 0);
70}
71
72/*
73 * serial_omap_get_divisor - calculate divisor value
74 * @port: uart port info
75 * @baud: baudrate for which divisor needs to be calculated.
76 *
77 * We have written our own function to get the divisor so as to support
78 * 13x mode. 3Mbps Baudrate as an different divisor.
79 * Reference OMAP TRM Chapter 17:
80 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
81 * referring to oversampling - divisor value
82 * baudrate 460,800 to 3,686,400 all have divisor 13
83 * except 3,000,000 which has divisor value 16
84 */
85static unsigned int
86serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
87{
88 unsigned int divisor;
89
90 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
91 divisor = 13;
92 else
93 divisor = 16;
94 return port->uartclk/(baud * divisor);
95}
96
97static void serial_omap_stop_rxdma(struct uart_omap_port *up)
98{
99 if (up->uart_dma.rx_dma_used) {
100 del_timer(&up->uart_dma.rx_timer);
101 omap_stop_dma(up->uart_dma.rx_dma_channel);
102 omap_free_dma(up->uart_dma.rx_dma_channel);
103 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
104 up->uart_dma.rx_dma_used = false;
105 }
106}
107
108static void serial_omap_enable_ms(struct uart_port *port)
109{
110 struct uart_omap_port *up = (struct uart_omap_port *)port;
111
112 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
113 up->ier |= UART_IER_MSI;
114 serial_out(up, UART_IER, up->ier);
115}
116
117static void serial_omap_stop_tx(struct uart_port *port)
118{
119 struct uart_omap_port *up = (struct uart_omap_port *)port;
120
121 if (up->use_dma &&
122 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
123 /*
124 * Check if dma is still active. If yes do nothing,
125 * return. Else stop dma
126 */
127 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
128 return;
129 omap_stop_dma(up->uart_dma.tx_dma_channel);
130 omap_free_dma(up->uart_dma.tx_dma_channel);
131 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
132 }
133
134 if (up->ier & UART_IER_THRI) {
135 up->ier &= ~UART_IER_THRI;
136 serial_out(up, UART_IER, up->ier);
137 }
138}
139
140static void serial_omap_stop_rx(struct uart_port *port)
141{
142 struct uart_omap_port *up = (struct uart_omap_port *)port;
143
144 if (up->use_dma)
145 serial_omap_stop_rxdma(up);
146 up->ier &= ~UART_IER_RLSI;
147 up->port.read_status_mask &= ~UART_LSR_DR;
148 serial_out(up, UART_IER, up->ier);
149}
150
151static inline void receive_chars(struct uart_omap_port *up, int *status)
152{
153 struct tty_struct *tty = up->port.state->port.tty;
154 unsigned int flag;
155 unsigned char ch, lsr = *status;
156 int max_count = 256;
157
158 do {
159 if (likely(lsr & UART_LSR_DR))
160 ch = serial_in(up, UART_RX);
161 flag = TTY_NORMAL;
162 up->port.icount.rx++;
163
164 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
165 /*
166 * For statistics only
167 */
168 if (lsr & UART_LSR_BI) {
169 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
170 up->port.icount.brk++;
171 /*
172 * We do the SysRQ and SAK checking
173 * here because otherwise the break
174 * may get masked by ignore_status_mask
175 * or read_status_mask.
176 */
177 if (uart_handle_break(&up->port))
178 goto ignore_char;
179 } else if (lsr & UART_LSR_PE) {
180 up->port.icount.parity++;
181 } else if (lsr & UART_LSR_FE) {
182 up->port.icount.frame++;
183 }
184
185 if (lsr & UART_LSR_OE)
186 up->port.icount.overrun++;
187
188 /*
189 * Mask off conditions which should be ignored.
190 */
191 lsr &= up->port.read_status_mask;
192
193#ifdef CONFIG_SERIAL_OMAP_CONSOLE
194 if (up->port.line == up->port.cons->index) {
195 /* Recover the break flag from console xmit */
196 lsr |= up->lsr_break_flag;
197 }
198#endif
199 if (lsr & UART_LSR_BI)
200 flag = TTY_BREAK;
201 else if (lsr & UART_LSR_PE)
202 flag = TTY_PARITY;
203 else if (lsr & UART_LSR_FE)
204 flag = TTY_FRAME;
205 }
206
207 if (uart_handle_sysrq_char(&up->port, ch))
208 goto ignore_char;
209 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
210ignore_char:
211 lsr = serial_in(up, UART_LSR);
212 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
213 spin_unlock(&up->port.lock);
214 tty_flip_buffer_push(tty);
215 spin_lock(&up->port.lock);
216}
217
218static void transmit_chars(struct uart_omap_port *up)
219{
220 struct circ_buf *xmit = &up->port.state->xmit;
221 int count;
222
223 if (up->port.x_char) {
224 serial_out(up, UART_TX, up->port.x_char);
225 up->port.icount.tx++;
226 up->port.x_char = 0;
227 return;
228 }
229 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
230 serial_omap_stop_tx(&up->port);
231 return;
232 }
233 count = up->port.fifosize / 4;
234 do {
235 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
236 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
237 up->port.icount.tx++;
238 if (uart_circ_empty(xmit))
239 break;
240 } while (--count > 0);
241
242 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
243 uart_write_wakeup(&up->port);
244
245 if (uart_circ_empty(xmit))
246 serial_omap_stop_tx(&up->port);
247}
248
249static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
250{
251 if (!(up->ier & UART_IER_THRI)) {
252 up->ier |= UART_IER_THRI;
253 serial_out(up, UART_IER, up->ier);
254 }
255}
256
257static void serial_omap_start_tx(struct uart_port *port)
258{
259 struct uart_omap_port *up = (struct uart_omap_port *)port;
260 struct circ_buf *xmit;
261 unsigned int start;
262 int ret = 0;
263
264 if (!up->use_dma) {
265 serial_omap_enable_ier_thri(up);
266 return;
267 }
268
269 if (up->uart_dma.tx_dma_used)
270 return;
271
272 xmit = &up->port.state->xmit;
273
274 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
275 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
276 "UART Tx DMA",
277 (void *)uart_tx_dma_callback, up,
278 &(up->uart_dma.tx_dma_channel));
279
280 if (ret < 0) {
281 serial_omap_enable_ier_thri(up);
282 return;
283 }
284 }
285 spin_lock(&(up->uart_dma.tx_lock));
286 up->uart_dma.tx_dma_used = true;
287 spin_unlock(&(up->uart_dma.tx_lock));
288
289 start = up->uart_dma.tx_buf_dma_phys +
290 (xmit->tail & (UART_XMIT_SIZE - 1));
291
292 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
293 /*
294 * It is a circular buffer. See if the buffer has wounded back.
295 * If yes it will have to be transferred in two separate dma
296 * transfers
297 */
298 if (start + up->uart_dma.tx_buf_size >=
299 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
300 up->uart_dma.tx_buf_size =
301 (up->uart_dma.tx_buf_dma_phys +
302 UART_XMIT_SIZE) - start;
303
304 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
305 OMAP_DMA_AMODE_CONSTANT,
306 up->uart_dma.uart_base, 0, 0);
307 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
308 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
309 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
310 OMAP_DMA_DATA_TYPE_S8,
311 up->uart_dma.tx_buf_size, 1,
312 OMAP_DMA_SYNC_ELEMENT,
313 up->uart_dma.uart_dma_tx, 0);
314 /* FIXME: Cache maintenance needed here? */
315 omap_start_dma(up->uart_dma.tx_dma_channel);
316}
317
318static unsigned int check_modem_status(struct uart_omap_port *up)
319{
320 unsigned int status;
321
322 status = serial_in(up, UART_MSR);
323 status |= up->msr_saved_flags;
324 up->msr_saved_flags = 0;
325 if ((status & UART_MSR_ANY_DELTA) == 0)
326 return status;
327
328 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
329 up->port.state != NULL) {
330 if (status & UART_MSR_TERI)
331 up->port.icount.rng++;
332 if (status & UART_MSR_DDSR)
333 up->port.icount.dsr++;
334 if (status & UART_MSR_DDCD)
335 uart_handle_dcd_change
336 (&up->port, status & UART_MSR_DCD);
337 if (status & UART_MSR_DCTS)
338 uart_handle_cts_change
339 (&up->port, status & UART_MSR_CTS);
340 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
341 }
342
343 return status;
344}
345
346/**
347 * serial_omap_irq() - This handles the interrupt from one port
348 * @irq: uart port irq number
349 * @dev_id: uart port info
350 */
351static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
352{
353 struct uart_omap_port *up = dev_id;
354 unsigned int iir, lsr;
355 unsigned long flags;
356
357 iir = serial_in(up, UART_IIR);
358 if (iir & UART_IIR_NO_INT)
359 return IRQ_NONE;
360
361 spin_lock_irqsave(&up->port.lock, flags);
362 lsr = serial_in(up, UART_LSR);
363 if (iir & UART_IIR_RLSI) {
364 if (!up->use_dma) {
365 if (lsr & UART_LSR_DR)
366 receive_chars(up, &lsr);
367 } else {
368 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
369 serial_out(up, UART_IER, up->ier);
370 if ((serial_omap_start_rxdma(up) != 0) &&
371 (lsr & UART_LSR_DR))
372 receive_chars(up, &lsr);
373 }
374 }
375
376 check_modem_status(up);
377 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
378 transmit_chars(up);
379
380 spin_unlock_irqrestore(&up->port.lock, flags);
381 up->port_activity = jiffies;
382 return IRQ_HANDLED;
383}
384
385static unsigned int serial_omap_tx_empty(struct uart_port *port)
386{
387 struct uart_omap_port *up = (struct uart_omap_port *)port;
388 unsigned long flags = 0;
389 unsigned int ret = 0;
390
391 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
392 spin_lock_irqsave(&up->port.lock, flags);
393 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
394 spin_unlock_irqrestore(&up->port.lock, flags);
395
396 return ret;
397}
398
399static unsigned int serial_omap_get_mctrl(struct uart_port *port)
400{
401 struct uart_omap_port *up = (struct uart_omap_port *)port;
402 unsigned char status;
403 unsigned int ret = 0;
404
405 status = check_modem_status(up);
406 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
407
408 if (status & UART_MSR_DCD)
409 ret |= TIOCM_CAR;
410 if (status & UART_MSR_RI)
411 ret |= TIOCM_RNG;
412 if (status & UART_MSR_DSR)
413 ret |= TIOCM_DSR;
414 if (status & UART_MSR_CTS)
415 ret |= TIOCM_CTS;
416 return ret;
417}
418
419static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
420{
421 struct uart_omap_port *up = (struct uart_omap_port *)port;
422 unsigned char mcr = 0;
423
424 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
425 if (mctrl & TIOCM_RTS)
426 mcr |= UART_MCR_RTS;
427 if (mctrl & TIOCM_DTR)
428 mcr |= UART_MCR_DTR;
429 if (mctrl & TIOCM_OUT1)
430 mcr |= UART_MCR_OUT1;
431 if (mctrl & TIOCM_OUT2)
432 mcr |= UART_MCR_OUT2;
433 if (mctrl & TIOCM_LOOP)
434 mcr |= UART_MCR_LOOP;
435
436 mcr |= up->mcr;
437 serial_out(up, UART_MCR, mcr);
438}
439
440static void serial_omap_break_ctl(struct uart_port *port, int break_state)
441{
442 struct uart_omap_port *up = (struct uart_omap_port *)port;
443 unsigned long flags = 0;
444
445 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
446 spin_lock_irqsave(&up->port.lock, flags);
447 if (break_state == -1)
448 up->lcr |= UART_LCR_SBC;
449 else
450 up->lcr &= ~UART_LCR_SBC;
451 serial_out(up, UART_LCR, up->lcr);
452 spin_unlock_irqrestore(&up->port.lock, flags);
453}
454
455static int serial_omap_startup(struct uart_port *port)
456{
457 struct uart_omap_port *up = (struct uart_omap_port *)port;
458 unsigned long flags = 0;
459 int retval;
460
461 /*
462 * Allocate the IRQ
463 */
464 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
465 up->name, up);
466 if (retval)
467 return retval;
468
469 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
470
471 /*
472 * Clear the FIFO buffers and disable them.
473 * (they will be reenabled in set_termios())
474 */
475 serial_omap_clear_fifos(up);
476 /* For Hardware flow control */
477 serial_out(up, UART_MCR, UART_MCR_RTS);
478
479 /*
480 * Clear the interrupt registers.
481 */
482 (void) serial_in(up, UART_LSR);
483 if (serial_in(up, UART_LSR) & UART_LSR_DR)
484 (void) serial_in(up, UART_RX);
485 (void) serial_in(up, UART_IIR);
486 (void) serial_in(up, UART_MSR);
487
488 /*
489 * Now, initialize the UART
490 */
491 serial_out(up, UART_LCR, UART_LCR_WLEN8);
492 spin_lock_irqsave(&up->port.lock, flags);
493 /*
494 * Most PC uarts need OUT2 raised to enable interrupts.
495 */
496 up->port.mctrl |= TIOCM_OUT2;
497 serial_omap_set_mctrl(&up->port, up->port.mctrl);
498 spin_unlock_irqrestore(&up->port.lock, flags);
499
500 up->msr_saved_flags = 0;
501 if (up->use_dma) {
502 free_page((unsigned long)up->port.state->xmit.buf);
503 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
504 UART_XMIT_SIZE,
505 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
506 0);
507 init_timer(&(up->uart_dma.rx_timer));
508 up->uart_dma.rx_timer.function = serial_omap_rx_timeout;
509 up->uart_dma.rx_timer.data = up->pdev->id;
510 /* Currently the buffer size is 4KB. Can increase it */
511 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
512 up->uart_dma.rx_buf_size,
513 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
514 }
515 /*
516 * Finally, enable interrupts. Note: Modem status interrupts
517 * are set via set_termios(), which will be occurring imminently
518 * anyway, so we don't enable them here.
519 */
520 up->ier = UART_IER_RLSI | UART_IER_RDI;
521 serial_out(up, UART_IER, up->ier);
522
523 /* Enable module level wake up */
524 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
525
526 up->port_activity = jiffies;
527 return 0;
528}
529
530static void serial_omap_shutdown(struct uart_port *port)
531{
532 struct uart_omap_port *up = (struct uart_omap_port *)port;
533 unsigned long flags = 0;
534
535 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
536 /*
537 * Disable interrupts from this port
538 */
539 up->ier = 0;
540 serial_out(up, UART_IER, 0);
541
542 spin_lock_irqsave(&up->port.lock, flags);
543 up->port.mctrl &= ~TIOCM_OUT2;
544 serial_omap_set_mctrl(&up->port, up->port.mctrl);
545 spin_unlock_irqrestore(&up->port.lock, flags);
546
547 /*
548 * Disable break condition and FIFOs
549 */
550 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
551 serial_omap_clear_fifos(up);
552
553 /*
554 * Read data port to reset things, and then free the irq
555 */
556 if (serial_in(up, UART_LSR) & UART_LSR_DR)
557 (void) serial_in(up, UART_RX);
558 if (up->use_dma) {
559 dma_free_coherent(up->port.dev,
560 UART_XMIT_SIZE, up->port.state->xmit.buf,
561 up->uart_dma.tx_buf_dma_phys);
562 up->port.state->xmit.buf = NULL;
563 serial_omap_stop_rx(port);
564 dma_free_coherent(up->port.dev,
565 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
566 up->uart_dma.rx_buf_dma_phys);
567 up->uart_dma.rx_buf = NULL;
568 }
569 free_irq(up->port.irq, up);
570}
571
572static inline void
573serial_omap_configure_xonxoff
574 (struct uart_omap_port *up, struct ktermios *termios)
575{
576 unsigned char efr = 0;
577
578 up->lcr = serial_in(up, UART_LCR);
579 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
580 up->efr = serial_in(up, UART_EFR);
581 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
582
583 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
584 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
585
586 /* clear SW control mode bits */
587 efr = up->efr;
588 efr &= OMAP_UART_SW_CLR;
589
590 /*
591 * IXON Flag:
592 * Enable XON/XOFF flow control on output.
593 * Transmit XON1, XOFF1
594 */
595 if (termios->c_iflag & IXON)
596 efr |= OMAP_UART_SW_TX;
597
598 /*
599 * IXOFF Flag:
600 * Enable XON/XOFF flow control on input.
601 * Receiver compares XON1, XOFF1.
602 */
603 if (termios->c_iflag & IXOFF)
604 efr |= OMAP_UART_SW_RX;
605
606 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
607 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
608
609 up->mcr = serial_in(up, UART_MCR);
610
611 /*
612 * IXANY Flag:
613 * Enable any character to restart output.
614 * Operation resumes after receiving any
615 * character after recognition of the XOFF character
616 */
617 if (termios->c_iflag & IXANY)
618 up->mcr |= UART_MCR_XONANY;
619
620 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
621 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
622 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
623 /* Enable special char function UARTi.EFR_REG[5] and
624 * load the new software flow control mode IXON or IXOFF
625 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
626 */
627 serial_out(up, UART_EFR, efr | UART_EFR_SCD);
628 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
629
630 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
631 serial_out(up, UART_LCR, up->lcr);
632}
633
634static void
635serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
636 struct ktermios *old)
637{
638 struct uart_omap_port *up = (struct uart_omap_port *)port;
639 unsigned char cval = 0;
640 unsigned char efr = 0;
641 unsigned long flags = 0;
642 unsigned int baud, quot;
643
644 switch (termios->c_cflag & CSIZE) {
645 case CS5:
646 cval = UART_LCR_WLEN5;
647 break;
648 case CS6:
649 cval = UART_LCR_WLEN6;
650 break;
651 case CS7:
652 cval = UART_LCR_WLEN7;
653 break;
654 default:
655 case CS8:
656 cval = UART_LCR_WLEN8;
657 break;
658 }
659
660 if (termios->c_cflag & CSTOPB)
661 cval |= UART_LCR_STOP;
662 if (termios->c_cflag & PARENB)
663 cval |= UART_LCR_PARITY;
664 if (!(termios->c_cflag & PARODD))
665 cval |= UART_LCR_EPAR;
666
667 /*
668 * Ask the core to calculate the divisor for us.
669 */
670
671 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
672 quot = serial_omap_get_divisor(port, baud);
673
674 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
675 UART_FCR_ENABLE_FIFO;
676 if (up->use_dma)
677 up->fcr |= UART_FCR_DMA_SELECT;
678
679 /*
680 * Ok, we're now changing the port state. Do it with
681 * interrupts disabled.
682 */
683 spin_lock_irqsave(&up->port.lock, flags);
684
685 /*
686 * Update the per-port timeout.
687 */
688 uart_update_timeout(port, termios->c_cflag, baud);
689
690 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
691 if (termios->c_iflag & INPCK)
692 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
693 if (termios->c_iflag & (BRKINT | PARMRK))
694 up->port.read_status_mask |= UART_LSR_BI;
695
696 /*
697 * Characters to ignore
698 */
699 up->port.ignore_status_mask = 0;
700 if (termios->c_iflag & IGNPAR)
701 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
702 if (termios->c_iflag & IGNBRK) {
703 up->port.ignore_status_mask |= UART_LSR_BI;
704 /*
705 * If we're ignoring parity and break indicators,
706 * ignore overruns too (for real raw support).
707 */
708 if (termios->c_iflag & IGNPAR)
709 up->port.ignore_status_mask |= UART_LSR_OE;
710 }
711
712 /*
713 * ignore all characters if CREAD is not set
714 */
715 if ((termios->c_cflag & CREAD) == 0)
716 up->port.ignore_status_mask |= UART_LSR_DR;
717
718 /*
719 * Modem status interrupts
720 */
721 up->ier &= ~UART_IER_MSI;
722 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
723 up->ier |= UART_IER_MSI;
724 serial_out(up, UART_IER, up->ier);
725 serial_out(up, UART_LCR, cval); /* reset DLAB */
726
727 /* FIFOs and DMA Settings */
728
729 /* FCR can be changed only when the
730 * baud clock is not running
731 * DLL_REG and DLH_REG set to 0.
732 */
733 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
734 serial_out(up, UART_DLL, 0);
735 serial_out(up, UART_DLM, 0);
736 serial_out(up, UART_LCR, 0);
737
738 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
739
740 up->efr = serial_in(up, UART_EFR);
741 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
742
743 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
744 up->mcr = serial_in(up, UART_MCR);
745 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
746 /* FIFO ENABLE, DMA MODE */
747 serial_out(up, UART_FCR, up->fcr);
748 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
749
750 if (up->use_dma) {
751 serial_out(up, UART_TI752_TLR, 0);
752 serial_out(up, UART_OMAP_SCR,
753 (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));
754 }
755
756 serial_out(up, UART_EFR, up->efr);
757 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
758 serial_out(up, UART_MCR, up->mcr);
759
760 /* Protocol, Baud Rate, and Interrupt Settings */
761
762 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
763 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
764
765 up->efr = serial_in(up, UART_EFR);
766 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
767
768 serial_out(up, UART_LCR, 0);
769 serial_out(up, UART_IER, 0);
770 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
771
772 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
773 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
774
775 serial_out(up, UART_LCR, 0);
776 serial_out(up, UART_IER, up->ier);
777 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
778
779 serial_out(up, UART_EFR, up->efr);
780 serial_out(up, UART_LCR, cval);
781
782 if (baud > 230400 && baud != 3000000)
783 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
784 else
785 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
786
787 /* Hardware Flow Control Configuration */
788
789 if (termios->c_cflag & CRTSCTS) {
790 efr |= (UART_EFR_CTS | UART_EFR_RTS);
791 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
792
793 up->mcr = serial_in(up, UART_MCR);
794 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
795
796 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
797 up->efr = serial_in(up, UART_EFR);
798 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
799
800 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
801 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
802 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
803 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
804 serial_out(up, UART_LCR, cval);
805 }
806
807 serial_omap_set_mctrl(&up->port, up->port.mctrl);
808 /* Software Flow Control Configuration */
809 serial_omap_configure_xonxoff(up, termios);
810
811 spin_unlock_irqrestore(&up->port.lock, flags);
812 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
813}
814
815static void
816serial_omap_pm(struct uart_port *port, unsigned int state,
817 unsigned int oldstate)
818{
819 struct uart_omap_port *up = (struct uart_omap_port *)port;
820 unsigned char efr;
821
822 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
823 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
824 efr = serial_in(up, UART_EFR);
825 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
826 serial_out(up, UART_LCR, 0);
827
828 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
829 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
830 serial_out(up, UART_EFR, efr);
831 serial_out(up, UART_LCR, 0);
832}
833
834static void serial_omap_release_port(struct uart_port *port)
835{
836 dev_dbg(port->dev, "serial_omap_release_port+\n");
837}
838
839static int serial_omap_request_port(struct uart_port *port)
840{
841 dev_dbg(port->dev, "serial_omap_request_port+\n");
842 return 0;
843}
844
845static void serial_omap_config_port(struct uart_port *port, int flags)
846{
847 struct uart_omap_port *up = (struct uart_omap_port *)port;
848
849 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
850 up->pdev->id);
851 up->port.type = PORT_OMAP;
852}
853
854static int
855serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
856{
857 /* we don't want the core code to modify any port params */
858 dev_dbg(port->dev, "serial_omap_verify_port+\n");
859 return -EINVAL;
860}
861
862static const char *
863serial_omap_type(struct uart_port *port)
864{
865 struct uart_omap_port *up = (struct uart_omap_port *)port;
866
867 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
868 return up->name;
869}
870
871#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
872
873static inline void wait_for_xmitr(struct uart_omap_port *up)
874{
875 unsigned int status, tmout = 10000;
876
877 /* Wait up to 10ms for the character(s) to be sent. */
878 do {
879 status = serial_in(up, UART_LSR);
880
881 if (status & UART_LSR_BI)
882 up->lsr_break_flag = UART_LSR_BI;
883
884 if (--tmout == 0)
885 break;
886 udelay(1);
887 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
888
889 /* Wait up to 1s for flow control if necessary */
890 if (up->port.flags & UPF_CONS_FLOW) {
891 tmout = 1000000;
892 for (tmout = 1000000; tmout; tmout--) {
893 unsigned int msr = serial_in(up, UART_MSR);
894
895 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
896 if (msr & UART_MSR_CTS)
897 break;
898
899 udelay(1);
900 }
901 }
902}
903
904#ifdef CONFIG_CONSOLE_POLL
905
906static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
907{
908 struct uart_omap_port *up = (struct uart_omap_port *)port;
909 wait_for_xmitr(up);
910 serial_out(up, UART_TX, ch);
911}
912
913static int serial_omap_poll_get_char(struct uart_port *port)
914{
915 struct uart_omap_port *up = (struct uart_omap_port *)port;
916 unsigned int status = serial_in(up, UART_LSR);
917
918 if (!(status & UART_LSR_DR))
919 return NO_POLL_CHAR;
920
921 return serial_in(up, UART_RX);
922}
923
924#endif /* CONFIG_CONSOLE_POLL */
925
926#ifdef CONFIG_SERIAL_OMAP_CONSOLE
927
928static struct uart_omap_port *serial_omap_console_ports[4];
929
930static struct uart_driver serial_omap_reg;
931
932static void serial_omap_console_putchar(struct uart_port *port, int ch)
933{
934 struct uart_omap_port *up = (struct uart_omap_port *)port;
935
936 wait_for_xmitr(up);
937 serial_out(up, UART_TX, ch);
938}
939
940static void
941serial_omap_console_write(struct console *co, const char *s,
942 unsigned int count)
943{
944 struct uart_omap_port *up = serial_omap_console_ports[co->index];
945 unsigned long flags;
946 unsigned int ier;
947 int locked = 1;
948
949 local_irq_save(flags);
950 if (up->port.sysrq)
951 locked = 0;
952 else if (oops_in_progress)
953 locked = spin_trylock(&up->port.lock);
954 else
955 spin_lock(&up->port.lock);
956
957 /*
958 * First save the IER then disable the interrupts
959 */
960 ier = serial_in(up, UART_IER);
961 serial_out(up, UART_IER, 0);
962
963 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
964
965 /*
966 * Finally, wait for transmitter to become empty
967 * and restore the IER
968 */
969 wait_for_xmitr(up);
970 serial_out(up, UART_IER, ier);
971 /*
972 * The receive handling will happen properly because the
973 * receive ready bit will still be set; it is not cleared
974 * on read. However, modem control will not, we must
975 * call it if we have saved something in the saved flags
976 * while processing with interrupts off.
977 */
978 if (up->msr_saved_flags)
979 check_modem_status(up);
980
981 if (locked)
982 spin_unlock(&up->port.lock);
983 local_irq_restore(flags);
984}
985
986static int __init
987serial_omap_console_setup(struct console *co, char *options)
988{
989 struct uart_omap_port *up;
990 int baud = 115200;
991 int bits = 8;
992 int parity = 'n';
993 int flow = 'n';
994
995 if (serial_omap_console_ports[co->index] == NULL)
996 return -ENODEV;
997 up = serial_omap_console_ports[co->index];
998
999 if (options)
1000 uart_parse_options(options, &baud, &parity, &bits, &flow);
1001
1002 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1003}
1004
1005static struct console serial_omap_console = {
1006 .name = OMAP_SERIAL_NAME,
1007 .write = serial_omap_console_write,
1008 .device = uart_console_device,
1009 .setup = serial_omap_console_setup,
1010 .flags = CON_PRINTBUFFER,
1011 .index = -1,
1012 .data = &serial_omap_reg,
1013};
1014
1015static void serial_omap_add_console_port(struct uart_omap_port *up)
1016{
1017 serial_omap_console_ports[up->pdev->id] = up;
1018}
1019
1020#define OMAP_CONSOLE (&serial_omap_console)
1021
1022#else
1023
1024#define OMAP_CONSOLE NULL
1025
1026static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1027{}
1028
1029#endif
1030
1031static struct uart_ops serial_omap_pops = {
1032 .tx_empty = serial_omap_tx_empty,
1033 .set_mctrl = serial_omap_set_mctrl,
1034 .get_mctrl = serial_omap_get_mctrl,
1035 .stop_tx = serial_omap_stop_tx,
1036 .start_tx = serial_omap_start_tx,
1037 .stop_rx = serial_omap_stop_rx,
1038 .enable_ms = serial_omap_enable_ms,
1039 .break_ctl = serial_omap_break_ctl,
1040 .startup = serial_omap_startup,
1041 .shutdown = serial_omap_shutdown,
1042 .set_termios = serial_omap_set_termios,
1043 .pm = serial_omap_pm,
1044 .type = serial_omap_type,
1045 .release_port = serial_omap_release_port,
1046 .request_port = serial_omap_request_port,
1047 .config_port = serial_omap_config_port,
1048 .verify_port = serial_omap_verify_port,
1049#ifdef CONFIG_CONSOLE_POLL
1050 .poll_put_char = serial_omap_poll_put_char,
1051 .poll_get_char = serial_omap_poll_get_char,
1052#endif
1053};
1054
1055static struct uart_driver serial_omap_reg = {
1056 .owner = THIS_MODULE,
1057 .driver_name = "OMAP-SERIAL",
1058 .dev_name = OMAP_SERIAL_NAME,
1059 .nr = OMAP_MAX_HSUART_PORTS,
1060 .cons = OMAP_CONSOLE,
1061};
1062
1063static int
1064serial_omap_suspend(struct platform_device *pdev, pm_message_t state)
1065{
1066 struct uart_omap_port *up = platform_get_drvdata(pdev);
1067
1068 if (up)
1069 uart_suspend_port(&serial_omap_reg, &up->port);
1070 return 0;
1071}
1072
1073static int serial_omap_resume(struct platform_device *dev)
1074{
1075 struct uart_omap_port *up = platform_get_drvdata(dev);
1076
1077 if (up)
1078 uart_resume_port(&serial_omap_reg, &up->port);
1079 return 0;
1080}
1081
1082static void serial_omap_rx_timeout(unsigned long uart_no)
1083{
1084 struct uart_omap_port *up = ui[uart_no];
1085 unsigned int curr_dma_pos, curr_transmitted_size;
1086 int ret = 0;
1087
1088 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1089 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1090 (curr_dma_pos == 0)) {
1091 if (jiffies_to_msecs(jiffies - up->port_activity) <
1092 RX_TIMEOUT) {
1093 mod_timer(&up->uart_dma.rx_timer, jiffies +
1094 usecs_to_jiffies(up->uart_dma.rx_timeout));
1095 } else {
1096 serial_omap_stop_rxdma(up);
1097 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1098 serial_out(up, UART_IER, up->ier);
1099 }
1100 return;
1101 }
1102
1103 curr_transmitted_size = curr_dma_pos -
1104 up->uart_dma.prev_rx_dma_pos;
1105 up->port.icount.rx += curr_transmitted_size;
1106 tty_insert_flip_string(up->port.state->port.tty,
1107 up->uart_dma.rx_buf +
1108 (up->uart_dma.prev_rx_dma_pos -
1109 up->uart_dma.rx_buf_dma_phys),
1110 curr_transmitted_size);
1111 tty_flip_buffer_push(up->port.state->port.tty);
1112 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1113 if (up->uart_dma.rx_buf_size +
1114 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1115 ret = serial_omap_start_rxdma(up);
1116 if (ret < 0) {
1117 serial_omap_stop_rxdma(up);
1118 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1119 serial_out(up, UART_IER, up->ier);
1120 }
1121 } else {
1122 mod_timer(&up->uart_dma.rx_timer, jiffies +
1123 usecs_to_jiffies(up->uart_dma.rx_timeout));
1124 }
1125 up->port_activity = jiffies;
1126}
1127
1128static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1129{
1130 return;
1131}
1132
1133static int serial_omap_start_rxdma(struct uart_omap_port *up)
1134{
1135 int ret = 0;
1136
1137 if (up->uart_dma.rx_dma_channel == -1) {
1138 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1139 "UART Rx DMA",
1140 (void *)uart_rx_dma_callback, up,
1141 &(up->uart_dma.rx_dma_channel));
1142 if (ret < 0)
1143 return ret;
1144
1145 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1146 OMAP_DMA_AMODE_CONSTANT,
1147 up->uart_dma.uart_base, 0, 0);
1148 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1149 OMAP_DMA_AMODE_POST_INC,
1150 up->uart_dma.rx_buf_dma_phys, 0, 0);
1151 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1152 OMAP_DMA_DATA_TYPE_S8,
1153 up->uart_dma.rx_buf_size, 1,
1154 OMAP_DMA_SYNC_ELEMENT,
1155 up->uart_dma.uart_dma_rx, 0);
1156 }
1157 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1158 /* FIXME: Cache maintenance needed here? */
1159 omap_start_dma(up->uart_dma.rx_dma_channel);
1160 mod_timer(&up->uart_dma.rx_timer, jiffies +
1161 usecs_to_jiffies(up->uart_dma.rx_timeout));
1162 up->uart_dma.rx_dma_used = true;
1163 return ret;
1164}
1165
1166static void serial_omap_continue_tx(struct uart_omap_port *up)
1167{
1168 struct circ_buf *xmit = &up->port.state->xmit;
1169 unsigned int start = up->uart_dma.tx_buf_dma_phys
1170 + (xmit->tail & (UART_XMIT_SIZE - 1));
1171
1172 if (uart_circ_empty(xmit))
1173 return;
1174
1175 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1176 /*
1177 * It is a circular buffer. See if the buffer has wounded back.
1178 * If yes it will have to be transferred in two separate dma
1179 * transfers
1180 */
1181 if (start + up->uart_dma.tx_buf_size >=
1182 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1183 up->uart_dma.tx_buf_size =
1184 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1185 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1186 OMAP_DMA_AMODE_CONSTANT,
1187 up->uart_dma.uart_base, 0, 0);
1188 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1189 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1190 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1191 OMAP_DMA_DATA_TYPE_S8,
1192 up->uart_dma.tx_buf_size, 1,
1193 OMAP_DMA_SYNC_ELEMENT,
1194 up->uart_dma.uart_dma_tx, 0);
1195 /* FIXME: Cache maintenance needed here? */
1196 omap_start_dma(up->uart_dma.tx_dma_channel);
1197}
1198
1199static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1200{
1201 struct uart_omap_port *up = (struct uart_omap_port *)data;
1202 struct circ_buf *xmit = &up->port.state->xmit;
1203
1204 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1205 (UART_XMIT_SIZE - 1);
1206 up->port.icount.tx += up->uart_dma.tx_buf_size;
1207
1208 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1209 uart_write_wakeup(&up->port);
1210
1211 if (uart_circ_empty(xmit)) {
1212 spin_lock(&(up->uart_dma.tx_lock));
1213 serial_omap_stop_tx(&up->port);
1214 up->uart_dma.tx_dma_used = false;
1215 spin_unlock(&(up->uart_dma.tx_lock));
1216 } else {
1217 omap_stop_dma(up->uart_dma.tx_dma_channel);
1218 serial_omap_continue_tx(up);
1219 }
1220 up->port_activity = jiffies;
1221 return;
1222}
1223
1224static int serial_omap_probe(struct platform_device *pdev)
1225{
1226 struct uart_omap_port *up;
1227 struct resource *mem, *irq, *dma_tx, *dma_rx;
1228 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1229 int ret = -ENOSPC;
1230
1231 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1232 if (!mem) {
1233 dev_err(&pdev->dev, "no mem resource?\n");
1234 return -ENODEV;
1235 }
1236
1237 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1238 if (!irq) {
1239 dev_err(&pdev->dev, "no irq resource?\n");
1240 return -ENODEV;
1241 }
1242
1243 if (!request_mem_region(mem->start, resource_size(mem),
1244 pdev->dev.driver->name)) {
1245 dev_err(&pdev->dev, "memory region already claimed\n");
1246 return -EBUSY;
1247 }
1248
1249 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1250 if (!dma_rx) {
1251 ret = -EINVAL;
1252 goto err;
1253 }
1254
1255 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1256 if (!dma_tx) {
1257 ret = -EINVAL;
1258 goto err;
1259 }
1260
1261 up = kzalloc(sizeof(*up), GFP_KERNEL);
1262 if (up == NULL) {
1263 ret = -ENOMEM;
1264 goto do_release_region;
1265 }
1266 sprintf(up->name, "OMAP UART%d", pdev->id);
1267 up->pdev = pdev;
1268 up->port.dev = &pdev->dev;
1269 up->port.type = PORT_OMAP;
1270 up->port.iotype = UPIO_MEM;
1271 up->port.irq = irq->start;
1272
1273 up->port.regshift = 2;
1274 up->port.fifosize = 64;
1275 up->port.ops = &serial_omap_pops;
1276 up->port.line = pdev->id;
1277
1278 up->port.membase = omap_up_info->membase;
1279 up->port.mapbase = omap_up_info->mapbase;
1280 up->port.flags = omap_up_info->flags;
1281 up->port.irqflags = omap_up_info->irqflags;
1282 up->port.uartclk = omap_up_info->uartclk;
1283 up->uart_dma.uart_base = mem->start;
1284
1285 if (omap_up_info->dma_enabled) {
1286 up->uart_dma.uart_dma_tx = dma_tx->start;
1287 up->uart_dma.uart_dma_rx = dma_rx->start;
1288 up->use_dma = 1;
1289 up->uart_dma.rx_buf_size = 4096;
1290 up->uart_dma.rx_timeout = 2;
1291 spin_lock_init(&(up->uart_dma.tx_lock));
1292 spin_lock_init(&(up->uart_dma.rx_lock));
1293 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1294 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1295 }
1296
1297 ui[pdev->id] = up;
1298 serial_omap_add_console_port(up);
1299
1300 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1301 if (ret != 0)
1302 goto do_release_region;
1303
1304 platform_set_drvdata(pdev, up);
1305 return 0;
1306err:
1307 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1308 pdev->id, __func__, ret);
1309do_release_region:
1310 release_mem_region(mem->start, resource_size(mem));
1311 return ret;
1312}
1313
1314static int serial_omap_remove(struct platform_device *dev)
1315{
1316 struct uart_omap_port *up = platform_get_drvdata(dev);
1317
1318 platform_set_drvdata(dev, NULL);
1319 if (up) {
1320 uart_remove_one_port(&serial_omap_reg, &up->port);
1321 kfree(up);
1322 }
1323 return 0;
1324}
1325
1326static struct platform_driver serial_omap_driver = {
1327 .probe = serial_omap_probe,
1328 .remove = serial_omap_remove,
1329
1330 .suspend = serial_omap_suspend,
1331 .resume = serial_omap_resume,
1332 .driver = {
1333 .name = DRIVER_NAME,
1334 },
1335};
1336
1337static int __init serial_omap_init(void)
1338{
1339 int ret;
1340
1341 ret = uart_register_driver(&serial_omap_reg);
1342 if (ret != 0)
1343 return ret;
1344 ret = platform_driver_register(&serial_omap_driver);
1345 if (ret != 0)
1346 uart_unregister_driver(&serial_omap_reg);
1347 return ret;
1348}
1349
1350static void __exit serial_omap_exit(void)
1351{
1352 platform_driver_unregister(&serial_omap_driver);
1353 uart_unregister_driver(&serial_omap_reg);
1354}
1355
1356module_init(serial_omap_init);
1357module_exit(serial_omap_exit);
1358
1359MODULE_DESCRIPTION("OMAP High Speed UART driver");
1360MODULE_LICENSE("GPL");
1361MODULE_AUTHOR("Texas Instruments Inc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/console.h>
26#include <linux/serial_reg.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/platform_device.h>
32#include <linux/io.h>
33#include <linux/clk.h>
34#include <linux/serial_core.h>
35#include <linux/irq.h>
36#include <linux/pm_runtime.h>
37#include <linux/pm_wakeirq.h>
38#include <linux/of.h>
39#include <linux/of_irq.h>
40#include <linux/gpio.h>
41#include <linux/of_gpio.h>
42#include <linux/platform_data/serial-omap.h>
43
44#include <dt-bindings/gpio/gpio.h>
45
46#define OMAP_MAX_HSUART_PORTS 10
47
48#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
49
50#define OMAP_UART_REV_42 0x0402
51#define OMAP_UART_REV_46 0x0406
52#define OMAP_UART_REV_52 0x0502
53#define OMAP_UART_REV_63 0x0603
54
55#define OMAP_UART_TX_WAKEUP_EN BIT(7)
56
57/* Feature flags */
58#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
59
60#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
61#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
62
63#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
64
65/* SCR register bitmasks */
66#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
67#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
68#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
69
70/* FCR register bitmasks */
71#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
72#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
73
74/* MVR register bitmasks */
75#define OMAP_UART_MVR_SCHEME_SHIFT 30
76
77#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
78#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
79#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
80
81#define OMAP_UART_MVR_MAJ_MASK 0x700
82#define OMAP_UART_MVR_MAJ_SHIFT 8
83#define OMAP_UART_MVR_MIN_MASK 0x3f
84
85#define OMAP_UART_DMA_CH_FREE -1
86
87#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
88#define OMAP_MODE13X_SPEED 230400
89
90/* WER = 0x7F
91 * Enable module level wakeup in WER reg
92 */
93#define OMAP_UART_WER_MOD_WKUP 0x7F
94
95/* Enable XON/XOFF flow control on output */
96#define OMAP_UART_SW_TX 0x08
97
98/* Enable XON/XOFF flow control on input */
99#define OMAP_UART_SW_RX 0x02
100
101#define OMAP_UART_SW_CLR 0xF0
102
103#define OMAP_UART_TCR_TRIG 0x0F
104
105struct uart_omap_dma {
106 u8 uart_dma_tx;
107 u8 uart_dma_rx;
108 int rx_dma_channel;
109 int tx_dma_channel;
110 dma_addr_t rx_buf_dma_phys;
111 dma_addr_t tx_buf_dma_phys;
112 unsigned int uart_base;
113 /*
114 * Buffer for rx dma. It is not required for tx because the buffer
115 * comes from port structure.
116 */
117 unsigned char *rx_buf;
118 unsigned int prev_rx_dma_pos;
119 int tx_buf_size;
120 int tx_dma_used;
121 int rx_dma_used;
122 spinlock_t tx_lock;
123 spinlock_t rx_lock;
124 /* timer to poll activity on rx dma */
125 struct timer_list rx_timer;
126 unsigned int rx_buf_size;
127 unsigned int rx_poll_rate;
128 unsigned int rx_timeout;
129};
130
131struct uart_omap_port {
132 struct uart_port port;
133 struct uart_omap_dma uart_dma;
134 struct device *dev;
135 int wakeirq;
136
137 unsigned char ier;
138 unsigned char lcr;
139 unsigned char mcr;
140 unsigned char fcr;
141 unsigned char efr;
142 unsigned char dll;
143 unsigned char dlh;
144 unsigned char mdr1;
145 unsigned char scr;
146 unsigned char wer;
147
148 int use_dma;
149 /*
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read, but the bits will not
152 * be immediately processed.
153 */
154 unsigned int lsr_break_flag;
155 unsigned char msr_saved_flags;
156 char name[20];
157 unsigned long port_activity;
158 int context_loss_cnt;
159 u32 errata;
160 u32 features;
161
162 int rts_gpio;
163
164 struct pm_qos_request pm_qos_request;
165 u32 latency;
166 u32 calc_latency;
167 struct work_struct qos_work;
168 bool is_suspending;
169};
170
171#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
172
173static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
174
175/* Forward declaration of functions */
176static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
177
178static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
179{
180 offset <<= up->port.regshift;
181 return readw(up->port.membase + offset);
182}
183
184static inline void serial_out(struct uart_omap_port *up, int offset, int value)
185{
186 offset <<= up->port.regshift;
187 writew(value, up->port.membase + offset);
188}
189
190static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
191{
192 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
193 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
194 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
195 serial_out(up, UART_FCR, 0);
196}
197
198#ifdef CONFIG_PM
199static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
200{
201 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
202
203 if (!pdata || !pdata->get_context_loss_count)
204 return -EINVAL;
205
206 return pdata->get_context_loss_count(up->dev);
207}
208
209/* REVISIT: Remove this when omap3 boots in device tree only mode */
210static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
211{
212 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
213
214 if (!pdata || !pdata->enable_wakeup)
215 return;
216
217 pdata->enable_wakeup(up->dev, enable);
218}
219#endif /* CONFIG_PM */
220
221/*
222 * Calculate the absolute difference between the desired and actual baud
223 * rate for the given mode.
224 */
225static inline int calculate_baud_abs_diff(struct uart_port *port,
226 unsigned int baud, unsigned int mode)
227{
228 unsigned int n = port->uartclk / (mode * baud);
229 int abs_diff;
230
231 if (n == 0)
232 n = 1;
233
234 abs_diff = baud - (port->uartclk / (mode * n));
235 if (abs_diff < 0)
236 abs_diff = -abs_diff;
237
238 return abs_diff;
239}
240
241/*
242 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
243 * @port: uart port info
244 * @baud: baudrate for which mode needs to be determined
245 *
246 * Returns true if baud rate is MODE16X and false if MODE13X
247 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
248 * and Error Rates" determines modes not for all common baud rates.
249 * E.g. for 1000000 baud rate mode must be 16x, but according to that
250 * table it's determined as 13x.
251 */
252static bool
253serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
254{
255 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
256 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
257
258 return (abs_diff_13 >= abs_diff_16);
259}
260
261/*
262 * serial_omap_get_divisor - calculate divisor value
263 * @port: uart port info
264 * @baud: baudrate for which divisor needs to be calculated.
265 */
266static unsigned int
267serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
268{
269 unsigned int mode;
270
271 if (!serial_omap_baud_is_mode16(port, baud))
272 mode = 13;
273 else
274 mode = 16;
275 return port->uartclk/(mode * baud);
276}
277
278static void serial_omap_enable_ms(struct uart_port *port)
279{
280 struct uart_omap_port *up = to_uart_omap_port(port);
281
282 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
283
284 pm_runtime_get_sync(up->dev);
285 up->ier |= UART_IER_MSI;
286 serial_out(up, UART_IER, up->ier);
287 pm_runtime_mark_last_busy(up->dev);
288 pm_runtime_put_autosuspend(up->dev);
289}
290
291static void serial_omap_stop_tx(struct uart_port *port)
292{
293 struct uart_omap_port *up = to_uart_omap_port(port);
294 int res;
295
296 pm_runtime_get_sync(up->dev);
297
298 /* Handle RS-485 */
299 if (port->rs485.flags & SER_RS485_ENABLED) {
300 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
301 /* THR interrupt is fired when both TX FIFO and TX
302 * shift register are empty. This means there's nothing
303 * left to transmit now, so make sure the THR interrupt
304 * is fired when TX FIFO is below the trigger level,
305 * disable THR interrupts and toggle the RS-485 GPIO
306 * data direction pin if needed.
307 */
308 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
309 serial_out(up, UART_OMAP_SCR, up->scr);
310 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
311 1 : 0;
312 if (gpio_get_value(up->rts_gpio) != res) {
313 if (port->rs485.delay_rts_after_send > 0)
314 mdelay(
315 port->rs485.delay_rts_after_send);
316 gpio_set_value(up->rts_gpio, res);
317 }
318 } else {
319 /* We're asked to stop, but there's still stuff in the
320 * UART FIFO, so make sure the THR interrupt is fired
321 * when both TX FIFO and TX shift register are empty.
322 * The next THR interrupt (if no transmission is started
323 * in the meantime) will indicate the end of a
324 * transmission. Therefore we _don't_ disable THR
325 * interrupts in this situation.
326 */
327 up->scr |= OMAP_UART_SCR_TX_EMPTY;
328 serial_out(up, UART_OMAP_SCR, up->scr);
329 return;
330 }
331 }
332
333 if (up->ier & UART_IER_THRI) {
334 up->ier &= ~UART_IER_THRI;
335 serial_out(up, UART_IER, up->ier);
336 }
337
338 if ((port->rs485.flags & SER_RS485_ENABLED) &&
339 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
340 /*
341 * Empty the RX FIFO, we are not interested in anything
342 * received during the half-duplex transmission.
343 */
344 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
345 /* Re-enable RX interrupts */
346 up->ier |= UART_IER_RLSI | UART_IER_RDI;
347 up->port.read_status_mask |= UART_LSR_DR;
348 serial_out(up, UART_IER, up->ier);
349 }
350
351 pm_runtime_mark_last_busy(up->dev);
352 pm_runtime_put_autosuspend(up->dev);
353}
354
355static void serial_omap_stop_rx(struct uart_port *port)
356{
357 struct uart_omap_port *up = to_uart_omap_port(port);
358
359 pm_runtime_get_sync(up->dev);
360 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
361 up->port.read_status_mask &= ~UART_LSR_DR;
362 serial_out(up, UART_IER, up->ier);
363 pm_runtime_mark_last_busy(up->dev);
364 pm_runtime_put_autosuspend(up->dev);
365}
366
367static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
368{
369 struct circ_buf *xmit = &up->port.state->xmit;
370 int count;
371
372 if (up->port.x_char) {
373 serial_out(up, UART_TX, up->port.x_char);
374 up->port.icount.tx++;
375 up->port.x_char = 0;
376 return;
377 }
378 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
379 serial_omap_stop_tx(&up->port);
380 return;
381 }
382 count = up->port.fifosize / 4;
383 do {
384 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
385 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
386 up->port.icount.tx++;
387 if (uart_circ_empty(xmit))
388 break;
389 } while (--count > 0);
390
391 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
392 uart_write_wakeup(&up->port);
393
394 if (uart_circ_empty(xmit))
395 serial_omap_stop_tx(&up->port);
396}
397
398static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
399{
400 if (!(up->ier & UART_IER_THRI)) {
401 up->ier |= UART_IER_THRI;
402 serial_out(up, UART_IER, up->ier);
403 }
404}
405
406static void serial_omap_start_tx(struct uart_port *port)
407{
408 struct uart_omap_port *up = to_uart_omap_port(port);
409 int res;
410
411 pm_runtime_get_sync(up->dev);
412
413 /* Handle RS-485 */
414 if (port->rs485.flags & SER_RS485_ENABLED) {
415 /* Fire THR interrupts when FIFO is below trigger level */
416 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
417 serial_out(up, UART_OMAP_SCR, up->scr);
418
419 /* if rts not already enabled */
420 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
421 if (gpio_get_value(up->rts_gpio) != res) {
422 gpio_set_value(up->rts_gpio, res);
423 if (port->rs485.delay_rts_before_send > 0)
424 mdelay(port->rs485.delay_rts_before_send);
425 }
426 }
427
428 if ((port->rs485.flags & SER_RS485_ENABLED) &&
429 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
430 serial_omap_stop_rx(port);
431
432 serial_omap_enable_ier_thri(up);
433 pm_runtime_mark_last_busy(up->dev);
434 pm_runtime_put_autosuspend(up->dev);
435}
436
437static void serial_omap_throttle(struct uart_port *port)
438{
439 struct uart_omap_port *up = to_uart_omap_port(port);
440 unsigned long flags;
441
442 pm_runtime_get_sync(up->dev);
443 spin_lock_irqsave(&up->port.lock, flags);
444 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
445 serial_out(up, UART_IER, up->ier);
446 spin_unlock_irqrestore(&up->port.lock, flags);
447 pm_runtime_mark_last_busy(up->dev);
448 pm_runtime_put_autosuspend(up->dev);
449}
450
451static void serial_omap_unthrottle(struct uart_port *port)
452{
453 struct uart_omap_port *up = to_uart_omap_port(port);
454 unsigned long flags;
455
456 pm_runtime_get_sync(up->dev);
457 spin_lock_irqsave(&up->port.lock, flags);
458 up->ier |= UART_IER_RLSI | UART_IER_RDI;
459 serial_out(up, UART_IER, up->ier);
460 spin_unlock_irqrestore(&up->port.lock, flags);
461 pm_runtime_mark_last_busy(up->dev);
462 pm_runtime_put_autosuspend(up->dev);
463}
464
465static unsigned int check_modem_status(struct uart_omap_port *up)
466{
467 unsigned int status;
468
469 status = serial_in(up, UART_MSR);
470 status |= up->msr_saved_flags;
471 up->msr_saved_flags = 0;
472 if ((status & UART_MSR_ANY_DELTA) == 0)
473 return status;
474
475 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
476 up->port.state != NULL) {
477 if (status & UART_MSR_TERI)
478 up->port.icount.rng++;
479 if (status & UART_MSR_DDSR)
480 up->port.icount.dsr++;
481 if (status & UART_MSR_DDCD)
482 uart_handle_dcd_change
483 (&up->port, status & UART_MSR_DCD);
484 if (status & UART_MSR_DCTS)
485 uart_handle_cts_change
486 (&up->port, status & UART_MSR_CTS);
487 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
488 }
489
490 return status;
491}
492
493static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
494{
495 unsigned int flag;
496 unsigned char ch = 0;
497
498 if (likely(lsr & UART_LSR_DR))
499 ch = serial_in(up, UART_RX);
500
501 up->port.icount.rx++;
502 flag = TTY_NORMAL;
503
504 if (lsr & UART_LSR_BI) {
505 flag = TTY_BREAK;
506 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
507 up->port.icount.brk++;
508 /*
509 * We do the SysRQ and SAK checking
510 * here because otherwise the break
511 * may get masked by ignore_status_mask
512 * or read_status_mask.
513 */
514 if (uart_handle_break(&up->port))
515 return;
516
517 }
518
519 if (lsr & UART_LSR_PE) {
520 flag = TTY_PARITY;
521 up->port.icount.parity++;
522 }
523
524 if (lsr & UART_LSR_FE) {
525 flag = TTY_FRAME;
526 up->port.icount.frame++;
527 }
528
529 if (lsr & UART_LSR_OE)
530 up->port.icount.overrun++;
531
532#ifdef CONFIG_SERIAL_OMAP_CONSOLE
533 if (up->port.line == up->port.cons->index) {
534 /* Recover the break flag from console xmit */
535 lsr |= up->lsr_break_flag;
536 }
537#endif
538 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
539}
540
541static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
542{
543 unsigned char ch = 0;
544 unsigned int flag;
545
546 if (!(lsr & UART_LSR_DR))
547 return;
548
549 ch = serial_in(up, UART_RX);
550 flag = TTY_NORMAL;
551 up->port.icount.rx++;
552
553 if (uart_handle_sysrq_char(&up->port, ch))
554 return;
555
556 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
557}
558
559/**
560 * serial_omap_irq() - This handles the interrupt from one port
561 * @irq: uart port irq number
562 * @dev_id: uart port info
563 */
564static irqreturn_t serial_omap_irq(int irq, void *dev_id)
565{
566 struct uart_omap_port *up = dev_id;
567 unsigned int iir, lsr;
568 unsigned int type;
569 irqreturn_t ret = IRQ_NONE;
570 int max_count = 256;
571
572 spin_lock(&up->port.lock);
573 pm_runtime_get_sync(up->dev);
574
575 do {
576 iir = serial_in(up, UART_IIR);
577 if (iir & UART_IIR_NO_INT)
578 break;
579
580 ret = IRQ_HANDLED;
581 lsr = serial_in(up, UART_LSR);
582
583 /* extract IRQ type from IIR register */
584 type = iir & 0x3e;
585
586 switch (type) {
587 case UART_IIR_MSI:
588 check_modem_status(up);
589 break;
590 case UART_IIR_THRI:
591 transmit_chars(up, lsr);
592 break;
593 case UART_IIR_RX_TIMEOUT:
594 /* FALLTHROUGH */
595 case UART_IIR_RDI:
596 serial_omap_rdi(up, lsr);
597 break;
598 case UART_IIR_RLSI:
599 serial_omap_rlsi(up, lsr);
600 break;
601 case UART_IIR_CTS_RTS_DSR:
602 /* simply try again */
603 break;
604 case UART_IIR_XOFF:
605 /* FALLTHROUGH */
606 default:
607 break;
608 }
609 } while (max_count--);
610
611 spin_unlock(&up->port.lock);
612
613 tty_flip_buffer_push(&up->port.state->port);
614
615 pm_runtime_mark_last_busy(up->dev);
616 pm_runtime_put_autosuspend(up->dev);
617 up->port_activity = jiffies;
618
619 return ret;
620}
621
622static unsigned int serial_omap_tx_empty(struct uart_port *port)
623{
624 struct uart_omap_port *up = to_uart_omap_port(port);
625 unsigned long flags = 0;
626 unsigned int ret = 0;
627
628 pm_runtime_get_sync(up->dev);
629 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
630 spin_lock_irqsave(&up->port.lock, flags);
631 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
632 spin_unlock_irqrestore(&up->port.lock, flags);
633 pm_runtime_mark_last_busy(up->dev);
634 pm_runtime_put_autosuspend(up->dev);
635 return ret;
636}
637
638static unsigned int serial_omap_get_mctrl(struct uart_port *port)
639{
640 struct uart_omap_port *up = to_uart_omap_port(port);
641 unsigned int status;
642 unsigned int ret = 0;
643
644 pm_runtime_get_sync(up->dev);
645 status = check_modem_status(up);
646 pm_runtime_mark_last_busy(up->dev);
647 pm_runtime_put_autosuspend(up->dev);
648
649 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
650
651 if (status & UART_MSR_DCD)
652 ret |= TIOCM_CAR;
653 if (status & UART_MSR_RI)
654 ret |= TIOCM_RNG;
655 if (status & UART_MSR_DSR)
656 ret |= TIOCM_DSR;
657 if (status & UART_MSR_CTS)
658 ret |= TIOCM_CTS;
659 return ret;
660}
661
662static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
663{
664 struct uart_omap_port *up = to_uart_omap_port(port);
665 unsigned char mcr = 0, old_mcr, lcr;
666
667 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
668 if (mctrl & TIOCM_RTS)
669 mcr |= UART_MCR_RTS;
670 if (mctrl & TIOCM_DTR)
671 mcr |= UART_MCR_DTR;
672 if (mctrl & TIOCM_OUT1)
673 mcr |= UART_MCR_OUT1;
674 if (mctrl & TIOCM_OUT2)
675 mcr |= UART_MCR_OUT2;
676 if (mctrl & TIOCM_LOOP)
677 mcr |= UART_MCR_LOOP;
678
679 pm_runtime_get_sync(up->dev);
680 old_mcr = serial_in(up, UART_MCR);
681 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
682 UART_MCR_DTR | UART_MCR_RTS);
683 up->mcr = old_mcr | mcr;
684 serial_out(up, UART_MCR, up->mcr);
685
686 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
687 lcr = serial_in(up, UART_LCR);
688 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
689 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
690 up->efr |= UART_EFR_RTS;
691 else
692 up->efr &= ~UART_EFR_RTS;
693 serial_out(up, UART_EFR, up->efr);
694 serial_out(up, UART_LCR, lcr);
695
696 pm_runtime_mark_last_busy(up->dev);
697 pm_runtime_put_autosuspend(up->dev);
698}
699
700static void serial_omap_break_ctl(struct uart_port *port, int break_state)
701{
702 struct uart_omap_port *up = to_uart_omap_port(port);
703 unsigned long flags = 0;
704
705 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
706 pm_runtime_get_sync(up->dev);
707 spin_lock_irqsave(&up->port.lock, flags);
708 if (break_state == -1)
709 up->lcr |= UART_LCR_SBC;
710 else
711 up->lcr &= ~UART_LCR_SBC;
712 serial_out(up, UART_LCR, up->lcr);
713 spin_unlock_irqrestore(&up->port.lock, flags);
714 pm_runtime_mark_last_busy(up->dev);
715 pm_runtime_put_autosuspend(up->dev);
716}
717
718static int serial_omap_startup(struct uart_port *port)
719{
720 struct uart_omap_port *up = to_uart_omap_port(port);
721 unsigned long flags = 0;
722 int retval;
723
724 /*
725 * Allocate the IRQ
726 */
727 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
728 up->name, up);
729 if (retval)
730 return retval;
731
732 /* Optional wake-up IRQ */
733 if (up->wakeirq) {
734 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
735 if (retval) {
736 free_irq(up->port.irq, up);
737 return retval;
738 }
739 }
740
741 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
742
743 pm_runtime_get_sync(up->dev);
744 /*
745 * Clear the FIFO buffers and disable them.
746 * (they will be reenabled in set_termios())
747 */
748 serial_omap_clear_fifos(up);
749
750 /*
751 * Clear the interrupt registers.
752 */
753 (void) serial_in(up, UART_LSR);
754 if (serial_in(up, UART_LSR) & UART_LSR_DR)
755 (void) serial_in(up, UART_RX);
756 (void) serial_in(up, UART_IIR);
757 (void) serial_in(up, UART_MSR);
758
759 /*
760 * Now, initialize the UART
761 */
762 serial_out(up, UART_LCR, UART_LCR_WLEN8);
763 spin_lock_irqsave(&up->port.lock, flags);
764 /*
765 * Most PC uarts need OUT2 raised to enable interrupts.
766 */
767 up->port.mctrl |= TIOCM_OUT2;
768 serial_omap_set_mctrl(&up->port, up->port.mctrl);
769 spin_unlock_irqrestore(&up->port.lock, flags);
770
771 up->msr_saved_flags = 0;
772 /*
773 * Finally, enable interrupts. Note: Modem status interrupts
774 * are set via set_termios(), which will be occurring imminently
775 * anyway, so we don't enable them here.
776 */
777 up->ier = UART_IER_RLSI | UART_IER_RDI;
778 serial_out(up, UART_IER, up->ier);
779
780 /* Enable module level wake up */
781 up->wer = OMAP_UART_WER_MOD_WKUP;
782 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
783 up->wer |= OMAP_UART_TX_WAKEUP_EN;
784
785 serial_out(up, UART_OMAP_WER, up->wer);
786
787 pm_runtime_mark_last_busy(up->dev);
788 pm_runtime_put_autosuspend(up->dev);
789 up->port_activity = jiffies;
790 return 0;
791}
792
793static void serial_omap_shutdown(struct uart_port *port)
794{
795 struct uart_omap_port *up = to_uart_omap_port(port);
796 unsigned long flags = 0;
797
798 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
799
800 pm_runtime_get_sync(up->dev);
801 /*
802 * Disable interrupts from this port
803 */
804 up->ier = 0;
805 serial_out(up, UART_IER, 0);
806
807 spin_lock_irqsave(&up->port.lock, flags);
808 up->port.mctrl &= ~TIOCM_OUT2;
809 serial_omap_set_mctrl(&up->port, up->port.mctrl);
810 spin_unlock_irqrestore(&up->port.lock, flags);
811
812 /*
813 * Disable break condition and FIFOs
814 */
815 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
816 serial_omap_clear_fifos(up);
817
818 /*
819 * Read data port to reset things, and then free the irq
820 */
821 if (serial_in(up, UART_LSR) & UART_LSR_DR)
822 (void) serial_in(up, UART_RX);
823
824 pm_runtime_mark_last_busy(up->dev);
825 pm_runtime_put_autosuspend(up->dev);
826 free_irq(up->port.irq, up);
827 dev_pm_clear_wake_irq(up->dev);
828}
829
830static void serial_omap_uart_qos_work(struct work_struct *work)
831{
832 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
833 qos_work);
834
835 pm_qos_update_request(&up->pm_qos_request, up->latency);
836}
837
838static void
839serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
840 struct ktermios *old)
841{
842 struct uart_omap_port *up = to_uart_omap_port(port);
843 unsigned char cval = 0;
844 unsigned long flags = 0;
845 unsigned int baud, quot;
846
847 switch (termios->c_cflag & CSIZE) {
848 case CS5:
849 cval = UART_LCR_WLEN5;
850 break;
851 case CS6:
852 cval = UART_LCR_WLEN6;
853 break;
854 case CS7:
855 cval = UART_LCR_WLEN7;
856 break;
857 default:
858 case CS8:
859 cval = UART_LCR_WLEN8;
860 break;
861 }
862
863 if (termios->c_cflag & CSTOPB)
864 cval |= UART_LCR_STOP;
865 if (termios->c_cflag & PARENB)
866 cval |= UART_LCR_PARITY;
867 if (!(termios->c_cflag & PARODD))
868 cval |= UART_LCR_EPAR;
869 if (termios->c_cflag & CMSPAR)
870 cval |= UART_LCR_SPAR;
871
872 /*
873 * Ask the core to calculate the divisor for us.
874 */
875
876 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
877 quot = serial_omap_get_divisor(port, baud);
878
879 /* calculate wakeup latency constraint */
880 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
881 up->latency = up->calc_latency;
882 schedule_work(&up->qos_work);
883
884 up->dll = quot & 0xff;
885 up->dlh = quot >> 8;
886 up->mdr1 = UART_OMAP_MDR1_DISABLE;
887
888 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
889 UART_FCR_ENABLE_FIFO;
890
891 /*
892 * Ok, we're now changing the port state. Do it with
893 * interrupts disabled.
894 */
895 pm_runtime_get_sync(up->dev);
896 spin_lock_irqsave(&up->port.lock, flags);
897
898 /*
899 * Update the per-port timeout.
900 */
901 uart_update_timeout(port, termios->c_cflag, baud);
902
903 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
904 if (termios->c_iflag & INPCK)
905 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
906 if (termios->c_iflag & (BRKINT | PARMRK))
907 up->port.read_status_mask |= UART_LSR_BI;
908
909 /*
910 * Characters to ignore
911 */
912 up->port.ignore_status_mask = 0;
913 if (termios->c_iflag & IGNPAR)
914 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
915 if (termios->c_iflag & IGNBRK) {
916 up->port.ignore_status_mask |= UART_LSR_BI;
917 /*
918 * If we're ignoring parity and break indicators,
919 * ignore overruns too (for real raw support).
920 */
921 if (termios->c_iflag & IGNPAR)
922 up->port.ignore_status_mask |= UART_LSR_OE;
923 }
924
925 /*
926 * ignore all characters if CREAD is not set
927 */
928 if ((termios->c_cflag & CREAD) == 0)
929 up->port.ignore_status_mask |= UART_LSR_DR;
930
931 /*
932 * Modem status interrupts
933 */
934 up->ier &= ~UART_IER_MSI;
935 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
936 up->ier |= UART_IER_MSI;
937 serial_out(up, UART_IER, up->ier);
938 serial_out(up, UART_LCR, cval); /* reset DLAB */
939 up->lcr = cval;
940 up->scr = 0;
941
942 /* FIFOs and DMA Settings */
943
944 /* FCR can be changed only when the
945 * baud clock is not running
946 * DLL_REG and DLH_REG set to 0.
947 */
948 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
949 serial_out(up, UART_DLL, 0);
950 serial_out(up, UART_DLM, 0);
951 serial_out(up, UART_LCR, 0);
952
953 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
954
955 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
956 up->efr &= ~UART_EFR_SCD;
957 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
958
959 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
960 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
961 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
962 /* FIFO ENABLE, DMA MODE */
963
964 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
965 /*
966 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
967 * sets Enables the granularity of 1 for TRIGGER RX
968 * level. Along with setting RX FIFO trigger level
969 * to 1 (as noted below, 16 characters) and TLR[3:0]
970 * to zero this will result RX FIFO threshold level
971 * to 1 character, instead of 16 as noted in comment
972 * below.
973 */
974
975 /* Set receive FIFO threshold to 16 characters and
976 * transmit FIFO threshold to 32 spaces
977 */
978 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
979 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
980 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
981 UART_FCR_ENABLE_FIFO;
982
983 serial_out(up, UART_FCR, up->fcr);
984 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
985
986 serial_out(up, UART_OMAP_SCR, up->scr);
987
988 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
990 serial_out(up, UART_MCR, up->mcr);
991 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
992 serial_out(up, UART_EFR, up->efr);
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
994
995 /* Protocol, Baud Rate, and Interrupt Settings */
996
997 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
998 serial_omap_mdr1_errataset(up, up->mdr1);
999 else
1000 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1001
1002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1003 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1004
1005 serial_out(up, UART_LCR, 0);
1006 serial_out(up, UART_IER, 0);
1007 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1008
1009 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1010 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1011
1012 serial_out(up, UART_LCR, 0);
1013 serial_out(up, UART_IER, up->ier);
1014 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1015
1016 serial_out(up, UART_EFR, up->efr);
1017 serial_out(up, UART_LCR, cval);
1018
1019 if (!serial_omap_baud_is_mode16(port, baud))
1020 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1021 else
1022 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1023
1024 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1025 serial_omap_mdr1_errataset(up, up->mdr1);
1026 else
1027 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1028
1029 /* Configure flow control */
1030 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1031
1032 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1033 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1034 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1035
1036 /* Enable access to TCR/TLR */
1037 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1038 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1039 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1040
1041 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1042
1043 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1044
1045 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1046 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1047 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1048 up->efr |= UART_EFR_CTS;
1049 } else {
1050 /* Disable AUTORTS and AUTOCTS */
1051 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1052 }
1053
1054 if (up->port.flags & UPF_SOFT_FLOW) {
1055 /* clear SW control mode bits */
1056 up->efr &= OMAP_UART_SW_CLR;
1057
1058 /*
1059 * IXON Flag:
1060 * Enable XON/XOFF flow control on input.
1061 * Receiver compares XON1, XOFF1.
1062 */
1063 if (termios->c_iflag & IXON)
1064 up->efr |= OMAP_UART_SW_RX;
1065
1066 /*
1067 * IXOFF Flag:
1068 * Enable XON/XOFF flow control on output.
1069 * Transmit XON1, XOFF1
1070 */
1071 if (termios->c_iflag & IXOFF) {
1072 up->port.status |= UPSTAT_AUTOXOFF;
1073 up->efr |= OMAP_UART_SW_TX;
1074 }
1075
1076 /*
1077 * IXANY Flag:
1078 * Enable any character to restart output.
1079 * Operation resumes after receiving any
1080 * character after recognition of the XOFF character
1081 */
1082 if (termios->c_iflag & IXANY)
1083 up->mcr |= UART_MCR_XONANY;
1084 else
1085 up->mcr &= ~UART_MCR_XONANY;
1086 }
1087 serial_out(up, UART_MCR, up->mcr);
1088 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1089 serial_out(up, UART_EFR, up->efr);
1090 serial_out(up, UART_LCR, up->lcr);
1091
1092 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1093
1094 spin_unlock_irqrestore(&up->port.lock, flags);
1095 pm_runtime_mark_last_busy(up->dev);
1096 pm_runtime_put_autosuspend(up->dev);
1097 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1098}
1099
1100static void
1101serial_omap_pm(struct uart_port *port, unsigned int state,
1102 unsigned int oldstate)
1103{
1104 struct uart_omap_port *up = to_uart_omap_port(port);
1105 unsigned char efr;
1106
1107 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1108
1109 pm_runtime_get_sync(up->dev);
1110 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1111 efr = serial_in(up, UART_EFR);
1112 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1113 serial_out(up, UART_LCR, 0);
1114
1115 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1116 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1117 serial_out(up, UART_EFR, efr);
1118 serial_out(up, UART_LCR, 0);
1119
1120 pm_runtime_mark_last_busy(up->dev);
1121 pm_runtime_put_autosuspend(up->dev);
1122}
1123
1124static void serial_omap_release_port(struct uart_port *port)
1125{
1126 dev_dbg(port->dev, "serial_omap_release_port+\n");
1127}
1128
1129static int serial_omap_request_port(struct uart_port *port)
1130{
1131 dev_dbg(port->dev, "serial_omap_request_port+\n");
1132 return 0;
1133}
1134
1135static void serial_omap_config_port(struct uart_port *port, int flags)
1136{
1137 struct uart_omap_port *up = to_uart_omap_port(port);
1138
1139 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1140 up->port.line);
1141 up->port.type = PORT_OMAP;
1142 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1143}
1144
1145static int
1146serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1147{
1148 /* we don't want the core code to modify any port params */
1149 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1150 return -EINVAL;
1151}
1152
1153static const char *
1154serial_omap_type(struct uart_port *port)
1155{
1156 struct uart_omap_port *up = to_uart_omap_port(port);
1157
1158 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1159 return up->name;
1160}
1161
1162#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1163
1164static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1165{
1166 unsigned int status, tmout = 10000;
1167
1168 /* Wait up to 10ms for the character(s) to be sent. */
1169 do {
1170 status = serial_in(up, UART_LSR);
1171
1172 if (status & UART_LSR_BI)
1173 up->lsr_break_flag = UART_LSR_BI;
1174
1175 if (--tmout == 0)
1176 break;
1177 udelay(1);
1178 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1179
1180 /* Wait up to 1s for flow control if necessary */
1181 if (up->port.flags & UPF_CONS_FLOW) {
1182 tmout = 1000000;
1183 for (tmout = 1000000; tmout; tmout--) {
1184 unsigned int msr = serial_in(up, UART_MSR);
1185
1186 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1187 if (msr & UART_MSR_CTS)
1188 break;
1189
1190 udelay(1);
1191 }
1192 }
1193}
1194
1195#ifdef CONFIG_CONSOLE_POLL
1196
1197static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1198{
1199 struct uart_omap_port *up = to_uart_omap_port(port);
1200
1201 pm_runtime_get_sync(up->dev);
1202 wait_for_xmitr(up);
1203 serial_out(up, UART_TX, ch);
1204 pm_runtime_mark_last_busy(up->dev);
1205 pm_runtime_put_autosuspend(up->dev);
1206}
1207
1208static int serial_omap_poll_get_char(struct uart_port *port)
1209{
1210 struct uart_omap_port *up = to_uart_omap_port(port);
1211 unsigned int status;
1212
1213 pm_runtime_get_sync(up->dev);
1214 status = serial_in(up, UART_LSR);
1215 if (!(status & UART_LSR_DR)) {
1216 status = NO_POLL_CHAR;
1217 goto out;
1218 }
1219
1220 status = serial_in(up, UART_RX);
1221
1222out:
1223 pm_runtime_mark_last_busy(up->dev);
1224 pm_runtime_put_autosuspend(up->dev);
1225
1226 return status;
1227}
1228
1229#endif /* CONFIG_CONSOLE_POLL */
1230
1231#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1232
1233#ifdef CONFIG_SERIAL_EARLYCON
1234static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1235{
1236 offset <<= port->regshift;
1237 return readw(port->membase + offset);
1238}
1239
1240static void omap_serial_early_out(struct uart_port *port, int offset,
1241 int value)
1242{
1243 offset <<= port->regshift;
1244 writew(value, port->membase + offset);
1245}
1246
1247static void omap_serial_early_putc(struct uart_port *port, int c)
1248{
1249 unsigned int status;
1250
1251 for (;;) {
1252 status = omap_serial_early_in(port, UART_LSR);
1253 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1254 break;
1255 cpu_relax();
1256 }
1257 omap_serial_early_out(port, UART_TX, c);
1258}
1259
1260static void early_omap_serial_write(struct console *console, const char *s,
1261 unsigned int count)
1262{
1263 struct earlycon_device *device = console->data;
1264 struct uart_port *port = &device->port;
1265
1266 uart_console_write(port, s, count, omap_serial_early_putc);
1267}
1268
1269static int __init early_omap_serial_setup(struct earlycon_device *device,
1270 const char *options)
1271{
1272 struct uart_port *port = &device->port;
1273
1274 if (!(device->port.membase || device->port.iobase))
1275 return -ENODEV;
1276
1277 port->regshift = 2;
1278 device->con->write = early_omap_serial_write;
1279 return 0;
1280}
1281
1282OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1283OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1284OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1285#endif /* CONFIG_SERIAL_EARLYCON */
1286
1287static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1288
1289static struct uart_driver serial_omap_reg;
1290
1291static void serial_omap_console_putchar(struct uart_port *port, int ch)
1292{
1293 struct uart_omap_port *up = to_uart_omap_port(port);
1294
1295 wait_for_xmitr(up);
1296 serial_out(up, UART_TX, ch);
1297}
1298
1299static void
1300serial_omap_console_write(struct console *co, const char *s,
1301 unsigned int count)
1302{
1303 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1304 unsigned long flags;
1305 unsigned int ier;
1306 int locked = 1;
1307
1308 pm_runtime_get_sync(up->dev);
1309
1310 local_irq_save(flags);
1311 if (up->port.sysrq)
1312 locked = 0;
1313 else if (oops_in_progress)
1314 locked = spin_trylock(&up->port.lock);
1315 else
1316 spin_lock(&up->port.lock);
1317
1318 /*
1319 * First save the IER then disable the interrupts
1320 */
1321 ier = serial_in(up, UART_IER);
1322 serial_out(up, UART_IER, 0);
1323
1324 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1325
1326 /*
1327 * Finally, wait for transmitter to become empty
1328 * and restore the IER
1329 */
1330 wait_for_xmitr(up);
1331 serial_out(up, UART_IER, ier);
1332 /*
1333 * The receive handling will happen properly because the
1334 * receive ready bit will still be set; it is not cleared
1335 * on read. However, modem control will not, we must
1336 * call it if we have saved something in the saved flags
1337 * while processing with interrupts off.
1338 */
1339 if (up->msr_saved_flags)
1340 check_modem_status(up);
1341
1342 pm_runtime_mark_last_busy(up->dev);
1343 pm_runtime_put_autosuspend(up->dev);
1344 if (locked)
1345 spin_unlock(&up->port.lock);
1346 local_irq_restore(flags);
1347}
1348
1349static int __init
1350serial_omap_console_setup(struct console *co, char *options)
1351{
1352 struct uart_omap_port *up;
1353 int baud = 115200;
1354 int bits = 8;
1355 int parity = 'n';
1356 int flow = 'n';
1357
1358 if (serial_omap_console_ports[co->index] == NULL)
1359 return -ENODEV;
1360 up = serial_omap_console_ports[co->index];
1361
1362 if (options)
1363 uart_parse_options(options, &baud, &parity, &bits, &flow);
1364
1365 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1366}
1367
1368static struct console serial_omap_console = {
1369 .name = OMAP_SERIAL_NAME,
1370 .write = serial_omap_console_write,
1371 .device = uart_console_device,
1372 .setup = serial_omap_console_setup,
1373 .flags = CON_PRINTBUFFER,
1374 .index = -1,
1375 .data = &serial_omap_reg,
1376};
1377
1378static void serial_omap_add_console_port(struct uart_omap_port *up)
1379{
1380 serial_omap_console_ports[up->port.line] = up;
1381}
1382
1383#define OMAP_CONSOLE (&serial_omap_console)
1384
1385#else
1386
1387#define OMAP_CONSOLE NULL
1388
1389static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1390{}
1391
1392#endif
1393
1394/* Enable or disable the rs485 support */
1395static int
1396serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1397{
1398 struct uart_omap_port *up = to_uart_omap_port(port);
1399 unsigned int mode;
1400 int val;
1401
1402 pm_runtime_get_sync(up->dev);
1403
1404 /* Disable interrupts from this port */
1405 mode = up->ier;
1406 up->ier = 0;
1407 serial_out(up, UART_IER, 0);
1408
1409 /* Clamp the delays to [0, 100ms] */
1410 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1411 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1412
1413 /* store new config */
1414 port->rs485 = *rs485;
1415
1416 /*
1417 * Just as a precaution, only allow rs485
1418 * to be enabled if the gpio pin is valid
1419 */
1420 if (gpio_is_valid(up->rts_gpio)) {
1421 /* enable / disable rts */
1422 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1423 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1424 val = (port->rs485.flags & val) ? 1 : 0;
1425 gpio_set_value(up->rts_gpio, val);
1426 } else
1427 port->rs485.flags &= ~SER_RS485_ENABLED;
1428
1429 /* Enable interrupts */
1430 up->ier = mode;
1431 serial_out(up, UART_IER, up->ier);
1432
1433 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1434 * TX FIFO is below the trigger level.
1435 */
1436 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1437 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1438 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1439 serial_out(up, UART_OMAP_SCR, up->scr);
1440 }
1441
1442 pm_runtime_mark_last_busy(up->dev);
1443 pm_runtime_put_autosuspend(up->dev);
1444
1445 return 0;
1446}
1447
1448static const struct uart_ops serial_omap_pops = {
1449 .tx_empty = serial_omap_tx_empty,
1450 .set_mctrl = serial_omap_set_mctrl,
1451 .get_mctrl = serial_omap_get_mctrl,
1452 .stop_tx = serial_omap_stop_tx,
1453 .start_tx = serial_omap_start_tx,
1454 .throttle = serial_omap_throttle,
1455 .unthrottle = serial_omap_unthrottle,
1456 .stop_rx = serial_omap_stop_rx,
1457 .enable_ms = serial_omap_enable_ms,
1458 .break_ctl = serial_omap_break_ctl,
1459 .startup = serial_omap_startup,
1460 .shutdown = serial_omap_shutdown,
1461 .set_termios = serial_omap_set_termios,
1462 .pm = serial_omap_pm,
1463 .type = serial_omap_type,
1464 .release_port = serial_omap_release_port,
1465 .request_port = serial_omap_request_port,
1466 .config_port = serial_omap_config_port,
1467 .verify_port = serial_omap_verify_port,
1468#ifdef CONFIG_CONSOLE_POLL
1469 .poll_put_char = serial_omap_poll_put_char,
1470 .poll_get_char = serial_omap_poll_get_char,
1471#endif
1472};
1473
1474static struct uart_driver serial_omap_reg = {
1475 .owner = THIS_MODULE,
1476 .driver_name = "OMAP-SERIAL",
1477 .dev_name = OMAP_SERIAL_NAME,
1478 .nr = OMAP_MAX_HSUART_PORTS,
1479 .cons = OMAP_CONSOLE,
1480};
1481
1482#ifdef CONFIG_PM_SLEEP
1483static int serial_omap_prepare(struct device *dev)
1484{
1485 struct uart_omap_port *up = dev_get_drvdata(dev);
1486
1487 up->is_suspending = true;
1488
1489 return 0;
1490}
1491
1492static void serial_omap_complete(struct device *dev)
1493{
1494 struct uart_omap_port *up = dev_get_drvdata(dev);
1495
1496 up->is_suspending = false;
1497}
1498
1499static int serial_omap_suspend(struct device *dev)
1500{
1501 struct uart_omap_port *up = dev_get_drvdata(dev);
1502
1503 uart_suspend_port(&serial_omap_reg, &up->port);
1504 flush_work(&up->qos_work);
1505
1506 if (device_may_wakeup(dev))
1507 serial_omap_enable_wakeup(up, true);
1508 else
1509 serial_omap_enable_wakeup(up, false);
1510
1511 return 0;
1512}
1513
1514static int serial_omap_resume(struct device *dev)
1515{
1516 struct uart_omap_port *up = dev_get_drvdata(dev);
1517
1518 if (device_may_wakeup(dev))
1519 serial_omap_enable_wakeup(up, false);
1520
1521 uart_resume_port(&serial_omap_reg, &up->port);
1522
1523 return 0;
1524}
1525#else
1526#define serial_omap_prepare NULL
1527#define serial_omap_complete NULL
1528#endif /* CONFIG_PM_SLEEP */
1529
1530static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1531{
1532 u32 mvr, scheme;
1533 u16 revision, major, minor;
1534
1535 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1536
1537 /* Check revision register scheme */
1538 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1539
1540 switch (scheme) {
1541 case 0: /* Legacy Scheme: OMAP2/3 */
1542 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1543 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1544 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1545 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1546 break;
1547 case 1:
1548 /* New Scheme: OMAP4+ */
1549 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1550 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1551 OMAP_UART_MVR_MAJ_SHIFT;
1552 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1553 break;
1554 default:
1555 dev_warn(up->dev,
1556 "Unknown %s revision, defaulting to highest\n",
1557 up->name);
1558 /* highest possible revision */
1559 major = 0xff;
1560 minor = 0xff;
1561 }
1562
1563 /* normalize revision for the driver */
1564 revision = UART_BUILD_REVISION(major, minor);
1565
1566 switch (revision) {
1567 case OMAP_UART_REV_46:
1568 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1569 UART_ERRATA_i291_DMA_FORCEIDLE);
1570 break;
1571 case OMAP_UART_REV_52:
1572 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1573 UART_ERRATA_i291_DMA_FORCEIDLE);
1574 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1575 break;
1576 case OMAP_UART_REV_63:
1577 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1578 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1579 break;
1580 default:
1581 break;
1582 }
1583}
1584
1585static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1586{
1587 struct omap_uart_port_info *omap_up_info;
1588
1589 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1590 if (!omap_up_info)
1591 return NULL; /* out of memory */
1592
1593 of_property_read_u32(dev->of_node, "clock-frequency",
1594 &omap_up_info->uartclk);
1595
1596 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1597
1598 return omap_up_info;
1599}
1600
1601static int serial_omap_probe_rs485(struct uart_omap_port *up,
1602 struct device_node *np)
1603{
1604 struct serial_rs485 *rs485conf = &up->port.rs485;
1605 int ret;
1606
1607 rs485conf->flags = 0;
1608 up->rts_gpio = -EINVAL;
1609
1610 if (!np)
1611 return 0;
1612
1613 uart_get_rs485_mode(up->dev, rs485conf);
1614
1615 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1616 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1617 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1618 } else {
1619 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1620 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1621 }
1622
1623 /* check for tx enable gpio */
1624 up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0);
1625 if (gpio_is_valid(up->rts_gpio)) {
1626 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1627 if (ret < 0)
1628 return ret;
1629 ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0;
1630 ret = gpio_direction_output(up->rts_gpio, ret);
1631 if (ret < 0)
1632 return ret;
1633 } else if (up->rts_gpio == -EPROBE_DEFER) {
1634 return -EPROBE_DEFER;
1635 } else {
1636 up->rts_gpio = -EINVAL;
1637 }
1638
1639 return 0;
1640}
1641
1642static int serial_omap_probe(struct platform_device *pdev)
1643{
1644 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1645 struct uart_omap_port *up;
1646 struct resource *mem;
1647 void __iomem *base;
1648 int uartirq = 0;
1649 int wakeirq = 0;
1650 int ret;
1651
1652 /* The optional wakeirq may be specified in the board dts file */
1653 if (pdev->dev.of_node) {
1654 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1655 if (!uartirq)
1656 return -EPROBE_DEFER;
1657 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1658 omap_up_info = of_get_uart_port_info(&pdev->dev);
1659 pdev->dev.platform_data = omap_up_info;
1660 } else {
1661 uartirq = platform_get_irq(pdev, 0);
1662 if (uartirq < 0)
1663 return -EPROBE_DEFER;
1664 }
1665
1666 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1667 if (!up)
1668 return -ENOMEM;
1669
1670 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1671 base = devm_ioremap_resource(&pdev->dev, mem);
1672 if (IS_ERR(base))
1673 return PTR_ERR(base);
1674
1675 up->dev = &pdev->dev;
1676 up->port.dev = &pdev->dev;
1677 up->port.type = PORT_OMAP;
1678 up->port.iotype = UPIO_MEM;
1679 up->port.irq = uartirq;
1680 up->port.regshift = 2;
1681 up->port.fifosize = 64;
1682 up->port.ops = &serial_omap_pops;
1683
1684 if (pdev->dev.of_node)
1685 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1686 else
1687 ret = pdev->id;
1688
1689 if (ret < 0) {
1690 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1691 ret);
1692 goto err_port_line;
1693 }
1694 up->port.line = ret;
1695
1696 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1697 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1698 OMAP_MAX_HSUART_PORTS);
1699 ret = -ENXIO;
1700 goto err_port_line;
1701 }
1702
1703 up->wakeirq = wakeirq;
1704 if (!up->wakeirq)
1705 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1706 up->port.line);
1707
1708 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1709 if (ret < 0)
1710 goto err_rs485;
1711
1712 sprintf(up->name, "OMAP UART%d", up->port.line);
1713 up->port.mapbase = mem->start;
1714 up->port.membase = base;
1715 up->port.flags = omap_up_info->flags;
1716 up->port.uartclk = omap_up_info->uartclk;
1717 up->port.rs485_config = serial_omap_config_rs485;
1718 if (!up->port.uartclk) {
1719 up->port.uartclk = DEFAULT_CLK_SPEED;
1720 dev_warn(&pdev->dev,
1721 "No clock speed specified: using default: %d\n",
1722 DEFAULT_CLK_SPEED);
1723 }
1724
1725 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1726 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1727 pm_qos_add_request(&up->pm_qos_request,
1728 PM_QOS_CPU_DMA_LATENCY, up->latency);
1729 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1730
1731 platform_set_drvdata(pdev, up);
1732 if (omap_up_info->autosuspend_timeout == 0)
1733 omap_up_info->autosuspend_timeout = -1;
1734
1735 device_init_wakeup(up->dev, true);
1736 pm_runtime_use_autosuspend(&pdev->dev);
1737 pm_runtime_set_autosuspend_delay(&pdev->dev,
1738 omap_up_info->autosuspend_timeout);
1739
1740 pm_runtime_irq_safe(&pdev->dev);
1741 pm_runtime_enable(&pdev->dev);
1742
1743 pm_runtime_get_sync(&pdev->dev);
1744
1745 omap_serial_fill_features_erratas(up);
1746
1747 ui[up->port.line] = up;
1748 serial_omap_add_console_port(up);
1749
1750 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1751 if (ret != 0)
1752 goto err_add_port;
1753
1754 pm_runtime_mark_last_busy(up->dev);
1755 pm_runtime_put_autosuspend(up->dev);
1756 return 0;
1757
1758err_add_port:
1759 pm_runtime_dont_use_autosuspend(&pdev->dev);
1760 pm_runtime_put_sync(&pdev->dev);
1761 pm_runtime_disable(&pdev->dev);
1762 pm_qos_remove_request(&up->pm_qos_request);
1763 device_init_wakeup(up->dev, false);
1764err_rs485:
1765err_port_line:
1766 return ret;
1767}
1768
1769static int serial_omap_remove(struct platform_device *dev)
1770{
1771 struct uart_omap_port *up = platform_get_drvdata(dev);
1772
1773 pm_runtime_get_sync(up->dev);
1774
1775 uart_remove_one_port(&serial_omap_reg, &up->port);
1776
1777 pm_runtime_dont_use_autosuspend(up->dev);
1778 pm_runtime_put_sync(up->dev);
1779 pm_runtime_disable(up->dev);
1780 pm_qos_remove_request(&up->pm_qos_request);
1781 device_init_wakeup(&dev->dev, false);
1782
1783 return 0;
1784}
1785
1786/*
1787 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1788 * The access to uart register after MDR1 Access
1789 * causes UART to corrupt data.
1790 *
1791 * Need a delay =
1792 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1793 * give 10 times as much
1794 */
1795static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1796{
1797 u8 timeout = 255;
1798
1799 serial_out(up, UART_OMAP_MDR1, mdr1);
1800 udelay(2);
1801 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1802 UART_FCR_CLEAR_RCVR);
1803 /*
1804 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1805 * TX_FIFO_E bit is 1.
1806 */
1807 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1808 (UART_LSR_THRE | UART_LSR_DR))) {
1809 timeout--;
1810 if (!timeout) {
1811 /* Should *never* happen. we warn and carry on */
1812 dev_crit(up->dev, "Errata i202: timedout %x\n",
1813 serial_in(up, UART_LSR));
1814 break;
1815 }
1816 udelay(1);
1817 }
1818}
1819
1820#ifdef CONFIG_PM
1821static void serial_omap_restore_context(struct uart_omap_port *up)
1822{
1823 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1824 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1825 else
1826 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1827
1828 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1829 serial_out(up, UART_EFR, UART_EFR_ECB);
1830 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1831 serial_out(up, UART_IER, 0x0);
1832 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833 serial_out(up, UART_DLL, up->dll);
1834 serial_out(up, UART_DLM, up->dlh);
1835 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1836 serial_out(up, UART_IER, up->ier);
1837 serial_out(up, UART_FCR, up->fcr);
1838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1839 serial_out(up, UART_MCR, up->mcr);
1840 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1841 serial_out(up, UART_OMAP_SCR, up->scr);
1842 serial_out(up, UART_EFR, up->efr);
1843 serial_out(up, UART_LCR, up->lcr);
1844 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1845 serial_omap_mdr1_errataset(up, up->mdr1);
1846 else
1847 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1848 serial_out(up, UART_OMAP_WER, up->wer);
1849}
1850
1851static int serial_omap_runtime_suspend(struct device *dev)
1852{
1853 struct uart_omap_port *up = dev_get_drvdata(dev);
1854
1855 if (!up)
1856 return -EINVAL;
1857
1858 /*
1859 * When using 'no_console_suspend', the console UART must not be
1860 * suspended. Since driver suspend is managed by runtime suspend,
1861 * preventing runtime suspend (by returning error) will keep device
1862 * active during suspend.
1863 */
1864 if (up->is_suspending && !console_suspend_enabled &&
1865 uart_console(&up->port))
1866 return -EBUSY;
1867
1868 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1869
1870 serial_omap_enable_wakeup(up, true);
1871
1872 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1873 schedule_work(&up->qos_work);
1874
1875 return 0;
1876}
1877
1878static int serial_omap_runtime_resume(struct device *dev)
1879{
1880 struct uart_omap_port *up = dev_get_drvdata(dev);
1881
1882 int loss_cnt = serial_omap_get_context_loss_count(up);
1883
1884 serial_omap_enable_wakeup(up, false);
1885
1886 if (loss_cnt < 0) {
1887 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1888 loss_cnt);
1889 serial_omap_restore_context(up);
1890 } else if (up->context_loss_cnt != loss_cnt) {
1891 serial_omap_restore_context(up);
1892 }
1893 up->latency = up->calc_latency;
1894 schedule_work(&up->qos_work);
1895
1896 return 0;
1897}
1898#endif
1899
1900static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1901 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1902 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1903 serial_omap_runtime_resume, NULL)
1904 .prepare = serial_omap_prepare,
1905 .complete = serial_omap_complete,
1906};
1907
1908#if defined(CONFIG_OF)
1909static const struct of_device_id omap_serial_of_match[] = {
1910 { .compatible = "ti,omap2-uart" },
1911 { .compatible = "ti,omap3-uart" },
1912 { .compatible = "ti,omap4-uart" },
1913 {},
1914};
1915MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1916#endif
1917
1918static struct platform_driver serial_omap_driver = {
1919 .probe = serial_omap_probe,
1920 .remove = serial_omap_remove,
1921 .driver = {
1922 .name = OMAP_SERIAL_DRIVER_NAME,
1923 .pm = &serial_omap_dev_pm_ops,
1924 .of_match_table = of_match_ptr(omap_serial_of_match),
1925 },
1926};
1927
1928static int __init serial_omap_init(void)
1929{
1930 int ret;
1931
1932 ret = uart_register_driver(&serial_omap_reg);
1933 if (ret != 0)
1934 return ret;
1935 ret = platform_driver_register(&serial_omap_driver);
1936 if (ret != 0)
1937 uart_unregister_driver(&serial_omap_reg);
1938 return ret;
1939}
1940
1941static void __exit serial_omap_exit(void)
1942{
1943 platform_driver_unregister(&serial_omap_driver);
1944 uart_unregister_driver(&serial_omap_reg);
1945}
1946
1947module_init(serial_omap_init);
1948module_exit(serial_omap_exit);
1949
1950MODULE_DESCRIPTION("OMAP High Speed UART driver");
1951MODULE_LICENSE("GPL");
1952MODULE_AUTHOR("Texas Instruments Inc");