Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel pinctrl/GPIO core driver.
4 *
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#include <linux/acpi.h>
11#include <linux/interrupt.h>
12#include <linux/gpio/driver.h>
13#include <linux/log2.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/property.h>
17#include <linux/time.h>
18
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/pinctrl/pinconf.h>
22#include <linux/pinctrl/pinconf-generic.h>
23
24#include "../core.h"
25#include "pinctrl-intel.h"
26
27/* Offset from regs */
28#define REVID 0x000
29#define REVID_SHIFT 16
30#define REVID_MASK GENMASK(31, 16)
31
32#define PADBAR 0x00c
33
34#define PADOWN_BITS 4
35#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
37#define PADOWN_GPP(p) ((p) / 8)
38
39/* Offset from pad_regs */
40#define PADCFG0 0x000
41#define PADCFG0_RXEVCFG_SHIFT 25
42#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
43#define PADCFG0_RXEVCFG_LEVEL 0
44#define PADCFG0_RXEVCFG_EDGE 1
45#define PADCFG0_RXEVCFG_DISABLED 2
46#define PADCFG0_RXEVCFG_EDGE_BOTH 3
47#define PADCFG0_PREGFRXSEL BIT(24)
48#define PADCFG0_RXINV BIT(23)
49#define PADCFG0_GPIROUTIOXAPIC BIT(20)
50#define PADCFG0_GPIROUTSCI BIT(19)
51#define PADCFG0_GPIROUTSMI BIT(18)
52#define PADCFG0_GPIROUTNMI BIT(17)
53#define PADCFG0_PMODE_SHIFT 10
54#define PADCFG0_PMODE_MASK GENMASK(13, 10)
55#define PADCFG0_PMODE_GPIO 0
56#define PADCFG0_GPIORXDIS BIT(9)
57#define PADCFG0_GPIOTXDIS BIT(8)
58#define PADCFG0_GPIORXSTATE BIT(1)
59#define PADCFG0_GPIOTXSTATE BIT(0)
60
61#define PADCFG1 0x004
62#define PADCFG1_TERM_UP BIT(13)
63#define PADCFG1_TERM_SHIFT 10
64#define PADCFG1_TERM_MASK GENMASK(12, 10)
65#define PADCFG1_TERM_20K 4
66#define PADCFG1_TERM_2K 3
67#define PADCFG1_TERM_5K 2
68#define PADCFG1_TERM_1K 1
69
70#define PADCFG2 0x008
71#define PADCFG2_DEBEN BIT(0)
72#define PADCFG2_DEBOUNCE_SHIFT 1
73#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
74
75#define DEBOUNCE_PERIOD_NSEC 31250
76
77struct intel_pad_context {
78 u32 padcfg0;
79 u32 padcfg1;
80 u32 padcfg2;
81};
82
83struct intel_community_context {
84 u32 *intmask;
85 u32 *hostown;
86};
87
88struct intel_pinctrl_context {
89 struct intel_pad_context *pads;
90 struct intel_community_context *communities;
91};
92
93/**
94 * struct intel_pinctrl - Intel pinctrl private structure
95 * @dev: Pointer to the device structure
96 * @lock: Lock to serialize register access
97 * @pctldesc: Pin controller description
98 * @pctldev: Pointer to the pin controller device
99 * @chip: GPIO chip in this pin controller
100 * @irqchip: IRQ chip in this pin controller
101 * @soc: SoC/PCH specific pin configuration data
102 * @communities: All communities in this pin controller
103 * @ncommunities: Number of communities in this pin controller
104 * @context: Configuration saved over system sleep
105 * @irq: pinctrl/GPIO chip irq number
106 */
107struct intel_pinctrl {
108 struct device *dev;
109 raw_spinlock_t lock;
110 struct pinctrl_desc pctldesc;
111 struct pinctrl_dev *pctldev;
112 struct gpio_chip chip;
113 struct irq_chip irqchip;
114 const struct intel_pinctrl_soc_data *soc;
115 struct intel_community *communities;
116 size_t ncommunities;
117 struct intel_pinctrl_context context;
118 int irq;
119};
120
121#define pin_to_padno(c, p) ((p) - (c)->pin_base)
122#define padgroup_offset(g, p) ((p) - (g)->base)
123
124static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
125 unsigned int pin)
126{
127 struct intel_community *community;
128 int i;
129
130 for (i = 0; i < pctrl->ncommunities; i++) {
131 community = &pctrl->communities[i];
132 if (pin >= community->pin_base &&
133 pin < community->pin_base + community->npins)
134 return community;
135 }
136
137 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
138 return NULL;
139}
140
141static const struct intel_padgroup *
142intel_community_get_padgroup(const struct intel_community *community,
143 unsigned int pin)
144{
145 int i;
146
147 for (i = 0; i < community->ngpps; i++) {
148 const struct intel_padgroup *padgrp = &community->gpps[i];
149
150 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
151 return padgrp;
152 }
153
154 return NULL;
155}
156
157static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
158 unsigned int pin, unsigned int reg)
159{
160 const struct intel_community *community;
161 unsigned int padno;
162 size_t nregs;
163
164 community = intel_get_community(pctrl, pin);
165 if (!community)
166 return NULL;
167
168 padno = pin_to_padno(community, pin);
169 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
170
171 if (reg >= nregs * 4)
172 return NULL;
173
174 return community->pad_regs + reg + padno * nregs * 4;
175}
176
177static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
178{
179 const struct intel_community *community;
180 const struct intel_padgroup *padgrp;
181 unsigned int gpp, offset, gpp_offset;
182 void __iomem *padown;
183
184 community = intel_get_community(pctrl, pin);
185 if (!community)
186 return false;
187 if (!community->padown_offset)
188 return true;
189
190 padgrp = intel_community_get_padgroup(community, pin);
191 if (!padgrp)
192 return false;
193
194 gpp_offset = padgroup_offset(padgrp, pin);
195 gpp = PADOWN_GPP(gpp_offset);
196 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
197 padown = community->regs + offset;
198
199 return !(readl(padown) & PADOWN_MASK(gpp_offset));
200}
201
202static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
203{
204 const struct intel_community *community;
205 const struct intel_padgroup *padgrp;
206 unsigned int offset, gpp_offset;
207 void __iomem *hostown;
208
209 community = intel_get_community(pctrl, pin);
210 if (!community)
211 return true;
212 if (!community->hostown_offset)
213 return false;
214
215 padgrp = intel_community_get_padgroup(community, pin);
216 if (!padgrp)
217 return true;
218
219 gpp_offset = padgroup_offset(padgrp, pin);
220 offset = community->hostown_offset + padgrp->reg_num * 4;
221 hostown = community->regs + offset;
222
223 return !(readl(hostown) & BIT(gpp_offset));
224}
225
226/**
227 * enum - Locking variants of the pad configuration
228 *
229 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers
230 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
231 * @PAD_LOCKED_TX: pad configuration TX state is locked
232 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
233 *
234 * Locking is considered as read-only mode for corresponding registers and
235 * their respective fields. That said, TX state bit is locked separately from
236 * the main locking scheme.
237 */
238enum {
239 PAD_UNLOCKED = 0,
240 PAD_LOCKED = 1,
241 PAD_LOCKED_TX = 2,
242 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
243};
244
245static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
246{
247 struct intel_community *community;
248 const struct intel_padgroup *padgrp;
249 unsigned int offset, gpp_offset;
250 u32 value;
251 int ret = PAD_UNLOCKED;
252
253 community = intel_get_community(pctrl, pin);
254 if (!community)
255 return PAD_LOCKED_FULL;
256 if (!community->padcfglock_offset)
257 return PAD_UNLOCKED;
258
259 padgrp = intel_community_get_padgroup(community, pin);
260 if (!padgrp)
261 return PAD_LOCKED_FULL;
262
263 gpp_offset = padgroup_offset(padgrp, pin);
264
265 /*
266 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
267 * the pad is considered unlocked. Any other case means that it is
268 * either fully or partially locked.
269 */
270 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
271 value = readl(community->regs + offset);
272 if (value & BIT(gpp_offset))
273 ret |= PAD_LOCKED;
274
275 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
276 value = readl(community->regs + offset);
277 if (value & BIT(gpp_offset))
278 ret |= PAD_LOCKED_TX;
279
280 return ret;
281}
282
283static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
284{
285 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
286}
287
288static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
289{
290 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
291}
292
293static int intel_get_groups_count(struct pinctrl_dev *pctldev)
294{
295 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
296
297 return pctrl->soc->ngroups;
298}
299
300static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
301 unsigned int group)
302{
303 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
304
305 return pctrl->soc->groups[group].name;
306}
307
308static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
309 const unsigned int **pins, unsigned int *npins)
310{
311 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
312
313 *pins = pctrl->soc->groups[group].pins;
314 *npins = pctrl->soc->groups[group].npins;
315 return 0;
316}
317
318static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
319 unsigned int pin)
320{
321 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
322 void __iomem *padcfg;
323 u32 cfg0, cfg1, mode;
324 int locked;
325 bool acpi;
326
327 if (!intel_pad_owned_by_host(pctrl, pin)) {
328 seq_puts(s, "not available");
329 return;
330 }
331
332 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
333 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
334
335 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
336 if (mode == PADCFG0_PMODE_GPIO)
337 seq_puts(s, "GPIO ");
338 else
339 seq_printf(s, "mode %d ", mode);
340
341 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
342
343 /* Dump the additional PADCFG registers if available */
344 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
345 if (padcfg)
346 seq_printf(s, " 0x%08x", readl(padcfg));
347
348 locked = intel_pad_locked(pctrl, pin);
349 acpi = intel_pad_acpi_mode(pctrl, pin);
350
351 if (locked || acpi) {
352 seq_puts(s, " [");
353 if (locked)
354 seq_puts(s, "LOCKED");
355 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
356 seq_puts(s, " tx");
357 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
358 seq_puts(s, " full");
359
360 if (locked && acpi)
361 seq_puts(s, ", ");
362
363 if (acpi)
364 seq_puts(s, "ACPI");
365 seq_puts(s, "]");
366 }
367}
368
369static const struct pinctrl_ops intel_pinctrl_ops = {
370 .get_groups_count = intel_get_groups_count,
371 .get_group_name = intel_get_group_name,
372 .get_group_pins = intel_get_group_pins,
373 .pin_dbg_show = intel_pin_dbg_show,
374};
375
376static int intel_get_functions_count(struct pinctrl_dev *pctldev)
377{
378 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
379
380 return pctrl->soc->nfunctions;
381}
382
383static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
384 unsigned int function)
385{
386 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
387
388 return pctrl->soc->functions[function].name;
389}
390
391static int intel_get_function_groups(struct pinctrl_dev *pctldev,
392 unsigned int function,
393 const char * const **groups,
394 unsigned int * const ngroups)
395{
396 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
397
398 *groups = pctrl->soc->functions[function].groups;
399 *ngroups = pctrl->soc->functions[function].ngroups;
400 return 0;
401}
402
403static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
404 unsigned int function, unsigned int group)
405{
406 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
407 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
408 unsigned long flags;
409 int i;
410
411 raw_spin_lock_irqsave(&pctrl->lock, flags);
412
413 /*
414 * All pins in the groups needs to be accessible and writable
415 * before we can enable the mux for this group.
416 */
417 for (i = 0; i < grp->npins; i++) {
418 if (!intel_pad_usable(pctrl, grp->pins[i])) {
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
420 return -EBUSY;
421 }
422 }
423
424 /* Now enable the mux setting for each pin in the group */
425 for (i = 0; i < grp->npins; i++) {
426 void __iomem *padcfg0;
427 u32 value;
428
429 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
430 value = readl(padcfg0);
431
432 value &= ~PADCFG0_PMODE_MASK;
433
434 if (grp->modes)
435 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
436 else
437 value |= grp->mode << PADCFG0_PMODE_SHIFT;
438
439 writel(value, padcfg0);
440 }
441
442 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
443
444 return 0;
445}
446
447static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
448{
449 u32 value;
450
451 value = readl(padcfg0);
452 if (input) {
453 value &= ~PADCFG0_GPIORXDIS;
454 value |= PADCFG0_GPIOTXDIS;
455 } else {
456 value &= ~PADCFG0_GPIOTXDIS;
457 value |= PADCFG0_GPIORXDIS;
458 }
459 writel(value, padcfg0);
460}
461
462static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
463{
464 return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
465}
466
467static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
468{
469 u32 value;
470
471 /* Put the pad into GPIO mode */
472 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
473 /* Disable SCI/SMI/NMI generation */
474 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
475 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
476 writel(value, padcfg0);
477}
478
479static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
480 struct pinctrl_gpio_range *range,
481 unsigned int pin)
482{
483 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
484 void __iomem *padcfg0;
485 unsigned long flags;
486
487 raw_spin_lock_irqsave(&pctrl->lock, flags);
488
489 if (!intel_pad_owned_by_host(pctrl, pin)) {
490 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
491 return -EBUSY;
492 }
493
494 if (!intel_pad_is_unlocked(pctrl, pin)) {
495 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
496 return 0;
497 }
498
499 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
500
501 /*
502 * If pin is already configured in GPIO mode, we assume that
503 * firmware provides correct settings. In such case we avoid
504 * potential glitches on the pin. Otherwise, for the pin in
505 * alternative mode, consumer has to supply respective flags.
506 */
507 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
508 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
509 return 0;
510 }
511
512 intel_gpio_set_gpio_mode(padcfg0);
513
514 /* Disable TX buffer and enable RX (this will be input) */
515 __intel_gpio_set_direction(padcfg0, true);
516
517 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
518
519 return 0;
520}
521
522static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
523 struct pinctrl_gpio_range *range,
524 unsigned int pin, bool input)
525{
526 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
527 void __iomem *padcfg0;
528 unsigned long flags;
529
530 raw_spin_lock_irqsave(&pctrl->lock, flags);
531
532 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
533 __intel_gpio_set_direction(padcfg0, input);
534
535 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
536
537 return 0;
538}
539
540static const struct pinmux_ops intel_pinmux_ops = {
541 .get_functions_count = intel_get_functions_count,
542 .get_function_name = intel_get_function_name,
543 .get_function_groups = intel_get_function_groups,
544 .set_mux = intel_pinmux_set_mux,
545 .gpio_request_enable = intel_gpio_request_enable,
546 .gpio_set_direction = intel_gpio_set_direction,
547};
548
549static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
550 unsigned long *config)
551{
552 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
553 enum pin_config_param param = pinconf_to_config_param(*config);
554 const struct intel_community *community;
555 u32 value, term;
556 u32 arg = 0;
557
558 if (!intel_pad_owned_by_host(pctrl, pin))
559 return -ENOTSUPP;
560
561 community = intel_get_community(pctrl, pin);
562 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
563 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
564
565 switch (param) {
566 case PIN_CONFIG_BIAS_DISABLE:
567 if (term)
568 return -EINVAL;
569 break;
570
571 case PIN_CONFIG_BIAS_PULL_UP:
572 if (!term || !(value & PADCFG1_TERM_UP))
573 return -EINVAL;
574
575 switch (term) {
576 case PADCFG1_TERM_1K:
577 arg = 1000;
578 break;
579 case PADCFG1_TERM_2K:
580 arg = 2000;
581 break;
582 case PADCFG1_TERM_5K:
583 arg = 5000;
584 break;
585 case PADCFG1_TERM_20K:
586 arg = 20000;
587 break;
588 }
589
590 break;
591
592 case PIN_CONFIG_BIAS_PULL_DOWN:
593 if (!term || value & PADCFG1_TERM_UP)
594 return -EINVAL;
595
596 switch (term) {
597 case PADCFG1_TERM_1K:
598 if (!(community->features & PINCTRL_FEATURE_1K_PD))
599 return -EINVAL;
600 arg = 1000;
601 break;
602 case PADCFG1_TERM_5K:
603 arg = 5000;
604 break;
605 case PADCFG1_TERM_20K:
606 arg = 20000;
607 break;
608 }
609
610 break;
611
612 case PIN_CONFIG_INPUT_DEBOUNCE: {
613 void __iomem *padcfg2;
614 u32 v;
615
616 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
617 if (!padcfg2)
618 return -ENOTSUPP;
619
620 v = readl(padcfg2);
621 if (!(v & PADCFG2_DEBEN))
622 return -EINVAL;
623
624 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
625 arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
626
627 break;
628 }
629
630 default:
631 return -ENOTSUPP;
632 }
633
634 *config = pinconf_to_config_packed(param, arg);
635 return 0;
636}
637
638static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
639 unsigned long config)
640{
641 unsigned int param = pinconf_to_config_param(config);
642 unsigned int arg = pinconf_to_config_argument(config);
643 const struct intel_community *community;
644 void __iomem *padcfg1;
645 unsigned long flags;
646 int ret = 0;
647 u32 value;
648
649 raw_spin_lock_irqsave(&pctrl->lock, flags);
650
651 community = intel_get_community(pctrl, pin);
652 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
653 value = readl(padcfg1);
654
655 switch (param) {
656 case PIN_CONFIG_BIAS_DISABLE:
657 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
658 break;
659
660 case PIN_CONFIG_BIAS_PULL_UP:
661 value &= ~PADCFG1_TERM_MASK;
662
663 value |= PADCFG1_TERM_UP;
664
665 switch (arg) {
666 case 20000:
667 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
668 break;
669 case 5000:
670 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
671 break;
672 case 2000:
673 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
674 break;
675 case 1000:
676 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
677 break;
678 default:
679 ret = -EINVAL;
680 }
681
682 break;
683
684 case PIN_CONFIG_BIAS_PULL_DOWN:
685 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
686
687 switch (arg) {
688 case 20000:
689 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
690 break;
691 case 5000:
692 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
693 break;
694 case 1000:
695 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
696 ret = -EINVAL;
697 break;
698 }
699 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
700 break;
701 default:
702 ret = -EINVAL;
703 }
704
705 break;
706 }
707
708 if (!ret)
709 writel(value, padcfg1);
710
711 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
712
713 return ret;
714}
715
716static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
717 unsigned int pin, unsigned int debounce)
718{
719 void __iomem *padcfg0, *padcfg2;
720 unsigned long flags;
721 u32 value0, value2;
722 int ret = 0;
723
724 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
725 if (!padcfg2)
726 return -ENOTSUPP;
727
728 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
729
730 raw_spin_lock_irqsave(&pctrl->lock, flags);
731
732 value0 = readl(padcfg0);
733 value2 = readl(padcfg2);
734
735 /* Disable glitch filter and debouncer */
736 value0 &= ~PADCFG0_PREGFRXSEL;
737 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
738
739 if (debounce) {
740 unsigned long v;
741
742 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
743 if (v < 3 || v > 15) {
744 ret = -EINVAL;
745 goto exit_unlock;
746 } else {
747 /* Enable glitch filter and debouncer */
748 value0 |= PADCFG0_PREGFRXSEL;
749 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
750 value2 |= PADCFG2_DEBEN;
751 }
752 }
753
754 writel(value0, padcfg0);
755 writel(value2, padcfg2);
756
757exit_unlock:
758 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
759
760 return ret;
761}
762
763static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
764 unsigned long *configs, unsigned int nconfigs)
765{
766 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
767 int i, ret;
768
769 if (!intel_pad_usable(pctrl, pin))
770 return -ENOTSUPP;
771
772 for (i = 0; i < nconfigs; i++) {
773 switch (pinconf_to_config_param(configs[i])) {
774 case PIN_CONFIG_BIAS_DISABLE:
775 case PIN_CONFIG_BIAS_PULL_UP:
776 case PIN_CONFIG_BIAS_PULL_DOWN:
777 ret = intel_config_set_pull(pctrl, pin, configs[i]);
778 if (ret)
779 return ret;
780 break;
781
782 case PIN_CONFIG_INPUT_DEBOUNCE:
783 ret = intel_config_set_debounce(pctrl, pin,
784 pinconf_to_config_argument(configs[i]));
785 if (ret)
786 return ret;
787 break;
788
789 default:
790 return -ENOTSUPP;
791 }
792 }
793
794 return 0;
795}
796
797static const struct pinconf_ops intel_pinconf_ops = {
798 .is_generic = true,
799 .pin_config_get = intel_config_get,
800 .pin_config_set = intel_config_set,
801};
802
803static const struct pinctrl_desc intel_pinctrl_desc = {
804 .pctlops = &intel_pinctrl_ops,
805 .pmxops = &intel_pinmux_ops,
806 .confops = &intel_pinconf_ops,
807 .owner = THIS_MODULE,
808};
809
810/**
811 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
812 * @pctrl: Pinctrl structure
813 * @offset: GPIO offset from gpiolib
814 * @community: Community is filled here if not %NULL
815 * @padgrp: Pad group is filled here if not %NULL
816 *
817 * When coming through gpiolib irqchip, the GPIO offset is not
818 * automatically translated to pinctrl pin number. This function can be
819 * used to find out the corresponding pinctrl pin.
820 */
821static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
822 const struct intel_community **community,
823 const struct intel_padgroup **padgrp)
824{
825 int i;
826
827 for (i = 0; i < pctrl->ncommunities; i++) {
828 const struct intel_community *comm = &pctrl->communities[i];
829 int j;
830
831 for (j = 0; j < comm->ngpps; j++) {
832 const struct intel_padgroup *pgrp = &comm->gpps[j];
833
834 if (pgrp->gpio_base < 0)
835 continue;
836
837 if (offset >= pgrp->gpio_base &&
838 offset < pgrp->gpio_base + pgrp->size) {
839 int pin;
840
841 pin = pgrp->base + offset - pgrp->gpio_base;
842 if (community)
843 *community = comm;
844 if (padgrp)
845 *padgrp = pgrp;
846
847 return pin;
848 }
849 }
850 }
851
852 return -EINVAL;
853}
854
855/**
856 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
857 * @pctrl: Pinctrl structure
858 * @pin: pin number
859 *
860 * Translate the pin number of pinctrl to GPIO offset
861 */
862static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
863{
864 const struct intel_community *community;
865 const struct intel_padgroup *padgrp;
866
867 community = intel_get_community(pctrl, pin);
868 if (!community)
869 return -EINVAL;
870
871 padgrp = intel_community_get_padgroup(community, pin);
872 if (!padgrp)
873 return -EINVAL;
874
875 return pin - padgrp->base + padgrp->gpio_base;
876}
877
878static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
879{
880 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
881 void __iomem *reg;
882 u32 padcfg0;
883 int pin;
884
885 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
886 if (pin < 0)
887 return -EINVAL;
888
889 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
890 if (!reg)
891 return -EINVAL;
892
893 padcfg0 = readl(reg);
894 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
895 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
896
897 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
898}
899
900static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
901 int value)
902{
903 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
904 unsigned long flags;
905 void __iomem *reg;
906 u32 padcfg0;
907 int pin;
908
909 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
910 if (pin < 0)
911 return;
912
913 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
914 if (!reg)
915 return;
916
917 raw_spin_lock_irqsave(&pctrl->lock, flags);
918 padcfg0 = readl(reg);
919 if (value)
920 padcfg0 |= PADCFG0_GPIOTXSTATE;
921 else
922 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
923 writel(padcfg0, reg);
924 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
925}
926
927static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
928{
929 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
930 void __iomem *reg;
931 u32 padcfg0;
932 int pin;
933
934 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
935 if (pin < 0)
936 return -EINVAL;
937
938 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
939 if (!reg)
940 return -EINVAL;
941
942 padcfg0 = readl(reg);
943
944 if (padcfg0 & PADCFG0_PMODE_MASK)
945 return -EINVAL;
946
947 return !!(padcfg0 & PADCFG0_GPIOTXDIS);
948}
949
950static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
951{
952 return pinctrl_gpio_direction_input(chip->base + offset);
953}
954
955static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
956 int value)
957{
958 intel_gpio_set(chip, offset, value);
959 return pinctrl_gpio_direction_output(chip->base + offset);
960}
961
962static const struct gpio_chip intel_gpio_chip = {
963 .owner = THIS_MODULE,
964 .request = gpiochip_generic_request,
965 .free = gpiochip_generic_free,
966 .get_direction = intel_gpio_get_direction,
967 .direction_input = intel_gpio_direction_input,
968 .direction_output = intel_gpio_direction_output,
969 .get = intel_gpio_get,
970 .set = intel_gpio_set,
971 .set_config = gpiochip_generic_config,
972};
973
974static void intel_gpio_irq_ack(struct irq_data *d)
975{
976 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
977 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
978 const struct intel_community *community;
979 const struct intel_padgroup *padgrp;
980 int pin;
981
982 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
983 if (pin >= 0) {
984 unsigned int gpp, gpp_offset, is_offset;
985
986 gpp = padgrp->reg_num;
987 gpp_offset = padgroup_offset(padgrp, pin);
988 is_offset = community->is_offset + gpp * 4;
989
990 raw_spin_lock(&pctrl->lock);
991 writel(BIT(gpp_offset), community->regs + is_offset);
992 raw_spin_unlock(&pctrl->lock);
993 }
994}
995
996static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
997{
998 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
999 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1000 const struct intel_community *community;
1001 const struct intel_padgroup *padgrp;
1002 int pin;
1003
1004 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1005 if (pin >= 0) {
1006 unsigned int gpp, gpp_offset;
1007 unsigned long flags;
1008 void __iomem *reg, *is;
1009 u32 value;
1010
1011 gpp = padgrp->reg_num;
1012 gpp_offset = padgroup_offset(padgrp, pin);
1013
1014 reg = community->regs + community->ie_offset + gpp * 4;
1015 is = community->regs + community->is_offset + gpp * 4;
1016
1017 raw_spin_lock_irqsave(&pctrl->lock, flags);
1018
1019 /* Clear interrupt status first to avoid unexpected interrupt */
1020 writel(BIT(gpp_offset), is);
1021
1022 value = readl(reg);
1023 if (mask)
1024 value &= ~BIT(gpp_offset);
1025 else
1026 value |= BIT(gpp_offset);
1027 writel(value, reg);
1028 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1029 }
1030}
1031
1032static void intel_gpio_irq_mask(struct irq_data *d)
1033{
1034 intel_gpio_irq_mask_unmask(d, true);
1035}
1036
1037static void intel_gpio_irq_unmask(struct irq_data *d)
1038{
1039 intel_gpio_irq_mask_unmask(d, false);
1040}
1041
1042static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1043{
1044 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1045 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1046 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1047 unsigned long flags;
1048 void __iomem *reg;
1049 u32 value;
1050
1051 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1052 if (!reg)
1053 return -EINVAL;
1054
1055 /*
1056 * If the pin is in ACPI mode it is still usable as a GPIO but it
1057 * cannot be used as IRQ because GPI_IS status bit will not be
1058 * updated by the host controller hardware.
1059 */
1060 if (intel_pad_acpi_mode(pctrl, pin)) {
1061 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1062 return -EPERM;
1063 }
1064
1065 raw_spin_lock_irqsave(&pctrl->lock, flags);
1066
1067 intel_gpio_set_gpio_mode(reg);
1068
1069 value = readl(reg);
1070
1071 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1072
1073 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1074 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1075 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1076 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1077 value |= PADCFG0_RXINV;
1078 } else if (type & IRQ_TYPE_EDGE_RISING) {
1079 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1080 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1081 if (type & IRQ_TYPE_LEVEL_LOW)
1082 value |= PADCFG0_RXINV;
1083 } else {
1084 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1085 }
1086
1087 writel(value, reg);
1088
1089 if (type & IRQ_TYPE_EDGE_BOTH)
1090 irq_set_handler_locked(d, handle_edge_irq);
1091 else if (type & IRQ_TYPE_LEVEL_MASK)
1092 irq_set_handler_locked(d, handle_level_irq);
1093
1094 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1095
1096 return 0;
1097}
1098
1099static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1100{
1101 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1102 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1103 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1104
1105 if (on)
1106 enable_irq_wake(pctrl->irq);
1107 else
1108 disable_irq_wake(pctrl->irq);
1109
1110 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1111 return 0;
1112}
1113
1114static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1115 const struct intel_community *community)
1116{
1117 struct gpio_chip *gc = &pctrl->chip;
1118 irqreturn_t ret = IRQ_NONE;
1119 int gpp;
1120
1121 for (gpp = 0; gpp < community->ngpps; gpp++) {
1122 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1123 unsigned long pending, enabled, gpp_offset;
1124
1125 pending = readl(community->regs + community->is_offset +
1126 padgrp->reg_num * 4);
1127 enabled = readl(community->regs + community->ie_offset +
1128 padgrp->reg_num * 4);
1129
1130 /* Only interrupts that are enabled */
1131 pending &= enabled;
1132
1133 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1134 unsigned irq;
1135
1136 irq = irq_find_mapping(gc->irq.domain,
1137 padgrp->gpio_base + gpp_offset);
1138 generic_handle_irq(irq);
1139
1140 ret |= IRQ_HANDLED;
1141 }
1142 }
1143
1144 return ret;
1145}
1146
1147static irqreturn_t intel_gpio_irq(int irq, void *data)
1148{
1149 const struct intel_community *community;
1150 struct intel_pinctrl *pctrl = data;
1151 irqreturn_t ret = IRQ_NONE;
1152 int i;
1153
1154 /* Need to check all communities for pending interrupts */
1155 for (i = 0; i < pctrl->ncommunities; i++) {
1156 community = &pctrl->communities[i];
1157 ret |= intel_gpio_community_irq_handler(pctrl, community);
1158 }
1159
1160 return ret;
1161}
1162
1163static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1164 const struct intel_community *community)
1165{
1166 int ret = 0, i;
1167
1168 for (i = 0; i < community->ngpps; i++) {
1169 const struct intel_padgroup *gpp = &community->gpps[i];
1170
1171 if (gpp->gpio_base < 0)
1172 continue;
1173
1174 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1175 gpp->gpio_base, gpp->base,
1176 gpp->size);
1177 if (ret)
1178 return ret;
1179 }
1180
1181 return ret;
1182}
1183
1184static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1185{
1186 const struct intel_community *community;
1187 unsigned int ngpio = 0;
1188 int i, j;
1189
1190 for (i = 0; i < pctrl->ncommunities; i++) {
1191 community = &pctrl->communities[i];
1192 for (j = 0; j < community->ngpps; j++) {
1193 const struct intel_padgroup *gpp = &community->gpps[j];
1194
1195 if (gpp->gpio_base < 0)
1196 continue;
1197
1198 if (gpp->gpio_base + gpp->size > ngpio)
1199 ngpio = gpp->gpio_base + gpp->size;
1200 }
1201 }
1202
1203 return ngpio;
1204}
1205
1206static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1207{
1208 int ret, i;
1209
1210 pctrl->chip = intel_gpio_chip;
1211
1212 /* Setup GPIO chip */
1213 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1214 pctrl->chip.label = dev_name(pctrl->dev);
1215 pctrl->chip.parent = pctrl->dev;
1216 pctrl->chip.base = -1;
1217 pctrl->irq = irq;
1218
1219 /* Setup IRQ chip */
1220 pctrl->irqchip.name = dev_name(pctrl->dev);
1221 pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1222 pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1223 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1224 pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1225 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1226 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1227
1228 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1229 if (ret) {
1230 dev_err(pctrl->dev, "failed to register gpiochip\n");
1231 return ret;
1232 }
1233
1234 for (i = 0; i < pctrl->ncommunities; i++) {
1235 struct intel_community *community = &pctrl->communities[i];
1236
1237 ret = intel_gpio_add_pin_ranges(pctrl, community);
1238 if (ret) {
1239 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1240 return ret;
1241 }
1242 }
1243
1244 /*
1245 * We need to request the interrupt here (instead of providing chip
1246 * to the irq directly) because on some platforms several GPIO
1247 * controllers share the same interrupt line.
1248 */
1249 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1250 IRQF_SHARED | IRQF_NO_THREAD,
1251 dev_name(pctrl->dev), pctrl);
1252 if (ret) {
1253 dev_err(pctrl->dev, "failed to request interrupt\n");
1254 return ret;
1255 }
1256
1257 ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0,
1258 handle_bad_irq, IRQ_TYPE_NONE);
1259 if (ret) {
1260 dev_err(pctrl->dev, "failed to add irqchip\n");
1261 return ret;
1262 }
1263
1264 gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL);
1265 return 0;
1266}
1267
1268static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1269 struct intel_community *community)
1270{
1271 struct intel_padgroup *gpps;
1272 unsigned int npins = community->npins;
1273 unsigned int padown_num = 0;
1274 size_t ngpps, i;
1275
1276 if (community->gpps)
1277 ngpps = community->ngpps;
1278 else
1279 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1280
1281 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1282 if (!gpps)
1283 return -ENOMEM;
1284
1285 for (i = 0; i < ngpps; i++) {
1286 if (community->gpps) {
1287 gpps[i] = community->gpps[i];
1288 } else {
1289 unsigned int gpp_size = community->gpp_size;
1290
1291 gpps[i].reg_num = i;
1292 gpps[i].base = community->pin_base + i * gpp_size;
1293 gpps[i].size = min(gpp_size, npins);
1294 npins -= gpps[i].size;
1295 }
1296
1297 if (gpps[i].size > 32)
1298 return -EINVAL;
1299
1300 if (!gpps[i].gpio_base)
1301 gpps[i].gpio_base = gpps[i].base;
1302
1303 gpps[i].padown_num = padown_num;
1304
1305 /*
1306 * In older hardware the number of padown registers per
1307 * group is fixed regardless of the group size.
1308 */
1309 if (community->gpp_num_padown_regs)
1310 padown_num += community->gpp_num_padown_regs;
1311 else
1312 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1313 }
1314
1315 community->ngpps = ngpps;
1316 community->gpps = gpps;
1317
1318 return 0;
1319}
1320
1321static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1322{
1323#ifdef CONFIG_PM_SLEEP
1324 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1325 struct intel_community_context *communities;
1326 struct intel_pad_context *pads;
1327 int i;
1328
1329 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1330 if (!pads)
1331 return -ENOMEM;
1332
1333 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1334 sizeof(*communities), GFP_KERNEL);
1335 if (!communities)
1336 return -ENOMEM;
1337
1338
1339 for (i = 0; i < pctrl->ncommunities; i++) {
1340 struct intel_community *community = &pctrl->communities[i];
1341 u32 *intmask, *hostown;
1342
1343 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1344 sizeof(*intmask), GFP_KERNEL);
1345 if (!intmask)
1346 return -ENOMEM;
1347
1348 communities[i].intmask = intmask;
1349
1350 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1351 sizeof(*hostown), GFP_KERNEL);
1352 if (!hostown)
1353 return -ENOMEM;
1354
1355 communities[i].hostown = hostown;
1356 }
1357
1358 pctrl->context.pads = pads;
1359 pctrl->context.communities = communities;
1360#endif
1361
1362 return 0;
1363}
1364
1365static int intel_pinctrl_probe(struct platform_device *pdev,
1366 const struct intel_pinctrl_soc_data *soc_data)
1367{
1368 struct intel_pinctrl *pctrl;
1369 int i, ret, irq;
1370
1371 if (!soc_data)
1372 return -EINVAL;
1373
1374 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1375 if (!pctrl)
1376 return -ENOMEM;
1377
1378 pctrl->dev = &pdev->dev;
1379 pctrl->soc = soc_data;
1380 raw_spin_lock_init(&pctrl->lock);
1381
1382 /*
1383 * Make a copy of the communities which we can use to hold pointers
1384 * to the registers.
1385 */
1386 pctrl->ncommunities = pctrl->soc->ncommunities;
1387 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1388 sizeof(*pctrl->communities), GFP_KERNEL);
1389 if (!pctrl->communities)
1390 return -ENOMEM;
1391
1392 for (i = 0; i < pctrl->ncommunities; i++) {
1393 struct intel_community *community = &pctrl->communities[i];
1394 void __iomem *regs;
1395 u32 padbar;
1396
1397 *community = pctrl->soc->communities[i];
1398
1399 regs = devm_platform_ioremap_resource(pdev, community->barno);
1400 if (IS_ERR(regs))
1401 return PTR_ERR(regs);
1402
1403 /*
1404 * Determine community features based on the revision if
1405 * not specified already.
1406 */
1407 if (!community->features) {
1408 u32 rev;
1409
1410 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1411 if (rev >= 0x94) {
1412 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1413 community->features |= PINCTRL_FEATURE_1K_PD;
1414 }
1415 }
1416
1417 /* Read offset of the pad configuration registers */
1418 padbar = readl(regs + PADBAR);
1419
1420 community->regs = regs;
1421 community->pad_regs = regs + padbar;
1422
1423 ret = intel_pinctrl_add_padgroups(pctrl, community);
1424 if (ret)
1425 return ret;
1426 }
1427
1428 irq = platform_get_irq(pdev, 0);
1429 if (irq < 0)
1430 return irq;
1431
1432 ret = intel_pinctrl_pm_init(pctrl);
1433 if (ret)
1434 return ret;
1435
1436 pctrl->pctldesc = intel_pinctrl_desc;
1437 pctrl->pctldesc.name = dev_name(&pdev->dev);
1438 pctrl->pctldesc.pins = pctrl->soc->pins;
1439 pctrl->pctldesc.npins = pctrl->soc->npins;
1440
1441 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1442 pctrl);
1443 if (IS_ERR(pctrl->pctldev)) {
1444 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1445 return PTR_ERR(pctrl->pctldev);
1446 }
1447
1448 ret = intel_gpio_probe(pctrl, irq);
1449 if (ret)
1450 return ret;
1451
1452 platform_set_drvdata(pdev, pctrl);
1453
1454 return 0;
1455}
1456
1457int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1458{
1459 const struct intel_pinctrl_soc_data *data;
1460
1461 data = device_get_match_data(&pdev->dev);
1462 return intel_pinctrl_probe(pdev, data);
1463}
1464EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1465
1466int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1467{
1468 const struct intel_pinctrl_soc_data *data = NULL;
1469 const struct intel_pinctrl_soc_data **table;
1470 struct acpi_device *adev;
1471 unsigned int i;
1472
1473 adev = ACPI_COMPANION(&pdev->dev);
1474 if (adev) {
1475 const void *match = device_get_match_data(&pdev->dev);
1476
1477 table = (const struct intel_pinctrl_soc_data **)match;
1478 for (i = 0; table[i]; i++) {
1479 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1480 data = table[i];
1481 break;
1482 }
1483 }
1484 } else {
1485 const struct platform_device_id *id;
1486
1487 id = platform_get_device_id(pdev);
1488 if (!id)
1489 return -ENODEV;
1490
1491 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1492 data = table[pdev->id];
1493 }
1494
1495 return intel_pinctrl_probe(pdev, data);
1496}
1497EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1498
1499#ifdef CONFIG_PM_SLEEP
1500static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1501{
1502 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1503
1504 if (!pd || !intel_pad_usable(pctrl, pin))
1505 return false;
1506
1507 /*
1508 * Only restore the pin if it is actually in use by the kernel (or
1509 * by userspace). It is possible that some pins are used by the
1510 * BIOS during resume and those are not always locked down so leave
1511 * them alone.
1512 */
1513 if (pd->mux_owner || pd->gpio_owner ||
1514 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1515 return true;
1516
1517 return false;
1518}
1519
1520int intel_pinctrl_suspend_noirq(struct device *dev)
1521{
1522 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1523 struct intel_community_context *communities;
1524 struct intel_pad_context *pads;
1525 int i;
1526
1527 pads = pctrl->context.pads;
1528 for (i = 0; i < pctrl->soc->npins; i++) {
1529 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1530 void __iomem *padcfg;
1531 u32 val;
1532
1533 if (!intel_pinctrl_should_save(pctrl, desc->number))
1534 continue;
1535
1536 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1537 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1538 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1539 pads[i].padcfg1 = val;
1540
1541 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1542 if (padcfg)
1543 pads[i].padcfg2 = readl(padcfg);
1544 }
1545
1546 communities = pctrl->context.communities;
1547 for (i = 0; i < pctrl->ncommunities; i++) {
1548 struct intel_community *community = &pctrl->communities[i];
1549 void __iomem *base;
1550 unsigned int gpp;
1551
1552 base = community->regs + community->ie_offset;
1553 for (gpp = 0; gpp < community->ngpps; gpp++)
1554 communities[i].intmask[gpp] = readl(base + gpp * 4);
1555
1556 base = community->regs + community->hostown_offset;
1557 for (gpp = 0; gpp < community->ngpps; gpp++)
1558 communities[i].hostown[gpp] = readl(base + gpp * 4);
1559 }
1560
1561 return 0;
1562}
1563EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1564
1565static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1566{
1567 size_t i;
1568
1569 for (i = 0; i < pctrl->ncommunities; i++) {
1570 const struct intel_community *community;
1571 void __iomem *base;
1572 unsigned int gpp;
1573
1574 community = &pctrl->communities[i];
1575 base = community->regs;
1576
1577 for (gpp = 0; gpp < community->ngpps; gpp++) {
1578 /* Mask and clear all interrupts */
1579 writel(0, base + community->ie_offset + gpp * 4);
1580 writel(0xffff, base + community->is_offset + gpp * 4);
1581 }
1582 }
1583}
1584
1585static u32
1586intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
1587{
1588 u32 requested = 0;
1589 unsigned int i;
1590
1591 for (i = 0; i < size; i++)
1592 if (gpiochip_is_requested(chip, base + i))
1593 requested |= BIT(i);
1594
1595 return requested;
1596}
1597
1598static u32
1599intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
1600{
1601 u32 curr, updated;
1602
1603 curr = readl(hostown);
1604 updated = (curr & ~mask) | (value & mask);
1605 writel(updated, hostown);
1606
1607 return curr;
1608}
1609
1610int intel_pinctrl_resume_noirq(struct device *dev)
1611{
1612 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1613 const struct intel_community_context *communities;
1614 const struct intel_pad_context *pads;
1615 int i;
1616
1617 /* Mask all interrupts */
1618 intel_gpio_irq_init(pctrl);
1619
1620 pads = pctrl->context.pads;
1621 for (i = 0; i < pctrl->soc->npins; i++) {
1622 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1623 void __iomem *padcfg;
1624 u32 val;
1625
1626 if (!intel_pinctrl_should_save(pctrl, desc->number))
1627 continue;
1628
1629 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1630 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1631 if (val != pads[i].padcfg0) {
1632 writel(pads[i].padcfg0, padcfg);
1633 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1634 desc->number, readl(padcfg));
1635 }
1636
1637 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1638 val = readl(padcfg);
1639 if (val != pads[i].padcfg1) {
1640 writel(pads[i].padcfg1, padcfg);
1641 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1642 desc->number, readl(padcfg));
1643 }
1644
1645 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1646 if (padcfg) {
1647 val = readl(padcfg);
1648 if (val != pads[i].padcfg2) {
1649 writel(pads[i].padcfg2, padcfg);
1650 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1651 desc->number, readl(padcfg));
1652 }
1653 }
1654 }
1655
1656 communities = pctrl->context.communities;
1657 for (i = 0; i < pctrl->ncommunities; i++) {
1658 struct intel_community *community = &pctrl->communities[i];
1659 void __iomem *base;
1660 unsigned int gpp;
1661
1662 base = community->regs + community->ie_offset;
1663 for (gpp = 0; gpp < community->ngpps; gpp++) {
1664 writel(communities[i].intmask[gpp], base + gpp * 4);
1665 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1666 readl(base + gpp * 4));
1667 }
1668
1669 base = community->regs + community->hostown_offset;
1670 for (gpp = 0; gpp < community->ngpps; gpp++) {
1671 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1672 u32 requested = 0, value = 0;
1673 u32 saved = communities[i].hostown[gpp];
1674
1675 if (padgrp->gpio_base < 0)
1676 continue;
1677
1678 requested = intel_gpio_is_requested(&pctrl->chip,
1679 padgrp->gpio_base, padgrp->size);
1680 value = intel_gpio_update_pad_mode(base + gpp * 4,
1681 requested, saved);
1682 if ((value ^ saved) & requested) {
1683 dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
1684 i, gpp, value, saved);
1685 }
1686 }
1687 }
1688
1689 return 0;
1690}
1691EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1692#endif
1693
1694MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1695MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1696MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1697MODULE_LICENSE("GPL v2");