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1/*
2 * Intel pinctrl/GPIO core driver.
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/gpio/driver.h>
16#include <linux/log2.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinconf-generic.h>
22
23#include "../core.h"
24#include "pinctrl-intel.h"
25
26/* Offset from regs */
27#define REVID 0x000
28#define REVID_SHIFT 16
29#define REVID_MASK GENMASK(31, 16)
30
31#define PADBAR 0x00c
32#define GPI_IS 0x100
33
34#define PADOWN_BITS 4
35#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
37#define PADOWN_GPP(p) ((p) / 8)
38
39/* Offset from pad_regs */
40#define PADCFG0 0x000
41#define PADCFG0_RXEVCFG_SHIFT 25
42#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
43#define PADCFG0_RXEVCFG_LEVEL 0
44#define PADCFG0_RXEVCFG_EDGE 1
45#define PADCFG0_RXEVCFG_DISABLED 2
46#define PADCFG0_RXEVCFG_EDGE_BOTH 3
47#define PADCFG0_PREGFRXSEL BIT(24)
48#define PADCFG0_RXINV BIT(23)
49#define PADCFG0_GPIROUTIOXAPIC BIT(20)
50#define PADCFG0_GPIROUTSCI BIT(19)
51#define PADCFG0_GPIROUTSMI BIT(18)
52#define PADCFG0_GPIROUTNMI BIT(17)
53#define PADCFG0_PMODE_SHIFT 10
54#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
55#define PADCFG0_GPIORXDIS BIT(9)
56#define PADCFG0_GPIOTXDIS BIT(8)
57#define PADCFG0_GPIORXSTATE BIT(1)
58#define PADCFG0_GPIOTXSTATE BIT(0)
59
60#define PADCFG1 0x004
61#define PADCFG1_TERM_UP BIT(13)
62#define PADCFG1_TERM_SHIFT 10
63#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
64#define PADCFG1_TERM_20K 4
65#define PADCFG1_TERM_2K 3
66#define PADCFG1_TERM_5K 2
67#define PADCFG1_TERM_1K 1
68
69#define PADCFG2 0x008
70#define PADCFG2_DEBEN BIT(0)
71#define PADCFG2_DEBOUNCE_SHIFT 1
72#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
73
74#define DEBOUNCE_PERIOD 31250 /* ns */
75
76struct intel_pad_context {
77 u32 padcfg0;
78 u32 padcfg1;
79 u32 padcfg2;
80};
81
82struct intel_community_context {
83 u32 *intmask;
84};
85
86struct intel_pinctrl_context {
87 struct intel_pad_context *pads;
88 struct intel_community_context *communities;
89};
90
91/**
92 * struct intel_pinctrl - Intel pinctrl private structure
93 * @dev: Pointer to the device structure
94 * @lock: Lock to serialize register access
95 * @pctldesc: Pin controller description
96 * @pctldev: Pointer to the pin controller device
97 * @chip: GPIO chip in this pin controller
98 * @soc: SoC/PCH specific pin configuration data
99 * @communities: All communities in this pin controller
100 * @ncommunities: Number of communities in this pin controller
101 * @context: Configuration saved over system sleep
102 * @irq: pinctrl/GPIO chip irq number
103 */
104struct intel_pinctrl {
105 struct device *dev;
106 raw_spinlock_t lock;
107 struct pinctrl_desc pctldesc;
108 struct pinctrl_dev *pctldev;
109 struct gpio_chip chip;
110 const struct intel_pinctrl_soc_data *soc;
111 struct intel_community *communities;
112 size_t ncommunities;
113 struct intel_pinctrl_context context;
114 int irq;
115};
116
117#define pin_to_padno(c, p) ((p) - (c)->pin_base)
118#define padgroup_offset(g, p) ((p) - (g)->base)
119
120static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
121 unsigned pin)
122{
123 struct intel_community *community;
124 int i;
125
126 for (i = 0; i < pctrl->ncommunities; i++) {
127 community = &pctrl->communities[i];
128 if (pin >= community->pin_base &&
129 pin < community->pin_base + community->npins)
130 return community;
131 }
132
133 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
134 return NULL;
135}
136
137static const struct intel_padgroup *
138intel_community_get_padgroup(const struct intel_community *community,
139 unsigned pin)
140{
141 int i;
142
143 for (i = 0; i < community->ngpps; i++) {
144 const struct intel_padgroup *padgrp = &community->gpps[i];
145
146 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
147 return padgrp;
148 }
149
150 return NULL;
151}
152
153static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
154 unsigned reg)
155{
156 const struct intel_community *community;
157 unsigned padno;
158 size_t nregs;
159
160 community = intel_get_community(pctrl, pin);
161 if (!community)
162 return NULL;
163
164 padno = pin_to_padno(community, pin);
165 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
166
167 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
168 return NULL;
169
170 return community->pad_regs + reg + padno * nregs * 4;
171}
172
173static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
174{
175 const struct intel_community *community;
176 const struct intel_padgroup *padgrp;
177 unsigned gpp, offset, gpp_offset;
178 void __iomem *padown;
179
180 community = intel_get_community(pctrl, pin);
181 if (!community)
182 return false;
183 if (!community->padown_offset)
184 return true;
185
186 padgrp = intel_community_get_padgroup(community, pin);
187 if (!padgrp)
188 return false;
189
190 gpp_offset = padgroup_offset(padgrp, pin);
191 gpp = PADOWN_GPP(gpp_offset);
192 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
193 padown = community->regs + offset;
194
195 return !(readl(padown) & PADOWN_MASK(gpp_offset));
196}
197
198static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
199{
200 const struct intel_community *community;
201 const struct intel_padgroup *padgrp;
202 unsigned offset, gpp_offset;
203 void __iomem *hostown;
204
205 community = intel_get_community(pctrl, pin);
206 if (!community)
207 return true;
208 if (!community->hostown_offset)
209 return false;
210
211 padgrp = intel_community_get_padgroup(community, pin);
212 if (!padgrp)
213 return true;
214
215 gpp_offset = padgroup_offset(padgrp, pin);
216 offset = community->hostown_offset + padgrp->reg_num * 4;
217 hostown = community->regs + offset;
218
219 return !(readl(hostown) & BIT(gpp_offset));
220}
221
222static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
223{
224 struct intel_community *community;
225 const struct intel_padgroup *padgrp;
226 unsigned offset, gpp_offset;
227 u32 value;
228
229 community = intel_get_community(pctrl, pin);
230 if (!community)
231 return true;
232 if (!community->padcfglock_offset)
233 return false;
234
235 padgrp = intel_community_get_padgroup(community, pin);
236 if (!padgrp)
237 return true;
238
239 gpp_offset = padgroup_offset(padgrp, pin);
240
241 /*
242 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
243 * the pad is considered unlocked. Any other case means that it is
244 * either fully or partially locked and we don't touch it.
245 */
246 offset = community->padcfglock_offset + padgrp->reg_num * 8;
247 value = readl(community->regs + offset);
248 if (value & BIT(gpp_offset))
249 return true;
250
251 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
252 value = readl(community->regs + offset);
253 if (value & BIT(gpp_offset))
254 return true;
255
256 return false;
257}
258
259static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
260{
261 return intel_pad_owned_by_host(pctrl, pin) &&
262 !intel_pad_locked(pctrl, pin);
263}
264
265static int intel_get_groups_count(struct pinctrl_dev *pctldev)
266{
267 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
268
269 return pctrl->soc->ngroups;
270}
271
272static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
273 unsigned group)
274{
275 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
276
277 return pctrl->soc->groups[group].name;
278}
279
280static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
281 const unsigned **pins, unsigned *npins)
282{
283 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
284
285 *pins = pctrl->soc->groups[group].pins;
286 *npins = pctrl->soc->groups[group].npins;
287 return 0;
288}
289
290static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
291 unsigned pin)
292{
293 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
294 void __iomem *padcfg;
295 u32 cfg0, cfg1, mode;
296 bool locked, acpi;
297
298 if (!intel_pad_owned_by_host(pctrl, pin)) {
299 seq_puts(s, "not available");
300 return;
301 }
302
303 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
304 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
305
306 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
307 if (!mode)
308 seq_puts(s, "GPIO ");
309 else
310 seq_printf(s, "mode %d ", mode);
311
312 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
313
314 /* Dump the additional PADCFG registers if available */
315 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
316 if (padcfg)
317 seq_printf(s, " 0x%08x", readl(padcfg));
318
319 locked = intel_pad_locked(pctrl, pin);
320 acpi = intel_pad_acpi_mode(pctrl, pin);
321
322 if (locked || acpi) {
323 seq_puts(s, " [");
324 if (locked) {
325 seq_puts(s, "LOCKED");
326 if (acpi)
327 seq_puts(s, ", ");
328 }
329 if (acpi)
330 seq_puts(s, "ACPI");
331 seq_puts(s, "]");
332 }
333}
334
335static const struct pinctrl_ops intel_pinctrl_ops = {
336 .get_groups_count = intel_get_groups_count,
337 .get_group_name = intel_get_group_name,
338 .get_group_pins = intel_get_group_pins,
339 .pin_dbg_show = intel_pin_dbg_show,
340};
341
342static int intel_get_functions_count(struct pinctrl_dev *pctldev)
343{
344 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
345
346 return pctrl->soc->nfunctions;
347}
348
349static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
350 unsigned function)
351{
352 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
353
354 return pctrl->soc->functions[function].name;
355}
356
357static int intel_get_function_groups(struct pinctrl_dev *pctldev,
358 unsigned function,
359 const char * const **groups,
360 unsigned * const ngroups)
361{
362 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
363
364 *groups = pctrl->soc->functions[function].groups;
365 *ngroups = pctrl->soc->functions[function].ngroups;
366 return 0;
367}
368
369static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
370 unsigned group)
371{
372 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
373 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
374 unsigned long flags;
375 int i;
376
377 raw_spin_lock_irqsave(&pctrl->lock, flags);
378
379 /*
380 * All pins in the groups needs to be accessible and writable
381 * before we can enable the mux for this group.
382 */
383 for (i = 0; i < grp->npins; i++) {
384 if (!intel_pad_usable(pctrl, grp->pins[i])) {
385 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
386 return -EBUSY;
387 }
388 }
389
390 /* Now enable the mux setting for each pin in the group */
391 for (i = 0; i < grp->npins; i++) {
392 void __iomem *padcfg0;
393 u32 value;
394
395 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
396 value = readl(padcfg0);
397
398 value &= ~PADCFG0_PMODE_MASK;
399
400 if (grp->modes)
401 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
402 else
403 value |= grp->mode << PADCFG0_PMODE_SHIFT;
404
405 writel(value, padcfg0);
406 }
407
408 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
409
410 return 0;
411}
412
413static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
414{
415 u32 value;
416
417 value = readl(padcfg0);
418 if (input) {
419 value &= ~PADCFG0_GPIORXDIS;
420 value |= PADCFG0_GPIOTXDIS;
421 } else {
422 value &= ~PADCFG0_GPIOTXDIS;
423 value |= PADCFG0_GPIORXDIS;
424 }
425 writel(value, padcfg0);
426}
427
428static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
429{
430 u32 value;
431
432 /* Put the pad into GPIO mode */
433 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
434 /* Disable SCI/SMI/NMI generation */
435 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
436 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
437 writel(value, padcfg0);
438}
439
440static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
441 struct pinctrl_gpio_range *range,
442 unsigned pin)
443{
444 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
445 void __iomem *padcfg0;
446 unsigned long flags;
447
448 raw_spin_lock_irqsave(&pctrl->lock, flags);
449
450 if (!intel_pad_usable(pctrl, pin)) {
451 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
452 return -EBUSY;
453 }
454
455 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
456 intel_gpio_set_gpio_mode(padcfg0);
457 /* Disable TX buffer and enable RX (this will be input) */
458 __intel_gpio_set_direction(padcfg0, true);
459
460 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
461
462 return 0;
463}
464
465static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
466 struct pinctrl_gpio_range *range,
467 unsigned pin, bool input)
468{
469 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
470 void __iomem *padcfg0;
471 unsigned long flags;
472
473 raw_spin_lock_irqsave(&pctrl->lock, flags);
474
475 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
476 __intel_gpio_set_direction(padcfg0, input);
477
478 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
479
480 return 0;
481}
482
483static const struct pinmux_ops intel_pinmux_ops = {
484 .get_functions_count = intel_get_functions_count,
485 .get_function_name = intel_get_function_name,
486 .get_function_groups = intel_get_function_groups,
487 .set_mux = intel_pinmux_set_mux,
488 .gpio_request_enable = intel_gpio_request_enable,
489 .gpio_set_direction = intel_gpio_set_direction,
490};
491
492static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
493 unsigned long *config)
494{
495 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
496 enum pin_config_param param = pinconf_to_config_param(*config);
497 const struct intel_community *community;
498 u32 value, term;
499 u32 arg = 0;
500
501 if (!intel_pad_owned_by_host(pctrl, pin))
502 return -ENOTSUPP;
503
504 community = intel_get_community(pctrl, pin);
505 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
506 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
507
508 switch (param) {
509 case PIN_CONFIG_BIAS_DISABLE:
510 if (term)
511 return -EINVAL;
512 break;
513
514 case PIN_CONFIG_BIAS_PULL_UP:
515 if (!term || !(value & PADCFG1_TERM_UP))
516 return -EINVAL;
517
518 switch (term) {
519 case PADCFG1_TERM_1K:
520 arg = 1000;
521 break;
522 case PADCFG1_TERM_2K:
523 arg = 2000;
524 break;
525 case PADCFG1_TERM_5K:
526 arg = 5000;
527 break;
528 case PADCFG1_TERM_20K:
529 arg = 20000;
530 break;
531 }
532
533 break;
534
535 case PIN_CONFIG_BIAS_PULL_DOWN:
536 if (!term || value & PADCFG1_TERM_UP)
537 return -EINVAL;
538
539 switch (term) {
540 case PADCFG1_TERM_1K:
541 if (!(community->features & PINCTRL_FEATURE_1K_PD))
542 return -EINVAL;
543 arg = 1000;
544 break;
545 case PADCFG1_TERM_5K:
546 arg = 5000;
547 break;
548 case PADCFG1_TERM_20K:
549 arg = 20000;
550 break;
551 }
552
553 break;
554
555 case PIN_CONFIG_INPUT_DEBOUNCE: {
556 void __iomem *padcfg2;
557 u32 v;
558
559 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
560 if (!padcfg2)
561 return -ENOTSUPP;
562
563 v = readl(padcfg2);
564 if (!(v & PADCFG2_DEBEN))
565 return -EINVAL;
566
567 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
568 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
569
570 break;
571 }
572
573 default:
574 return -ENOTSUPP;
575 }
576
577 *config = pinconf_to_config_packed(param, arg);
578 return 0;
579}
580
581static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
582 unsigned long config)
583{
584 unsigned param = pinconf_to_config_param(config);
585 unsigned arg = pinconf_to_config_argument(config);
586 const struct intel_community *community;
587 void __iomem *padcfg1;
588 unsigned long flags;
589 int ret = 0;
590 u32 value;
591
592 raw_spin_lock_irqsave(&pctrl->lock, flags);
593
594 community = intel_get_community(pctrl, pin);
595 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
596 value = readl(padcfg1);
597
598 switch (param) {
599 case PIN_CONFIG_BIAS_DISABLE:
600 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
601 break;
602
603 case PIN_CONFIG_BIAS_PULL_UP:
604 value &= ~PADCFG1_TERM_MASK;
605
606 value |= PADCFG1_TERM_UP;
607
608 switch (arg) {
609 case 20000:
610 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
611 break;
612 case 5000:
613 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
614 break;
615 case 2000:
616 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
617 break;
618 case 1000:
619 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
620 break;
621 default:
622 ret = -EINVAL;
623 }
624
625 break;
626
627 case PIN_CONFIG_BIAS_PULL_DOWN:
628 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
629
630 switch (arg) {
631 case 20000:
632 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
633 break;
634 case 5000:
635 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
636 break;
637 case 1000:
638 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
639 ret = -EINVAL;
640 break;
641 }
642 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
643 break;
644 default:
645 ret = -EINVAL;
646 }
647
648 break;
649 }
650
651 if (!ret)
652 writel(value, padcfg1);
653
654 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
655
656 return ret;
657}
658
659static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
660 unsigned debounce)
661{
662 void __iomem *padcfg0, *padcfg2;
663 unsigned long flags;
664 u32 value0, value2;
665 int ret = 0;
666
667 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
668 if (!padcfg2)
669 return -ENOTSUPP;
670
671 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
672
673 raw_spin_lock_irqsave(&pctrl->lock, flags);
674
675 value0 = readl(padcfg0);
676 value2 = readl(padcfg2);
677
678 /* Disable glitch filter and debouncer */
679 value0 &= ~PADCFG0_PREGFRXSEL;
680 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
681
682 if (debounce) {
683 unsigned long v;
684
685 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
686 if (v < 3 || v > 15) {
687 ret = -EINVAL;
688 goto exit_unlock;
689 } else {
690 /* Enable glitch filter and debouncer */
691 value0 |= PADCFG0_PREGFRXSEL;
692 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
693 value2 |= PADCFG2_DEBEN;
694 }
695 }
696
697 writel(value0, padcfg0);
698 writel(value2, padcfg2);
699
700exit_unlock:
701 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
702
703 return ret;
704}
705
706static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
707 unsigned long *configs, unsigned nconfigs)
708{
709 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
710 int i, ret;
711
712 if (!intel_pad_usable(pctrl, pin))
713 return -ENOTSUPP;
714
715 for (i = 0; i < nconfigs; i++) {
716 switch (pinconf_to_config_param(configs[i])) {
717 case PIN_CONFIG_BIAS_DISABLE:
718 case PIN_CONFIG_BIAS_PULL_UP:
719 case PIN_CONFIG_BIAS_PULL_DOWN:
720 ret = intel_config_set_pull(pctrl, pin, configs[i]);
721 if (ret)
722 return ret;
723 break;
724
725 case PIN_CONFIG_INPUT_DEBOUNCE:
726 ret = intel_config_set_debounce(pctrl, pin,
727 pinconf_to_config_argument(configs[i]));
728 if (ret)
729 return ret;
730 break;
731
732 default:
733 return -ENOTSUPP;
734 }
735 }
736
737 return 0;
738}
739
740static const struct pinconf_ops intel_pinconf_ops = {
741 .is_generic = true,
742 .pin_config_get = intel_config_get,
743 .pin_config_set = intel_config_set,
744};
745
746static const struct pinctrl_desc intel_pinctrl_desc = {
747 .pctlops = &intel_pinctrl_ops,
748 .pmxops = &intel_pinmux_ops,
749 .confops = &intel_pinconf_ops,
750 .owner = THIS_MODULE,
751};
752
753static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
754{
755 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
756 void __iomem *reg;
757 u32 padcfg0;
758
759 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
760 if (!reg)
761 return -EINVAL;
762
763 padcfg0 = readl(reg);
764 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
765 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
766
767 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
768}
769
770static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
771{
772 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
773 unsigned long flags;
774 void __iomem *reg;
775 u32 padcfg0;
776
777 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
778 if (!reg)
779 return;
780
781 raw_spin_lock_irqsave(&pctrl->lock, flags);
782 padcfg0 = readl(reg);
783 if (value)
784 padcfg0 |= PADCFG0_GPIOTXSTATE;
785 else
786 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
787 writel(padcfg0, reg);
788 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
789}
790
791static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
792{
793 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
794 void __iomem *reg;
795 u32 padcfg0;
796
797 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
798 if (!reg)
799 return -EINVAL;
800
801 padcfg0 = readl(reg);
802
803 if (padcfg0 & PADCFG0_PMODE_MASK)
804 return -EINVAL;
805
806 return !!(padcfg0 & PADCFG0_GPIOTXDIS);
807}
808
809static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
810{
811 return pinctrl_gpio_direction_input(chip->base + offset);
812}
813
814static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
815 int value)
816{
817 intel_gpio_set(chip, offset, value);
818 return pinctrl_gpio_direction_output(chip->base + offset);
819}
820
821static const struct gpio_chip intel_gpio_chip = {
822 .owner = THIS_MODULE,
823 .request = gpiochip_generic_request,
824 .free = gpiochip_generic_free,
825 .get_direction = intel_gpio_get_direction,
826 .direction_input = intel_gpio_direction_input,
827 .direction_output = intel_gpio_direction_output,
828 .get = intel_gpio_get,
829 .set = intel_gpio_set,
830 .set_config = gpiochip_generic_config,
831};
832
833/**
834 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
835 * @pctrl: Pinctrl structure
836 * @offset: GPIO offset from gpiolib
837 * @commmunity: Community is filled here if not %NULL
838 * @padgrp: Pad group is filled here if not %NULL
839 *
840 * When coming through gpiolib irqchip, the GPIO offset is not
841 * automatically translated to pinctrl pin number. This function can be
842 * used to find out the corresponding pinctrl pin.
843 */
844static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
845 const struct intel_community **community,
846 const struct intel_padgroup **padgrp)
847{
848 int i;
849
850 for (i = 0; i < pctrl->ncommunities; i++) {
851 const struct intel_community *comm = &pctrl->communities[i];
852 int j;
853
854 for (j = 0; j < comm->ngpps; j++) {
855 const struct intel_padgroup *pgrp = &comm->gpps[j];
856
857 if (pgrp->gpio_base < 0)
858 continue;
859
860 if (offset >= pgrp->gpio_base &&
861 offset < pgrp->gpio_base + pgrp->size) {
862 int pin;
863
864 pin = pgrp->base + offset - pgrp->gpio_base;
865 if (community)
866 *community = comm;
867 if (padgrp)
868 *padgrp = pgrp;
869
870 return pin;
871 }
872 }
873 }
874
875 return -EINVAL;
876}
877
878static void intel_gpio_irq_ack(struct irq_data *d)
879{
880 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
881 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
882 const struct intel_community *community;
883 const struct intel_padgroup *padgrp;
884 int pin;
885
886 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
887 if (pin >= 0) {
888 unsigned gpp, gpp_offset, is_offset;
889
890 gpp = padgrp->reg_num;
891 gpp_offset = padgroup_offset(padgrp, pin);
892 is_offset = community->is_offset + gpp * 4;
893
894 raw_spin_lock(&pctrl->lock);
895 writel(BIT(gpp_offset), community->regs + is_offset);
896 raw_spin_unlock(&pctrl->lock);
897 }
898}
899
900static void intel_gpio_irq_enable(struct irq_data *d)
901{
902 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
903 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
904 const struct intel_community *community;
905 const struct intel_padgroup *padgrp;
906 int pin;
907
908 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
909 if (pin >= 0) {
910 unsigned gpp, gpp_offset, is_offset;
911 unsigned long flags;
912 u32 value;
913
914 gpp = padgrp->reg_num;
915 gpp_offset = padgroup_offset(padgrp, pin);
916 is_offset = community->is_offset + gpp * 4;
917
918 raw_spin_lock_irqsave(&pctrl->lock, flags);
919 /* Clear interrupt status first to avoid unexpected interrupt */
920 writel(BIT(gpp_offset), community->regs + is_offset);
921
922 value = readl(community->regs + community->ie_offset + gpp * 4);
923 value |= BIT(gpp_offset);
924 writel(value, community->regs + community->ie_offset + gpp * 4);
925 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
926 }
927}
928
929static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
930{
931 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
932 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
933 const struct intel_community *community;
934 const struct intel_padgroup *padgrp;
935 int pin;
936
937 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
938 if (pin >= 0) {
939 unsigned gpp, gpp_offset;
940 unsigned long flags;
941 void __iomem *reg;
942 u32 value;
943
944 gpp = padgrp->reg_num;
945 gpp_offset = padgroup_offset(padgrp, pin);
946
947 reg = community->regs + community->ie_offset + gpp * 4;
948
949 raw_spin_lock_irqsave(&pctrl->lock, flags);
950 value = readl(reg);
951 if (mask)
952 value &= ~BIT(gpp_offset);
953 else
954 value |= BIT(gpp_offset);
955 writel(value, reg);
956 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
957 }
958}
959
960static void intel_gpio_irq_mask(struct irq_data *d)
961{
962 intel_gpio_irq_mask_unmask(d, true);
963}
964
965static void intel_gpio_irq_unmask(struct irq_data *d)
966{
967 intel_gpio_irq_mask_unmask(d, false);
968}
969
970static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
971{
972 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
973 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
974 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
975 unsigned long flags;
976 void __iomem *reg;
977 u32 value;
978
979 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
980 if (!reg)
981 return -EINVAL;
982
983 /*
984 * If the pin is in ACPI mode it is still usable as a GPIO but it
985 * cannot be used as IRQ because GPI_IS status bit will not be
986 * updated by the host controller hardware.
987 */
988 if (intel_pad_acpi_mode(pctrl, pin)) {
989 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
990 return -EPERM;
991 }
992
993 raw_spin_lock_irqsave(&pctrl->lock, flags);
994
995 intel_gpio_set_gpio_mode(reg);
996
997 value = readl(reg);
998
999 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1000
1001 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1002 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1003 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1004 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1005 value |= PADCFG0_RXINV;
1006 } else if (type & IRQ_TYPE_EDGE_RISING) {
1007 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1008 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1009 if (type & IRQ_TYPE_LEVEL_LOW)
1010 value |= PADCFG0_RXINV;
1011 } else {
1012 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1013 }
1014
1015 writel(value, reg);
1016
1017 if (type & IRQ_TYPE_EDGE_BOTH)
1018 irq_set_handler_locked(d, handle_edge_irq);
1019 else if (type & IRQ_TYPE_LEVEL_MASK)
1020 irq_set_handler_locked(d, handle_level_irq);
1021
1022 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1023
1024 return 0;
1025}
1026
1027static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1028{
1029 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1030 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1031 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1032
1033 if (on)
1034 enable_irq_wake(pctrl->irq);
1035 else
1036 disable_irq_wake(pctrl->irq);
1037
1038 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1039 return 0;
1040}
1041
1042static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1043 const struct intel_community *community)
1044{
1045 struct gpio_chip *gc = &pctrl->chip;
1046 irqreturn_t ret = IRQ_NONE;
1047 int gpp;
1048
1049 for (gpp = 0; gpp < community->ngpps; gpp++) {
1050 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1051 unsigned long pending, enabled, gpp_offset;
1052
1053 pending = readl(community->regs + community->is_offset +
1054 padgrp->reg_num * 4);
1055 enabled = readl(community->regs + community->ie_offset +
1056 padgrp->reg_num * 4);
1057
1058 /* Only interrupts that are enabled */
1059 pending &= enabled;
1060
1061 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1062 unsigned irq;
1063
1064 irq = irq_find_mapping(gc->irq.domain,
1065 padgrp->gpio_base + gpp_offset);
1066 generic_handle_irq(irq);
1067
1068 ret |= IRQ_HANDLED;
1069 }
1070 }
1071
1072 return ret;
1073}
1074
1075static irqreturn_t intel_gpio_irq(int irq, void *data)
1076{
1077 const struct intel_community *community;
1078 struct intel_pinctrl *pctrl = data;
1079 irqreturn_t ret = IRQ_NONE;
1080 int i;
1081
1082 /* Need to check all communities for pending interrupts */
1083 for (i = 0; i < pctrl->ncommunities; i++) {
1084 community = &pctrl->communities[i];
1085 ret |= intel_gpio_community_irq_handler(pctrl, community);
1086 }
1087
1088 return ret;
1089}
1090
1091static struct irq_chip intel_gpio_irqchip = {
1092 .name = "intel-gpio",
1093 .irq_enable = intel_gpio_irq_enable,
1094 .irq_ack = intel_gpio_irq_ack,
1095 .irq_mask = intel_gpio_irq_mask,
1096 .irq_unmask = intel_gpio_irq_unmask,
1097 .irq_set_type = intel_gpio_irq_type,
1098 .irq_set_wake = intel_gpio_irq_wake,
1099 .flags = IRQCHIP_MASK_ON_SUSPEND,
1100};
1101
1102static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1103 const struct intel_community *community)
1104{
1105 int ret = 0, i;
1106
1107 for (i = 0; i < community->ngpps; i++) {
1108 const struct intel_padgroup *gpp = &community->gpps[i];
1109
1110 if (gpp->gpio_base < 0)
1111 continue;
1112
1113 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1114 gpp->gpio_base, gpp->base,
1115 gpp->size);
1116 if (ret)
1117 return ret;
1118 }
1119
1120 return ret;
1121}
1122
1123static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1124{
1125 const struct intel_community *community;
1126 unsigned ngpio = 0;
1127 int i, j;
1128
1129 for (i = 0; i < pctrl->ncommunities; i++) {
1130 community = &pctrl->communities[i];
1131 for (j = 0; j < community->ngpps; j++) {
1132 const struct intel_padgroup *gpp = &community->gpps[j];
1133
1134 if (gpp->gpio_base < 0)
1135 continue;
1136
1137 if (gpp->gpio_base + gpp->size > ngpio)
1138 ngpio = gpp->gpio_base + gpp->size;
1139 }
1140 }
1141
1142 return ngpio;
1143}
1144
1145static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1146{
1147 int ret, i;
1148
1149 pctrl->chip = intel_gpio_chip;
1150
1151 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1152 pctrl->chip.label = dev_name(pctrl->dev);
1153 pctrl->chip.parent = pctrl->dev;
1154 pctrl->chip.base = -1;
1155 pctrl->irq = irq;
1156
1157 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1158 if (ret) {
1159 dev_err(pctrl->dev, "failed to register gpiochip\n");
1160 return ret;
1161 }
1162
1163 for (i = 0; i < pctrl->ncommunities; i++) {
1164 struct intel_community *community = &pctrl->communities[i];
1165
1166 ret = intel_gpio_add_pin_ranges(pctrl, community);
1167 if (ret) {
1168 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1169 return ret;
1170 }
1171 }
1172
1173 /*
1174 * We need to request the interrupt here (instead of providing chip
1175 * to the irq directly) because on some platforms several GPIO
1176 * controllers share the same interrupt line.
1177 */
1178 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1179 IRQF_SHARED | IRQF_NO_THREAD,
1180 dev_name(pctrl->dev), pctrl);
1181 if (ret) {
1182 dev_err(pctrl->dev, "failed to request interrupt\n");
1183 return ret;
1184 }
1185
1186 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1187 handle_bad_irq, IRQ_TYPE_NONE);
1188 if (ret) {
1189 dev_err(pctrl->dev, "failed to add irqchip\n");
1190 return ret;
1191 }
1192
1193 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1194 NULL);
1195 return 0;
1196}
1197
1198static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1199 struct intel_community *community)
1200{
1201 struct intel_padgroup *gpps;
1202 unsigned npins = community->npins;
1203 unsigned padown_num = 0;
1204 size_t ngpps, i;
1205
1206 if (community->gpps)
1207 ngpps = community->ngpps;
1208 else
1209 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1210
1211 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1212 if (!gpps)
1213 return -ENOMEM;
1214
1215 for (i = 0; i < ngpps; i++) {
1216 if (community->gpps) {
1217 gpps[i] = community->gpps[i];
1218 } else {
1219 unsigned gpp_size = community->gpp_size;
1220
1221 gpps[i].reg_num = i;
1222 gpps[i].base = community->pin_base + i * gpp_size;
1223 gpps[i].size = min(gpp_size, npins);
1224 npins -= gpps[i].size;
1225 }
1226
1227 if (gpps[i].size > 32)
1228 return -EINVAL;
1229
1230 if (!gpps[i].gpio_base)
1231 gpps[i].gpio_base = gpps[i].base;
1232
1233 gpps[i].padown_num = padown_num;
1234
1235 /*
1236 * In older hardware the number of padown registers per
1237 * group is fixed regardless of the group size.
1238 */
1239 if (community->gpp_num_padown_regs)
1240 padown_num += community->gpp_num_padown_regs;
1241 else
1242 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1243 }
1244
1245 community->ngpps = ngpps;
1246 community->gpps = gpps;
1247
1248 return 0;
1249}
1250
1251static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1252{
1253#ifdef CONFIG_PM_SLEEP
1254 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1255 struct intel_community_context *communities;
1256 struct intel_pad_context *pads;
1257 int i;
1258
1259 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1260 if (!pads)
1261 return -ENOMEM;
1262
1263 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1264 sizeof(*communities), GFP_KERNEL);
1265 if (!communities)
1266 return -ENOMEM;
1267
1268
1269 for (i = 0; i < pctrl->ncommunities; i++) {
1270 struct intel_community *community = &pctrl->communities[i];
1271 u32 *intmask;
1272
1273 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1274 sizeof(*intmask), GFP_KERNEL);
1275 if (!intmask)
1276 return -ENOMEM;
1277
1278 communities[i].intmask = intmask;
1279 }
1280
1281 pctrl->context.pads = pads;
1282 pctrl->context.communities = communities;
1283#endif
1284
1285 return 0;
1286}
1287
1288int intel_pinctrl_probe(struct platform_device *pdev,
1289 const struct intel_pinctrl_soc_data *soc_data)
1290{
1291 struct intel_pinctrl *pctrl;
1292 int i, ret, irq;
1293
1294 if (!soc_data)
1295 return -EINVAL;
1296
1297 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1298 if (!pctrl)
1299 return -ENOMEM;
1300
1301 pctrl->dev = &pdev->dev;
1302 pctrl->soc = soc_data;
1303 raw_spin_lock_init(&pctrl->lock);
1304
1305 /*
1306 * Make a copy of the communities which we can use to hold pointers
1307 * to the registers.
1308 */
1309 pctrl->ncommunities = pctrl->soc->ncommunities;
1310 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1311 sizeof(*pctrl->communities), GFP_KERNEL);
1312 if (!pctrl->communities)
1313 return -ENOMEM;
1314
1315 for (i = 0; i < pctrl->ncommunities; i++) {
1316 struct intel_community *community = &pctrl->communities[i];
1317 struct resource *res;
1318 void __iomem *regs;
1319 u32 padbar;
1320
1321 *community = pctrl->soc->communities[i];
1322
1323 res = platform_get_resource(pdev, IORESOURCE_MEM,
1324 community->barno);
1325 regs = devm_ioremap_resource(&pdev->dev, res);
1326 if (IS_ERR(regs))
1327 return PTR_ERR(regs);
1328
1329 /*
1330 * Determine community features based on the revision if
1331 * not specified already.
1332 */
1333 if (!community->features) {
1334 u32 rev;
1335
1336 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1337 if (rev >= 0x94) {
1338 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1339 community->features |= PINCTRL_FEATURE_1K_PD;
1340 }
1341 }
1342
1343 /* Read offset of the pad configuration registers */
1344 padbar = readl(regs + PADBAR);
1345
1346 community->regs = regs;
1347 community->pad_regs = regs + padbar;
1348
1349 if (!community->is_offset)
1350 community->is_offset = GPI_IS;
1351
1352 ret = intel_pinctrl_add_padgroups(pctrl, community);
1353 if (ret)
1354 return ret;
1355 }
1356
1357 irq = platform_get_irq(pdev, 0);
1358 if (irq < 0) {
1359 dev_err(&pdev->dev, "failed to get interrupt number\n");
1360 return irq;
1361 }
1362
1363 ret = intel_pinctrl_pm_init(pctrl);
1364 if (ret)
1365 return ret;
1366
1367 pctrl->pctldesc = intel_pinctrl_desc;
1368 pctrl->pctldesc.name = dev_name(&pdev->dev);
1369 pctrl->pctldesc.pins = pctrl->soc->pins;
1370 pctrl->pctldesc.npins = pctrl->soc->npins;
1371
1372 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1373 pctrl);
1374 if (IS_ERR(pctrl->pctldev)) {
1375 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1376 return PTR_ERR(pctrl->pctldev);
1377 }
1378
1379 ret = intel_gpio_probe(pctrl, irq);
1380 if (ret)
1381 return ret;
1382
1383 platform_set_drvdata(pdev, pctrl);
1384
1385 return 0;
1386}
1387EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1388
1389#ifdef CONFIG_PM_SLEEP
1390static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1391{
1392 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1393
1394 if (!pd || !intel_pad_usable(pctrl, pin))
1395 return false;
1396
1397 /*
1398 * Only restore the pin if it is actually in use by the kernel (or
1399 * by userspace). It is possible that some pins are used by the
1400 * BIOS during resume and those are not always locked down so leave
1401 * them alone.
1402 */
1403 if (pd->mux_owner || pd->gpio_owner ||
1404 gpiochip_line_is_irq(&pctrl->chip, pin))
1405 return true;
1406
1407 return false;
1408}
1409
1410int intel_pinctrl_suspend(struct device *dev)
1411{
1412 struct platform_device *pdev = to_platform_device(dev);
1413 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1414 struct intel_community_context *communities;
1415 struct intel_pad_context *pads;
1416 int i;
1417
1418 pads = pctrl->context.pads;
1419 for (i = 0; i < pctrl->soc->npins; i++) {
1420 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1421 void __iomem *padcfg;
1422 u32 val;
1423
1424 if (!intel_pinctrl_should_save(pctrl, desc->number))
1425 continue;
1426
1427 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1428 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1429 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1430 pads[i].padcfg1 = val;
1431
1432 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1433 if (padcfg)
1434 pads[i].padcfg2 = readl(padcfg);
1435 }
1436
1437 communities = pctrl->context.communities;
1438 for (i = 0; i < pctrl->ncommunities; i++) {
1439 struct intel_community *community = &pctrl->communities[i];
1440 void __iomem *base;
1441 unsigned gpp;
1442
1443 base = community->regs + community->ie_offset;
1444 for (gpp = 0; gpp < community->ngpps; gpp++)
1445 communities[i].intmask[gpp] = readl(base + gpp * 4);
1446 }
1447
1448 return 0;
1449}
1450EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1451
1452static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1453{
1454 size_t i;
1455
1456 for (i = 0; i < pctrl->ncommunities; i++) {
1457 const struct intel_community *community;
1458 void __iomem *base;
1459 unsigned gpp;
1460
1461 community = &pctrl->communities[i];
1462 base = community->regs;
1463
1464 for (gpp = 0; gpp < community->ngpps; gpp++) {
1465 /* Mask and clear all interrupts */
1466 writel(0, base + community->ie_offset + gpp * 4);
1467 writel(0xffff, base + community->is_offset + gpp * 4);
1468 }
1469 }
1470}
1471
1472int intel_pinctrl_resume(struct device *dev)
1473{
1474 struct platform_device *pdev = to_platform_device(dev);
1475 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1476 const struct intel_community_context *communities;
1477 const struct intel_pad_context *pads;
1478 int i;
1479
1480 /* Mask all interrupts */
1481 intel_gpio_irq_init(pctrl);
1482
1483 pads = pctrl->context.pads;
1484 for (i = 0; i < pctrl->soc->npins; i++) {
1485 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1486 void __iomem *padcfg;
1487 u32 val;
1488
1489 if (!intel_pinctrl_should_save(pctrl, desc->number))
1490 continue;
1491
1492 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1493 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1494 if (val != pads[i].padcfg0) {
1495 writel(pads[i].padcfg0, padcfg);
1496 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1497 desc->number, readl(padcfg));
1498 }
1499
1500 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1501 val = readl(padcfg);
1502 if (val != pads[i].padcfg1) {
1503 writel(pads[i].padcfg1, padcfg);
1504 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1505 desc->number, readl(padcfg));
1506 }
1507
1508 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1509 if (padcfg) {
1510 val = readl(padcfg);
1511 if (val != pads[i].padcfg2) {
1512 writel(pads[i].padcfg2, padcfg);
1513 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1514 desc->number, readl(padcfg));
1515 }
1516 }
1517 }
1518
1519 communities = pctrl->context.communities;
1520 for (i = 0; i < pctrl->ncommunities; i++) {
1521 struct intel_community *community = &pctrl->communities[i];
1522 void __iomem *base;
1523 unsigned gpp;
1524
1525 base = community->regs + community->ie_offset;
1526 for (gpp = 0; gpp < community->ngpps; gpp++) {
1527 writel(communities[i].intmask[gpp], base + gpp * 4);
1528 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1529 readl(base + gpp * 4));
1530 }
1531 }
1532
1533 return 0;
1534}
1535EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1536#endif
1537
1538MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1539MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1540MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1541MODULE_LICENSE("GPL v2");