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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/gpio.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of_gpio.h>
13#include <linux/pinctrl/pinconf-generic.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
20#include <linux/workqueue.h>
21
22#include <drm/drm_dp_helper.h>
23#include <drm/drm_panel.h>
24
25#include "dpaux.h"
26#include "drm.h"
27#include "trace.h"
28
29static DEFINE_MUTEX(dpaux_lock);
30static LIST_HEAD(dpaux_list);
31
32struct tegra_dpaux {
33 struct drm_dp_aux aux;
34 struct device *dev;
35
36 void __iomem *regs;
37 int irq;
38
39 struct tegra_output *output;
40
41 struct reset_control *rst;
42 struct clk *clk_parent;
43 struct clk *clk;
44
45 struct regulator *vdd;
46
47 struct completion complete;
48 struct work_struct work;
49 struct list_head list;
50
51#ifdef CONFIG_GENERIC_PINCONF
52 struct pinctrl_dev *pinctrl;
53 struct pinctrl_desc desc;
54#endif
55};
56
57static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
58{
59 return container_of(aux, struct tegra_dpaux, aux);
60}
61
62static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
63{
64 return container_of(work, struct tegra_dpaux, work);
65}
66
67static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
68 unsigned int offset)
69{
70 u32 value = readl(dpaux->regs + (offset << 2));
71
72 trace_dpaux_readl(dpaux->dev, offset, value);
73
74 return value;
75}
76
77static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
78 u32 value, unsigned int offset)
79{
80 trace_dpaux_writel(dpaux->dev, offset, value);
81 writel(value, dpaux->regs + (offset << 2));
82}
83
84static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
85 size_t size)
86{
87 size_t i, j;
88
89 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
90 size_t num = min_t(size_t, size - i * 4, 4);
91 u32 value = 0;
92
93 for (j = 0; j < num; j++)
94 value |= buffer[i * 4 + j] << (j * 8);
95
96 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
97 }
98}
99
100static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
101 size_t size)
102{
103 size_t i, j;
104
105 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
106 size_t num = min_t(size_t, size - i * 4, 4);
107 u32 value;
108
109 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
110
111 for (j = 0; j < num; j++)
112 buffer[i * 4 + j] = value >> (j * 8);
113 }
114}
115
116static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
117 struct drm_dp_aux_msg *msg)
118{
119 unsigned long timeout = msecs_to_jiffies(250);
120 struct tegra_dpaux *dpaux = to_dpaux(aux);
121 unsigned long status;
122 ssize_t ret = 0;
123 u32 value;
124
125 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
126 if (msg->size > 16)
127 return -EINVAL;
128
129 /*
130 * Allow zero-sized messages only for I2C, in which case they specify
131 * address-only transactions.
132 */
133 if (msg->size < 1) {
134 switch (msg->request & ~DP_AUX_I2C_MOT) {
135 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
136 case DP_AUX_I2C_WRITE:
137 case DP_AUX_I2C_READ:
138 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
139 break;
140
141 default:
142 return -EINVAL;
143 }
144 } else {
145 /* For non-zero-sized messages, set the CMDLEN field. */
146 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
147 }
148
149 switch (msg->request & ~DP_AUX_I2C_MOT) {
150 case DP_AUX_I2C_WRITE:
151 if (msg->request & DP_AUX_I2C_MOT)
152 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
153 else
154 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
155
156 break;
157
158 case DP_AUX_I2C_READ:
159 if (msg->request & DP_AUX_I2C_MOT)
160 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
161 else
162 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
163
164 break;
165
166 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
167 if (msg->request & DP_AUX_I2C_MOT)
168 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
169 else
170 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
171
172 break;
173
174 case DP_AUX_NATIVE_WRITE:
175 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
176 break;
177
178 case DP_AUX_NATIVE_READ:
179 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
180 break;
181
182 default:
183 return -EINVAL;
184 }
185
186 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
187 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
188
189 if ((msg->request & DP_AUX_I2C_READ) == 0) {
190 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
191 ret = msg->size;
192 }
193
194 /* start transaction */
195 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
196 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
197 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
198
199 status = wait_for_completion_timeout(&dpaux->complete, timeout);
200 if (!status)
201 return -ETIMEDOUT;
202
203 /* read status and clear errors */
204 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
205 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
206
207 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
208 return -ETIMEDOUT;
209
210 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
211 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
212 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
213 return -EIO;
214
215 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
216 case 0x00:
217 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
218 break;
219
220 case 0x01:
221 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
222 break;
223
224 case 0x02:
225 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
226 break;
227
228 case 0x04:
229 msg->reply = DP_AUX_I2C_REPLY_NACK;
230 break;
231
232 case 0x08:
233 msg->reply = DP_AUX_I2C_REPLY_DEFER;
234 break;
235 }
236
237 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
238 if (msg->request & DP_AUX_I2C_READ) {
239 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
240
241 if (WARN_ON(count != msg->size))
242 count = min_t(size_t, count, msg->size);
243
244 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
245 ret = count;
246 }
247 }
248
249 return ret;
250}
251
252static void tegra_dpaux_hotplug(struct work_struct *work)
253{
254 struct tegra_dpaux *dpaux = work_to_dpaux(work);
255
256 if (dpaux->output)
257 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
258}
259
260static irqreturn_t tegra_dpaux_irq(int irq, void *data)
261{
262 struct tegra_dpaux *dpaux = data;
263 irqreturn_t ret = IRQ_HANDLED;
264 u32 value;
265
266 /* clear interrupts */
267 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
268 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
269
270 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
271 schedule_work(&dpaux->work);
272
273 if (value & DPAUX_INTR_IRQ_EVENT) {
274 /* TODO: handle this */
275 }
276
277 if (value & DPAUX_INTR_AUX_DONE)
278 complete(&dpaux->complete);
279
280 return ret;
281}
282
283enum tegra_dpaux_functions {
284 DPAUX_PADCTL_FUNC_AUX,
285 DPAUX_PADCTL_FUNC_I2C,
286 DPAUX_PADCTL_FUNC_OFF,
287};
288
289static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
290{
291 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
292
293 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
294
295 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
296}
297
298static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
299{
300 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
301
302 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
303
304 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
305}
306
307static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
308{
309 u32 value;
310
311 switch (function) {
312 case DPAUX_PADCTL_FUNC_AUX:
313 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
314 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
315 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
316 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
317 DPAUX_HYBRID_PADCTL_MODE_AUX;
318 break;
319
320 case DPAUX_PADCTL_FUNC_I2C:
321 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
322 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
323 DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
324 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
325 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
326 DPAUX_HYBRID_PADCTL_MODE_I2C;
327 break;
328
329 case DPAUX_PADCTL_FUNC_OFF:
330 tegra_dpaux_pad_power_down(dpaux);
331 return 0;
332
333 default:
334 return -ENOTSUPP;
335 }
336
337 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
338 tegra_dpaux_pad_power_up(dpaux);
339
340 return 0;
341}
342
343#ifdef CONFIG_GENERIC_PINCONF
344static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
345 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
346 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
347};
348
349static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
350
351static const char * const tegra_dpaux_groups[] = {
352 "dpaux-io",
353};
354
355static const char * const tegra_dpaux_functions[] = {
356 "aux",
357 "i2c",
358 "off",
359};
360
361static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
362{
363 return ARRAY_SIZE(tegra_dpaux_groups);
364}
365
366static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
367 unsigned int group)
368{
369 return tegra_dpaux_groups[group];
370}
371
372static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
373 unsigned group, const unsigned **pins,
374 unsigned *num_pins)
375{
376 *pins = tegra_dpaux_pin_numbers;
377 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
378
379 return 0;
380}
381
382static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
383 .get_groups_count = tegra_dpaux_get_groups_count,
384 .get_group_name = tegra_dpaux_get_group_name,
385 .get_group_pins = tegra_dpaux_get_group_pins,
386 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
387 .dt_free_map = pinconf_generic_dt_free_map,
388};
389
390static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
391{
392 return ARRAY_SIZE(tegra_dpaux_functions);
393}
394
395static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
396 unsigned int function)
397{
398 return tegra_dpaux_functions[function];
399}
400
401static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
402 unsigned int function,
403 const char * const **groups,
404 unsigned * const num_groups)
405{
406 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
407 *groups = tegra_dpaux_groups;
408
409 return 0;
410}
411
412static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
413 unsigned int function, unsigned int group)
414{
415 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
416
417 return tegra_dpaux_pad_config(dpaux, function);
418}
419
420static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
421 .get_functions_count = tegra_dpaux_get_functions_count,
422 .get_function_name = tegra_dpaux_get_function_name,
423 .get_function_groups = tegra_dpaux_get_function_groups,
424 .set_mux = tegra_dpaux_set_mux,
425};
426#endif
427
428static int tegra_dpaux_probe(struct platform_device *pdev)
429{
430 struct tegra_dpaux *dpaux;
431 struct resource *regs;
432 u32 value;
433 int err;
434
435 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
436 if (!dpaux)
437 return -ENOMEM;
438
439 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
440 init_completion(&dpaux->complete);
441 INIT_LIST_HEAD(&dpaux->list);
442 dpaux->dev = &pdev->dev;
443
444 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
445 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
446 if (IS_ERR(dpaux->regs))
447 return PTR_ERR(dpaux->regs);
448
449 dpaux->irq = platform_get_irq(pdev, 0);
450 if (dpaux->irq < 0) {
451 dev_err(&pdev->dev, "failed to get IRQ\n");
452 return -ENXIO;
453 }
454
455 if (!pdev->dev.pm_domain) {
456 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
457 if (IS_ERR(dpaux->rst)) {
458 dev_err(&pdev->dev,
459 "failed to get reset control: %ld\n",
460 PTR_ERR(dpaux->rst));
461 return PTR_ERR(dpaux->rst);
462 }
463 }
464
465 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
466 if (IS_ERR(dpaux->clk)) {
467 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
468 PTR_ERR(dpaux->clk));
469 return PTR_ERR(dpaux->clk);
470 }
471
472 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
473 if (IS_ERR(dpaux->clk_parent)) {
474 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
475 PTR_ERR(dpaux->clk_parent));
476 return PTR_ERR(dpaux->clk_parent);
477 }
478
479 err = clk_set_rate(dpaux->clk_parent, 270000000);
480 if (err < 0) {
481 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
482 err);
483 return err;
484 }
485
486 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
487 if (IS_ERR(dpaux->vdd)) {
488 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
489 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
490 dev_err(&pdev->dev,
491 "failed to get VDD supply: %ld\n",
492 PTR_ERR(dpaux->vdd));
493
494 return PTR_ERR(dpaux->vdd);
495 }
496 }
497
498 platform_set_drvdata(pdev, dpaux);
499 pm_runtime_enable(&pdev->dev);
500 pm_runtime_get_sync(&pdev->dev);
501
502 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
503 dev_name(dpaux->dev), dpaux);
504 if (err < 0) {
505 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
506 dpaux->irq, err);
507 return err;
508 }
509
510 disable_irq(dpaux->irq);
511
512 dpaux->aux.transfer = tegra_dpaux_transfer;
513 dpaux->aux.dev = &pdev->dev;
514
515 err = drm_dp_aux_register(&dpaux->aux);
516 if (err < 0)
517 return err;
518
519 /*
520 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
521 * so power them up and configure them in I2C mode.
522 *
523 * The DPAUX code paths reconfigure the pads in AUX mode, but there
524 * is no possibility to perform the I2C mode configuration in the
525 * HDMI path.
526 */
527 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
528 if (err < 0)
529 return err;
530
531#ifdef CONFIG_GENERIC_PINCONF
532 dpaux->desc.name = dev_name(&pdev->dev);
533 dpaux->desc.pins = tegra_dpaux_pins;
534 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
535 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
536 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
537 dpaux->desc.owner = THIS_MODULE;
538
539 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
540 if (IS_ERR(dpaux->pinctrl)) {
541 dev_err(&pdev->dev, "failed to register pincontrol\n");
542 return PTR_ERR(dpaux->pinctrl);
543 }
544#endif
545 /* enable and clear all interrupts */
546 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
547 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
548 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
549 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
550
551 mutex_lock(&dpaux_lock);
552 list_add_tail(&dpaux->list, &dpaux_list);
553 mutex_unlock(&dpaux_lock);
554
555 return 0;
556}
557
558static int tegra_dpaux_remove(struct platform_device *pdev)
559{
560 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
561
562 cancel_work_sync(&dpaux->work);
563
564 /* make sure pads are powered down when not in use */
565 tegra_dpaux_pad_power_down(dpaux);
566
567 pm_runtime_put(&pdev->dev);
568 pm_runtime_disable(&pdev->dev);
569
570 drm_dp_aux_unregister(&dpaux->aux);
571
572 mutex_lock(&dpaux_lock);
573 list_del(&dpaux->list);
574 mutex_unlock(&dpaux_lock);
575
576 return 0;
577}
578
579#ifdef CONFIG_PM
580static int tegra_dpaux_suspend(struct device *dev)
581{
582 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
583 int err = 0;
584
585 if (dpaux->rst) {
586 err = reset_control_assert(dpaux->rst);
587 if (err < 0) {
588 dev_err(dev, "failed to assert reset: %d\n", err);
589 return err;
590 }
591 }
592
593 usleep_range(1000, 2000);
594
595 clk_disable_unprepare(dpaux->clk_parent);
596 clk_disable_unprepare(dpaux->clk);
597
598 return err;
599}
600
601static int tegra_dpaux_resume(struct device *dev)
602{
603 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
604 int err;
605
606 err = clk_prepare_enable(dpaux->clk);
607 if (err < 0) {
608 dev_err(dev, "failed to enable clock: %d\n", err);
609 return err;
610 }
611
612 err = clk_prepare_enable(dpaux->clk_parent);
613 if (err < 0) {
614 dev_err(dev, "failed to enable parent clock: %d\n", err);
615 goto disable_clk;
616 }
617
618 usleep_range(1000, 2000);
619
620 if (dpaux->rst) {
621 err = reset_control_deassert(dpaux->rst);
622 if (err < 0) {
623 dev_err(dev, "failed to deassert reset: %d\n", err);
624 goto disable_parent;
625 }
626
627 usleep_range(1000, 2000);
628 }
629
630 return 0;
631
632disable_parent:
633 clk_disable_unprepare(dpaux->clk_parent);
634disable_clk:
635 clk_disable_unprepare(dpaux->clk);
636 return err;
637}
638#endif
639
640static const struct dev_pm_ops tegra_dpaux_pm_ops = {
641 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
642};
643
644static const struct of_device_id tegra_dpaux_of_match[] = {
645 { .compatible = "nvidia,tegra194-dpaux", },
646 { .compatible = "nvidia,tegra186-dpaux", },
647 { .compatible = "nvidia,tegra210-dpaux", },
648 { .compatible = "nvidia,tegra124-dpaux", },
649 { },
650};
651MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
652
653struct platform_driver tegra_dpaux_driver = {
654 .driver = {
655 .name = "tegra-dpaux",
656 .of_match_table = tegra_dpaux_of_match,
657 .pm = &tegra_dpaux_pm_ops,
658 },
659 .probe = tegra_dpaux_probe,
660 .remove = tegra_dpaux_remove,
661};
662
663struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
664{
665 struct tegra_dpaux *dpaux;
666
667 mutex_lock(&dpaux_lock);
668
669 list_for_each_entry(dpaux, &dpaux_list, list)
670 if (np == dpaux->dev->of_node) {
671 mutex_unlock(&dpaux_lock);
672 return &dpaux->aux;
673 }
674
675 mutex_unlock(&dpaux_lock);
676
677 return NULL;
678}
679
680int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
681{
682 struct tegra_dpaux *dpaux = to_dpaux(aux);
683 unsigned long timeout;
684 int err;
685
686 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
687 dpaux->output = output;
688
689 err = regulator_enable(dpaux->vdd);
690 if (err < 0)
691 return err;
692
693 timeout = jiffies + msecs_to_jiffies(250);
694
695 while (time_before(jiffies, timeout)) {
696 enum drm_connector_status status;
697
698 status = drm_dp_aux_detect(aux);
699 if (status == connector_status_connected) {
700 enable_irq(dpaux->irq);
701 return 0;
702 }
703
704 usleep_range(1000, 2000);
705 }
706
707 return -ETIMEDOUT;
708}
709
710int drm_dp_aux_detach(struct drm_dp_aux *aux)
711{
712 struct tegra_dpaux *dpaux = to_dpaux(aux);
713 unsigned long timeout;
714 int err;
715
716 disable_irq(dpaux->irq);
717
718 err = regulator_disable(dpaux->vdd);
719 if (err < 0)
720 return err;
721
722 timeout = jiffies + msecs_to_jiffies(250);
723
724 while (time_before(jiffies, timeout)) {
725 enum drm_connector_status status;
726
727 status = drm_dp_aux_detect(aux);
728 if (status == connector_status_disconnected) {
729 dpaux->output = NULL;
730 return 0;
731 }
732
733 usleep_range(1000, 2000);
734 }
735
736 return -ETIMEDOUT;
737}
738
739enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
740{
741 struct tegra_dpaux *dpaux = to_dpaux(aux);
742 u32 value;
743
744 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
745
746 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
747 return connector_status_connected;
748
749 return connector_status_disconnected;
750}
751
752int drm_dp_aux_enable(struct drm_dp_aux *aux)
753{
754 struct tegra_dpaux *dpaux = to_dpaux(aux);
755
756 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
757}
758
759int drm_dp_aux_disable(struct drm_dp_aux *aux)
760{
761 struct tegra_dpaux *dpaux = to_dpaux(aux);
762
763 tegra_dpaux_pad_power_down(dpaux);
764
765 return 0;
766}
767
768int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
769{
770 int err;
771
772 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
773 encoding);
774 if (err < 0)
775 return err;
776
777 return 0;
778}
779
780int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
781 u8 pattern)
782{
783 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
784 u8 status[DP_LINK_STATUS_SIZE], values[4];
785 unsigned int i;
786 int err;
787
788 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
789 if (err < 0)
790 return err;
791
792 if (tp == DP_TRAINING_PATTERN_DISABLE)
793 return 0;
794
795 for (i = 0; i < link->num_lanes; i++)
796 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
797 DP_TRAIN_PRE_EMPH_LEVEL_0 |
798 DP_TRAIN_MAX_SWING_REACHED |
799 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
800
801 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
802 link->num_lanes);
803 if (err < 0)
804 return err;
805
806 usleep_range(500, 1000);
807
808 err = drm_dp_dpcd_read_link_status(aux, status);
809 if (err < 0)
810 return err;
811
812 switch (tp) {
813 case DP_TRAINING_PATTERN_1:
814 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
815 return -EAGAIN;
816
817 break;
818
819 case DP_TRAINING_PATTERN_2:
820 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
821 return -EAGAIN;
822
823 break;
824
825 default:
826 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
827 return -EINVAL;
828 }
829
830 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
831 if (err < 0)
832 return err;
833
834 return 0;
835}