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1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/of_gpio.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/regulator/consumer.h>
18#include <linux/workqueue.h>
19
20#include <drm/drm_dp_helper.h>
21#include <drm/drm_panel.h>
22
23#include "dpaux.h"
24#include "drm.h"
25
26static DEFINE_MUTEX(dpaux_lock);
27static LIST_HEAD(dpaux_list);
28
29struct tegra_dpaux {
30 struct drm_dp_aux aux;
31 struct device *dev;
32
33 void __iomem *regs;
34 int irq;
35
36 struct tegra_output *output;
37
38 struct reset_control *rst;
39 struct clk *clk_parent;
40 struct clk *clk;
41
42 struct regulator *vdd;
43
44 struct completion complete;
45 struct work_struct work;
46 struct list_head list;
47};
48
49static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
50{
51 return container_of(aux, struct tegra_dpaux, aux);
52}
53
54static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
55{
56 return container_of(work, struct tegra_dpaux, work);
57}
58
59static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
60 unsigned long offset)
61{
62 return readl(dpaux->regs + (offset << 2));
63}
64
65static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
66 u32 value, unsigned long offset)
67{
68 writel(value, dpaux->regs + (offset << 2));
69}
70
71static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
72 size_t size)
73{
74 size_t i, j;
75
76 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
77 size_t num = min_t(size_t, size - i * 4, 4);
78 u32 value = 0;
79
80 for (j = 0; j < num; j++)
81 value |= buffer[i * 4 + j] << (j * 8);
82
83 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
84 }
85}
86
87static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
88 size_t size)
89{
90 size_t i, j;
91
92 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
93 size_t num = min_t(size_t, size - i * 4, 4);
94 u32 value;
95
96 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
97
98 for (j = 0; j < num; j++)
99 buffer[i * 4 + j] = value >> (j * 8);
100 }
101}
102
103static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
104 struct drm_dp_aux_msg *msg)
105{
106 unsigned long timeout = msecs_to_jiffies(250);
107 struct tegra_dpaux *dpaux = to_dpaux(aux);
108 unsigned long status;
109 ssize_t ret = 0;
110 u32 value;
111
112 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
113 if (msg->size > 16)
114 return -EINVAL;
115
116 /*
117 * Allow zero-sized messages only for I2C, in which case they specify
118 * address-only transactions.
119 */
120 if (msg->size < 1) {
121 switch (msg->request & ~DP_AUX_I2C_MOT) {
122 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
123 case DP_AUX_I2C_WRITE:
124 case DP_AUX_I2C_READ:
125 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
126 break;
127
128 default:
129 return -EINVAL;
130 }
131 } else {
132 /* For non-zero-sized messages, set the CMDLEN field. */
133 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
134 }
135
136 switch (msg->request & ~DP_AUX_I2C_MOT) {
137 case DP_AUX_I2C_WRITE:
138 if (msg->request & DP_AUX_I2C_MOT)
139 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
140 else
141 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
142
143 break;
144
145 case DP_AUX_I2C_READ:
146 if (msg->request & DP_AUX_I2C_MOT)
147 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
148 else
149 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
150
151 break;
152
153 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
154 if (msg->request & DP_AUX_I2C_MOT)
155 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
156 else
157 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
158
159 break;
160
161 case DP_AUX_NATIVE_WRITE:
162 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
163 break;
164
165 case DP_AUX_NATIVE_READ:
166 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
167 break;
168
169 default:
170 return -EINVAL;
171 }
172
173 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
174 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
175
176 if ((msg->request & DP_AUX_I2C_READ) == 0) {
177 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
178 ret = msg->size;
179 }
180
181 /* start transaction */
182 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
183 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
184 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
185
186 status = wait_for_completion_timeout(&dpaux->complete, timeout);
187 if (!status)
188 return -ETIMEDOUT;
189
190 /* read status and clear errors */
191 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
192 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
193
194 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
195 return -ETIMEDOUT;
196
197 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
198 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
199 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
200 return -EIO;
201
202 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
203 case 0x00:
204 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
205 break;
206
207 case 0x01:
208 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
209 break;
210
211 case 0x02:
212 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
213 break;
214
215 case 0x04:
216 msg->reply = DP_AUX_I2C_REPLY_NACK;
217 break;
218
219 case 0x08:
220 msg->reply = DP_AUX_I2C_REPLY_DEFER;
221 break;
222 }
223
224 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
225 if (msg->request & DP_AUX_I2C_READ) {
226 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
227
228 if (WARN_ON(count != msg->size))
229 count = min_t(size_t, count, msg->size);
230
231 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
232 ret = count;
233 }
234 }
235
236 return ret;
237}
238
239static void tegra_dpaux_hotplug(struct work_struct *work)
240{
241 struct tegra_dpaux *dpaux = work_to_dpaux(work);
242
243 if (dpaux->output)
244 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
245}
246
247static irqreturn_t tegra_dpaux_irq(int irq, void *data)
248{
249 struct tegra_dpaux *dpaux = data;
250 irqreturn_t ret = IRQ_HANDLED;
251 u32 value;
252
253 /* clear interrupts */
254 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
255 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
256
257 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
258 schedule_work(&dpaux->work);
259
260 if (value & DPAUX_INTR_IRQ_EVENT) {
261 /* TODO: handle this */
262 }
263
264 if (value & DPAUX_INTR_AUX_DONE)
265 complete(&dpaux->complete);
266
267 return ret;
268}
269
270static int tegra_dpaux_probe(struct platform_device *pdev)
271{
272 struct tegra_dpaux *dpaux;
273 struct resource *regs;
274 u32 value;
275 int err;
276
277 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
278 if (!dpaux)
279 return -ENOMEM;
280
281 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
282 init_completion(&dpaux->complete);
283 INIT_LIST_HEAD(&dpaux->list);
284 dpaux->dev = &pdev->dev;
285
286 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
287 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
288 if (IS_ERR(dpaux->regs))
289 return PTR_ERR(dpaux->regs);
290
291 dpaux->irq = platform_get_irq(pdev, 0);
292 if (dpaux->irq < 0) {
293 dev_err(&pdev->dev, "failed to get IRQ\n");
294 return -ENXIO;
295 }
296
297 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
298 if (IS_ERR(dpaux->rst)) {
299 dev_err(&pdev->dev, "failed to get reset control: %ld\n",
300 PTR_ERR(dpaux->rst));
301 return PTR_ERR(dpaux->rst);
302 }
303
304 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
305 if (IS_ERR(dpaux->clk)) {
306 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
307 PTR_ERR(dpaux->clk));
308 return PTR_ERR(dpaux->clk);
309 }
310
311 err = clk_prepare_enable(dpaux->clk);
312 if (err < 0) {
313 dev_err(&pdev->dev, "failed to enable module clock: %d\n",
314 err);
315 return err;
316 }
317
318 reset_control_deassert(dpaux->rst);
319
320 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
321 if (IS_ERR(dpaux->clk_parent)) {
322 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
323 PTR_ERR(dpaux->clk_parent));
324 return PTR_ERR(dpaux->clk_parent);
325 }
326
327 err = clk_prepare_enable(dpaux->clk_parent);
328 if (err < 0) {
329 dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
330 err);
331 return err;
332 }
333
334 err = clk_set_rate(dpaux->clk_parent, 270000000);
335 if (err < 0) {
336 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
337 err);
338 return err;
339 }
340
341 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
342 if (IS_ERR(dpaux->vdd)) {
343 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
344 PTR_ERR(dpaux->vdd));
345 return PTR_ERR(dpaux->vdd);
346 }
347
348 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
349 dev_name(dpaux->dev), dpaux);
350 if (err < 0) {
351 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
352 dpaux->irq, err);
353 return err;
354 }
355
356 disable_irq(dpaux->irq);
357
358 dpaux->aux.transfer = tegra_dpaux_transfer;
359 dpaux->aux.dev = &pdev->dev;
360
361 err = drm_dp_aux_register(&dpaux->aux);
362 if (err < 0)
363 return err;
364
365 /*
366 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
367 * so power them up and configure them in I2C mode.
368 *
369 * The DPAUX code paths reconfigure the pads in AUX mode, but there
370 * is no possibility to perform the I2C mode configuration in the
371 * HDMI path.
372 */
373 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
374 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
375 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
376
377 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL);
378 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
379 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
380 DPAUX_HYBRID_PADCTL_MODE_I2C;
381 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
382
383 /* enable and clear all interrupts */
384 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
385 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
386 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
387 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
388
389 mutex_lock(&dpaux_lock);
390 list_add_tail(&dpaux->list, &dpaux_list);
391 mutex_unlock(&dpaux_lock);
392
393 platform_set_drvdata(pdev, dpaux);
394
395 return 0;
396}
397
398static int tegra_dpaux_remove(struct platform_device *pdev)
399{
400 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
401 u32 value;
402
403 /* make sure pads are powered down when not in use */
404 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
405 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
406 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
407
408 drm_dp_aux_unregister(&dpaux->aux);
409
410 mutex_lock(&dpaux_lock);
411 list_del(&dpaux->list);
412 mutex_unlock(&dpaux_lock);
413
414 cancel_work_sync(&dpaux->work);
415
416 clk_disable_unprepare(dpaux->clk_parent);
417 reset_control_assert(dpaux->rst);
418 clk_disable_unprepare(dpaux->clk);
419
420 return 0;
421}
422
423static const struct of_device_id tegra_dpaux_of_match[] = {
424 { .compatible = "nvidia,tegra210-dpaux", },
425 { .compatible = "nvidia,tegra124-dpaux", },
426 { },
427};
428MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
429
430struct platform_driver tegra_dpaux_driver = {
431 .driver = {
432 .name = "tegra-dpaux",
433 .of_match_table = tegra_dpaux_of_match,
434 },
435 .probe = tegra_dpaux_probe,
436 .remove = tegra_dpaux_remove,
437};
438
439struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
440{
441 struct tegra_dpaux *dpaux;
442
443 mutex_lock(&dpaux_lock);
444
445 list_for_each_entry(dpaux, &dpaux_list, list)
446 if (np == dpaux->dev->of_node) {
447 mutex_unlock(&dpaux_lock);
448 return &dpaux->aux;
449 }
450
451 mutex_unlock(&dpaux_lock);
452
453 return NULL;
454}
455
456int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
457{
458 struct tegra_dpaux *dpaux = to_dpaux(aux);
459 unsigned long timeout;
460 int err;
461
462 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
463 dpaux->output = output;
464
465 err = regulator_enable(dpaux->vdd);
466 if (err < 0)
467 return err;
468
469 timeout = jiffies + msecs_to_jiffies(250);
470
471 while (time_before(jiffies, timeout)) {
472 enum drm_connector_status status;
473
474 status = drm_dp_aux_detect(aux);
475 if (status == connector_status_connected) {
476 enable_irq(dpaux->irq);
477 return 0;
478 }
479
480 usleep_range(1000, 2000);
481 }
482
483 return -ETIMEDOUT;
484}
485
486int drm_dp_aux_detach(struct drm_dp_aux *aux)
487{
488 struct tegra_dpaux *dpaux = to_dpaux(aux);
489 unsigned long timeout;
490 int err;
491
492 disable_irq(dpaux->irq);
493
494 err = regulator_disable(dpaux->vdd);
495 if (err < 0)
496 return err;
497
498 timeout = jiffies + msecs_to_jiffies(250);
499
500 while (time_before(jiffies, timeout)) {
501 enum drm_connector_status status;
502
503 status = drm_dp_aux_detect(aux);
504 if (status == connector_status_disconnected) {
505 dpaux->output = NULL;
506 return 0;
507 }
508
509 usleep_range(1000, 2000);
510 }
511
512 return -ETIMEDOUT;
513}
514
515enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
516{
517 struct tegra_dpaux *dpaux = to_dpaux(aux);
518 u32 value;
519
520 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
521
522 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
523 return connector_status_connected;
524
525 return connector_status_disconnected;
526}
527
528int drm_dp_aux_enable(struct drm_dp_aux *aux)
529{
530 struct tegra_dpaux *dpaux = to_dpaux(aux);
531 u32 value;
532
533 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
534 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
535 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
536 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
537 DPAUX_HYBRID_PADCTL_MODE_AUX;
538 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
539
540 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
541 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
542 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
543
544 return 0;
545}
546
547int drm_dp_aux_disable(struct drm_dp_aux *aux)
548{
549 struct tegra_dpaux *dpaux = to_dpaux(aux);
550 u32 value;
551
552 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
553 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
554 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
555
556 return 0;
557}
558
559int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
560{
561 int err;
562
563 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
564 encoding);
565 if (err < 0)
566 return err;
567
568 return 0;
569}
570
571int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
572 u8 pattern)
573{
574 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
575 u8 status[DP_LINK_STATUS_SIZE], values[4];
576 unsigned int i;
577 int err;
578
579 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
580 if (err < 0)
581 return err;
582
583 if (tp == DP_TRAINING_PATTERN_DISABLE)
584 return 0;
585
586 for (i = 0; i < link->num_lanes; i++)
587 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
588 DP_TRAIN_PRE_EMPH_LEVEL_0 |
589 DP_TRAIN_MAX_SWING_REACHED |
590 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
591
592 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
593 link->num_lanes);
594 if (err < 0)
595 return err;
596
597 usleep_range(500, 1000);
598
599 err = drm_dp_dpcd_read_link_status(aux, status);
600 if (err < 0)
601 return err;
602
603 switch (tp) {
604 case DP_TRAINING_PATTERN_1:
605 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
606 return -EAGAIN;
607
608 break;
609
610 case DP_TRAINING_PATTERN_2:
611 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
612 return -EAGAIN;
613
614 break;
615
616 default:
617 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
618 return -EINVAL;
619 }
620
621 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
622 if (err < 0)
623 return err;
624
625 return 0;
626}