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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
71static void dce4_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99}
100
101static void dce5_crtc_load_lut(struct drm_crtc *crtc)
102{
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107
108 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
109
110 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
113 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
114 NI_GRPH_PRESCALE_BYPASS);
115 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
116 NI_OVL_PRESCALE_BYPASS);
117 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
120
121 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
122
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
126
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
130
131 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
133
134 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
135 for (i = 0; i < 256; i++) {
136 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
137 (radeon_crtc->lut_r[i] << 20) |
138 (radeon_crtc->lut_g[i] << 10) |
139 (radeon_crtc->lut_b[i] << 0));
140 }
141
142 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
147 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
150 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
153 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
158
159}
160
161static void legacy_crtc_load_lut(struct drm_crtc *crtc)
162{
163 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
164 struct drm_device *dev = crtc->dev;
165 struct radeon_device *rdev = dev->dev_private;
166 int i;
167 uint32_t dac2_cntl;
168
169 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
170 if (radeon_crtc->crtc_id == 0)
171 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
172 else
173 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
174 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
175
176 WREG8(RADEON_PALETTE_INDEX, 0);
177 for (i = 0; i < 256; i++) {
178 WREG32(RADEON_PALETTE_30_DATA,
179 (radeon_crtc->lut_r[i] << 20) |
180 (radeon_crtc->lut_g[i] << 10) |
181 (radeon_crtc->lut_b[i] << 0));
182 }
183}
184
185void radeon_crtc_load_lut(struct drm_crtc *crtc)
186{
187 struct drm_device *dev = crtc->dev;
188 struct radeon_device *rdev = dev->dev_private;
189
190 if (!crtc->enabled)
191 return;
192
193 if (ASIC_IS_DCE5(rdev))
194 dce5_crtc_load_lut(crtc);
195 else if (ASIC_IS_DCE4(rdev))
196 dce4_crtc_load_lut(crtc);
197 else if (ASIC_IS_AVIVO(rdev))
198 avivo_crtc_load_lut(crtc);
199 else
200 legacy_crtc_load_lut(crtc);
201}
202
203/** Sets the color ramps on behalf of fbcon */
204void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
205 u16 blue, int regno)
206{
207 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
208
209 radeon_crtc->lut_r[regno] = red >> 6;
210 radeon_crtc->lut_g[regno] = green >> 6;
211 radeon_crtc->lut_b[regno] = blue >> 6;
212}
213
214/** Gets the color ramps on behalf of fbcon */
215void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
216 u16 *blue, int regno)
217{
218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
219
220 *red = radeon_crtc->lut_r[regno] << 6;
221 *green = radeon_crtc->lut_g[regno] << 6;
222 *blue = radeon_crtc->lut_b[regno] << 6;
223}
224
225static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
226 u16 *blue, uint32_t start, uint32_t size)
227{
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 int end = (start + size > 256) ? 256 : start + size, i;
230
231 /* userspace palettes are always correct as is */
232 for (i = start; i < end; i++) {
233 radeon_crtc->lut_r[i] = red[i] >> 6;
234 radeon_crtc->lut_g[i] = green[i] >> 6;
235 radeon_crtc->lut_b[i] = blue[i] >> 6;
236 }
237 radeon_crtc_load_lut(crtc);
238}
239
240static void radeon_crtc_destroy(struct drm_crtc *crtc)
241{
242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
243
244 drm_crtc_cleanup(crtc);
245 kfree(radeon_crtc);
246}
247
248/*
249 * Handle unpin events outside the interrupt handler proper.
250 */
251static void radeon_unpin_work_func(struct work_struct *__work)
252{
253 struct radeon_unpin_work *work =
254 container_of(__work, struct radeon_unpin_work, work);
255 int r;
256
257 /* unpin of the old buffer */
258 r = radeon_bo_reserve(work->old_rbo, false);
259 if (likely(r == 0)) {
260 r = radeon_bo_unpin(work->old_rbo);
261 if (unlikely(r != 0)) {
262 DRM_ERROR("failed to unpin buffer after flip\n");
263 }
264 radeon_bo_unreserve(work->old_rbo);
265 } else
266 DRM_ERROR("failed to reserve buffer after flip\n");
267
268 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
269 kfree(work);
270}
271
272void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
273{
274 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
275 struct radeon_unpin_work *work;
276 struct drm_pending_vblank_event *e;
277 struct timeval now;
278 unsigned long flags;
279 u32 update_pending;
280 int vpos, hpos;
281
282 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
283 work = radeon_crtc->unpin_work;
284 if (work == NULL ||
285 (work->fence && !radeon_fence_signaled(work->fence))) {
286 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
287 return;
288 }
289 /* New pageflip, or just completion of a previous one? */
290 if (!radeon_crtc->deferred_flip_completion) {
291 /* do the flip (mmio) */
292 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
293 } else {
294 /* This is just a completion of a flip queued in crtc
295 * at last invocation. Make sure we go directly to
296 * completion routine.
297 */
298 update_pending = 0;
299 radeon_crtc->deferred_flip_completion = 0;
300 }
301
302 /* Has the pageflip already completed in crtc, or is it certain
303 * to complete in this vblank?
304 */
305 if (update_pending &&
306 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
307 &vpos, &hpos)) &&
308 (vpos >=0) &&
309 (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
310 /* crtc didn't flip in this target vblank interval,
311 * but flip is pending in crtc. It will complete it
312 * in next vblank interval, so complete the flip at
313 * next vblank irq.
314 */
315 radeon_crtc->deferred_flip_completion = 1;
316 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
317 return;
318 }
319
320 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
321 radeon_crtc->unpin_work = NULL;
322
323 /* wakeup userspace */
324 if (work->event) {
325 e = work->event;
326 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
327 e->event.tv_sec = now.tv_sec;
328 e->event.tv_usec = now.tv_usec;
329 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
330 wake_up_interruptible(&e->base.file_priv->event_wait);
331 }
332 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
333
334 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
335 radeon_fence_unref(&work->fence);
336 radeon_post_page_flip(work->rdev, work->crtc_id);
337 schedule_work(&work->work);
338}
339
340static int radeon_crtc_page_flip(struct drm_crtc *crtc,
341 struct drm_framebuffer *fb,
342 struct drm_pending_vblank_event *event)
343{
344 struct drm_device *dev = crtc->dev;
345 struct radeon_device *rdev = dev->dev_private;
346 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
347 struct radeon_framebuffer *old_radeon_fb;
348 struct radeon_framebuffer *new_radeon_fb;
349 struct drm_gem_object *obj;
350 struct radeon_bo *rbo;
351 struct radeon_unpin_work *work;
352 unsigned long flags;
353 u32 tiling_flags, pitch_pixels;
354 u64 base;
355 int r;
356
357 work = kzalloc(sizeof *work, GFP_KERNEL);
358 if (work == NULL)
359 return -ENOMEM;
360
361 work->event = event;
362 work->rdev = rdev;
363 work->crtc_id = radeon_crtc->crtc_id;
364 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
365 new_radeon_fb = to_radeon_framebuffer(fb);
366 /* schedule unpin of the old buffer */
367 obj = old_radeon_fb->obj;
368 /* take a reference to the old object */
369 drm_gem_object_reference(obj);
370 rbo = gem_to_radeon_bo(obj);
371 work->old_rbo = rbo;
372 obj = new_radeon_fb->obj;
373 rbo = gem_to_radeon_bo(obj);
374 if (rbo->tbo.sync_obj)
375 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
376 INIT_WORK(&work->work, radeon_unpin_work_func);
377
378 /* We borrow the event spin lock for protecting unpin_work */
379 spin_lock_irqsave(&dev->event_lock, flags);
380 if (radeon_crtc->unpin_work) {
381 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
382 r = -EBUSY;
383 goto unlock_free;
384 }
385 radeon_crtc->unpin_work = work;
386 radeon_crtc->deferred_flip_completion = 0;
387 spin_unlock_irqrestore(&dev->event_lock, flags);
388
389 /* pin the new buffer */
390 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
391 work->old_rbo, rbo);
392
393 r = radeon_bo_reserve(rbo, false);
394 if (unlikely(r != 0)) {
395 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
396 goto pflip_cleanup;
397 }
398 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
399 if (unlikely(r != 0)) {
400 radeon_bo_unreserve(rbo);
401 r = -EINVAL;
402 DRM_ERROR("failed to pin new rbo buffer before flip\n");
403 goto pflip_cleanup;
404 }
405 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
406 radeon_bo_unreserve(rbo);
407
408 if (!ASIC_IS_AVIVO(rdev)) {
409 /* crtc offset is from display base addr not FB location */
410 base -= radeon_crtc->legacy_display_base_addr;
411 pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
412
413 if (tiling_flags & RADEON_TILING_MACRO) {
414 if (ASIC_IS_R300(rdev)) {
415 base &= ~0x7ff;
416 } else {
417 int byteshift = fb->bits_per_pixel >> 4;
418 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
419 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
420 }
421 } else {
422 int offset = crtc->y * pitch_pixels + crtc->x;
423 switch (fb->bits_per_pixel) {
424 case 8:
425 default:
426 offset *= 1;
427 break;
428 case 15:
429 case 16:
430 offset *= 2;
431 break;
432 case 24:
433 offset *= 3;
434 break;
435 case 32:
436 offset *= 4;
437 break;
438 }
439 base += offset;
440 }
441 base &= ~7;
442 }
443
444 spin_lock_irqsave(&dev->event_lock, flags);
445 work->new_crtc_base = base;
446 spin_unlock_irqrestore(&dev->event_lock, flags);
447
448 /* update crtc fb */
449 crtc->fb = fb;
450
451 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
452 if (r) {
453 DRM_ERROR("failed to get vblank before flip\n");
454 goto pflip_cleanup1;
455 }
456
457 /* set the proper interrupt */
458 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
459
460 return 0;
461
462pflip_cleanup1:
463 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
464 DRM_ERROR("failed to reserve new rbo in error path\n");
465 goto pflip_cleanup;
466 }
467 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
468 DRM_ERROR("failed to unpin new rbo in error path\n");
469 }
470 radeon_bo_unreserve(rbo);
471
472pflip_cleanup:
473 spin_lock_irqsave(&dev->event_lock, flags);
474 radeon_crtc->unpin_work = NULL;
475unlock_free:
476 spin_unlock_irqrestore(&dev->event_lock, flags);
477 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
478 radeon_fence_unref(&work->fence);
479 kfree(work);
480
481 return r;
482}
483
484static const struct drm_crtc_funcs radeon_crtc_funcs = {
485 .cursor_set = radeon_crtc_cursor_set,
486 .cursor_move = radeon_crtc_cursor_move,
487 .gamma_set = radeon_crtc_gamma_set,
488 .set_config = drm_crtc_helper_set_config,
489 .destroy = radeon_crtc_destroy,
490 .page_flip = radeon_crtc_page_flip,
491};
492
493static void radeon_crtc_init(struct drm_device *dev, int index)
494{
495 struct radeon_device *rdev = dev->dev_private;
496 struct radeon_crtc *radeon_crtc;
497 int i;
498
499 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
500 if (radeon_crtc == NULL)
501 return;
502
503 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
504
505 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
506 radeon_crtc->crtc_id = index;
507 rdev->mode_info.crtcs[index] = radeon_crtc;
508
509#if 0
510 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
511 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
512 radeon_crtc->mode_set.num_connectors = 0;
513#endif
514
515 for (i = 0; i < 256; i++) {
516 radeon_crtc->lut_r[i] = i << 2;
517 radeon_crtc->lut_g[i] = i << 2;
518 radeon_crtc->lut_b[i] = i << 2;
519 }
520
521 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
522 radeon_atombios_init_crtc(dev, radeon_crtc);
523 else
524 radeon_legacy_init_crtc(dev, radeon_crtc);
525}
526
527static const char *encoder_names[36] = {
528 "NONE",
529 "INTERNAL_LVDS",
530 "INTERNAL_TMDS1",
531 "INTERNAL_TMDS2",
532 "INTERNAL_DAC1",
533 "INTERNAL_DAC2",
534 "INTERNAL_SDVOA",
535 "INTERNAL_SDVOB",
536 "SI170B",
537 "CH7303",
538 "CH7301",
539 "INTERNAL_DVO1",
540 "EXTERNAL_SDVOA",
541 "EXTERNAL_SDVOB",
542 "TITFP513",
543 "INTERNAL_LVTM1",
544 "VT1623",
545 "HDMI_SI1930",
546 "HDMI_INTERNAL",
547 "INTERNAL_KLDSCP_TMDS1",
548 "INTERNAL_KLDSCP_DVO1",
549 "INTERNAL_KLDSCP_DAC1",
550 "INTERNAL_KLDSCP_DAC2",
551 "SI178",
552 "MVPU_FPGA",
553 "INTERNAL_DDI",
554 "VT1625",
555 "HDMI_SI1932",
556 "DP_AN9801",
557 "DP_DP501",
558 "INTERNAL_UNIPHY",
559 "INTERNAL_KLDSCP_LVTMA",
560 "INTERNAL_UNIPHY1",
561 "INTERNAL_UNIPHY2",
562 "NUTMEG",
563 "TRAVIS",
564};
565
566static const char *connector_names[15] = {
567 "Unknown",
568 "VGA",
569 "DVI-I",
570 "DVI-D",
571 "DVI-A",
572 "Composite",
573 "S-video",
574 "LVDS",
575 "Component",
576 "DIN",
577 "DisplayPort",
578 "HDMI-A",
579 "HDMI-B",
580 "TV",
581 "eDP",
582};
583
584static const char *hpd_names[6] = {
585 "HPD1",
586 "HPD2",
587 "HPD3",
588 "HPD4",
589 "HPD5",
590 "HPD6",
591};
592
593static void radeon_print_display_setup(struct drm_device *dev)
594{
595 struct drm_connector *connector;
596 struct radeon_connector *radeon_connector;
597 struct drm_encoder *encoder;
598 struct radeon_encoder *radeon_encoder;
599 uint32_t devices;
600 int i = 0;
601
602 DRM_INFO("Radeon Display Connectors\n");
603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
604 radeon_connector = to_radeon_connector(connector);
605 DRM_INFO("Connector %d:\n", i);
606 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
607 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
608 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
609 if (radeon_connector->ddc_bus) {
610 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
611 radeon_connector->ddc_bus->rec.mask_clk_reg,
612 radeon_connector->ddc_bus->rec.mask_data_reg,
613 radeon_connector->ddc_bus->rec.a_clk_reg,
614 radeon_connector->ddc_bus->rec.a_data_reg,
615 radeon_connector->ddc_bus->rec.en_clk_reg,
616 radeon_connector->ddc_bus->rec.en_data_reg,
617 radeon_connector->ddc_bus->rec.y_clk_reg,
618 radeon_connector->ddc_bus->rec.y_data_reg);
619 if (radeon_connector->router.ddc_valid)
620 DRM_INFO(" DDC Router 0x%x/0x%x\n",
621 radeon_connector->router.ddc_mux_control_pin,
622 radeon_connector->router.ddc_mux_state);
623 if (radeon_connector->router.cd_valid)
624 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
625 radeon_connector->router.cd_mux_control_pin,
626 radeon_connector->router.cd_mux_state);
627 } else {
628 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
629 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
630 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
631 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
632 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
633 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
634 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
635 }
636 DRM_INFO(" Encoders:\n");
637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
638 radeon_encoder = to_radeon_encoder(encoder);
639 devices = radeon_encoder->devices & radeon_connector->devices;
640 if (devices) {
641 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
642 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
643 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
644 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
645 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
646 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
647 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
648 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
649 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
650 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
651 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
652 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
654 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
655 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
656 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
657 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
658 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 if (devices & ATOM_DEVICE_TV1_SUPPORT)
660 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
661 if (devices & ATOM_DEVICE_CV_SUPPORT)
662 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
663 }
664 }
665 i++;
666 }
667}
668
669static bool radeon_setup_enc_conn(struct drm_device *dev)
670{
671 struct radeon_device *rdev = dev->dev_private;
672 struct drm_connector *drm_connector;
673 bool ret = false;
674
675 if (rdev->bios) {
676 if (rdev->is_atom_bios) {
677 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
678 if (ret == false)
679 ret = radeon_get_atom_connector_info_from_object_table(dev);
680 } else {
681 ret = radeon_get_legacy_connector_info_from_bios(dev);
682 if (ret == false)
683 ret = radeon_get_legacy_connector_info_from_table(dev);
684 }
685 } else {
686 if (!ASIC_IS_AVIVO(rdev))
687 ret = radeon_get_legacy_connector_info_from_table(dev);
688 }
689 if (ret) {
690 radeon_setup_encoder_clones(dev);
691 radeon_print_display_setup(dev);
692 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
693 radeon_ddc_dump(drm_connector);
694 }
695
696 return ret;
697}
698
699int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
700{
701 struct drm_device *dev = radeon_connector->base.dev;
702 struct radeon_device *rdev = dev->dev_private;
703 int ret = 0;
704
705 /* on hw with routers, select right port */
706 if (radeon_connector->router.ddc_valid)
707 radeon_router_select_ddc_port(radeon_connector);
708
709 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
710 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
711 radeon_connector_encoder_is_dp_bridge(&radeon_connector->base)) {
712 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
713
714 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
715 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
716 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
717 &dig->dp_i2c_bus->adapter);
718 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
719 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
720 &radeon_connector->ddc_bus->adapter);
721 } else {
722 if (radeon_connector->ddc_bus && !radeon_connector->edid)
723 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
724 &radeon_connector->ddc_bus->adapter);
725 }
726
727 if (!radeon_connector->edid) {
728 if (rdev->is_atom_bios) {
729 /* some laptops provide a hardcoded edid in rom for LCDs */
730 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
731 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
732 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
733 } else
734 /* some servers provide a hardcoded edid in rom for KVMs */
735 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
736 }
737 if (radeon_connector->edid) {
738 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
739 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
740 return ret;
741 }
742 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
743 return 0;
744}
745
746static int radeon_ddc_dump(struct drm_connector *connector)
747{
748 struct edid *edid;
749 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
750 int ret = 0;
751
752 /* on hw with routers, select right port */
753 if (radeon_connector->router.ddc_valid)
754 radeon_router_select_ddc_port(radeon_connector);
755
756 if (!radeon_connector->ddc_bus)
757 return -1;
758 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
759 /* Log EDID retrieval status here. In particular with regard to
760 * connectors with requires_extended_probe flag set, that will prevent
761 * function radeon_dvi_detect() to fetch EDID on this connector,
762 * as long as there is no valid EDID header found */
763 if (edid) {
764 DRM_INFO("Radeon display connector %s: Found valid EDID",
765 drm_get_connector_name(connector));
766 kfree(edid);
767 } else {
768 DRM_INFO("Radeon display connector %s: No monitor connected or invalid EDID",
769 drm_get_connector_name(connector));
770 }
771 return ret;
772}
773
774/* avivo */
775static void avivo_get_fb_div(struct radeon_pll *pll,
776 u32 target_clock,
777 u32 post_div,
778 u32 ref_div,
779 u32 *fb_div,
780 u32 *frac_fb_div)
781{
782 u32 tmp = post_div * ref_div;
783
784 tmp *= target_clock;
785 *fb_div = tmp / pll->reference_freq;
786 *frac_fb_div = tmp % pll->reference_freq;
787
788 if (*fb_div > pll->max_feedback_div)
789 *fb_div = pll->max_feedback_div;
790 else if (*fb_div < pll->min_feedback_div)
791 *fb_div = pll->min_feedback_div;
792}
793
794static u32 avivo_get_post_div(struct radeon_pll *pll,
795 u32 target_clock)
796{
797 u32 vco, post_div, tmp;
798
799 if (pll->flags & RADEON_PLL_USE_POST_DIV)
800 return pll->post_div;
801
802 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
803 if (pll->flags & RADEON_PLL_IS_LCD)
804 vco = pll->lcd_pll_out_min;
805 else
806 vco = pll->pll_out_min;
807 } else {
808 if (pll->flags & RADEON_PLL_IS_LCD)
809 vco = pll->lcd_pll_out_max;
810 else
811 vco = pll->pll_out_max;
812 }
813
814 post_div = vco / target_clock;
815 tmp = vco % target_clock;
816
817 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
818 if (tmp)
819 post_div++;
820 } else {
821 if (!tmp)
822 post_div--;
823 }
824
825 if (post_div > pll->max_post_div)
826 post_div = pll->max_post_div;
827 else if (post_div < pll->min_post_div)
828 post_div = pll->min_post_div;
829
830 return post_div;
831}
832
833#define MAX_TOLERANCE 10
834
835void radeon_compute_pll_avivo(struct radeon_pll *pll,
836 u32 freq,
837 u32 *dot_clock_p,
838 u32 *fb_div_p,
839 u32 *frac_fb_div_p,
840 u32 *ref_div_p,
841 u32 *post_div_p)
842{
843 u32 target_clock = freq / 10;
844 u32 post_div = avivo_get_post_div(pll, target_clock);
845 u32 ref_div = pll->min_ref_div;
846 u32 fb_div = 0, frac_fb_div = 0, tmp;
847
848 if (pll->flags & RADEON_PLL_USE_REF_DIV)
849 ref_div = pll->reference_div;
850
851 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
852 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
853 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
854 if (frac_fb_div >= 5) {
855 frac_fb_div -= 5;
856 frac_fb_div = frac_fb_div / 10;
857 frac_fb_div++;
858 }
859 if (frac_fb_div >= 10) {
860 fb_div++;
861 frac_fb_div = 0;
862 }
863 } else {
864 while (ref_div <= pll->max_ref_div) {
865 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
866 &fb_div, &frac_fb_div);
867 if (frac_fb_div >= (pll->reference_freq / 2))
868 fb_div++;
869 frac_fb_div = 0;
870 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
871 tmp = (tmp * 10000) / target_clock;
872
873 if (tmp > (10000 + MAX_TOLERANCE))
874 ref_div++;
875 else if (tmp >= (10000 - MAX_TOLERANCE))
876 break;
877 else
878 ref_div++;
879 }
880 }
881
882 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
883 (ref_div * post_div * 10);
884 *fb_div_p = fb_div;
885 *frac_fb_div_p = frac_fb_div;
886 *ref_div_p = ref_div;
887 *post_div_p = post_div;
888 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
889 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
890}
891
892/* pre-avivo */
893static inline uint32_t radeon_div(uint64_t n, uint32_t d)
894{
895 uint64_t mod;
896
897 n += d / 2;
898
899 mod = do_div(n, d);
900 return n;
901}
902
903void radeon_compute_pll_legacy(struct radeon_pll *pll,
904 uint64_t freq,
905 uint32_t *dot_clock_p,
906 uint32_t *fb_div_p,
907 uint32_t *frac_fb_div_p,
908 uint32_t *ref_div_p,
909 uint32_t *post_div_p)
910{
911 uint32_t min_ref_div = pll->min_ref_div;
912 uint32_t max_ref_div = pll->max_ref_div;
913 uint32_t min_post_div = pll->min_post_div;
914 uint32_t max_post_div = pll->max_post_div;
915 uint32_t min_fractional_feed_div = 0;
916 uint32_t max_fractional_feed_div = 0;
917 uint32_t best_vco = pll->best_vco;
918 uint32_t best_post_div = 1;
919 uint32_t best_ref_div = 1;
920 uint32_t best_feedback_div = 1;
921 uint32_t best_frac_feedback_div = 0;
922 uint32_t best_freq = -1;
923 uint32_t best_error = 0xffffffff;
924 uint32_t best_vco_diff = 1;
925 uint32_t post_div;
926 u32 pll_out_min, pll_out_max;
927
928 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
929 freq = freq * 1000;
930
931 if (pll->flags & RADEON_PLL_IS_LCD) {
932 pll_out_min = pll->lcd_pll_out_min;
933 pll_out_max = pll->lcd_pll_out_max;
934 } else {
935 pll_out_min = pll->pll_out_min;
936 pll_out_max = pll->pll_out_max;
937 }
938
939 if (pll_out_min > 64800)
940 pll_out_min = 64800;
941
942 if (pll->flags & RADEON_PLL_USE_REF_DIV)
943 min_ref_div = max_ref_div = pll->reference_div;
944 else {
945 while (min_ref_div < max_ref_div-1) {
946 uint32_t mid = (min_ref_div + max_ref_div) / 2;
947 uint32_t pll_in = pll->reference_freq / mid;
948 if (pll_in < pll->pll_in_min)
949 max_ref_div = mid;
950 else if (pll_in > pll->pll_in_max)
951 min_ref_div = mid;
952 else
953 break;
954 }
955 }
956
957 if (pll->flags & RADEON_PLL_USE_POST_DIV)
958 min_post_div = max_post_div = pll->post_div;
959
960 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
961 min_fractional_feed_div = pll->min_frac_feedback_div;
962 max_fractional_feed_div = pll->max_frac_feedback_div;
963 }
964
965 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
966 uint32_t ref_div;
967
968 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
969 continue;
970
971 /* legacy radeons only have a few post_divs */
972 if (pll->flags & RADEON_PLL_LEGACY) {
973 if ((post_div == 5) ||
974 (post_div == 7) ||
975 (post_div == 9) ||
976 (post_div == 10) ||
977 (post_div == 11) ||
978 (post_div == 13) ||
979 (post_div == 14) ||
980 (post_div == 15))
981 continue;
982 }
983
984 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
985 uint32_t feedback_div, current_freq = 0, error, vco_diff;
986 uint32_t pll_in = pll->reference_freq / ref_div;
987 uint32_t min_feed_div = pll->min_feedback_div;
988 uint32_t max_feed_div = pll->max_feedback_div + 1;
989
990 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
991 continue;
992
993 while (min_feed_div < max_feed_div) {
994 uint32_t vco;
995 uint32_t min_frac_feed_div = min_fractional_feed_div;
996 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
997 uint32_t frac_feedback_div;
998 uint64_t tmp;
999
1000 feedback_div = (min_feed_div + max_feed_div) / 2;
1001
1002 tmp = (uint64_t)pll->reference_freq * feedback_div;
1003 vco = radeon_div(tmp, ref_div);
1004
1005 if (vco < pll_out_min) {
1006 min_feed_div = feedback_div + 1;
1007 continue;
1008 } else if (vco > pll_out_max) {
1009 max_feed_div = feedback_div;
1010 continue;
1011 }
1012
1013 while (min_frac_feed_div < max_frac_feed_div) {
1014 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1015 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1016 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1017 current_freq = radeon_div(tmp, ref_div * post_div);
1018
1019 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1020 if (freq < current_freq)
1021 error = 0xffffffff;
1022 else
1023 error = freq - current_freq;
1024 } else
1025 error = abs(current_freq - freq);
1026 vco_diff = abs(vco - best_vco);
1027
1028 if ((best_vco == 0 && error < best_error) ||
1029 (best_vco != 0 &&
1030 ((best_error > 100 && error < best_error - 100) ||
1031 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1032 best_post_div = post_div;
1033 best_ref_div = ref_div;
1034 best_feedback_div = feedback_div;
1035 best_frac_feedback_div = frac_feedback_div;
1036 best_freq = current_freq;
1037 best_error = error;
1038 best_vco_diff = vco_diff;
1039 } else if (current_freq == freq) {
1040 if (best_freq == -1) {
1041 best_post_div = post_div;
1042 best_ref_div = ref_div;
1043 best_feedback_div = feedback_div;
1044 best_frac_feedback_div = frac_feedback_div;
1045 best_freq = current_freq;
1046 best_error = error;
1047 best_vco_diff = vco_diff;
1048 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1049 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1050 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1051 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1052 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1053 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1054 best_post_div = post_div;
1055 best_ref_div = ref_div;
1056 best_feedback_div = feedback_div;
1057 best_frac_feedback_div = frac_feedback_div;
1058 best_freq = current_freq;
1059 best_error = error;
1060 best_vco_diff = vco_diff;
1061 }
1062 }
1063 if (current_freq < freq)
1064 min_frac_feed_div = frac_feedback_div + 1;
1065 else
1066 max_frac_feed_div = frac_feedback_div;
1067 }
1068 if (current_freq < freq)
1069 min_feed_div = feedback_div + 1;
1070 else
1071 max_feed_div = feedback_div;
1072 }
1073 }
1074 }
1075
1076 *dot_clock_p = best_freq / 10000;
1077 *fb_div_p = best_feedback_div;
1078 *frac_fb_div_p = best_frac_feedback_div;
1079 *ref_div_p = best_ref_div;
1080 *post_div_p = best_post_div;
1081 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1082 (long long)freq,
1083 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1084 best_ref_div, best_post_div);
1085
1086}
1087
1088static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1089{
1090 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1091
1092 if (radeon_fb->obj) {
1093 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1094 }
1095 drm_framebuffer_cleanup(fb);
1096 kfree(radeon_fb);
1097}
1098
1099static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1100 struct drm_file *file_priv,
1101 unsigned int *handle)
1102{
1103 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1104
1105 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1106}
1107
1108static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1109 .destroy = radeon_user_framebuffer_destroy,
1110 .create_handle = radeon_user_framebuffer_create_handle,
1111};
1112
1113void
1114radeon_framebuffer_init(struct drm_device *dev,
1115 struct radeon_framebuffer *rfb,
1116 struct drm_mode_fb_cmd *mode_cmd,
1117 struct drm_gem_object *obj)
1118{
1119 rfb->obj = obj;
1120 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1121 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1122}
1123
1124static struct drm_framebuffer *
1125radeon_user_framebuffer_create(struct drm_device *dev,
1126 struct drm_file *file_priv,
1127 struct drm_mode_fb_cmd *mode_cmd)
1128{
1129 struct drm_gem_object *obj;
1130 struct radeon_framebuffer *radeon_fb;
1131
1132 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
1133 if (obj == NULL) {
1134 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1135 "can't create framebuffer\n", mode_cmd->handle);
1136 return ERR_PTR(-ENOENT);
1137 }
1138
1139 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1140 if (radeon_fb == NULL)
1141 return ERR_PTR(-ENOMEM);
1142
1143 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1144
1145 return &radeon_fb->base;
1146}
1147
1148static void radeon_output_poll_changed(struct drm_device *dev)
1149{
1150 struct radeon_device *rdev = dev->dev_private;
1151 radeon_fb_output_poll_changed(rdev);
1152}
1153
1154static const struct drm_mode_config_funcs radeon_mode_funcs = {
1155 .fb_create = radeon_user_framebuffer_create,
1156 .output_poll_changed = radeon_output_poll_changed
1157};
1158
1159struct drm_prop_enum_list {
1160 int type;
1161 char *name;
1162};
1163
1164static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1165{ { 0, "driver" },
1166 { 1, "bios" },
1167};
1168
1169static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1170{ { TV_STD_NTSC, "ntsc" },
1171 { TV_STD_PAL, "pal" },
1172 { TV_STD_PAL_M, "pal-m" },
1173 { TV_STD_PAL_60, "pal-60" },
1174 { TV_STD_NTSC_J, "ntsc-j" },
1175 { TV_STD_SCART_PAL, "scart-pal" },
1176 { TV_STD_PAL_CN, "pal-cn" },
1177 { TV_STD_SECAM, "secam" },
1178};
1179
1180static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1181{ { UNDERSCAN_OFF, "off" },
1182 { UNDERSCAN_ON, "on" },
1183 { UNDERSCAN_AUTO, "auto" },
1184};
1185
1186static int radeon_modeset_create_props(struct radeon_device *rdev)
1187{
1188 int i, sz;
1189
1190 if (rdev->is_atom_bios) {
1191 rdev->mode_info.coherent_mode_property =
1192 drm_property_create(rdev->ddev,
1193 DRM_MODE_PROP_RANGE,
1194 "coherent", 2);
1195 if (!rdev->mode_info.coherent_mode_property)
1196 return -ENOMEM;
1197
1198 rdev->mode_info.coherent_mode_property->values[0] = 0;
1199 rdev->mode_info.coherent_mode_property->values[1] = 1;
1200 }
1201
1202 if (!ASIC_IS_AVIVO(rdev)) {
1203 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1204 rdev->mode_info.tmds_pll_property =
1205 drm_property_create(rdev->ddev,
1206 DRM_MODE_PROP_ENUM,
1207 "tmds_pll", sz);
1208 for (i = 0; i < sz; i++) {
1209 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1210 i,
1211 radeon_tmds_pll_enum_list[i].type,
1212 radeon_tmds_pll_enum_list[i].name);
1213 }
1214 }
1215
1216 rdev->mode_info.load_detect_property =
1217 drm_property_create(rdev->ddev,
1218 DRM_MODE_PROP_RANGE,
1219 "load detection", 2);
1220 if (!rdev->mode_info.load_detect_property)
1221 return -ENOMEM;
1222 rdev->mode_info.load_detect_property->values[0] = 0;
1223 rdev->mode_info.load_detect_property->values[1] = 1;
1224
1225 drm_mode_create_scaling_mode_property(rdev->ddev);
1226
1227 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1228 rdev->mode_info.tv_std_property =
1229 drm_property_create(rdev->ddev,
1230 DRM_MODE_PROP_ENUM,
1231 "tv standard", sz);
1232 for (i = 0; i < sz; i++) {
1233 drm_property_add_enum(rdev->mode_info.tv_std_property,
1234 i,
1235 radeon_tv_std_enum_list[i].type,
1236 radeon_tv_std_enum_list[i].name);
1237 }
1238
1239 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1240 rdev->mode_info.underscan_property =
1241 drm_property_create(rdev->ddev,
1242 DRM_MODE_PROP_ENUM,
1243 "underscan", sz);
1244 for (i = 0; i < sz; i++) {
1245 drm_property_add_enum(rdev->mode_info.underscan_property,
1246 i,
1247 radeon_underscan_enum_list[i].type,
1248 radeon_underscan_enum_list[i].name);
1249 }
1250
1251 rdev->mode_info.underscan_hborder_property =
1252 drm_property_create(rdev->ddev,
1253 DRM_MODE_PROP_RANGE,
1254 "underscan hborder", 2);
1255 if (!rdev->mode_info.underscan_hborder_property)
1256 return -ENOMEM;
1257 rdev->mode_info.underscan_hborder_property->values[0] = 0;
1258 rdev->mode_info.underscan_hborder_property->values[1] = 128;
1259
1260 rdev->mode_info.underscan_vborder_property =
1261 drm_property_create(rdev->ddev,
1262 DRM_MODE_PROP_RANGE,
1263 "underscan vborder", 2);
1264 if (!rdev->mode_info.underscan_vborder_property)
1265 return -ENOMEM;
1266 rdev->mode_info.underscan_vborder_property->values[0] = 0;
1267 rdev->mode_info.underscan_vborder_property->values[1] = 128;
1268
1269 return 0;
1270}
1271
1272void radeon_update_display_priority(struct radeon_device *rdev)
1273{
1274 /* adjustment options for the display watermarks */
1275 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1276 /* set display priority to high for r3xx, rv515 chips
1277 * this avoids flickering due to underflow to the
1278 * display controllers during heavy acceleration.
1279 * Don't force high on rs4xx igp chips as it seems to
1280 * affect the sound card. See kernel bug 15982.
1281 */
1282 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1283 !(rdev->flags & RADEON_IS_IGP))
1284 rdev->disp_priority = 2;
1285 else
1286 rdev->disp_priority = 0;
1287 } else
1288 rdev->disp_priority = radeon_disp_priority;
1289
1290}
1291
1292int radeon_modeset_init(struct radeon_device *rdev)
1293{
1294 int i;
1295 int ret;
1296
1297 drm_mode_config_init(rdev->ddev);
1298 rdev->mode_info.mode_config_initialized = true;
1299
1300 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1301
1302 if (ASIC_IS_DCE5(rdev)) {
1303 rdev->ddev->mode_config.max_width = 16384;
1304 rdev->ddev->mode_config.max_height = 16384;
1305 } else if (ASIC_IS_AVIVO(rdev)) {
1306 rdev->ddev->mode_config.max_width = 8192;
1307 rdev->ddev->mode_config.max_height = 8192;
1308 } else {
1309 rdev->ddev->mode_config.max_width = 4096;
1310 rdev->ddev->mode_config.max_height = 4096;
1311 }
1312
1313 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1314
1315 ret = radeon_modeset_create_props(rdev);
1316 if (ret) {
1317 return ret;
1318 }
1319
1320 /* init i2c buses */
1321 radeon_i2c_init(rdev);
1322
1323 /* check combios for a valid hardcoded EDID - Sun servers */
1324 if (!rdev->is_atom_bios) {
1325 /* check for hardcoded EDID in BIOS */
1326 radeon_combios_check_hardcoded_edid(rdev);
1327 }
1328
1329 /* allocate crtcs */
1330 for (i = 0; i < rdev->num_crtc; i++) {
1331 radeon_crtc_init(rdev->ddev, i);
1332 }
1333
1334 /* okay we should have all the bios connectors */
1335 ret = radeon_setup_enc_conn(rdev->ddev);
1336 if (!ret) {
1337 return ret;
1338 }
1339
1340 /* init dig PHYs */
1341 if (rdev->is_atom_bios)
1342 radeon_atom_encoder_init(rdev);
1343
1344 /* initialize hpd */
1345 radeon_hpd_init(rdev);
1346
1347 /* Initialize power management */
1348 radeon_pm_init(rdev);
1349
1350 radeon_fbdev_init(rdev);
1351 drm_kms_helper_poll_init(rdev->ddev);
1352
1353 return 0;
1354}
1355
1356void radeon_modeset_fini(struct radeon_device *rdev)
1357{
1358 radeon_fbdev_fini(rdev);
1359 kfree(rdev->mode_info.bios_hardcoded_edid);
1360 radeon_pm_fini(rdev);
1361
1362 if (rdev->mode_info.mode_config_initialized) {
1363 drm_kms_helper_poll_fini(rdev->ddev);
1364 radeon_hpd_fini(rdev);
1365 drm_mode_config_cleanup(rdev->ddev);
1366 rdev->mode_info.mode_config_initialized = false;
1367 }
1368 /* free i2c buses */
1369 radeon_i2c_fini(rdev);
1370}
1371
1372static bool is_hdtv_mode(struct drm_display_mode *mode)
1373{
1374 /* try and guess if this is a tv or a monitor */
1375 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1376 (mode->vdisplay == 576) || /* 576p */
1377 (mode->vdisplay == 720) || /* 720p */
1378 (mode->vdisplay == 1080)) /* 1080p */
1379 return true;
1380 else
1381 return false;
1382}
1383
1384bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1385 struct drm_display_mode *mode,
1386 struct drm_display_mode *adjusted_mode)
1387{
1388 struct drm_device *dev = crtc->dev;
1389 struct radeon_device *rdev = dev->dev_private;
1390 struct drm_encoder *encoder;
1391 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1392 struct radeon_encoder *radeon_encoder;
1393 struct drm_connector *connector;
1394 struct radeon_connector *radeon_connector;
1395 bool first = true;
1396 u32 src_v = 1, dst_v = 1;
1397 u32 src_h = 1, dst_h = 1;
1398
1399 radeon_crtc->h_border = 0;
1400 radeon_crtc->v_border = 0;
1401
1402 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1403 if (encoder->crtc != crtc)
1404 continue;
1405 radeon_encoder = to_radeon_encoder(encoder);
1406 connector = radeon_get_connector_for_encoder(encoder);
1407 radeon_connector = to_radeon_connector(connector);
1408
1409 if (first) {
1410 /* set scaling */
1411 if (radeon_encoder->rmx_type == RMX_OFF)
1412 radeon_crtc->rmx_type = RMX_OFF;
1413 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1414 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1415 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1416 else
1417 radeon_crtc->rmx_type = RMX_OFF;
1418 /* copy native mode */
1419 memcpy(&radeon_crtc->native_mode,
1420 &radeon_encoder->native_mode,
1421 sizeof(struct drm_display_mode));
1422 src_v = crtc->mode.vdisplay;
1423 dst_v = radeon_crtc->native_mode.vdisplay;
1424 src_h = crtc->mode.hdisplay;
1425 dst_h = radeon_crtc->native_mode.hdisplay;
1426
1427 /* fix up for overscan on hdmi */
1428 if (ASIC_IS_AVIVO(rdev) &&
1429 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1430 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1431 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1432 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1433 is_hdtv_mode(mode)))) {
1434 if (radeon_encoder->underscan_hborder != 0)
1435 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1436 else
1437 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1438 if (radeon_encoder->underscan_vborder != 0)
1439 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1440 else
1441 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1442 radeon_crtc->rmx_type = RMX_FULL;
1443 src_v = crtc->mode.vdisplay;
1444 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1445 src_h = crtc->mode.hdisplay;
1446 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1447 }
1448 first = false;
1449 } else {
1450 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1451 /* WARNING: Right now this can't happen but
1452 * in the future we need to check that scaling
1453 * are consistent across different encoder
1454 * (ie all encoder can work with the same
1455 * scaling).
1456 */
1457 DRM_ERROR("Scaling not consistent across encoder.\n");
1458 return false;
1459 }
1460 }
1461 }
1462 if (radeon_crtc->rmx_type != RMX_OFF) {
1463 fixed20_12 a, b;
1464 a.full = dfixed_const(src_v);
1465 b.full = dfixed_const(dst_v);
1466 radeon_crtc->vsc.full = dfixed_div(a, b);
1467 a.full = dfixed_const(src_h);
1468 b.full = dfixed_const(dst_h);
1469 radeon_crtc->hsc.full = dfixed_div(a, b);
1470 } else {
1471 radeon_crtc->vsc.full = dfixed_const(1);
1472 radeon_crtc->hsc.full = dfixed_const(1);
1473 }
1474 return true;
1475}
1476
1477/*
1478 * Retrieve current video scanout position of crtc on a given gpu.
1479 *
1480 * \param dev Device to query.
1481 * \param crtc Crtc to query.
1482 * \param *vpos Location where vertical scanout position should be stored.
1483 * \param *hpos Location where horizontal scanout position should go.
1484 *
1485 * Returns vpos as a positive number while in active scanout area.
1486 * Returns vpos as a negative number inside vblank, counting the number
1487 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1488 * until start of active scanout / end of vblank."
1489 *
1490 * \return Flags, or'ed together as follows:
1491 *
1492 * DRM_SCANOUTPOS_VALID = Query successful.
1493 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1494 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1495 * this flag means that returned position may be offset by a constant but
1496 * unknown small number of scanlines wrt. real scanout position.
1497 *
1498 */
1499int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1500{
1501 u32 stat_crtc = 0, vbl = 0, position = 0;
1502 int vbl_start, vbl_end, vtotal, ret = 0;
1503 bool in_vbl = true;
1504
1505 struct radeon_device *rdev = dev->dev_private;
1506
1507 if (ASIC_IS_DCE4(rdev)) {
1508 if (crtc == 0) {
1509 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1510 EVERGREEN_CRTC0_REGISTER_OFFSET);
1511 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1512 EVERGREEN_CRTC0_REGISTER_OFFSET);
1513 ret |= DRM_SCANOUTPOS_VALID;
1514 }
1515 if (crtc == 1) {
1516 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1517 EVERGREEN_CRTC1_REGISTER_OFFSET);
1518 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1519 EVERGREEN_CRTC1_REGISTER_OFFSET);
1520 ret |= DRM_SCANOUTPOS_VALID;
1521 }
1522 if (crtc == 2) {
1523 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1524 EVERGREEN_CRTC2_REGISTER_OFFSET);
1525 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1526 EVERGREEN_CRTC2_REGISTER_OFFSET);
1527 ret |= DRM_SCANOUTPOS_VALID;
1528 }
1529 if (crtc == 3) {
1530 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1531 EVERGREEN_CRTC3_REGISTER_OFFSET);
1532 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1533 EVERGREEN_CRTC3_REGISTER_OFFSET);
1534 ret |= DRM_SCANOUTPOS_VALID;
1535 }
1536 if (crtc == 4) {
1537 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1538 EVERGREEN_CRTC4_REGISTER_OFFSET);
1539 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1540 EVERGREEN_CRTC4_REGISTER_OFFSET);
1541 ret |= DRM_SCANOUTPOS_VALID;
1542 }
1543 if (crtc == 5) {
1544 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1545 EVERGREEN_CRTC5_REGISTER_OFFSET);
1546 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1547 EVERGREEN_CRTC5_REGISTER_OFFSET);
1548 ret |= DRM_SCANOUTPOS_VALID;
1549 }
1550 } else if (ASIC_IS_AVIVO(rdev)) {
1551 if (crtc == 0) {
1552 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1553 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1554 ret |= DRM_SCANOUTPOS_VALID;
1555 }
1556 if (crtc == 1) {
1557 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1558 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1559 ret |= DRM_SCANOUTPOS_VALID;
1560 }
1561 } else {
1562 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1563 if (crtc == 0) {
1564 /* Assume vbl_end == 0, get vbl_start from
1565 * upper 16 bits.
1566 */
1567 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1568 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1569 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1570 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1571 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1572 if (!(stat_crtc & 1))
1573 in_vbl = false;
1574
1575 ret |= DRM_SCANOUTPOS_VALID;
1576 }
1577 if (crtc == 1) {
1578 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1579 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1580 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1581 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1582 if (!(stat_crtc & 1))
1583 in_vbl = false;
1584
1585 ret |= DRM_SCANOUTPOS_VALID;
1586 }
1587 }
1588
1589 /* Decode into vertical and horizontal scanout position. */
1590 *vpos = position & 0x1fff;
1591 *hpos = (position >> 16) & 0x1fff;
1592
1593 /* Valid vblank area boundaries from gpu retrieved? */
1594 if (vbl > 0) {
1595 /* Yes: Decode. */
1596 ret |= DRM_SCANOUTPOS_ACCURATE;
1597 vbl_start = vbl & 0x1fff;
1598 vbl_end = (vbl >> 16) & 0x1fff;
1599 }
1600 else {
1601 /* No: Fake something reasonable which gives at least ok results. */
1602 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1603 vbl_end = 0;
1604 }
1605
1606 /* Test scanout position against vblank region. */
1607 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1608 in_vbl = false;
1609
1610 /* Check if inside vblank area and apply corrective offsets:
1611 * vpos will then be >=0 in video scanout area, but negative
1612 * within vblank area, counting down the number of lines until
1613 * start of scanout.
1614 */
1615
1616 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1617 if (in_vbl && (*vpos >= vbl_start)) {
1618 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1619 *vpos = *vpos - vtotal;
1620 }
1621
1622 /* Correct for shifted end of vbl at vbl_end. */
1623 *vpos = *vpos - vbl_end;
1624
1625 /* In vblank? */
1626 if (in_vbl)
1627 ret |= DRM_SCANOUTPOS_INVBL;
1628
1629 return ret;
1630}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <linux/pm_runtime.h>
28#include <linux/gcd.h>
29
30#include <asm/div64.h>
31
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_device.h>
34#include <drm/drm_drv.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_fb_helper.h>
37#include <drm/drm_fourcc.h>
38#include <drm/drm_gem_framebuffer_helper.h>
39#include <drm/drm_pci.h>
40#include <drm/drm_plane_helper.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_vblank.h>
43#include <drm/radeon_drm.h>
44
45#include "atom.h"
46#include "radeon.h"
47
48static void avivo_crtc_load_lut(struct drm_crtc *crtc)
49{
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51 struct drm_device *dev = crtc->dev;
52 struct radeon_device *rdev = dev->dev_private;
53 u16 *r, *g, *b;
54 int i;
55
56 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
58
59 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
62
63 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
64 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
66
67 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
68 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
69 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
70
71 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
72 r = crtc->gamma_store;
73 g = r + crtc->gamma_size;
74 b = g + crtc->gamma_size;
75 for (i = 0; i < 256; i++) {
76 WREG32(AVIVO_DC_LUT_30_COLOR,
77 ((*r++ & 0xffc0) << 14) |
78 ((*g++ & 0xffc0) << 4) |
79 (*b++ >> 6));
80 }
81
82 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
83 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
84}
85
86static void dce4_crtc_load_lut(struct drm_crtc *crtc)
87{
88 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
89 struct drm_device *dev = crtc->dev;
90 struct radeon_device *rdev = dev->dev_private;
91 u16 *r, *g, *b;
92 int i;
93
94 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
95 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
96
97 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
98 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
99 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
100
101 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
102 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
103 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
104
105 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
106 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
107
108 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
109 r = crtc->gamma_store;
110 g = r + crtc->gamma_size;
111 b = g + crtc->gamma_size;
112 for (i = 0; i < 256; i++) {
113 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
114 ((*r++ & 0xffc0) << 14) |
115 ((*g++ & 0xffc0) << 4) |
116 (*b++ >> 6));
117 }
118}
119
120static void dce5_crtc_load_lut(struct drm_crtc *crtc)
121{
122 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
123 struct drm_device *dev = crtc->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 u16 *r, *g, *b;
126 int i;
127
128 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
129
130 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
131 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
132 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
133 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
134 NI_GRPH_PRESCALE_BYPASS);
135 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
136 NI_OVL_PRESCALE_BYPASS);
137 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
138 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
139 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
140
141 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
142
143 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
144 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
145 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
146
147 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
148 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
149 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
150
151 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
152 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
153
154 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
155 r = crtc->gamma_store;
156 g = r + crtc->gamma_size;
157 b = g + crtc->gamma_size;
158 for (i = 0; i < 256; i++) {
159 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
160 ((*r++ & 0xffc0) << 14) |
161 ((*g++ & 0xffc0) << 4) |
162 (*b++ >> 6));
163 }
164
165 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
166 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
167 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
168 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
169 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
170 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
171 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
172 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
173 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
174 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
175 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
176 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
177 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
178 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
179 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
180 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
181 if (ASIC_IS_DCE8(rdev)) {
182 /* XXX this only needs to be programmed once per crtc at startup,
183 * not sure where the best place for it is
184 */
185 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
186 CIK_CURSOR_ALPHA_BLND_ENA);
187 }
188}
189
190static void legacy_crtc_load_lut(struct drm_crtc *crtc)
191{
192 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
193 struct drm_device *dev = crtc->dev;
194 struct radeon_device *rdev = dev->dev_private;
195 u16 *r, *g, *b;
196 int i;
197 uint32_t dac2_cntl;
198
199 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
200 if (radeon_crtc->crtc_id == 0)
201 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
202 else
203 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
204 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
205
206 WREG8(RADEON_PALETTE_INDEX, 0);
207 r = crtc->gamma_store;
208 g = r + crtc->gamma_size;
209 b = g + crtc->gamma_size;
210 for (i = 0; i < 256; i++) {
211 WREG32(RADEON_PALETTE_30_DATA,
212 ((*r++ & 0xffc0) << 14) |
213 ((*g++ & 0xffc0) << 4) |
214 (*b++ >> 6));
215 }
216}
217
218void radeon_crtc_load_lut(struct drm_crtc *crtc)
219{
220 struct drm_device *dev = crtc->dev;
221 struct radeon_device *rdev = dev->dev_private;
222
223 if (!crtc->enabled)
224 return;
225
226 if (ASIC_IS_DCE5(rdev))
227 dce5_crtc_load_lut(crtc);
228 else if (ASIC_IS_DCE4(rdev))
229 dce4_crtc_load_lut(crtc);
230 else if (ASIC_IS_AVIVO(rdev))
231 avivo_crtc_load_lut(crtc);
232 else
233 legacy_crtc_load_lut(crtc);
234}
235
236static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
237 u16 *blue, uint32_t size,
238 struct drm_modeset_acquire_ctx *ctx)
239{
240 radeon_crtc_load_lut(crtc);
241
242 return 0;
243}
244
245static void radeon_crtc_destroy(struct drm_crtc *crtc)
246{
247 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
248
249 drm_crtc_cleanup(crtc);
250 destroy_workqueue(radeon_crtc->flip_queue);
251 kfree(radeon_crtc);
252}
253
254/**
255 * radeon_unpin_work_func - unpin old buffer object
256 *
257 * @__work - kernel work item
258 *
259 * Unpin the old frame buffer object outside of the interrupt handler
260 */
261static void radeon_unpin_work_func(struct work_struct *__work)
262{
263 struct radeon_flip_work *work =
264 container_of(__work, struct radeon_flip_work, unpin_work);
265 int r;
266
267 /* unpin of the old buffer */
268 r = radeon_bo_reserve(work->old_rbo, false);
269 if (likely(r == 0)) {
270 r = radeon_bo_unpin(work->old_rbo);
271 if (unlikely(r != 0)) {
272 DRM_ERROR("failed to unpin buffer after flip\n");
273 }
274 radeon_bo_unreserve(work->old_rbo);
275 } else
276 DRM_ERROR("failed to reserve buffer after flip\n");
277
278 drm_gem_object_put_unlocked(&work->old_rbo->tbo.base);
279 kfree(work);
280}
281
282void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
283{
284 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
285 unsigned long flags;
286 u32 update_pending;
287 int vpos, hpos;
288
289 /* can happen during initialization */
290 if (radeon_crtc == NULL)
291 return;
292
293 /* Skip the pageflip completion check below (based on polling) on
294 * asics which reliably support hw pageflip completion irqs. pflip
295 * irqs are a reliable and race-free method of handling pageflip
296 * completion detection. A use_pflipirq module parameter < 2 allows
297 * to override this in case of asics with faulty pflip irqs.
298 * A module parameter of 0 would only use this polling based path,
299 * a parameter of 1 would use pflip irq only as a backup to this
300 * path, as in Linux 3.16.
301 */
302 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
303 return;
304
305 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
306 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
307 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
308 "RADEON_FLIP_SUBMITTED(%d)\n",
309 radeon_crtc->flip_status,
310 RADEON_FLIP_SUBMITTED);
311 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
312 return;
313 }
314
315 update_pending = radeon_page_flip_pending(rdev, crtc_id);
316
317 /* Has the pageflip already completed in crtc, or is it certain
318 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
319 * distance to start of "fudged earlier" vblank in vpos, distance to
320 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
321 * the last few scanlines before start of real vblank, where the vblank
322 * irq can fire, so we have sampled update_pending a bit too early and
323 * know the flip will complete at leading edge of the upcoming real
324 * vblank. On pre-AVIVO hardware, flips also complete inside the real
325 * vblank, not only at leading edge, so if update_pending for hpos >= 0
326 * == inside real vblank, the flip will complete almost immediately.
327 * Note that this method of completion handling is still not 100% race
328 * free, as we could execute before the radeon_flip_work_func managed
329 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
330 * but the flip still gets programmed into hw and completed during
331 * vblank, leading to a delayed emission of the flip completion event.
332 * This applies at least to pre-AVIVO hardware, where flips are always
333 * completing inside vblank, not only at leading edge of vblank.
334 */
335 if (update_pending &&
336 (DRM_SCANOUTPOS_VALID &
337 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
338 GET_DISTANCE_TO_VBLANKSTART,
339 &vpos, &hpos, NULL, NULL,
340 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
341 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
342 /* crtc didn't flip in this target vblank interval,
343 * but flip is pending in crtc. Based on the current
344 * scanout position we know that the current frame is
345 * (nearly) complete and the flip will (likely)
346 * complete before the start of the next frame.
347 */
348 update_pending = 0;
349 }
350 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
351 if (!update_pending)
352 radeon_crtc_handle_flip(rdev, crtc_id);
353}
354
355/**
356 * radeon_crtc_handle_flip - page flip completed
357 *
358 * @rdev: radeon device pointer
359 * @crtc_id: crtc number this event is for
360 *
361 * Called when we are sure that a page flip for this crtc is completed.
362 */
363void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
364{
365 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
366 struct radeon_flip_work *work;
367 unsigned long flags;
368
369 /* this can happen at init */
370 if (radeon_crtc == NULL)
371 return;
372
373 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
374 work = radeon_crtc->flip_work;
375 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
376 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
377 "RADEON_FLIP_SUBMITTED(%d)\n",
378 radeon_crtc->flip_status,
379 RADEON_FLIP_SUBMITTED);
380 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
381 return;
382 }
383
384 /* Pageflip completed. Clean up. */
385 radeon_crtc->flip_status = RADEON_FLIP_NONE;
386 radeon_crtc->flip_work = NULL;
387
388 /* wakeup userspace */
389 if (work->event)
390 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
391
392 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
393
394 drm_crtc_vblank_put(&radeon_crtc->base);
395 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
396 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
397}
398
399/**
400 * radeon_flip_work_func - page flip framebuffer
401 *
402 * @work - kernel work item
403 *
404 * Wait for the buffer object to become idle and do the actual page flip
405 */
406static void radeon_flip_work_func(struct work_struct *__work)
407{
408 struct radeon_flip_work *work =
409 container_of(__work, struct radeon_flip_work, flip_work);
410 struct radeon_device *rdev = work->rdev;
411 struct drm_device *dev = rdev->ddev;
412 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
413
414 struct drm_crtc *crtc = &radeon_crtc->base;
415 unsigned long flags;
416 int r;
417 int vpos, hpos;
418
419 down_read(&rdev->exclusive_lock);
420 if (work->fence) {
421 struct radeon_fence *fence;
422
423 fence = to_radeon_fence(work->fence);
424 if (fence && fence->rdev == rdev) {
425 r = radeon_fence_wait(fence, false);
426 if (r == -EDEADLK) {
427 up_read(&rdev->exclusive_lock);
428 do {
429 r = radeon_gpu_reset(rdev);
430 } while (r == -EAGAIN);
431 down_read(&rdev->exclusive_lock);
432 }
433 } else
434 r = dma_fence_wait(work->fence, false);
435
436 if (r)
437 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
438
439 /* We continue with the page flip even if we failed to wait on
440 * the fence, otherwise the DRM core and userspace will be
441 * confused about which BO the CRTC is scanning out
442 */
443
444 dma_fence_put(work->fence);
445 work->fence = NULL;
446 }
447
448 /* Wait until we're out of the vertical blank period before the one
449 * targeted by the flip. Always wait on pre DCE4 to avoid races with
450 * flip completion handling from vblank irq, as these old asics don't
451 * have reliable pageflip completion interrupts.
452 */
453 while (radeon_crtc->enabled &&
454 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
455 &vpos, &hpos, NULL, NULL,
456 &crtc->hwmode)
457 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
458 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
459 (!ASIC_IS_AVIVO(rdev) ||
460 ((int) (work->target_vblank -
461 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)))
462 usleep_range(1000, 2000);
463
464 /* We borrow the event spin lock for protecting flip_status */
465 spin_lock_irqsave(&crtc->dev->event_lock, flags);
466
467 /* set the proper interrupt */
468 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
469
470 /* do the flip (mmio) */
471 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
472
473 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
474 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
475 up_read(&rdev->exclusive_lock);
476}
477
478static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
479 struct drm_framebuffer *fb,
480 struct drm_pending_vblank_event *event,
481 uint32_t page_flip_flags,
482 uint32_t target,
483 struct drm_modeset_acquire_ctx *ctx)
484{
485 struct drm_device *dev = crtc->dev;
486 struct radeon_device *rdev = dev->dev_private;
487 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
488 struct drm_gem_object *obj;
489 struct radeon_flip_work *work;
490 struct radeon_bo *new_rbo;
491 uint32_t tiling_flags, pitch_pixels;
492 uint64_t base;
493 unsigned long flags;
494 int r;
495
496 work = kzalloc(sizeof *work, GFP_KERNEL);
497 if (work == NULL)
498 return -ENOMEM;
499
500 INIT_WORK(&work->flip_work, radeon_flip_work_func);
501 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
502
503 work->rdev = rdev;
504 work->crtc_id = radeon_crtc->crtc_id;
505 work->event = event;
506 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
507
508 /* schedule unpin of the old buffer */
509 obj = crtc->primary->fb->obj[0];
510
511 /* take a reference to the old object */
512 drm_gem_object_get(obj);
513 work->old_rbo = gem_to_radeon_bo(obj);
514
515 obj = fb->obj[0];
516 new_rbo = gem_to_radeon_bo(obj);
517
518 /* pin the new buffer */
519 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
520 work->old_rbo, new_rbo);
521
522 r = radeon_bo_reserve(new_rbo, false);
523 if (unlikely(r != 0)) {
524 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
525 goto cleanup;
526 }
527 /* Only 27 bit offset for legacy CRTC */
528 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
529 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
530 if (unlikely(r != 0)) {
531 radeon_bo_unreserve(new_rbo);
532 r = -EINVAL;
533 DRM_ERROR("failed to pin new rbo buffer before flip\n");
534 goto cleanup;
535 }
536 work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv));
537 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
538 radeon_bo_unreserve(new_rbo);
539
540 if (!ASIC_IS_AVIVO(rdev)) {
541 /* crtc offset is from display base addr not FB location */
542 base -= radeon_crtc->legacy_display_base_addr;
543 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
544
545 if (tiling_flags & RADEON_TILING_MACRO) {
546 if (ASIC_IS_R300(rdev)) {
547 base &= ~0x7ff;
548 } else {
549 int byteshift = fb->format->cpp[0] * 8 >> 4;
550 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
551 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
552 }
553 } else {
554 int offset = crtc->y * pitch_pixels + crtc->x;
555 switch (fb->format->cpp[0] * 8) {
556 case 8:
557 default:
558 offset *= 1;
559 break;
560 case 15:
561 case 16:
562 offset *= 2;
563 break;
564 case 24:
565 offset *= 3;
566 break;
567 case 32:
568 offset *= 4;
569 break;
570 }
571 base += offset;
572 }
573 base &= ~7;
574 }
575 work->base = base;
576 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
577 dev->driver->get_vblank_counter(dev, work->crtc_id);
578
579 /* We borrow the event spin lock for protecting flip_work */
580 spin_lock_irqsave(&crtc->dev->event_lock, flags);
581
582 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
583 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
584 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
585 r = -EBUSY;
586 goto pflip_cleanup;
587 }
588 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
589 radeon_crtc->flip_work = work;
590
591 /* update crtc fb */
592 crtc->primary->fb = fb;
593
594 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
595
596 queue_work(radeon_crtc->flip_queue, &work->flip_work);
597 return 0;
598
599pflip_cleanup:
600 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
601 DRM_ERROR("failed to reserve new rbo in error path\n");
602 goto cleanup;
603 }
604 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
605 DRM_ERROR("failed to unpin new rbo in error path\n");
606 }
607 radeon_bo_unreserve(new_rbo);
608
609cleanup:
610 drm_gem_object_put_unlocked(&work->old_rbo->tbo.base);
611 dma_fence_put(work->fence);
612 kfree(work);
613 return r;
614}
615
616static int
617radeon_crtc_set_config(struct drm_mode_set *set,
618 struct drm_modeset_acquire_ctx *ctx)
619{
620 struct drm_device *dev;
621 struct radeon_device *rdev;
622 struct drm_crtc *crtc;
623 bool active = false;
624 int ret;
625
626 if (!set || !set->crtc)
627 return -EINVAL;
628
629 dev = set->crtc->dev;
630
631 ret = pm_runtime_get_sync(dev->dev);
632 if (ret < 0)
633 return ret;
634
635 ret = drm_crtc_helper_set_config(set, ctx);
636
637 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
638 if (crtc->enabled)
639 active = true;
640
641 pm_runtime_mark_last_busy(dev->dev);
642
643 rdev = dev->dev_private;
644 /* if we have active crtcs and we don't have a power ref,
645 take the current one */
646 if (active && !rdev->have_disp_power_ref) {
647 rdev->have_disp_power_ref = true;
648 return ret;
649 }
650 /* if we have no active crtcs, then drop the power ref
651 we got before */
652 if (!active && rdev->have_disp_power_ref) {
653 pm_runtime_put_autosuspend(dev->dev);
654 rdev->have_disp_power_ref = false;
655 }
656
657 /* drop the power reference we got coming in here */
658 pm_runtime_put_autosuspend(dev->dev);
659 return ret;
660}
661
662static const struct drm_crtc_funcs radeon_crtc_funcs = {
663 .cursor_set2 = radeon_crtc_cursor_set2,
664 .cursor_move = radeon_crtc_cursor_move,
665 .gamma_set = radeon_crtc_gamma_set,
666 .set_config = radeon_crtc_set_config,
667 .destroy = radeon_crtc_destroy,
668 .page_flip_target = radeon_crtc_page_flip_target,
669};
670
671static void radeon_crtc_init(struct drm_device *dev, int index)
672{
673 struct radeon_device *rdev = dev->dev_private;
674 struct radeon_crtc *radeon_crtc;
675 int i;
676
677 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
678 if (radeon_crtc == NULL)
679 return;
680
681 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
682
683 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
684 radeon_crtc->crtc_id = index;
685 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
686 rdev->mode_info.crtcs[index] = radeon_crtc;
687
688 if (rdev->family >= CHIP_BONAIRE) {
689 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
690 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
691 } else {
692 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
693 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
694 }
695 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
696 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
697
698#if 0
699 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
700 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
701 radeon_crtc->mode_set.num_connectors = 0;
702#endif
703
704 for (i = 0; i < 256; i++) {
705 radeon_crtc->lut_r[i] = i << 2;
706 radeon_crtc->lut_g[i] = i << 2;
707 radeon_crtc->lut_b[i] = i << 2;
708 }
709
710 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
711 radeon_atombios_init_crtc(dev, radeon_crtc);
712 else
713 radeon_legacy_init_crtc(dev, radeon_crtc);
714}
715
716static const char *encoder_names[38] = {
717 "NONE",
718 "INTERNAL_LVDS",
719 "INTERNAL_TMDS1",
720 "INTERNAL_TMDS2",
721 "INTERNAL_DAC1",
722 "INTERNAL_DAC2",
723 "INTERNAL_SDVOA",
724 "INTERNAL_SDVOB",
725 "SI170B",
726 "CH7303",
727 "CH7301",
728 "INTERNAL_DVO1",
729 "EXTERNAL_SDVOA",
730 "EXTERNAL_SDVOB",
731 "TITFP513",
732 "INTERNAL_LVTM1",
733 "VT1623",
734 "HDMI_SI1930",
735 "HDMI_INTERNAL",
736 "INTERNAL_KLDSCP_TMDS1",
737 "INTERNAL_KLDSCP_DVO1",
738 "INTERNAL_KLDSCP_DAC1",
739 "INTERNAL_KLDSCP_DAC2",
740 "SI178",
741 "MVPU_FPGA",
742 "INTERNAL_DDI",
743 "VT1625",
744 "HDMI_SI1932",
745 "DP_AN9801",
746 "DP_DP501",
747 "INTERNAL_UNIPHY",
748 "INTERNAL_KLDSCP_LVTMA",
749 "INTERNAL_UNIPHY1",
750 "INTERNAL_UNIPHY2",
751 "NUTMEG",
752 "TRAVIS",
753 "INTERNAL_VCE",
754 "INTERNAL_UNIPHY3",
755};
756
757static const char *hpd_names[6] = {
758 "HPD1",
759 "HPD2",
760 "HPD3",
761 "HPD4",
762 "HPD5",
763 "HPD6",
764};
765
766static void radeon_print_display_setup(struct drm_device *dev)
767{
768 struct drm_connector *connector;
769 struct radeon_connector *radeon_connector;
770 struct drm_encoder *encoder;
771 struct radeon_encoder *radeon_encoder;
772 uint32_t devices;
773 int i = 0;
774
775 DRM_INFO("Radeon Display Connectors\n");
776 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
777 radeon_connector = to_radeon_connector(connector);
778 DRM_INFO("Connector %d:\n", i);
779 DRM_INFO(" %s\n", connector->name);
780 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
781 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
782 if (radeon_connector->ddc_bus) {
783 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
784 radeon_connector->ddc_bus->rec.mask_clk_reg,
785 radeon_connector->ddc_bus->rec.mask_data_reg,
786 radeon_connector->ddc_bus->rec.a_clk_reg,
787 radeon_connector->ddc_bus->rec.a_data_reg,
788 radeon_connector->ddc_bus->rec.en_clk_reg,
789 radeon_connector->ddc_bus->rec.en_data_reg,
790 radeon_connector->ddc_bus->rec.y_clk_reg,
791 radeon_connector->ddc_bus->rec.y_data_reg);
792 if (radeon_connector->router.ddc_valid)
793 DRM_INFO(" DDC Router 0x%x/0x%x\n",
794 radeon_connector->router.ddc_mux_control_pin,
795 radeon_connector->router.ddc_mux_state);
796 if (radeon_connector->router.cd_valid)
797 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
798 radeon_connector->router.cd_mux_control_pin,
799 radeon_connector->router.cd_mux_state);
800 } else {
801 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
802 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
803 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
804 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
805 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
806 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
807 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
808 }
809 DRM_INFO(" Encoders:\n");
810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
811 radeon_encoder = to_radeon_encoder(encoder);
812 devices = radeon_encoder->devices & radeon_connector->devices;
813 if (devices) {
814 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
815 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
816 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
817 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
818 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
819 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
820 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
821 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
822 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
823 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
824 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
825 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
826 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
827 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
828 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
829 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
830 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
831 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
832 if (devices & ATOM_DEVICE_TV1_SUPPORT)
833 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
834 if (devices & ATOM_DEVICE_CV_SUPPORT)
835 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
836 }
837 }
838 i++;
839 }
840}
841
842static bool radeon_setup_enc_conn(struct drm_device *dev)
843{
844 struct radeon_device *rdev = dev->dev_private;
845 bool ret = false;
846
847 if (rdev->bios) {
848 if (rdev->is_atom_bios) {
849 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
850 if (ret == false)
851 ret = radeon_get_atom_connector_info_from_object_table(dev);
852 } else {
853 ret = radeon_get_legacy_connector_info_from_bios(dev);
854 if (ret == false)
855 ret = radeon_get_legacy_connector_info_from_table(dev);
856 }
857 } else {
858 if (!ASIC_IS_AVIVO(rdev))
859 ret = radeon_get_legacy_connector_info_from_table(dev);
860 }
861 if (ret) {
862 radeon_setup_encoder_clones(dev);
863 radeon_print_display_setup(dev);
864 }
865
866 return ret;
867}
868
869/* avivo */
870
871/**
872 * avivo_reduce_ratio - fractional number reduction
873 *
874 * @nom: nominator
875 * @den: denominator
876 * @nom_min: minimum value for nominator
877 * @den_min: minimum value for denominator
878 *
879 * Find the greatest common divisor and apply it on both nominator and
880 * denominator, but make nominator and denominator are at least as large
881 * as their minimum values.
882 */
883static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
884 unsigned nom_min, unsigned den_min)
885{
886 unsigned tmp;
887
888 /* reduce the numbers to a simpler ratio */
889 tmp = gcd(*nom, *den);
890 *nom /= tmp;
891 *den /= tmp;
892
893 /* make sure nominator is large enough */
894 if (*nom < nom_min) {
895 tmp = DIV_ROUND_UP(nom_min, *nom);
896 *nom *= tmp;
897 *den *= tmp;
898 }
899
900 /* make sure the denominator is large enough */
901 if (*den < den_min) {
902 tmp = DIV_ROUND_UP(den_min, *den);
903 *nom *= tmp;
904 *den *= tmp;
905 }
906}
907
908/**
909 * avivo_get_fb_ref_div - feedback and ref divider calculation
910 *
911 * @nom: nominator
912 * @den: denominator
913 * @post_div: post divider
914 * @fb_div_max: feedback divider maximum
915 * @ref_div_max: reference divider maximum
916 * @fb_div: resulting feedback divider
917 * @ref_div: resulting reference divider
918 *
919 * Calculate feedback and reference divider for a given post divider. Makes
920 * sure we stay within the limits.
921 */
922static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
923 unsigned fb_div_max, unsigned ref_div_max,
924 unsigned *fb_div, unsigned *ref_div)
925{
926 /* limit reference * post divider to a maximum */
927 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
928
929 /* get matching reference and feedback divider */
930 *ref_div = min(max(den/post_div, 1u), ref_div_max);
931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
932
933 /* limit fb divider to its maximum */
934 if (*fb_div > fb_div_max) {
935 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
936 *fb_div = fb_div_max;
937 }
938}
939
940/**
941 * radeon_compute_pll_avivo - compute PLL paramaters
942 *
943 * @pll: information about the PLL
944 * @dot_clock_p: resulting pixel clock
945 * fb_div_p: resulting feedback divider
946 * frac_fb_div_p: fractional part of the feedback divider
947 * ref_div_p: resulting reference divider
948 * post_div_p: resulting reference divider
949 *
950 * Try to calculate the PLL parameters to generate the given frequency:
951 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
952 */
953void radeon_compute_pll_avivo(struct radeon_pll *pll,
954 u32 freq,
955 u32 *dot_clock_p,
956 u32 *fb_div_p,
957 u32 *frac_fb_div_p,
958 u32 *ref_div_p,
959 u32 *post_div_p)
960{
961 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
962 freq : freq / 10;
963
964 unsigned fb_div_min, fb_div_max, fb_div;
965 unsigned post_div_min, post_div_max, post_div;
966 unsigned ref_div_min, ref_div_max, ref_div;
967 unsigned post_div_best, diff_best;
968 unsigned nom, den;
969
970 /* determine allowed feedback divider range */
971 fb_div_min = pll->min_feedback_div;
972 fb_div_max = pll->max_feedback_div;
973
974 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
975 fb_div_min *= 10;
976 fb_div_max *= 10;
977 }
978
979 /* determine allowed ref divider range */
980 if (pll->flags & RADEON_PLL_USE_REF_DIV)
981 ref_div_min = pll->reference_div;
982 else
983 ref_div_min = pll->min_ref_div;
984
985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
986 pll->flags & RADEON_PLL_USE_REF_DIV)
987 ref_div_max = pll->reference_div;
988 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
989 /* fix for problems on RS880 */
990 ref_div_max = min(pll->max_ref_div, 7u);
991 else
992 ref_div_max = pll->max_ref_div;
993
994 /* determine allowed post divider range */
995 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
996 post_div_min = pll->post_div;
997 post_div_max = pll->post_div;
998 } else {
999 unsigned vco_min, vco_max;
1000
1001 if (pll->flags & RADEON_PLL_IS_LCD) {
1002 vco_min = pll->lcd_pll_out_min;
1003 vco_max = pll->lcd_pll_out_max;
1004 } else {
1005 vco_min = pll->pll_out_min;
1006 vco_max = pll->pll_out_max;
1007 }
1008
1009 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1010 vco_min *= 10;
1011 vco_max *= 10;
1012 }
1013
1014 post_div_min = vco_min / target_clock;
1015 if ((target_clock * post_div_min) < vco_min)
1016 ++post_div_min;
1017 if (post_div_min < pll->min_post_div)
1018 post_div_min = pll->min_post_div;
1019
1020 post_div_max = vco_max / target_clock;
1021 if ((target_clock * post_div_max) > vco_max)
1022 --post_div_max;
1023 if (post_div_max > pll->max_post_div)
1024 post_div_max = pll->max_post_div;
1025 }
1026
1027 /* represent the searched ratio as fractional number */
1028 nom = target_clock;
1029 den = pll->reference_freq;
1030
1031 /* reduce the numbers to a simpler ratio */
1032 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1033
1034 /* now search for a post divider */
1035 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1036 post_div_best = post_div_min;
1037 else
1038 post_div_best = post_div_max;
1039 diff_best = ~0;
1040
1041 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1042 unsigned diff;
1043 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1044 ref_div_max, &fb_div, &ref_div);
1045 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1046 (ref_div * post_div));
1047
1048 if (diff < diff_best || (diff == diff_best &&
1049 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1050
1051 post_div_best = post_div;
1052 diff_best = diff;
1053 }
1054 }
1055 post_div = post_div_best;
1056
1057 /* get the feedback and reference divider for the optimal value */
1058 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1059 &fb_div, &ref_div);
1060
1061 /* reduce the numbers to a simpler ratio once more */
1062 /* this also makes sure that the reference divider is large enough */
1063 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1064
1065 /* avoid high jitter with small fractional dividers */
1066 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1067 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1068 if (fb_div < fb_div_min) {
1069 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1070 fb_div *= tmp;
1071 ref_div *= tmp;
1072 }
1073 }
1074
1075 /* and finally save the result */
1076 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1077 *fb_div_p = fb_div / 10;
1078 *frac_fb_div_p = fb_div % 10;
1079 } else {
1080 *fb_div_p = fb_div;
1081 *frac_fb_div_p = 0;
1082 }
1083
1084 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1085 (pll->reference_freq * *frac_fb_div_p)) /
1086 (ref_div * post_div * 10);
1087 *ref_div_p = ref_div;
1088 *post_div_p = post_div;
1089
1090 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1091 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1092 ref_div, post_div);
1093}
1094
1095/* pre-avivo */
1096static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1097{
1098 uint64_t mod;
1099
1100 n += d / 2;
1101
1102 mod = do_div(n, d);
1103 return n;
1104}
1105
1106void radeon_compute_pll_legacy(struct radeon_pll *pll,
1107 uint64_t freq,
1108 uint32_t *dot_clock_p,
1109 uint32_t *fb_div_p,
1110 uint32_t *frac_fb_div_p,
1111 uint32_t *ref_div_p,
1112 uint32_t *post_div_p)
1113{
1114 uint32_t min_ref_div = pll->min_ref_div;
1115 uint32_t max_ref_div = pll->max_ref_div;
1116 uint32_t min_post_div = pll->min_post_div;
1117 uint32_t max_post_div = pll->max_post_div;
1118 uint32_t min_fractional_feed_div = 0;
1119 uint32_t max_fractional_feed_div = 0;
1120 uint32_t best_vco = pll->best_vco;
1121 uint32_t best_post_div = 1;
1122 uint32_t best_ref_div = 1;
1123 uint32_t best_feedback_div = 1;
1124 uint32_t best_frac_feedback_div = 0;
1125 uint32_t best_freq = -1;
1126 uint32_t best_error = 0xffffffff;
1127 uint32_t best_vco_diff = 1;
1128 uint32_t post_div;
1129 u32 pll_out_min, pll_out_max;
1130
1131 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1132 freq = freq * 1000;
1133
1134 if (pll->flags & RADEON_PLL_IS_LCD) {
1135 pll_out_min = pll->lcd_pll_out_min;
1136 pll_out_max = pll->lcd_pll_out_max;
1137 } else {
1138 pll_out_min = pll->pll_out_min;
1139 pll_out_max = pll->pll_out_max;
1140 }
1141
1142 if (pll_out_min > 64800)
1143 pll_out_min = 64800;
1144
1145 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1146 min_ref_div = max_ref_div = pll->reference_div;
1147 else {
1148 while (min_ref_div < max_ref_div-1) {
1149 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1150 uint32_t pll_in = pll->reference_freq / mid;
1151 if (pll_in < pll->pll_in_min)
1152 max_ref_div = mid;
1153 else if (pll_in > pll->pll_in_max)
1154 min_ref_div = mid;
1155 else
1156 break;
1157 }
1158 }
1159
1160 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1161 min_post_div = max_post_div = pll->post_div;
1162
1163 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1164 min_fractional_feed_div = pll->min_frac_feedback_div;
1165 max_fractional_feed_div = pll->max_frac_feedback_div;
1166 }
1167
1168 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1169 uint32_t ref_div;
1170
1171 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1172 continue;
1173
1174 /* legacy radeons only have a few post_divs */
1175 if (pll->flags & RADEON_PLL_LEGACY) {
1176 if ((post_div == 5) ||
1177 (post_div == 7) ||
1178 (post_div == 9) ||
1179 (post_div == 10) ||
1180 (post_div == 11) ||
1181 (post_div == 13) ||
1182 (post_div == 14) ||
1183 (post_div == 15))
1184 continue;
1185 }
1186
1187 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1188 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1189 uint32_t pll_in = pll->reference_freq / ref_div;
1190 uint32_t min_feed_div = pll->min_feedback_div;
1191 uint32_t max_feed_div = pll->max_feedback_div + 1;
1192
1193 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1194 continue;
1195
1196 while (min_feed_div < max_feed_div) {
1197 uint32_t vco;
1198 uint32_t min_frac_feed_div = min_fractional_feed_div;
1199 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1200 uint32_t frac_feedback_div;
1201 uint64_t tmp;
1202
1203 feedback_div = (min_feed_div + max_feed_div) / 2;
1204
1205 tmp = (uint64_t)pll->reference_freq * feedback_div;
1206 vco = radeon_div(tmp, ref_div);
1207
1208 if (vco < pll_out_min) {
1209 min_feed_div = feedback_div + 1;
1210 continue;
1211 } else if (vco > pll_out_max) {
1212 max_feed_div = feedback_div;
1213 continue;
1214 }
1215
1216 while (min_frac_feed_div < max_frac_feed_div) {
1217 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1218 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1219 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1220 current_freq = radeon_div(tmp, ref_div * post_div);
1221
1222 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1223 if (freq < current_freq)
1224 error = 0xffffffff;
1225 else
1226 error = freq - current_freq;
1227 } else
1228 error = abs(current_freq - freq);
1229 vco_diff = abs(vco - best_vco);
1230
1231 if ((best_vco == 0 && error < best_error) ||
1232 (best_vco != 0 &&
1233 ((best_error > 100 && error < best_error - 100) ||
1234 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1235 best_post_div = post_div;
1236 best_ref_div = ref_div;
1237 best_feedback_div = feedback_div;
1238 best_frac_feedback_div = frac_feedback_div;
1239 best_freq = current_freq;
1240 best_error = error;
1241 best_vco_diff = vco_diff;
1242 } else if (current_freq == freq) {
1243 if (best_freq == -1) {
1244 best_post_div = post_div;
1245 best_ref_div = ref_div;
1246 best_feedback_div = feedback_div;
1247 best_frac_feedback_div = frac_feedback_div;
1248 best_freq = current_freq;
1249 best_error = error;
1250 best_vco_diff = vco_diff;
1251 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1252 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1253 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1254 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1255 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1256 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1257 best_post_div = post_div;
1258 best_ref_div = ref_div;
1259 best_feedback_div = feedback_div;
1260 best_frac_feedback_div = frac_feedback_div;
1261 best_freq = current_freq;
1262 best_error = error;
1263 best_vco_diff = vco_diff;
1264 }
1265 }
1266 if (current_freq < freq)
1267 min_frac_feed_div = frac_feedback_div + 1;
1268 else
1269 max_frac_feed_div = frac_feedback_div;
1270 }
1271 if (current_freq < freq)
1272 min_feed_div = feedback_div + 1;
1273 else
1274 max_feed_div = feedback_div;
1275 }
1276 }
1277 }
1278
1279 *dot_clock_p = best_freq / 10000;
1280 *fb_div_p = best_feedback_div;
1281 *frac_fb_div_p = best_frac_feedback_div;
1282 *ref_div_p = best_ref_div;
1283 *post_div_p = best_post_div;
1284 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1285 (long long)freq,
1286 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1287 best_ref_div, best_post_div);
1288
1289}
1290
1291static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1292 .destroy = drm_gem_fb_destroy,
1293 .create_handle = drm_gem_fb_create_handle,
1294};
1295
1296int
1297radeon_framebuffer_init(struct drm_device *dev,
1298 struct drm_framebuffer *fb,
1299 const struct drm_mode_fb_cmd2 *mode_cmd,
1300 struct drm_gem_object *obj)
1301{
1302 int ret;
1303 fb->obj[0] = obj;
1304 drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1305 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1306 if (ret) {
1307 fb->obj[0] = NULL;
1308 return ret;
1309 }
1310 return 0;
1311}
1312
1313static struct drm_framebuffer *
1314radeon_user_framebuffer_create(struct drm_device *dev,
1315 struct drm_file *file_priv,
1316 const struct drm_mode_fb_cmd2 *mode_cmd)
1317{
1318 struct drm_gem_object *obj;
1319 struct drm_framebuffer *fb;
1320 int ret;
1321
1322 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1323 if (obj == NULL) {
1324 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1325 "can't create framebuffer\n", mode_cmd->handles[0]);
1326 return ERR_PTR(-ENOENT);
1327 }
1328
1329 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1330 if (obj->import_attach) {
1331 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1332 return ERR_PTR(-EINVAL);
1333 }
1334
1335 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1336 if (fb == NULL) {
1337 drm_gem_object_put_unlocked(obj);
1338 return ERR_PTR(-ENOMEM);
1339 }
1340
1341 ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1342 if (ret) {
1343 kfree(fb);
1344 drm_gem_object_put_unlocked(obj);
1345 return ERR_PTR(ret);
1346 }
1347
1348 return fb;
1349}
1350
1351static const struct drm_mode_config_funcs radeon_mode_funcs = {
1352 .fb_create = radeon_user_framebuffer_create,
1353 .output_poll_changed = drm_fb_helper_output_poll_changed,
1354};
1355
1356static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1357{ { 0, "driver" },
1358 { 1, "bios" },
1359};
1360
1361static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1362{ { TV_STD_NTSC, "ntsc" },
1363 { TV_STD_PAL, "pal" },
1364 { TV_STD_PAL_M, "pal-m" },
1365 { TV_STD_PAL_60, "pal-60" },
1366 { TV_STD_NTSC_J, "ntsc-j" },
1367 { TV_STD_SCART_PAL, "scart-pal" },
1368 { TV_STD_PAL_CN, "pal-cn" },
1369 { TV_STD_SECAM, "secam" },
1370};
1371
1372static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1373{ { UNDERSCAN_OFF, "off" },
1374 { UNDERSCAN_ON, "on" },
1375 { UNDERSCAN_AUTO, "auto" },
1376};
1377
1378static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1379{ { RADEON_AUDIO_DISABLE, "off" },
1380 { RADEON_AUDIO_ENABLE, "on" },
1381 { RADEON_AUDIO_AUTO, "auto" },
1382};
1383
1384/* XXX support different dither options? spatial, temporal, both, etc. */
1385static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1386{ { RADEON_FMT_DITHER_DISABLE, "off" },
1387 { RADEON_FMT_DITHER_ENABLE, "on" },
1388};
1389
1390static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1391{ { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1392 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1393 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1394 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1395};
1396
1397static int radeon_modeset_create_props(struct radeon_device *rdev)
1398{
1399 int sz;
1400
1401 if (rdev->is_atom_bios) {
1402 rdev->mode_info.coherent_mode_property =
1403 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1404 if (!rdev->mode_info.coherent_mode_property)
1405 return -ENOMEM;
1406 }
1407
1408 if (!ASIC_IS_AVIVO(rdev)) {
1409 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1410 rdev->mode_info.tmds_pll_property =
1411 drm_property_create_enum(rdev->ddev, 0,
1412 "tmds_pll",
1413 radeon_tmds_pll_enum_list, sz);
1414 }
1415
1416 rdev->mode_info.load_detect_property =
1417 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1418 if (!rdev->mode_info.load_detect_property)
1419 return -ENOMEM;
1420
1421 drm_mode_create_scaling_mode_property(rdev->ddev);
1422
1423 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1424 rdev->mode_info.tv_std_property =
1425 drm_property_create_enum(rdev->ddev, 0,
1426 "tv standard",
1427 radeon_tv_std_enum_list, sz);
1428
1429 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1430 rdev->mode_info.underscan_property =
1431 drm_property_create_enum(rdev->ddev, 0,
1432 "underscan",
1433 radeon_underscan_enum_list, sz);
1434
1435 rdev->mode_info.underscan_hborder_property =
1436 drm_property_create_range(rdev->ddev, 0,
1437 "underscan hborder", 0, 128);
1438 if (!rdev->mode_info.underscan_hborder_property)
1439 return -ENOMEM;
1440
1441 rdev->mode_info.underscan_vborder_property =
1442 drm_property_create_range(rdev->ddev, 0,
1443 "underscan vborder", 0, 128);
1444 if (!rdev->mode_info.underscan_vborder_property)
1445 return -ENOMEM;
1446
1447 sz = ARRAY_SIZE(radeon_audio_enum_list);
1448 rdev->mode_info.audio_property =
1449 drm_property_create_enum(rdev->ddev, 0,
1450 "audio",
1451 radeon_audio_enum_list, sz);
1452
1453 sz = ARRAY_SIZE(radeon_dither_enum_list);
1454 rdev->mode_info.dither_property =
1455 drm_property_create_enum(rdev->ddev, 0,
1456 "dither",
1457 radeon_dither_enum_list, sz);
1458
1459 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1460 rdev->mode_info.output_csc_property =
1461 drm_property_create_enum(rdev->ddev, 0,
1462 "output_csc",
1463 radeon_output_csc_enum_list, sz);
1464
1465 return 0;
1466}
1467
1468void radeon_update_display_priority(struct radeon_device *rdev)
1469{
1470 /* adjustment options for the display watermarks */
1471 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1472 /* set display priority to high for r3xx, rv515 chips
1473 * this avoids flickering due to underflow to the
1474 * display controllers during heavy acceleration.
1475 * Don't force high on rs4xx igp chips as it seems to
1476 * affect the sound card. See kernel bug 15982.
1477 */
1478 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1479 !(rdev->flags & RADEON_IS_IGP))
1480 rdev->disp_priority = 2;
1481 else
1482 rdev->disp_priority = 0;
1483 } else
1484 rdev->disp_priority = radeon_disp_priority;
1485
1486}
1487
1488/*
1489 * Allocate hdmi structs and determine register offsets
1490 */
1491static void radeon_afmt_init(struct radeon_device *rdev)
1492{
1493 int i;
1494
1495 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1496 rdev->mode_info.afmt[i] = NULL;
1497
1498 if (ASIC_IS_NODCE(rdev)) {
1499 /* nothing to do */
1500 } else if (ASIC_IS_DCE4(rdev)) {
1501 static uint32_t eg_offsets[] = {
1502 EVERGREEN_CRTC0_REGISTER_OFFSET,
1503 EVERGREEN_CRTC1_REGISTER_OFFSET,
1504 EVERGREEN_CRTC2_REGISTER_OFFSET,
1505 EVERGREEN_CRTC3_REGISTER_OFFSET,
1506 EVERGREEN_CRTC4_REGISTER_OFFSET,
1507 EVERGREEN_CRTC5_REGISTER_OFFSET,
1508 0x13830 - 0x7030,
1509 };
1510 int num_afmt;
1511
1512 /* DCE8 has 7 audio blocks tied to DIG encoders */
1513 /* DCE6 has 6 audio blocks tied to DIG encoders */
1514 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1515 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1516 if (ASIC_IS_DCE8(rdev))
1517 num_afmt = 7;
1518 else if (ASIC_IS_DCE6(rdev))
1519 num_afmt = 6;
1520 else if (ASIC_IS_DCE5(rdev))
1521 num_afmt = 6;
1522 else if (ASIC_IS_DCE41(rdev))
1523 num_afmt = 2;
1524 else /* DCE4 */
1525 num_afmt = 6;
1526
1527 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1528 for (i = 0; i < num_afmt; i++) {
1529 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1530 if (rdev->mode_info.afmt[i]) {
1531 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1532 rdev->mode_info.afmt[i]->id = i;
1533 }
1534 }
1535 } else if (ASIC_IS_DCE3(rdev)) {
1536 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1537 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1538 if (rdev->mode_info.afmt[0]) {
1539 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1540 rdev->mode_info.afmt[0]->id = 0;
1541 }
1542 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1543 if (rdev->mode_info.afmt[1]) {
1544 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1545 rdev->mode_info.afmt[1]->id = 1;
1546 }
1547 } else if (ASIC_IS_DCE2(rdev)) {
1548 /* DCE2 has at least 1 routable audio block */
1549 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1550 if (rdev->mode_info.afmt[0]) {
1551 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1552 rdev->mode_info.afmt[0]->id = 0;
1553 }
1554 /* r6xx has 2 routable audio blocks */
1555 if (rdev->family >= CHIP_R600) {
1556 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1557 if (rdev->mode_info.afmt[1]) {
1558 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1559 rdev->mode_info.afmt[1]->id = 1;
1560 }
1561 }
1562 }
1563}
1564
1565static void radeon_afmt_fini(struct radeon_device *rdev)
1566{
1567 int i;
1568
1569 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1570 kfree(rdev->mode_info.afmt[i]);
1571 rdev->mode_info.afmt[i] = NULL;
1572 }
1573}
1574
1575int radeon_modeset_init(struct radeon_device *rdev)
1576{
1577 int i;
1578 int ret;
1579
1580 drm_mode_config_init(rdev->ddev);
1581 rdev->mode_info.mode_config_initialized = true;
1582
1583 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1584
1585 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1586 rdev->ddev->mode_config.async_page_flip = true;
1587
1588 if (ASIC_IS_DCE5(rdev)) {
1589 rdev->ddev->mode_config.max_width = 16384;
1590 rdev->ddev->mode_config.max_height = 16384;
1591 } else if (ASIC_IS_AVIVO(rdev)) {
1592 rdev->ddev->mode_config.max_width = 8192;
1593 rdev->ddev->mode_config.max_height = 8192;
1594 } else {
1595 rdev->ddev->mode_config.max_width = 4096;
1596 rdev->ddev->mode_config.max_height = 4096;
1597 }
1598
1599 rdev->ddev->mode_config.preferred_depth = 24;
1600 rdev->ddev->mode_config.prefer_shadow = 1;
1601
1602 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1603
1604 ret = radeon_modeset_create_props(rdev);
1605 if (ret) {
1606 return ret;
1607 }
1608
1609 /* init i2c buses */
1610 radeon_i2c_init(rdev);
1611
1612 /* check combios for a valid hardcoded EDID - Sun servers */
1613 if (!rdev->is_atom_bios) {
1614 /* check for hardcoded EDID in BIOS */
1615 radeon_combios_check_hardcoded_edid(rdev);
1616 }
1617
1618 /* allocate crtcs */
1619 for (i = 0; i < rdev->num_crtc; i++) {
1620 radeon_crtc_init(rdev->ddev, i);
1621 }
1622
1623 /* okay we should have all the bios connectors */
1624 ret = radeon_setup_enc_conn(rdev->ddev);
1625 if (!ret) {
1626 return ret;
1627 }
1628
1629 /* init dig PHYs, disp eng pll */
1630 if (rdev->is_atom_bios) {
1631 radeon_atom_encoder_init(rdev);
1632 radeon_atom_disp_eng_pll_init(rdev);
1633 }
1634
1635 /* initialize hpd */
1636 radeon_hpd_init(rdev);
1637
1638 /* setup afmt */
1639 radeon_afmt_init(rdev);
1640
1641 radeon_fbdev_init(rdev);
1642 drm_kms_helper_poll_init(rdev->ddev);
1643
1644 /* do pm late init */
1645 ret = radeon_pm_late_init(rdev);
1646
1647 return 0;
1648}
1649
1650void radeon_modeset_fini(struct radeon_device *rdev)
1651{
1652 if (rdev->mode_info.mode_config_initialized) {
1653 drm_kms_helper_poll_fini(rdev->ddev);
1654 radeon_hpd_fini(rdev);
1655 drm_helper_force_disable_all(rdev->ddev);
1656 radeon_fbdev_fini(rdev);
1657 radeon_afmt_fini(rdev);
1658 drm_mode_config_cleanup(rdev->ddev);
1659 rdev->mode_info.mode_config_initialized = false;
1660 }
1661
1662 kfree(rdev->mode_info.bios_hardcoded_edid);
1663
1664 /* free i2c buses */
1665 radeon_i2c_fini(rdev);
1666}
1667
1668static bool is_hdtv_mode(const struct drm_display_mode *mode)
1669{
1670 /* try and guess if this is a tv or a monitor */
1671 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1672 (mode->vdisplay == 576) || /* 576p */
1673 (mode->vdisplay == 720) || /* 720p */
1674 (mode->vdisplay == 1080)) /* 1080p */
1675 return true;
1676 else
1677 return false;
1678}
1679
1680bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1681 const struct drm_display_mode *mode,
1682 struct drm_display_mode *adjusted_mode)
1683{
1684 struct drm_device *dev = crtc->dev;
1685 struct radeon_device *rdev = dev->dev_private;
1686 struct drm_encoder *encoder;
1687 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1688 struct radeon_encoder *radeon_encoder;
1689 struct drm_connector *connector;
1690 struct radeon_connector *radeon_connector;
1691 bool first = true;
1692 u32 src_v = 1, dst_v = 1;
1693 u32 src_h = 1, dst_h = 1;
1694
1695 radeon_crtc->h_border = 0;
1696 radeon_crtc->v_border = 0;
1697
1698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1699 if (encoder->crtc != crtc)
1700 continue;
1701 radeon_encoder = to_radeon_encoder(encoder);
1702 connector = radeon_get_connector_for_encoder(encoder);
1703 radeon_connector = to_radeon_connector(connector);
1704
1705 if (first) {
1706 /* set scaling */
1707 if (radeon_encoder->rmx_type == RMX_OFF)
1708 radeon_crtc->rmx_type = RMX_OFF;
1709 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1710 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1711 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1712 else
1713 radeon_crtc->rmx_type = RMX_OFF;
1714 /* copy native mode */
1715 memcpy(&radeon_crtc->native_mode,
1716 &radeon_encoder->native_mode,
1717 sizeof(struct drm_display_mode));
1718 src_v = crtc->mode.vdisplay;
1719 dst_v = radeon_crtc->native_mode.vdisplay;
1720 src_h = crtc->mode.hdisplay;
1721 dst_h = radeon_crtc->native_mode.hdisplay;
1722
1723 /* fix up for overscan on hdmi */
1724 if (ASIC_IS_AVIVO(rdev) &&
1725 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1726 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1727 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1728 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1729 is_hdtv_mode(mode)))) {
1730 if (radeon_encoder->underscan_hborder != 0)
1731 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1732 else
1733 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1734 if (radeon_encoder->underscan_vborder != 0)
1735 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1736 else
1737 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1738 radeon_crtc->rmx_type = RMX_FULL;
1739 src_v = crtc->mode.vdisplay;
1740 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1741 src_h = crtc->mode.hdisplay;
1742 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1743 }
1744 first = false;
1745 } else {
1746 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1747 /* WARNING: Right now this can't happen but
1748 * in the future we need to check that scaling
1749 * are consistent across different encoder
1750 * (ie all encoder can work with the same
1751 * scaling).
1752 */
1753 DRM_ERROR("Scaling not consistent across encoder.\n");
1754 return false;
1755 }
1756 }
1757 }
1758 if (radeon_crtc->rmx_type != RMX_OFF) {
1759 fixed20_12 a, b;
1760 a.full = dfixed_const(src_v);
1761 b.full = dfixed_const(dst_v);
1762 radeon_crtc->vsc.full = dfixed_div(a, b);
1763 a.full = dfixed_const(src_h);
1764 b.full = dfixed_const(dst_h);
1765 radeon_crtc->hsc.full = dfixed_div(a, b);
1766 } else {
1767 radeon_crtc->vsc.full = dfixed_const(1);
1768 radeon_crtc->hsc.full = dfixed_const(1);
1769 }
1770 return true;
1771}
1772
1773/*
1774 * Retrieve current video scanout position of crtc on a given gpu, and
1775 * an optional accurate timestamp of when query happened.
1776 *
1777 * \param dev Device to query.
1778 * \param crtc Crtc to query.
1779 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1780 * For driver internal use only also supports these flags:
1781 *
1782 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1783 * of a fudged earlier start of vblank.
1784 *
1785 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1786 * fudged earlier start of vblank in *vpos and the distance
1787 * to true start of vblank in *hpos.
1788 *
1789 * \param *vpos Location where vertical scanout position should be stored.
1790 * \param *hpos Location where horizontal scanout position should go.
1791 * \param *stime Target location for timestamp taken immediately before
1792 * scanout position query. Can be NULL to skip timestamp.
1793 * \param *etime Target location for timestamp taken immediately after
1794 * scanout position query. Can be NULL to skip timestamp.
1795 *
1796 * Returns vpos as a positive number while in active scanout area.
1797 * Returns vpos as a negative number inside vblank, counting the number
1798 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1799 * until start of active scanout / end of vblank."
1800 *
1801 * \return Flags, or'ed together as follows:
1802 *
1803 * DRM_SCANOUTPOS_VALID = Query successful.
1804 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1805 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1806 * this flag means that returned position may be offset by a constant but
1807 * unknown small number of scanlines wrt. real scanout position.
1808 *
1809 */
1810int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1811 unsigned int flags, int *vpos, int *hpos,
1812 ktime_t *stime, ktime_t *etime,
1813 const struct drm_display_mode *mode)
1814{
1815 u32 stat_crtc = 0, vbl = 0, position = 0;
1816 int vbl_start, vbl_end, vtotal, ret = 0;
1817 bool in_vbl = true;
1818
1819 struct radeon_device *rdev = dev->dev_private;
1820
1821 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1822
1823 /* Get optional system timestamp before query. */
1824 if (stime)
1825 *stime = ktime_get();
1826
1827 if (ASIC_IS_DCE4(rdev)) {
1828 if (pipe == 0) {
1829 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1830 EVERGREEN_CRTC0_REGISTER_OFFSET);
1831 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1832 EVERGREEN_CRTC0_REGISTER_OFFSET);
1833 ret |= DRM_SCANOUTPOS_VALID;
1834 }
1835 if (pipe == 1) {
1836 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1837 EVERGREEN_CRTC1_REGISTER_OFFSET);
1838 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1839 EVERGREEN_CRTC1_REGISTER_OFFSET);
1840 ret |= DRM_SCANOUTPOS_VALID;
1841 }
1842 if (pipe == 2) {
1843 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1844 EVERGREEN_CRTC2_REGISTER_OFFSET);
1845 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1846 EVERGREEN_CRTC2_REGISTER_OFFSET);
1847 ret |= DRM_SCANOUTPOS_VALID;
1848 }
1849 if (pipe == 3) {
1850 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1851 EVERGREEN_CRTC3_REGISTER_OFFSET);
1852 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1853 EVERGREEN_CRTC3_REGISTER_OFFSET);
1854 ret |= DRM_SCANOUTPOS_VALID;
1855 }
1856 if (pipe == 4) {
1857 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1858 EVERGREEN_CRTC4_REGISTER_OFFSET);
1859 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1860 EVERGREEN_CRTC4_REGISTER_OFFSET);
1861 ret |= DRM_SCANOUTPOS_VALID;
1862 }
1863 if (pipe == 5) {
1864 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1865 EVERGREEN_CRTC5_REGISTER_OFFSET);
1866 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1867 EVERGREEN_CRTC5_REGISTER_OFFSET);
1868 ret |= DRM_SCANOUTPOS_VALID;
1869 }
1870 } else if (ASIC_IS_AVIVO(rdev)) {
1871 if (pipe == 0) {
1872 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1873 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1874 ret |= DRM_SCANOUTPOS_VALID;
1875 }
1876 if (pipe == 1) {
1877 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1878 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1879 ret |= DRM_SCANOUTPOS_VALID;
1880 }
1881 } else {
1882 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1883 if (pipe == 0) {
1884 /* Assume vbl_end == 0, get vbl_start from
1885 * upper 16 bits.
1886 */
1887 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1888 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1889 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1890 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1891 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1892 if (!(stat_crtc & 1))
1893 in_vbl = false;
1894
1895 ret |= DRM_SCANOUTPOS_VALID;
1896 }
1897 if (pipe == 1) {
1898 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1899 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1900 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1901 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1902 if (!(stat_crtc & 1))
1903 in_vbl = false;
1904
1905 ret |= DRM_SCANOUTPOS_VALID;
1906 }
1907 }
1908
1909 /* Get optional system timestamp after query. */
1910 if (etime)
1911 *etime = ktime_get();
1912
1913 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1914
1915 /* Decode into vertical and horizontal scanout position. */
1916 *vpos = position & 0x1fff;
1917 *hpos = (position >> 16) & 0x1fff;
1918
1919 /* Valid vblank area boundaries from gpu retrieved? */
1920 if (vbl > 0) {
1921 /* Yes: Decode. */
1922 ret |= DRM_SCANOUTPOS_ACCURATE;
1923 vbl_start = vbl & 0x1fff;
1924 vbl_end = (vbl >> 16) & 0x1fff;
1925 }
1926 else {
1927 /* No: Fake something reasonable which gives at least ok results. */
1928 vbl_start = mode->crtc_vdisplay;
1929 vbl_end = 0;
1930 }
1931
1932 /* Called from driver internal vblank counter query code? */
1933 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1934 /* Caller wants distance from real vbl_start in *hpos */
1935 *hpos = *vpos - vbl_start;
1936 }
1937
1938 /* Fudge vblank to start a few scanlines earlier to handle the
1939 * problem that vblank irqs fire a few scanlines before start
1940 * of vblank. Some driver internal callers need the true vblank
1941 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1942 *
1943 * The cause of the "early" vblank irq is that the irq is triggered
1944 * by the line buffer logic when the line buffer read position enters
1945 * the vblank, whereas our crtc scanout position naturally lags the
1946 * line buffer read position.
1947 */
1948 if (!(flags & USE_REAL_VBLANKSTART))
1949 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1950
1951 /* Test scanout position against vblank region. */
1952 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1953 in_vbl = false;
1954
1955 /* In vblank? */
1956 if (in_vbl)
1957 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1958
1959 /* Called from driver internal vblank counter query code? */
1960 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1961 /* Caller wants distance from fudged earlier vbl_start */
1962 *vpos -= vbl_start;
1963 return ret;
1964 }
1965
1966 /* Check if inside vblank area and apply corrective offsets:
1967 * vpos will then be >=0 in video scanout area, but negative
1968 * within vblank area, counting down the number of lines until
1969 * start of scanout.
1970 */
1971
1972 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1973 if (in_vbl && (*vpos >= vbl_start)) {
1974 vtotal = mode->crtc_vtotal;
1975 *vpos = *vpos - vtotal;
1976 }
1977
1978 /* Correct for shifted end of vbl at vbl_end. */
1979 *vpos = *vpos - vbl_end;
1980
1981 return ret;
1982}