1// SPDX-License-Identifier: GPL-2.0 OR MIT
 2/* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
 3
 4#include <linux/iopoll.h>
 5#include <linux/device.h>
 6
 7#include "lima_device.h"
 8#include "lima_pmu.h"
 9#include "lima_regs.h"
10
11#define pmu_write(reg, data) writel(data, ip->iomem + reg)
12#define pmu_read(reg) readl(ip->iomem + reg)
13
14static int lima_pmu_wait_cmd(struct lima_ip *ip)
15{
16	struct lima_device *dev = ip->dev;
17	int err;
18	u32 v;
19
20	err = readl_poll_timeout(ip->iomem + LIMA_PMU_INT_RAWSTAT,
21				 v, v & LIMA_PMU_INT_CMD_MASK,
22				 100, 100000);
23	if (err) {
24		dev_err(dev->dev, "timeout wait pmd cmd\n");
25		return err;
26	}
27
28	pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
29	return 0;
30}
31
32int lima_pmu_init(struct lima_ip *ip)
33{
34	int err;
35	u32 stat;
36
37	pmu_write(LIMA_PMU_INT_MASK, 0);
38
39	/* If this value is too low, when in high GPU clk freq,
40	 * GPU will be in unstable state.
41	 */
42	pmu_write(LIMA_PMU_SW_DELAY, 0xffff);
43
44	/* status reg 1=off 0=on */
45	stat = pmu_read(LIMA_PMU_STATUS);
46
47	/* power up all ip */
48	if (stat) {
49		pmu_write(LIMA_PMU_POWER_UP, stat);
50		err = lima_pmu_wait_cmd(ip);
51		if (err)
52			return err;
53	}
54	return 0;
55}
56
57void lima_pmu_fini(struct lima_ip *ip)
58{
59
60}