1// SPDX-License-Identifier: GPL-2.0 OR MIT
  2/* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
  3
  4#include <linux/iopoll.h>
  5#include <linux/device.h>
  6
  7#include "lima_device.h"
  8#include "lima_pmu.h"
  9#include "lima_regs.h"
 10
 11#define pmu_write(reg, data) writel(data, ip->iomem + reg)
 12#define pmu_read(reg) readl(ip->iomem + reg)
 13
 14static int lima_pmu_wait_cmd(struct lima_ip *ip)
 15{
 16	struct lima_device *dev = ip->dev;
 17	int err;
 18	u32 v;
 19
 20	err = readl_poll_timeout(ip->iomem + LIMA_PMU_INT_RAWSTAT,
 21				 v, v & LIMA_PMU_INT_CMD_MASK,
 22				 100, 100000);
 23	if (err) {
 24		dev_err(dev->dev, "%s timeout wait pmu cmd\n",
 25			lima_ip_name(ip));
 26		return err;
 27	}
 28
 29	pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
 30	return 0;
 31}
 32
 33static u32 lima_pmu_get_ip_mask(struct lima_ip *ip)
 34{
 35	struct lima_device *dev = ip->dev;
 36	u32 ret = 0;
 37	int i;
 38
 39	ret |= LIMA_PMU_POWER_GP0_MASK;
 40
 41	if (dev->id == lima_gpu_mali400) {
 42		ret |= LIMA_PMU_POWER_L2_MASK;
 43		for (i = 0; i < 4; i++) {
 44			if (dev->ip[lima_ip_pp0 + i].present)
 45				ret |= LIMA_PMU_POWER_PP_MASK(i);
 46		}
 47	} else {
 48		if (dev->ip[lima_ip_pp0].present)
 49			ret |= LIMA450_PMU_POWER_PP0_MASK;
 50		for (i = lima_ip_pp1; i <= lima_ip_pp3; i++) {
 51			if (dev->ip[i].present) {
 52				ret |= LIMA450_PMU_POWER_PP13_MASK;
 53				break;
 54			}
 55		}
 56		for (i = lima_ip_pp4; i <= lima_ip_pp7; i++) {
 57			if (dev->ip[i].present) {
 58				ret |= LIMA450_PMU_POWER_PP47_MASK;
 59				break;
 60			}
 61		}
 62	}
 63
 64	return ret;
 65}
 66
 67static int lima_pmu_hw_init(struct lima_ip *ip)
 68{
 69	int err;
 70	u32 stat;
 71
 72	pmu_write(LIMA_PMU_INT_MASK, 0);
 73
 74	/* If this value is too low, when in high GPU clk freq,
 75	 * GPU will be in unstable state.
 76	 */
 77	pmu_write(LIMA_PMU_SW_DELAY, 0xffff);
 78
 79	/* status reg 1=off 0=on */
 80	stat = pmu_read(LIMA_PMU_STATUS);
 81
 82	/* power up all ip */
 83	if (stat) {
 84		pmu_write(LIMA_PMU_POWER_UP, stat);
 85		err = lima_pmu_wait_cmd(ip);
 86		if (err)
 87			return err;
 88	}
 89	return 0;
 90}
 91
 92static void lima_pmu_hw_fini(struct lima_ip *ip)
 93{
 94	u32 stat;
 95
 96	if (!ip->data.mask)
 97		ip->data.mask = lima_pmu_get_ip_mask(ip);
 98
 99	stat = ~pmu_read(LIMA_PMU_STATUS) & ip->data.mask;
100	if (stat) {
101		pmu_write(LIMA_PMU_POWER_DOWN, stat);
102
103		/* Don't wait for interrupt on Mali400 if all domains are
104		 * powered off because the HW won't generate an interrupt
105		 * in this case.
106		 */
107		if (ip->dev->id == lima_gpu_mali400)
108			pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
109		else
110			lima_pmu_wait_cmd(ip);
111	}
112}
113
114int lima_pmu_resume(struct lima_ip *ip)
115{
116	return lima_pmu_hw_init(ip);
117}
118
119void lima_pmu_suspend(struct lima_ip *ip)
120{
121	lima_pmu_hw_fini(ip);
122}
123
124int lima_pmu_init(struct lima_ip *ip)
125{
126	return lima_pmu_hw_init(ip);
127}
128
129void lima_pmu_fini(struct lima_ip *ip)
130{
131	lima_pmu_hw_fini(ip);
132}