1/*
 2 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef __AMDGPU_UMC_H__
22#define __AMDGPU_UMC_H__
23
24/* implement 64 bits REG operations via 32 bits interface */
25#define RREG64_UMC(reg)	(RREG32(reg) | \
26				((uint64_t)RREG32((reg) + 1) << 32))
27#define WREG64_UMC(reg, v)	\
28	do {	\
29		WREG32((reg), lower_32_bits(v));	\
30		WREG32((reg) + 1, upper_32_bits(v));	\
31	} while (0)
32
33/*
34 * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
35 *				uint32_t umc_reg_offset, uint32_t channel_index)
36 */
37#define amdgpu_umc_for_each_channel(func)	\
38	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;	\
39	uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index;	\
40	for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {	\
41		/* enable the index mode to query eror count per channel */	\
42		adev->umc.funcs->enable_umc_index_mode(adev, umc_inst);	\
43		for (channel_inst = 0;	\
44			channel_inst < adev->umc.channel_inst_num;	\
45			channel_inst++) {	\
46			/* calc the register offset according to channel instance */	\
47			umc_reg_offset = adev->umc.channel_offs * channel_inst;	\
48			/* get channel index of interleaved memory */	\
49			channel_index = adev->umc.channel_idx_tbl[	\
50				umc_inst * adev->umc.channel_inst_num + channel_inst];	\
51			(func)(adev, err_data, umc_reg_offset, channel_index);	\
52		}	\
53	}	\
54	adev->umc.funcs->disable_umc_index_mode(adev);
55
56struct amdgpu_umc_funcs {
57	void (*ras_init)(struct amdgpu_device *adev);
58	void (*query_ras_error_count)(struct amdgpu_device *adev,
59					void *ras_error_status);
60	void (*query_ras_error_address)(struct amdgpu_device *adev,
61					void *ras_error_status);
62	void (*enable_umc_index_mode)(struct amdgpu_device *adev,
63					uint32_t umc_instance);
64	void (*disable_umc_index_mode)(struct amdgpu_device *adev);
65};
66
67struct amdgpu_umc {
68	/* max error count in one ras query call */
69	uint32_t max_ras_err_cnt_per_query;
70	/* number of umc channel instance with memory map register access */
71	uint32_t channel_inst_num;
72	/* number of umc instance with memory map register access */
73	uint32_t umc_inst_num;
74	/* UMC regiser per channel offset */
75	uint32_t channel_offs;
76	/* channel index table of interleaved memory */
77	const uint32_t *channel_idx_tbl;
78
79	const struct amdgpu_umc_funcs *funcs;
80};
81
82#endif