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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32
33#define PSP_FENCE_BUFFER_SIZE 0x1000
34#define PSP_CMD_BUFFER_SIZE 0x1000
35#define PSP_ASD_SHARED_MEM_SIZE 0x4000
36#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
37#define PSP_RAS_SHARED_MEM_SIZE 0x4000
38#define PSP_1_MEG 0x100000
39#define PSP_TMR_SIZE 0x400000
40
41struct psp_context;
42struct psp_xgmi_node_info;
43struct psp_xgmi_topology_info;
44
45enum psp_bootloader_cmd {
46 PSP_BL__LOAD_SYSDRV = 0x10000,
47 PSP_BL__LOAD_SOSDRV = 0x20000,
48 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
49};
50
51enum psp_ring_type
52{
53 PSP_RING_TYPE__INVALID = 0,
54 /*
55 * These values map to the way the PSP kernel identifies the
56 * rings.
57 */
58 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
59 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
60};
61
62struct psp_ring
63{
64 enum psp_ring_type ring_type;
65 struct psp_gfx_rb_frame *ring_mem;
66 uint64_t ring_mem_mc_addr;
67 void *ring_mem_handle;
68 uint32_t ring_size;
69};
70
71/* More registers may will be supported */
72enum psp_reg_prog_id {
73 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
74 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
75 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
76 PSP_REG_LAST
77};
78
79struct psp_funcs
80{
81 int (*init_microcode)(struct psp_context *psp);
82 int (*bootloader_load_kdb)(struct psp_context *psp);
83 int (*bootloader_load_sysdrv)(struct psp_context *psp);
84 int (*bootloader_load_sos)(struct psp_context *psp);
85 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
86 int (*ring_create)(struct psp_context *psp,
87 enum psp_ring_type ring_type);
88 int (*ring_stop)(struct psp_context *psp,
89 enum psp_ring_type ring_type);
90 int (*ring_destroy)(struct psp_context *psp,
91 enum psp_ring_type ring_type);
92 int (*cmd_submit)(struct psp_context *psp,
93 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
94 int index);
95 bool (*compare_sram_data)(struct psp_context *psp,
96 struct amdgpu_firmware_info *ucode,
97 enum AMDGPU_UCODE_ID ucode_type);
98 bool (*smu_reload_quirk)(struct psp_context *psp);
99 int (*mode1_reset)(struct psp_context *psp);
100 int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
101 int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
102 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
103 struct psp_xgmi_topology_info *topology);
104 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
105 struct psp_xgmi_topology_info *topology);
106 bool (*support_vmr_ring)(struct psp_context *psp);
107 int (*ras_trigger_error)(struct psp_context *psp,
108 struct ta_ras_trigger_error_input *info);
109 int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
110 int (*rlc_autoload_start)(struct psp_context *psp);
111};
112
113#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
114struct psp_xgmi_node_info {
115 uint64_t node_id;
116 uint8_t num_hops;
117 uint8_t is_sharing_enabled;
118 enum ta_xgmi_assigned_sdma_engine sdma_engine;
119};
120
121struct psp_xgmi_topology_info {
122 uint32_t num_nodes;
123 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
124};
125
126struct psp_xgmi_context {
127 uint8_t initialized;
128 uint32_t session_id;
129 struct amdgpu_bo *xgmi_shared_bo;
130 uint64_t xgmi_shared_mc_addr;
131 void *xgmi_shared_buf;
132 struct psp_xgmi_topology_info top_info;
133};
134
135struct psp_ras_context {
136 /*ras fw*/
137 bool ras_initialized;
138 uint32_t session_id;
139 struct amdgpu_bo *ras_shared_bo;
140 uint64_t ras_shared_mc_addr;
141 void *ras_shared_buf;
142 struct amdgpu_ras *ras;
143};
144
145struct psp_context
146{
147 struct amdgpu_device *adev;
148 struct psp_ring km_ring;
149 struct psp_gfx_cmd_resp *cmd;
150
151 const struct psp_funcs *funcs;
152
153 /* firmware buffer */
154 struct amdgpu_bo *fw_pri_bo;
155 uint64_t fw_pri_mc_addr;
156 void *fw_pri_buf;
157
158 /* sos firmware */
159 const struct firmware *sos_fw;
160 uint32_t sos_fw_version;
161 uint32_t sos_feature_version;
162 uint32_t sys_bin_size;
163 uint32_t sos_bin_size;
164 uint32_t toc_bin_size;
165 uint32_t kdb_bin_size;
166 uint8_t *sys_start_addr;
167 uint8_t *sos_start_addr;
168 uint8_t *toc_start_addr;
169 uint8_t *kdb_start_addr;
170
171 /* tmr buffer */
172 struct amdgpu_bo *tmr_bo;
173 uint64_t tmr_mc_addr;
174
175 /* asd firmware and buffer */
176 const struct firmware *asd_fw;
177 uint32_t asd_fw_version;
178 uint32_t asd_feature_version;
179 uint32_t asd_ucode_size;
180 uint8_t *asd_start_addr;
181 struct amdgpu_bo *asd_shared_bo;
182 uint64_t asd_shared_mc_addr;
183 void *asd_shared_buf;
184
185 /* fence buffer */
186 struct amdgpu_bo *fence_buf_bo;
187 uint64_t fence_buf_mc_addr;
188 void *fence_buf;
189
190 /* cmd buffer */
191 struct amdgpu_bo *cmd_buf_bo;
192 uint64_t cmd_buf_mc_addr;
193 struct psp_gfx_cmd_resp *cmd_buf_mem;
194
195 /* fence value associated with cmd buffer */
196 atomic_t fence_value;
197 /* flag to mark whether gfx fw autoload is supported or not */
198 bool autoload_supported;
199
200 /* xgmi ta firmware and buffer */
201 const struct firmware *ta_fw;
202 uint32_t ta_fw_version;
203 uint32_t ta_xgmi_ucode_version;
204 uint32_t ta_xgmi_ucode_size;
205 uint8_t *ta_xgmi_start_addr;
206 uint32_t ta_ras_ucode_version;
207 uint32_t ta_ras_ucode_size;
208 uint8_t *ta_ras_start_addr;
209 struct psp_xgmi_context xgmi_context;
210 struct psp_ras_context ras;
211 struct mutex mutex;
212};
213
214struct amdgpu_psp_funcs {
215 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
216 enum AMDGPU_UCODE_ID);
217};
218
219
220#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
221#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
222#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
223#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
224#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
225 (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
226#define psp_compare_sram_data(psp, ucode, type) \
227 (psp)->funcs->compare_sram_data((psp), (ucode), (type))
228#define psp_init_microcode(psp) \
229 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
230#define psp_bootloader_load_kdb(psp) \
231 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
232#define psp_bootloader_load_sysdrv(psp) \
233 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
234#define psp_bootloader_load_sos(psp) \
235 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
236#define psp_smu_reload_quirk(psp) \
237 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
238#define psp_support_vmr_ring(psp) \
239 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
240#define psp_mode1_reset(psp) \
241 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
242#define psp_xgmi_get_node_id(psp, node_id) \
243 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
244#define psp_xgmi_get_hive_id(psp, hive_id) \
245 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
246#define psp_xgmi_get_topology_info(psp, num_device, topology) \
247 ((psp)->funcs->xgmi_get_topology_info ? \
248 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
249#define psp_xgmi_set_topology_info(psp, num_device, topology) \
250 ((psp)->funcs->xgmi_set_topology_info ? \
251 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
252#define psp_rlc_autoload(psp) \
253 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
254
255#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
256
257#define psp_ras_trigger_error(psp, info) \
258 ((psp)->funcs->ras_trigger_error ? \
259 (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL)
260#define psp_ras_cure_posion(psp, addr) \
261 ((psp)->funcs->ras_cure_posion ? \
262 (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
263
264extern const struct amd_ip_funcs psp_ip_funcs;
265
266extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
267extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
268 uint32_t field_val, uint32_t mask, bool check_changed);
269
270extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
271extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
272
273int psp_gpu_reset(struct amdgpu_device *adev);
274int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
275 uint64_t cmd_gpu_addr, int cmd_size);
276
277int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
278
279int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
280int psp_ras_enable_features(struct psp_context *psp,
281 union ta_ras_cmd_input *info, bool enable);
282
283int psp_rlc_autoload_start(struct psp_context *psp);
284
285extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
286int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
287 uint32_t value);
288#endif