Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32#include "ta_rap_if.h"
33#include "ta_secureDisplay_if.h"
34
35#define PSP_FENCE_BUFFER_SIZE 0x1000
36#define PSP_CMD_BUFFER_SIZE 0x1000
37#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
38#define PSP_RAS_SHARED_MEM_SIZE 0x4000
39#define PSP_1_MEG 0x100000
40#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
41#define PSP_HDCP_SHARED_MEM_SIZE 0x4000
42#define PSP_DTM_SHARED_MEM_SIZE 0x4000
43#define PSP_RAP_SHARED_MEM_SIZE 0x4000
44#define PSP_SECUREDISPLAY_SHARED_MEM_SIZE 0x4000
45#define PSP_SHARED_MEM_SIZE 0x4000
46#define PSP_FW_NAME_LEN 0x24
47
48struct psp_context;
49struct psp_xgmi_node_info;
50struct psp_xgmi_topology_info;
51
52enum psp_bootloader_cmd {
53 PSP_BL__LOAD_SYSDRV = 0x10000,
54 PSP_BL__LOAD_SOSDRV = 0x20000,
55 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
56 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
57 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
58 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
59};
60
61enum psp_ring_type
62{
63 PSP_RING_TYPE__INVALID = 0,
64 /*
65 * These values map to the way the PSP kernel identifies the
66 * rings.
67 */
68 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
69 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
70};
71
72struct psp_ring
73{
74 enum psp_ring_type ring_type;
75 struct psp_gfx_rb_frame *ring_mem;
76 uint64_t ring_mem_mc_addr;
77 void *ring_mem_handle;
78 uint32_t ring_size;
79 uint32_t ring_wptr;
80};
81
82/* More registers may will be supported */
83enum psp_reg_prog_id {
84 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
85 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
86 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
87 PSP_REG_LAST
88};
89
90struct psp_funcs
91{
92 int (*init_microcode)(struct psp_context *psp);
93 int (*bootloader_load_kdb)(struct psp_context *psp);
94 int (*bootloader_load_spl)(struct psp_context *psp);
95 int (*bootloader_load_sysdrv)(struct psp_context *psp);
96 int (*bootloader_load_sos)(struct psp_context *psp);
97 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
98 int (*ring_create)(struct psp_context *psp,
99 enum psp_ring_type ring_type);
100 int (*ring_stop)(struct psp_context *psp,
101 enum psp_ring_type ring_type);
102 int (*ring_destroy)(struct psp_context *psp,
103 enum psp_ring_type ring_type);
104 bool (*smu_reload_quirk)(struct psp_context *psp);
105 int (*mode1_reset)(struct psp_context *psp);
106 int (*mem_training)(struct psp_context *psp, uint32_t ops);
107 uint32_t (*ring_get_wptr)(struct psp_context *psp);
108 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
109 int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr);
110 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
111};
112
113#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
114struct psp_xgmi_node_info {
115 uint64_t node_id;
116 uint8_t num_hops;
117 uint8_t is_sharing_enabled;
118 enum ta_xgmi_assigned_sdma_engine sdma_engine;
119};
120
121struct psp_xgmi_topology_info {
122 uint32_t num_nodes;
123 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
124};
125
126struct psp_asd_context {
127 bool asd_initialized;
128 uint32_t session_id;
129};
130
131struct psp_xgmi_context {
132 uint8_t initialized;
133 uint32_t session_id;
134 struct amdgpu_bo *xgmi_shared_bo;
135 uint64_t xgmi_shared_mc_addr;
136 void *xgmi_shared_buf;
137 struct psp_xgmi_topology_info top_info;
138};
139
140struct psp_ras_context {
141 /*ras fw*/
142 bool ras_initialized;
143 uint32_t session_id;
144 struct amdgpu_bo *ras_shared_bo;
145 uint64_t ras_shared_mc_addr;
146 void *ras_shared_buf;
147 struct amdgpu_ras *ras;
148};
149
150struct psp_hdcp_context {
151 bool hdcp_initialized;
152 uint32_t session_id;
153 struct amdgpu_bo *hdcp_shared_bo;
154 uint64_t hdcp_shared_mc_addr;
155 void *hdcp_shared_buf;
156 struct mutex mutex;
157};
158
159struct psp_dtm_context {
160 bool dtm_initialized;
161 uint32_t session_id;
162 struct amdgpu_bo *dtm_shared_bo;
163 uint64_t dtm_shared_mc_addr;
164 void *dtm_shared_buf;
165 struct mutex mutex;
166};
167
168struct psp_rap_context {
169 bool rap_initialized;
170 uint32_t session_id;
171 struct amdgpu_bo *rap_shared_bo;
172 uint64_t rap_shared_mc_addr;
173 void *rap_shared_buf;
174 struct mutex mutex;
175};
176
177struct psp_securedisplay_context {
178 bool securedisplay_initialized;
179 uint32_t session_id;
180 struct amdgpu_bo *securedisplay_shared_bo;
181 uint64_t securedisplay_shared_mc_addr;
182 void *securedisplay_shared_buf;
183 struct mutex mutex;
184};
185
186#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
187#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
188#define GDDR6_MEM_TRAINING_OFFSET 0x8000
189/*Define the VRAM size that will be encroached by BIST training.*/
190#define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
191
192enum psp_memory_training_init_flag {
193 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
194 PSP_MEM_TRAIN_SUPPORT = 0x1,
195 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
196 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
197 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
198};
199
200enum psp_memory_training_ops {
201 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
202 PSP_MEM_TRAIN_SAVE = 0x2,
203 PSP_MEM_TRAIN_RESTORE = 0x4,
204 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
205 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
206 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
207};
208
209struct psp_memory_training_context {
210 /*training data size*/
211 u64 train_data_size;
212 /*
213 * sys_cache
214 * cpu virtual address
215 * system memory buffer that used to store the training data.
216 */
217 void *sys_cache;
218
219 /*vram offset of the p2c training data*/
220 u64 p2c_train_data_offset;
221
222 /*vram offset of the c2p training data*/
223 u64 c2p_train_data_offset;
224 struct amdgpu_bo *c2p_bo;
225
226 enum psp_memory_training_init_flag init;
227 u32 training_cnt;
228 bool enable_mem_training;
229};
230
231/** PSP runtime DB **/
232#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
233#define PSP_RUNTIME_DB_OFFSET 0x100000
234#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
235#define PSP_RUNTIME_DB_VER_1 0x0100
236#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
237
238enum psp_runtime_entry_type {
239 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
240 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
241 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
242 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
243 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
244 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
245};
246
247/* PSP runtime DB header */
248struct psp_runtime_data_header {
249 /* determine the existence of runtime db */
250 uint16_t cookie;
251 /* version of runtime db */
252 uint16_t version;
253};
254
255/* PSP runtime DB entry */
256struct psp_runtime_entry {
257 /* type of runtime db entry */
258 uint32_t entry_type;
259 /* offset of entry in bytes */
260 uint16_t offset;
261 /* size of entry in bytes */
262 uint16_t size;
263};
264
265/* PSP runtime DB directory */
266struct psp_runtime_data_directory {
267 /* number of valid entries */
268 uint16_t entry_count;
269 /* db entries*/
270 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
271};
272
273/* PSP runtime DB boot config feature bitmask */
274enum psp_runtime_boot_cfg_feature {
275 BOOT_CFG_FEATURE_GECC = 0x1,
276 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
277};
278
279/* PSP runtime DB boot config entry */
280struct psp_runtime_boot_cfg_entry {
281 uint32_t boot_cfg_bitmask;
282 uint32_t reserved;
283};
284
285struct psp_context
286{
287 struct amdgpu_device *adev;
288 struct psp_ring km_ring;
289 struct psp_gfx_cmd_resp *cmd;
290
291 const struct psp_funcs *funcs;
292
293 /* firmware buffer */
294 struct amdgpu_bo *fw_pri_bo;
295 uint64_t fw_pri_mc_addr;
296 void *fw_pri_buf;
297
298 /* sos firmware */
299 const struct firmware *sos_fw;
300 uint32_t sos_fw_version;
301 uint32_t sos_feature_version;
302 uint32_t sys_bin_size;
303 uint32_t sos_bin_size;
304 uint32_t toc_bin_size;
305 uint32_t kdb_bin_size;
306 uint32_t spl_bin_size;
307 uint32_t rl_bin_size;
308 uint8_t *sys_start_addr;
309 uint8_t *sos_start_addr;
310 uint8_t *toc_start_addr;
311 uint8_t *kdb_start_addr;
312 uint8_t *spl_start_addr;
313 uint8_t *rl_start_addr;
314
315 /* tmr buffer */
316 struct amdgpu_bo *tmr_bo;
317 uint64_t tmr_mc_addr;
318
319 /* asd firmware */
320 const struct firmware *asd_fw;
321 uint32_t asd_fw_version;
322 uint32_t asd_feature_version;
323 uint32_t asd_ucode_size;
324 uint8_t *asd_start_addr;
325
326 /* toc firmware */
327 const struct firmware *toc_fw;
328 uint32_t toc_fw_version;
329 uint32_t toc_feature_version;
330
331 /* fence buffer */
332 struct amdgpu_bo *fence_buf_bo;
333 uint64_t fence_buf_mc_addr;
334 void *fence_buf;
335
336 /* cmd buffer */
337 struct amdgpu_bo *cmd_buf_bo;
338 uint64_t cmd_buf_mc_addr;
339 struct psp_gfx_cmd_resp *cmd_buf_mem;
340
341 /* fence value associated with cmd buffer */
342 atomic_t fence_value;
343 /* flag to mark whether gfx fw autoload is supported or not */
344 bool autoload_supported;
345 /* flag to mark whether df cstate management centralized to PMFW */
346 bool pmfw_centralized_cstate_management;
347
348 /* xgmi ta firmware and buffer */
349 const struct firmware *ta_fw;
350 uint32_t ta_fw_version;
351 uint32_t ta_xgmi_ucode_version;
352 uint32_t ta_xgmi_ucode_size;
353 uint8_t *ta_xgmi_start_addr;
354 uint32_t ta_ras_ucode_version;
355 uint32_t ta_ras_ucode_size;
356 uint8_t *ta_ras_start_addr;
357
358 uint32_t ta_hdcp_ucode_version;
359 uint32_t ta_hdcp_ucode_size;
360 uint8_t *ta_hdcp_start_addr;
361
362 uint32_t ta_dtm_ucode_version;
363 uint32_t ta_dtm_ucode_size;
364 uint8_t *ta_dtm_start_addr;
365
366 uint32_t ta_rap_ucode_version;
367 uint32_t ta_rap_ucode_size;
368 uint8_t *ta_rap_start_addr;
369
370 uint32_t ta_securedisplay_ucode_version;
371 uint32_t ta_securedisplay_ucode_size;
372 uint8_t *ta_securedisplay_start_addr;
373
374 struct psp_asd_context asd_context;
375 struct psp_xgmi_context xgmi_context;
376 struct psp_ras_context ras;
377 struct psp_hdcp_context hdcp_context;
378 struct psp_dtm_context dtm_context;
379 struct psp_rap_context rap_context;
380 struct psp_securedisplay_context securedisplay_context;
381 struct mutex mutex;
382 struct psp_memory_training_context mem_train_ctx;
383
384 uint32_t boot_cfg_bitmask;
385};
386
387struct amdgpu_psp_funcs {
388 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
389 enum AMDGPU_UCODE_ID);
390};
391
392
393#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
394#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
395#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
396#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
397#define psp_init_microcode(psp) \
398 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
399#define psp_bootloader_load_kdb(psp) \
400 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
401#define psp_bootloader_load_spl(psp) \
402 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
403#define psp_bootloader_load_sysdrv(psp) \
404 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
405#define psp_bootloader_load_sos(psp) \
406 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
407#define psp_smu_reload_quirk(psp) \
408 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
409#define psp_mode1_reset(psp) \
410 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
411#define psp_mem_training(psp, ops) \
412 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
413
414#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
415#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
416
417#define psp_load_usbc_pd_fw(psp, dma_addr) \
418 ((psp)->funcs->load_usbc_pd_fw ? \
419 (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL)
420
421#define psp_read_usbc_pd_fw(psp, fw_ver) \
422 ((psp)->funcs->read_usbc_pd_fw ? \
423 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
424
425extern const struct amd_ip_funcs psp_ip_funcs;
426
427extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
428extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
429extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
430extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
431extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
432
433extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
434 uint32_t field_val, uint32_t mask, bool check_changed);
435
436int psp_gpu_reset(struct amdgpu_device *adev);
437int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
438 uint64_t cmd_gpu_addr, int cmd_size);
439
440int psp_xgmi_initialize(struct psp_context *psp);
441int psp_xgmi_terminate(struct psp_context *psp);
442int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
443int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
444int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
445int psp_xgmi_get_topology_info(struct psp_context *psp,
446 int number_devices,
447 struct psp_xgmi_topology_info *topology);
448int psp_xgmi_set_topology_info(struct psp_context *psp,
449 int number_devices,
450 struct psp_xgmi_topology_info *topology);
451
452int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
453int psp_ras_enable_features(struct psp_context *psp,
454 union ta_ras_cmd_input *info, bool enable);
455int psp_ras_trigger_error(struct psp_context *psp,
456 struct ta_ras_trigger_error_input *info);
457
458int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
459int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
460int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
461int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
462
463int psp_rlc_autoload_start(struct psp_context *psp);
464
465int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
466 uint32_t value);
467int psp_ring_cmd_submit(struct psp_context *psp,
468 uint64_t cmd_buf_mc_addr,
469 uint64_t fence_mc_addr,
470 int index);
471int psp_init_asd_microcode(struct psp_context *psp,
472 const char *chip_name);
473int psp_init_toc_microcode(struct psp_context *psp,
474 const char *chip_name);
475int psp_init_sos_microcode(struct psp_context *psp,
476 const char *chip_name);
477int psp_init_ta_microcode(struct psp_context *psp,
478 const char *chip_name);
479int psp_get_fw_attestation_records_addr(struct psp_context *psp,
480 uint64_t *output_ptr);
481
482int psp_load_fw_list(struct psp_context *psp,
483 struct amdgpu_firmware_info **ucode_list, int ucode_count);
484void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
485
486#endif