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1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#include <drm/amdgpu_drm.h>
26#include <drm/drm_drv.h>
27#include <drm/drm_gem.h>
28#include <drm/drm_vblank.h>
29#include "amdgpu_drv.h"
30
31#include <drm/drm_pciids.h>
32#include <linux/console.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
37#include <drm/drm_probe_helper.h>
38#include <linux/mmu_notifier.h>
39
40#include "amdgpu.h"
41#include "amdgpu_irq.h"
42#include "amdgpu_dma_buf.h"
43
44#include "amdgpu_amdkfd.h"
45
46/*
47 * KMS wrapper.
48 * - 3.0.0 - initial driver
49 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
50 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
51 * at the end of IBs.
52 * - 3.3.0 - Add VM support for UVD on supported hardware.
53 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
54 * - 3.5.0 - Add support for new UVD_NO_OP register.
55 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
56 * - 3.7.0 - Add support for VCE clock list packet
57 * - 3.8.0 - Add support raster config init in the kernel
58 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
59 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
60 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
61 * - 3.12.0 - Add query for double offchip LDS buffers
62 * - 3.13.0 - Add PRT support
63 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
64 * - 3.15.0 - Export more gpu info for gfx9
65 * - 3.16.0 - Add reserved vmid support
66 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
67 * - 3.18.0 - Export gpu always on cu bitmap
68 * - 3.19.0 - Add support for UVD MJPEG decode
69 * - 3.20.0 - Add support for local BOs
70 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
71 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
72 * - 3.23.0 - Add query for VRAM lost counter
73 * - 3.24.0 - Add high priority compute support for gfx9
74 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
75 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
76 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
77 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
78 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
79 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
80 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
81 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
82 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
83 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
84 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
85 */
86#define KMS_DRIVER_MAJOR 3
87#define KMS_DRIVER_MINOR 35
88#define KMS_DRIVER_PATCHLEVEL 0
89
90#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
91
92int amdgpu_vram_limit = 0;
93int amdgpu_vis_vram_limit = 0;
94int amdgpu_gart_size = -1; /* auto */
95int amdgpu_gtt_size = -1; /* auto */
96int amdgpu_moverate = -1; /* auto */
97int amdgpu_benchmarking = 0;
98int amdgpu_testing = 0;
99int amdgpu_audio = -1;
100int amdgpu_disp_priority = 0;
101int amdgpu_hw_i2c = 0;
102int amdgpu_pcie_gen2 = -1;
103int amdgpu_msi = -1;
104char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
105int amdgpu_dpm = -1;
106int amdgpu_fw_load_type = -1;
107int amdgpu_aspm = -1;
108int amdgpu_runtime_pm = -1;
109uint amdgpu_ip_block_mask = 0xffffffff;
110int amdgpu_bapm = -1;
111int amdgpu_deep_color = 0;
112int amdgpu_vm_size = -1;
113int amdgpu_vm_fragment_size = -1;
114int amdgpu_vm_block_size = -1;
115int amdgpu_vm_fault_stop = 0;
116int amdgpu_vm_debug = 0;
117int amdgpu_vm_update_mode = -1;
118int amdgpu_exp_hw_support = 0;
119int amdgpu_dc = -1;
120int amdgpu_sched_jobs = 32;
121int amdgpu_sched_hw_submission = 2;
122uint amdgpu_pcie_gen_cap = 0;
123uint amdgpu_pcie_lane_cap = 0;
124uint amdgpu_cg_mask = 0xffffffff;
125uint amdgpu_pg_mask = 0xffffffff;
126uint amdgpu_sdma_phase_quantum = 32;
127char *amdgpu_disable_cu = NULL;
128char *amdgpu_virtual_display = NULL;
129/* OverDrive(bit 14) disabled by default*/
130uint amdgpu_pp_feature_mask = 0xffffbfff;
131int amdgpu_ngg = 0;
132int amdgpu_prim_buf_per_se = 0;
133int amdgpu_pos_buf_per_se = 0;
134int amdgpu_cntl_sb_buf_per_se = 0;
135int amdgpu_param_buf_per_se = 0;
136int amdgpu_job_hang_limit = 0;
137int amdgpu_lbpw = -1;
138int amdgpu_compute_multipipe = -1;
139int amdgpu_gpu_recovery = -1; /* auto */
140int amdgpu_emu_mode = 0;
141uint amdgpu_smu_memory_pool_size = 0;
142/* FBC (bit 0) disabled by default*/
143uint amdgpu_dc_feature_mask = 0;
144int amdgpu_async_gfx_ring = 1;
145int amdgpu_mcbp = 0;
146int amdgpu_discovery = -1;
147int amdgpu_mes = 0;
148int amdgpu_noretry = 1;
149
150struct amdgpu_mgpu_info mgpu_info = {
151 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
152};
153int amdgpu_ras_enable = -1;
154uint amdgpu_ras_mask = 0xfffffffb;
155
156/**
157 * DOC: vramlimit (int)
158 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
159 */
160MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
161module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
162
163/**
164 * DOC: vis_vramlimit (int)
165 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
166 */
167MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
168module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
169
170/**
171 * DOC: gartsize (uint)
172 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
173 */
174MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
175module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
176
177/**
178 * DOC: gttsize (int)
179 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
180 * otherwise 3/4 RAM size).
181 */
182MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
183module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
184
185/**
186 * DOC: moverate (int)
187 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
188 */
189MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
190module_param_named(moverate, amdgpu_moverate, int, 0600);
191
192/**
193 * DOC: benchmark (int)
194 * Run benchmarks. The default is 0 (Skip benchmarks).
195 */
196MODULE_PARM_DESC(benchmark, "Run benchmark");
197module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
198
199/**
200 * DOC: test (int)
201 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
202 */
203MODULE_PARM_DESC(test, "Run tests");
204module_param_named(test, amdgpu_testing, int, 0444);
205
206/**
207 * DOC: audio (int)
208 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
209 */
210MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
211module_param_named(audio, amdgpu_audio, int, 0444);
212
213/**
214 * DOC: disp_priority (int)
215 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
216 */
217MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
218module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
219
220/**
221 * DOC: hw_i2c (int)
222 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
223 */
224MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
225module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
226
227/**
228 * DOC: pcie_gen2 (int)
229 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
230 */
231MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
232module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
233
234/**
235 * DOC: msi (int)
236 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
237 */
238MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
239module_param_named(msi, amdgpu_msi, int, 0444);
240
241/**
242 * DOC: lockup_timeout (string)
243 * Set GPU scheduler timeout value in ms.
244 *
245 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
246 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
247 * to default timeout.
248 * - With one value specified, the setting will apply to all non-compute jobs.
249 * - With multiple values specified, the first one will be for GFX. The second one is for Compute.
250 * And the third and fourth ones are for SDMA and Video.
251 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
252 * jobs is 10000. And there is no timeout enforced on compute jobs.
253 */
254MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs."
255 " 0: keep default value. negative: infinity timeout), "
256 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
257module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
258
259/**
260 * DOC: dpm (int)
261 * Override for dynamic power management setting
262 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20)
263 * The default is -1 (auto).
264 */
265MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
266module_param_named(dpm, amdgpu_dpm, int, 0444);
267
268/**
269 * DOC: fw_load_type (int)
270 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
271 */
272MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
273module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
274
275/**
276 * DOC: aspm (int)
277 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
278 */
279MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
280module_param_named(aspm, amdgpu_aspm, int, 0444);
281
282/**
283 * DOC: runpm (int)
284 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
285 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
286 */
287MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
288module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
289
290/**
291 * DOC: ip_block_mask (uint)
292 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
293 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
294 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
295 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
296 */
297MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
298module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
299
300/**
301 * DOC: bapm (int)
302 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
303 * The default -1 (auto, enabled)
304 */
305MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
306module_param_named(bapm, amdgpu_bapm, int, 0444);
307
308/**
309 * DOC: deep_color (int)
310 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
311 */
312MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
313module_param_named(deep_color, amdgpu_deep_color, int, 0444);
314
315/**
316 * DOC: vm_size (int)
317 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
318 */
319MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
320module_param_named(vm_size, amdgpu_vm_size, int, 0444);
321
322/**
323 * DOC: vm_fragment_size (int)
324 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
325 */
326MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
327module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
328
329/**
330 * DOC: vm_block_size (int)
331 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
332 */
333MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
334module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
335
336/**
337 * DOC: vm_fault_stop (int)
338 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
339 */
340MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
341module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
342
343/**
344 * DOC: vm_debug (int)
345 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
346 */
347MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
348module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
349
350/**
351 * DOC: vm_update_mode (int)
352 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
353 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
354 */
355MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
356module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
357
358/**
359 * DOC: exp_hw_support (int)
360 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
361 */
362MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
363module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
364
365/**
366 * DOC: dc (int)
367 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
368 */
369MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
370module_param_named(dc, amdgpu_dc, int, 0444);
371
372/**
373 * DOC: sched_jobs (int)
374 * Override the max number of jobs supported in the sw queue. The default is 32.
375 */
376MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
377module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
378
379/**
380 * DOC: sched_hw_submission (int)
381 * Override the max number of HW submissions. The default is 2.
382 */
383MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
384module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
385
386/**
387 * DOC: ppfeaturemask (uint)
388 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
389 * The default is the current set of stable power features.
390 */
391MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
392module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
393
394/**
395 * DOC: pcie_gen_cap (uint)
396 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
397 * The default is 0 (automatic for each asic).
398 */
399MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
400module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
401
402/**
403 * DOC: pcie_lane_cap (uint)
404 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
405 * The default is 0 (automatic for each asic).
406 */
407MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
408module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
409
410/**
411 * DOC: cg_mask (uint)
412 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
413 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
414 */
415MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
416module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
417
418/**
419 * DOC: pg_mask (uint)
420 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
421 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
422 */
423MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
424module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
425
426/**
427 * DOC: sdma_phase_quantum (uint)
428 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
429 */
430MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
431module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
432
433/**
434 * DOC: disable_cu (charp)
435 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
436 */
437MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
438module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
439
440/**
441 * DOC: virtual_display (charp)
442 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
443 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
444 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
445 * device at 26:00.0. The default is NULL.
446 */
447MODULE_PARM_DESC(virtual_display,
448 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
449module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
450
451/**
452 * DOC: ngg (int)
453 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
454 */
455MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
456module_param_named(ngg, amdgpu_ngg, int, 0444);
457
458/**
459 * DOC: prim_buf_per_se (int)
460 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
461 */
462MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
463module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
464
465/**
466 * DOC: pos_buf_per_se (int)
467 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
468 */
469MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
470module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
471
472/**
473 * DOC: cntl_sb_buf_per_se (int)
474 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
475 */
476MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
477module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
478
479/**
480 * DOC: param_buf_per_se (int)
481 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
482 * The default is 0 (depending on gfx).
483 */
484MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
485module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
486
487/**
488 * DOC: job_hang_limit (int)
489 * Set how much time allow a job hang and not drop it. The default is 0.
490 */
491MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
492module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
493
494/**
495 * DOC: lbpw (int)
496 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
497 */
498MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
499module_param_named(lbpw, amdgpu_lbpw, int, 0444);
500
501MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
502module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
503
504/**
505 * DOC: gpu_recovery (int)
506 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
507 */
508MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
509module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
510
511/**
512 * DOC: emu_mode (int)
513 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
514 */
515MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
516module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
517
518/**
519 * DOC: ras_enable (int)
520 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
521 */
522MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
523module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
524
525/**
526 * DOC: ras_mask (uint)
527 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
528 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
529 */
530MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
531module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
532
533/**
534 * DOC: si_support (int)
535 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
536 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
537 * otherwise using amdgpu driver.
538 */
539#ifdef CONFIG_DRM_AMDGPU_SI
540
541#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
542int amdgpu_si_support = 0;
543MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
544#else
545int amdgpu_si_support = 1;
546MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
547#endif
548
549module_param_named(si_support, amdgpu_si_support, int, 0444);
550#endif
551
552/**
553 * DOC: cik_support (int)
554 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
555 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
556 * otherwise using amdgpu driver.
557 */
558#ifdef CONFIG_DRM_AMDGPU_CIK
559
560#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
561int amdgpu_cik_support = 0;
562MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
563#else
564int amdgpu_cik_support = 1;
565MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
566#endif
567
568module_param_named(cik_support, amdgpu_cik_support, int, 0444);
569#endif
570
571/**
572 * DOC: smu_memory_pool_size (uint)
573 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
574 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
575 */
576MODULE_PARM_DESC(smu_memory_pool_size,
577 "reserve gtt for smu debug usage, 0 = disable,"
578 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
579module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
580
581/**
582 * DOC: async_gfx_ring (int)
583 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
584 */
585MODULE_PARM_DESC(async_gfx_ring,
586 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
587module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
588
589/**
590 * DOC: mcbp (int)
591 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
592 */
593MODULE_PARM_DESC(mcbp,
594 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
595module_param_named(mcbp, amdgpu_mcbp, int, 0444);
596
597/**
598 * DOC: discovery (int)
599 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
600 * (-1 = auto (default), 0 = disabled, 1 = enabled)
601 */
602MODULE_PARM_DESC(discovery,
603 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
604module_param_named(discovery, amdgpu_discovery, int, 0444);
605
606/**
607 * DOC: mes (int)
608 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
609 * (0 = disabled (default), 1 = enabled)
610 */
611MODULE_PARM_DESC(mes,
612 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
613module_param_named(mes, amdgpu_mes, int, 0444);
614
615MODULE_PARM_DESC(noretry,
616 "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
617module_param_named(noretry, amdgpu_noretry, int, 0644);
618
619#ifdef CONFIG_HSA_AMD
620/**
621 * DOC: sched_policy (int)
622 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
623 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
624 * assigns queues to HQDs.
625 */
626int sched_policy = KFD_SCHED_POLICY_HWS;
627module_param(sched_policy, int, 0444);
628MODULE_PARM_DESC(sched_policy,
629 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
630
631/**
632 * DOC: hws_max_conc_proc (int)
633 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
634 * number of VMIDs assigned to the HWS, which is also the default.
635 */
636int hws_max_conc_proc = 8;
637module_param(hws_max_conc_proc, int, 0444);
638MODULE_PARM_DESC(hws_max_conc_proc,
639 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
640
641/**
642 * DOC: cwsr_enable (int)
643 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
644 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
645 * disables it.
646 */
647int cwsr_enable = 1;
648module_param(cwsr_enable, int, 0444);
649MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
650
651/**
652 * DOC: max_num_of_queues_per_device (int)
653 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
654 * is 4096.
655 */
656int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
657module_param(max_num_of_queues_per_device, int, 0444);
658MODULE_PARM_DESC(max_num_of_queues_per_device,
659 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
660
661/**
662 * DOC: send_sigterm (int)
663 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
664 * but just print errors on dmesg. Setting 1 enables sending sigterm.
665 */
666int send_sigterm;
667module_param(send_sigterm, int, 0444);
668MODULE_PARM_DESC(send_sigterm,
669 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
670
671/**
672 * DOC: debug_largebar (int)
673 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
674 * system. This limits the VRAM size reported to ROCm applications to the visible
675 * size, usually 256MB.
676 * Default value is 0, diabled.
677 */
678int debug_largebar;
679module_param(debug_largebar, int, 0444);
680MODULE_PARM_DESC(debug_largebar,
681 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
682
683/**
684 * DOC: ignore_crat (int)
685 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
686 * table to get information about AMD APUs. This option can serve as a workaround on
687 * systems with a broken CRAT table.
688 */
689int ignore_crat;
690module_param(ignore_crat, int, 0444);
691MODULE_PARM_DESC(ignore_crat,
692 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
693
694/**
695 * DOC: halt_if_hws_hang (int)
696 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
697 * Setting 1 enables halt on hang.
698 */
699int halt_if_hws_hang;
700module_param(halt_if_hws_hang, int, 0644);
701MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
702
703/**
704 * DOC: hws_gws_support(bool)
705 * Whether HWS support gws barriers. Default value: false (not supported)
706 * This will be replaced with a MEC firmware version check once firmware
707 * is ready
708 */
709bool hws_gws_support;
710module_param(hws_gws_support, bool, 0444);
711MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)");
712
713/**
714 * DOC: queue_preemption_timeout_ms (int)
715 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
716 */
717int queue_preemption_timeout_ms = 9000;
718module_param(queue_preemption_timeout_ms, int, 0644);
719MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
720#endif
721
722/**
723 * DOC: dcfeaturemask (uint)
724 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
725 * The default is the current set of stable display features.
726 */
727MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
728module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
729
730/**
731 * DOC: abmlevel (uint)
732 * Override the default ABM (Adaptive Backlight Management) level used for DC
733 * enabled hardware. Requires DMCU to be supported and loaded.
734 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
735 * default. Values 1-4 control the maximum allowable brightness reduction via
736 * the ABM algorithm, with 1 being the least reduction and 4 being the most
737 * reduction.
738 *
739 * Defaults to 0, or disabled. Userspace can still override this level later
740 * after boot.
741 */
742uint amdgpu_dm_abm_level = 0;
743MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
744module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
745
746static const struct pci_device_id pciidlist[] = {
747#ifdef CONFIG_DRM_AMDGPU_SI
748 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
749 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
750 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
751 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
752 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
753 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
754 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
755 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
756 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
757 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
758 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
759 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
760 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
761 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
762 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
763 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
764 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
765 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
766 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
767 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
768 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
769 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
770 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
771 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
772 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
773 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
774 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
775 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
776 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
777 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
778 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
779 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
780 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
781 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
782 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
783 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
784 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
785 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
786 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
787 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
788 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
789 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
790 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
791 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
792 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
793 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
794 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
795 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
796 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
797 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
798 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
799 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
800 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
801 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
802 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
803 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
804 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
805 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
806 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
807 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
808 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
809 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
810 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
811 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
812 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
813 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
814 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
815 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
816 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
817 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
818 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
819 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
820#endif
821#ifdef CONFIG_DRM_AMDGPU_CIK
822 /* Kaveri */
823 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
824 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
825 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
826 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
827 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
828 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
829 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
830 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
831 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
832 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
833 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
834 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
835 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
836 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
837 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
838 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
839 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
840 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
841 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
842 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
843 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
844 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
845 /* Bonaire */
846 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
847 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
848 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
849 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
850 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
851 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
852 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
853 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
854 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
855 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
856 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
857 /* Hawaii */
858 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
859 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
860 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
861 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
862 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
863 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
864 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
865 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
866 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
867 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
868 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
869 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
870 /* Kabini */
871 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
872 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
873 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
874 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
875 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
876 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
877 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
878 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
879 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
880 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
881 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
882 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
883 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
884 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
885 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
886 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
887 /* mullins */
888 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
889 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
890 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
891 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
892 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
893 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
894 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
895 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
896 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
897 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
898 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
899 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
900 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
901 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
902 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
903 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
904#endif
905 /* topaz */
906 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
907 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
908 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
909 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
910 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
911 /* tonga */
912 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
913 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
914 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
915 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
916 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
917 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
918 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
919 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
920 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
921 /* fiji */
922 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
923 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
924 /* carrizo */
925 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
926 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
927 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
928 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
929 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
930 /* stoney */
931 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
932 /* Polaris11 */
933 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
934 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
935 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
936 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
937 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
938 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
939 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
940 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
941 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
942 /* Polaris10 */
943 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
944 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
945 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
946 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
947 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
948 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
949 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
950 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
951 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
952 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
953 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
954 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
955 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
956 /* Polaris12 */
957 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
958 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
959 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
960 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
961 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
962 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
963 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
964 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
965 /* VEGAM */
966 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
967 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
968 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
969 /* Vega 10 */
970 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
971 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
972 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
973 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
974 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
975 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
976 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
977 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
978 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
979 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
980 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
981 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
982 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
983 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
984 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
985 /* Vega 12 */
986 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
987 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
988 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
989 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
990 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
991 /* Vega 20 */
992 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
993 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
994 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
995 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
996 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
997 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
998 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
999 /* Raven */
1000 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1001 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1002 /* Arcturus */
1003 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1004 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1005 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1006 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1007 /* Navi10 */
1008 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1009 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1010 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1011 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1012 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1013 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1014 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1015 /* Navi14 */
1016 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1017 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1018 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1019 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1020
1021 /* Renoir */
1022 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
1023
1024 /* Navi12 */
1025 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
1026
1027 {0, 0, 0}
1028};
1029
1030MODULE_DEVICE_TABLE(pci, pciidlist);
1031
1032static struct drm_driver kms_driver;
1033
1034static int amdgpu_pci_probe(struct pci_dev *pdev,
1035 const struct pci_device_id *ent)
1036{
1037 struct drm_device *dev;
1038 unsigned long flags = ent->driver_data;
1039 int ret, retry = 0;
1040 bool supports_atomic = false;
1041
1042 if (!amdgpu_virtual_display &&
1043 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1044 supports_atomic = true;
1045
1046 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1047 DRM_INFO("This hardware requires experimental hardware support.\n"
1048 "See modparam exp_hw_support\n");
1049 return -ENODEV;
1050 }
1051
1052#ifdef CONFIG_DRM_AMDGPU_SI
1053 if (!amdgpu_si_support) {
1054 switch (flags & AMD_ASIC_MASK) {
1055 case CHIP_TAHITI:
1056 case CHIP_PITCAIRN:
1057 case CHIP_VERDE:
1058 case CHIP_OLAND:
1059 case CHIP_HAINAN:
1060 dev_info(&pdev->dev,
1061 "SI support provided by radeon.\n");
1062 dev_info(&pdev->dev,
1063 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1064 );
1065 return -ENODEV;
1066 }
1067 }
1068#endif
1069#ifdef CONFIG_DRM_AMDGPU_CIK
1070 if (!amdgpu_cik_support) {
1071 switch (flags & AMD_ASIC_MASK) {
1072 case CHIP_KAVERI:
1073 case CHIP_BONAIRE:
1074 case CHIP_HAWAII:
1075 case CHIP_KABINI:
1076 case CHIP_MULLINS:
1077 dev_info(&pdev->dev,
1078 "CIK support provided by radeon.\n");
1079 dev_info(&pdev->dev,
1080 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1081 );
1082 return -ENODEV;
1083 }
1084 }
1085#endif
1086
1087 /* Get rid of things like offb */
1088 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
1089 if (ret)
1090 return ret;
1091
1092 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
1093 if (IS_ERR(dev))
1094 return PTR_ERR(dev);
1095
1096 if (!supports_atomic)
1097 dev->driver_features &= ~DRIVER_ATOMIC;
1098
1099 ret = pci_enable_device(pdev);
1100 if (ret)
1101 goto err_free;
1102
1103 dev->pdev = pdev;
1104
1105 pci_set_drvdata(pdev, dev);
1106
1107retry_init:
1108 ret = drm_dev_register(dev, ent->driver_data);
1109 if (ret == -EAGAIN && ++retry <= 3) {
1110 DRM_INFO("retry init %d\n", retry);
1111 /* Don't request EX mode too frequently which is attacking */
1112 msleep(5000);
1113 goto retry_init;
1114 } else if (ret)
1115 goto err_pci;
1116
1117 return 0;
1118
1119err_pci:
1120 pci_disable_device(pdev);
1121err_free:
1122 drm_dev_put(dev);
1123 return ret;
1124}
1125
1126static void
1127amdgpu_pci_remove(struct pci_dev *pdev)
1128{
1129 struct drm_device *dev = pci_get_drvdata(pdev);
1130
1131 DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
1132 drm_dev_unplug(dev);
1133 drm_dev_put(dev);
1134 pci_disable_device(pdev);
1135 pci_set_drvdata(pdev, NULL);
1136}
1137
1138static void
1139amdgpu_pci_shutdown(struct pci_dev *pdev)
1140{
1141 struct drm_device *dev = pci_get_drvdata(pdev);
1142 struct amdgpu_device *adev = dev->dev_private;
1143
1144 /* if we are running in a VM, make sure the device
1145 * torn down properly on reboot/shutdown.
1146 * unfortunately we can't detect certain
1147 * hypervisors so just do this all the time.
1148 */
1149 adev->mp1_state = PP_MP1_STATE_UNLOAD;
1150 amdgpu_device_ip_suspend(adev);
1151 adev->mp1_state = PP_MP1_STATE_NONE;
1152}
1153
1154static int amdgpu_pmops_suspend(struct device *dev)
1155{
1156 struct drm_device *drm_dev = dev_get_drvdata(dev);
1157
1158 return amdgpu_device_suspend(drm_dev, true, true);
1159}
1160
1161static int amdgpu_pmops_resume(struct device *dev)
1162{
1163 struct drm_device *drm_dev = dev_get_drvdata(dev);
1164
1165 /* GPU comes up enabled by the bios on resume */
1166 if (amdgpu_device_is_px(drm_dev)) {
1167 pm_runtime_disable(dev);
1168 pm_runtime_set_active(dev);
1169 pm_runtime_enable(dev);
1170 }
1171
1172 return amdgpu_device_resume(drm_dev, true, true);
1173}
1174
1175static int amdgpu_pmops_freeze(struct device *dev)
1176{
1177 struct drm_device *drm_dev = dev_get_drvdata(dev);
1178
1179 return amdgpu_device_suspend(drm_dev, false, true);
1180}
1181
1182static int amdgpu_pmops_thaw(struct device *dev)
1183{
1184 struct drm_device *drm_dev = dev_get_drvdata(dev);
1185
1186 return amdgpu_device_resume(drm_dev, false, true);
1187}
1188
1189static int amdgpu_pmops_poweroff(struct device *dev)
1190{
1191 struct drm_device *drm_dev = dev_get_drvdata(dev);
1192
1193 return amdgpu_device_suspend(drm_dev, true, true);
1194}
1195
1196static int amdgpu_pmops_restore(struct device *dev)
1197{
1198 struct drm_device *drm_dev = dev_get_drvdata(dev);
1199
1200 return amdgpu_device_resume(drm_dev, false, true);
1201}
1202
1203static int amdgpu_pmops_runtime_suspend(struct device *dev)
1204{
1205 struct pci_dev *pdev = to_pci_dev(dev);
1206 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1207 int ret;
1208
1209 if (!amdgpu_device_is_px(drm_dev)) {
1210 pm_runtime_forbid(dev);
1211 return -EBUSY;
1212 }
1213
1214 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1215 drm_kms_helper_poll_disable(drm_dev);
1216
1217 ret = amdgpu_device_suspend(drm_dev, false, false);
1218 pci_save_state(pdev);
1219 pci_disable_device(pdev);
1220 pci_ignore_hotplug(pdev);
1221 if (amdgpu_is_atpx_hybrid())
1222 pci_set_power_state(pdev, PCI_D3cold);
1223 else if (!amdgpu_has_atpx_dgpu_power_cntl())
1224 pci_set_power_state(pdev, PCI_D3hot);
1225 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1226
1227 return 0;
1228}
1229
1230static int amdgpu_pmops_runtime_resume(struct device *dev)
1231{
1232 struct pci_dev *pdev = to_pci_dev(dev);
1233 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1234 int ret;
1235
1236 if (!amdgpu_device_is_px(drm_dev))
1237 return -EINVAL;
1238
1239 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1240
1241 if (amdgpu_is_atpx_hybrid() ||
1242 !amdgpu_has_atpx_dgpu_power_cntl())
1243 pci_set_power_state(pdev, PCI_D0);
1244 pci_restore_state(pdev);
1245 ret = pci_enable_device(pdev);
1246 if (ret)
1247 return ret;
1248 pci_set_master(pdev);
1249
1250 ret = amdgpu_device_resume(drm_dev, false, false);
1251 drm_kms_helper_poll_enable(drm_dev);
1252 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1253 return 0;
1254}
1255
1256static int amdgpu_pmops_runtime_idle(struct device *dev)
1257{
1258 struct drm_device *drm_dev = dev_get_drvdata(dev);
1259 struct drm_crtc *crtc;
1260
1261 if (!amdgpu_device_is_px(drm_dev)) {
1262 pm_runtime_forbid(dev);
1263 return -EBUSY;
1264 }
1265
1266 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1267 if (crtc->enabled) {
1268 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1269 return -EBUSY;
1270 }
1271 }
1272
1273 pm_runtime_mark_last_busy(dev);
1274 pm_runtime_autosuspend(dev);
1275 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1276 return 1;
1277}
1278
1279long amdgpu_drm_ioctl(struct file *filp,
1280 unsigned int cmd, unsigned long arg)
1281{
1282 struct drm_file *file_priv = filp->private_data;
1283 struct drm_device *dev;
1284 long ret;
1285 dev = file_priv->minor->dev;
1286 ret = pm_runtime_get_sync(dev->dev);
1287 if (ret < 0)
1288 return ret;
1289
1290 ret = drm_ioctl(filp, cmd, arg);
1291
1292 pm_runtime_mark_last_busy(dev->dev);
1293 pm_runtime_put_autosuspend(dev->dev);
1294 return ret;
1295}
1296
1297static const struct dev_pm_ops amdgpu_pm_ops = {
1298 .suspend = amdgpu_pmops_suspend,
1299 .resume = amdgpu_pmops_resume,
1300 .freeze = amdgpu_pmops_freeze,
1301 .thaw = amdgpu_pmops_thaw,
1302 .poweroff = amdgpu_pmops_poweroff,
1303 .restore = amdgpu_pmops_restore,
1304 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1305 .runtime_resume = amdgpu_pmops_runtime_resume,
1306 .runtime_idle = amdgpu_pmops_runtime_idle,
1307};
1308
1309static int amdgpu_flush(struct file *f, fl_owner_t id)
1310{
1311 struct drm_file *file_priv = f->private_data;
1312 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1313 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1314
1315 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1316 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1317
1318 return timeout >= 0 ? 0 : timeout;
1319}
1320
1321static const struct file_operations amdgpu_driver_kms_fops = {
1322 .owner = THIS_MODULE,
1323 .open = drm_open,
1324 .flush = amdgpu_flush,
1325 .release = drm_release,
1326 .unlocked_ioctl = amdgpu_drm_ioctl,
1327 .mmap = amdgpu_mmap,
1328 .poll = drm_poll,
1329 .read = drm_read,
1330#ifdef CONFIG_COMPAT
1331 .compat_ioctl = amdgpu_kms_compat_ioctl,
1332#endif
1333};
1334
1335int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1336{
1337 struct drm_file *file;
1338
1339 if (!filp)
1340 return -EINVAL;
1341
1342 if (filp->f_op != &amdgpu_driver_kms_fops) {
1343 return -EINVAL;
1344 }
1345
1346 file = filp->private_data;
1347 *fpriv = file->driver_priv;
1348 return 0;
1349}
1350
1351int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
1352{
1353 char *input = amdgpu_lockup_timeout;
1354 char *timeout_setting = NULL;
1355 int index = 0;
1356 long timeout;
1357 int ret = 0;
1358
1359 /*
1360 * By default timeout for non compute jobs is 10000.
1361 * And there is no timeout enforced on compute jobs.
1362 */
1363 adev->gfx_timeout = msecs_to_jiffies(10000);
1364 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1365 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
1366
1367 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1368 while ((timeout_setting = strsep(&input, ",")) &&
1369 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1370 ret = kstrtol(timeout_setting, 0, &timeout);
1371 if (ret)
1372 return ret;
1373
1374 if (timeout == 0) {
1375 index++;
1376 continue;
1377 } else if (timeout < 0) {
1378 timeout = MAX_SCHEDULE_TIMEOUT;
1379 } else {
1380 timeout = msecs_to_jiffies(timeout);
1381 }
1382
1383 switch (index++) {
1384 case 0:
1385 adev->gfx_timeout = timeout;
1386 break;
1387 case 1:
1388 adev->compute_timeout = timeout;
1389 break;
1390 case 2:
1391 adev->sdma_timeout = timeout;
1392 break;
1393 case 3:
1394 adev->video_timeout = timeout;
1395 break;
1396 default:
1397 break;
1398 }
1399 }
1400 /*
1401 * There is only one value specified and
1402 * it should apply to all non-compute jobs.
1403 */
1404 if (index == 1)
1405 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1406 }
1407
1408 return ret;
1409}
1410
1411static bool
1412amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1413 bool in_vblank_irq, int *vpos, int *hpos,
1414 ktime_t *stime, ktime_t *etime,
1415 const struct drm_display_mode *mode)
1416{
1417 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1418 stime, etime, mode);
1419}
1420
1421static struct drm_driver kms_driver = {
1422 .driver_features =
1423 DRIVER_USE_AGP | DRIVER_ATOMIC |
1424 DRIVER_GEM |
1425 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1426 .load = amdgpu_driver_load_kms,
1427 .open = amdgpu_driver_open_kms,
1428 .postclose = amdgpu_driver_postclose_kms,
1429 .lastclose = amdgpu_driver_lastclose_kms,
1430 .unload = amdgpu_driver_unload_kms,
1431 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1432 .enable_vblank = amdgpu_enable_vblank_kms,
1433 .disable_vblank = amdgpu_disable_vblank_kms,
1434 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1435 .get_scanout_position = amdgpu_get_crtc_scanout_position,
1436 .irq_handler = amdgpu_irq_handler,
1437 .ioctls = amdgpu_ioctls_kms,
1438 .gem_free_object_unlocked = amdgpu_gem_object_free,
1439 .gem_open_object = amdgpu_gem_object_open,
1440 .gem_close_object = amdgpu_gem_object_close,
1441 .dumb_create = amdgpu_mode_dumb_create,
1442 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1443 .fops = &amdgpu_driver_kms_fops,
1444
1445 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1446 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1447 .gem_prime_export = amdgpu_gem_prime_export,
1448 .gem_prime_import = amdgpu_gem_prime_import,
1449 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1450 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1451 .gem_prime_vmap = amdgpu_gem_prime_vmap,
1452 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1453 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1454
1455 .name = DRIVER_NAME,
1456 .desc = DRIVER_DESC,
1457 .date = DRIVER_DATE,
1458 .major = KMS_DRIVER_MAJOR,
1459 .minor = KMS_DRIVER_MINOR,
1460 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1461};
1462
1463static struct pci_driver amdgpu_kms_pci_driver = {
1464 .name = DRIVER_NAME,
1465 .id_table = pciidlist,
1466 .probe = amdgpu_pci_probe,
1467 .remove = amdgpu_pci_remove,
1468 .shutdown = amdgpu_pci_shutdown,
1469 .driver.pm = &amdgpu_pm_ops,
1470};
1471
1472
1473
1474static int __init amdgpu_init(void)
1475{
1476 int r;
1477
1478 if (vgacon_text_force()) {
1479 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1480 return -EINVAL;
1481 }
1482
1483 r = amdgpu_sync_init();
1484 if (r)
1485 goto error_sync;
1486
1487 r = amdgpu_fence_slab_init();
1488 if (r)
1489 goto error_fence;
1490
1491 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1492 kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
1493 amdgpu_register_atpx_handler();
1494
1495 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1496 amdgpu_amdkfd_init();
1497
1498 /* let modprobe override vga console setting */
1499 return pci_register_driver(&amdgpu_kms_pci_driver);
1500
1501error_fence:
1502 amdgpu_sync_fini();
1503
1504error_sync:
1505 return r;
1506}
1507
1508static void __exit amdgpu_exit(void)
1509{
1510 amdgpu_amdkfd_fini();
1511 pci_unregister_driver(&amdgpu_kms_pci_driver);
1512 amdgpu_unregister_atpx_handler();
1513 amdgpu_sync_fini();
1514 amdgpu_fence_slab_fini();
1515 mmu_notifier_synchronize();
1516}
1517
1518module_init(amdgpu_init);
1519module_exit(amdgpu_exit);
1520
1521MODULE_AUTHOR(DRIVER_AUTHOR);
1522MODULE_DESCRIPTION(DRIVER_DESC);
1523MODULE_LICENSE("GPL and additional rights");