1/**
  2 * \file amdgpu_drv.c
  3 * AMD Amdgpu driver
  4 *
  5 * \author Gareth Hughes <gareth@valinux.com>
  6 */
  7
  8/*
  9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 10 * All Rights Reserved.
 11 *
 12 * Permission is hereby granted, free of charge, to any person obtaining a
 13 * copy of this software and associated documentation files (the "Software"),
 14 * to deal in the Software without restriction, including without limitation
 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 16 * and/or sell copies of the Software, and to permit persons to whom the
 17 * Software is furnished to do so, subject to the following conditions:
 18 *
 19 * The above copyright notice and this permission notice (including the next
 20 * paragraph) shall be included in all copies or substantial portions of the
 21 * Software.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 29 * OTHER DEALINGS IN THE SOFTWARE.
 30 */
 31
 32#include <drm/drmP.h>
 33#include <drm/amdgpu_drm.h>
 34#include <drm/drm_gem.h>
 35#include "amdgpu_drv.h"
 36
 37#include <drm/drm_pciids.h>
 38#include <linux/console.h>
 39#include <linux/module.h>
 40#include <linux/pm_runtime.h>
 41#include <linux/vga_switcheroo.h>
 42#include "drm_crtc_helper.h"
 43
 44#include "amdgpu.h"
 45#include "amdgpu_irq.h"
 46
 47#include "amdgpu_amdkfd.h"
 48
 49/*
 50 * KMS wrapper.
 51 * - 3.0.0 - initial driver
 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
 54 *           at the end of IBs.
 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
 57 * - 3.5.0 - Add support for new UVD_NO_OP register.
 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
 59 * - 3.7.0 - Add support for VCE clock list packet
 60 * - 3.8.0 - Add support raster config init in the kernel
 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
 62 */
 63#define KMS_DRIVER_MAJOR	3
 64#define KMS_DRIVER_MINOR	9
 65#define KMS_DRIVER_PATCHLEVEL	0
 66
 67int amdgpu_vram_limit = 0;
 68int amdgpu_gart_size = -1; /* auto */
 69int amdgpu_moverate = -1; /* auto */
 70int amdgpu_benchmarking = 0;
 71int amdgpu_testing = 0;
 72int amdgpu_audio = -1;
 73int amdgpu_disp_priority = 0;
 74int amdgpu_hw_i2c = 0;
 75int amdgpu_pcie_gen2 = -1;
 76int amdgpu_msi = -1;
 77int amdgpu_lockup_timeout = 0;
 78int amdgpu_dpm = -1;
 79int amdgpu_smc_load_fw = 1;
 80int amdgpu_aspm = -1;
 81int amdgpu_runtime_pm = -1;
 82unsigned amdgpu_ip_block_mask = 0xffffffff;
 83int amdgpu_bapm = -1;
 84int amdgpu_deep_color = 0;
 85int amdgpu_vm_size = 64;
 86int amdgpu_vm_block_size = -1;
 87int amdgpu_vm_fault_stop = 0;
 88int amdgpu_vm_debug = 0;
 89int amdgpu_vram_page_split = 1024;
 90int amdgpu_exp_hw_support = 0;
 91int amdgpu_sched_jobs = 32;
 92int amdgpu_sched_hw_submission = 2;
 93int amdgpu_powerplay = -1;
 94int amdgpu_no_evict = 0;
 95int amdgpu_direct_gma_size = 0;
 96unsigned amdgpu_pcie_gen_cap = 0;
 97unsigned amdgpu_pcie_lane_cap = 0;
 98unsigned amdgpu_cg_mask = 0xffffffff;
 99unsigned amdgpu_pg_mask = 0xffffffff;
100char *amdgpu_disable_cu = NULL;
101char *amdgpu_virtual_display = NULL;
102unsigned amdgpu_pp_feature_mask = 0xffffffff;
103
104MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
105module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
106
107MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
108module_param_named(gartsize, amdgpu_gart_size, int, 0600);
109
110MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
111module_param_named(moverate, amdgpu_moverate, int, 0600);
112
113MODULE_PARM_DESC(benchmark, "Run benchmark");
114module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
115
116MODULE_PARM_DESC(test, "Run tests");
117module_param_named(test, amdgpu_testing, int, 0444);
118
119MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
120module_param_named(audio, amdgpu_audio, int, 0444);
121
122MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
123module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
124
125MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
126module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
127
128MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
129module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
130
131MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
132module_param_named(msi, amdgpu_msi, int, 0444);
133
134MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
135module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
136
137MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
138module_param_named(dpm, amdgpu_dpm, int, 0444);
139
140MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
141module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
142
143MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
144module_param_named(aspm, amdgpu_aspm, int, 0444);
145
146MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
147module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
148
149MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
150module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
151
152MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
153module_param_named(bapm, amdgpu_bapm, int, 0444);
154
155MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
156module_param_named(deep_color, amdgpu_deep_color, int, 0444);
157
158MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
159module_param_named(vm_size, amdgpu_vm_size, int, 0444);
160
161MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
162module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
163
164MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
165module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
166
167MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
168module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
169
170MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)");
171module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
172
173MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
174module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
175
176MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
177module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
178
179MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
180module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
181
182MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
183module_param_named(powerplay, amdgpu_powerplay, int, 0444);
184
185MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
186module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
187
188MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
189module_param_named(no_evict, amdgpu_no_evict, int, 0444);
190
191MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
192module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
193
194MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
195module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
196
197MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
198module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
199
200MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
201module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
202
203MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
204module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
205
206MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
207module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
208
209MODULE_PARM_DESC(virtual_display,
210		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
211module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
212
213static const struct pci_device_id pciidlist[] = {
214#ifdef  CONFIG_DRM_AMDGPU_SI
215	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
216	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
217	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
218	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
219	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
220	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
221	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
222	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
223	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
224	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
225	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
226	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
227	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
228	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
229	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
230	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
231	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
232	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
233	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
234	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
235	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
236	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
237	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
238	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
239	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
240	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
241	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
242	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
243	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
244	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
245	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
246	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
247	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
248	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
249	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
250	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
251	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
252	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
253	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
254	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
255	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
256	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
257	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
258	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
259	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
260	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
261	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
262	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
263	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
264	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
265	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
266	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
267	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
268	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
269	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
270	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
271	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
272	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
273	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
274	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
275	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
276	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
277	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
278	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
279	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
280	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
281	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
282	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
283	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
284	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
285	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
286	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
287#endif
288#ifdef CONFIG_DRM_AMDGPU_CIK
289	/* Kaveri */
290	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
291	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
292	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
293	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
294	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
295	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
296	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
297	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
298	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
299	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
300	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
301	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
302	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
303	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
304	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
305	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
306	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
307	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
308	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
309	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
310	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
311	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
312	/* Bonaire */
313	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
314	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
315	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
316	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
317	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
318	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
319	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
320	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
321	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
322	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
323	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
324	/* Hawaii */
325	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
326	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
327	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
328	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
329	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
330	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
331	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
332	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
333	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
334	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
335	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
336	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
337	/* Kabini */
338	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
339	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
340	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
341	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
342	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
343	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
344	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
345	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
346	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
347	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
348	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
349	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
350	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
351	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
352	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
353	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
354	/* mullins */
355	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
356	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
357	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
358	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
359	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
360	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
361	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
362	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
363	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
364	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
365	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
366	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
367	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
368	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
369	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
370	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
371#endif
372	/* topaz */
373	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
374	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
375	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
376	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
377	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
378	/* tonga */
379	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
380	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
381	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
382	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
383	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
384	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
385	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
386	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
387	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
388	/* fiji */
389	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
390	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
391	/* carrizo */
392	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
393	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
394	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
395	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
396	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
397	/* stoney */
398	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
399	/* Polaris11 */
400	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
401	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
402	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
403	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
404	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
405	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
406	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
407	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
408	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
409	/* Polaris10 */
410	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
411	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
412	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
413	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
414	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
415	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
416	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
417	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
418	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
419	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
420	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
421	/* Polaris12 */
422	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
423	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
424	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
425	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
426	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
427	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
428	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
429
430	{0, 0, 0}
431};
432
433MODULE_DEVICE_TABLE(pci, pciidlist);
434
435static struct drm_driver kms_driver;
436
437static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
438{
439	struct apertures_struct *ap;
440	bool primary = false;
441
442	ap = alloc_apertures(1);
443	if (!ap)
444		return -ENOMEM;
445
446	ap->ranges[0].base = pci_resource_start(pdev, 0);
447	ap->ranges[0].size = pci_resource_len(pdev, 0);
448
449#ifdef CONFIG_X86
450	primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
451#endif
452	drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
453	kfree(ap);
454
455	return 0;
456}
457
458static int amdgpu_pci_probe(struct pci_dev *pdev,
459			    const struct pci_device_id *ent)
460{
461	unsigned long flags = ent->driver_data;
462	int ret;
463
464	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
465		DRM_INFO("This hardware requires experimental hardware support.\n"
466			 "See modparam exp_hw_support\n");
467		return -ENODEV;
468	}
469
470	/*
471	 * Initialize amdkfd before starting radeon. If it was not loaded yet,
472	 * defer radeon probing
473	 */
474	ret = amdgpu_amdkfd_init();
475	if (ret == -EPROBE_DEFER)
476		return ret;
477
478	/* Get rid of things like offb */
479	ret = amdgpu_kick_out_firmware_fb(pdev);
480	if (ret)
481		return ret;
482
483	return drm_get_pci_dev(pdev, ent, &kms_driver);
484}
485
486static void
487amdgpu_pci_remove(struct pci_dev *pdev)
488{
489	struct drm_device *dev = pci_get_drvdata(pdev);
490
491	drm_put_dev(dev);
492}
493
494static void
495amdgpu_pci_shutdown(struct pci_dev *pdev)
496{
497	struct drm_device *dev = pci_get_drvdata(pdev);
498	struct amdgpu_device *adev = dev->dev_private;
499
500	/* if we are running in a VM, make sure the device
501	 * torn down properly on reboot/shutdown.
502	 * unfortunately we can't detect certain
503	 * hypervisors so just do this all the time.
504	 */
505	amdgpu_suspend(adev);
506}
507
508static int amdgpu_pmops_suspend(struct device *dev)
509{
510	struct pci_dev *pdev = to_pci_dev(dev);
511
512	struct drm_device *drm_dev = pci_get_drvdata(pdev);
513	return amdgpu_device_suspend(drm_dev, true, true);
514}
515
516static int amdgpu_pmops_resume(struct device *dev)
517{
518	struct pci_dev *pdev = to_pci_dev(dev);
519	struct drm_device *drm_dev = pci_get_drvdata(pdev);
520
521	/* GPU comes up enabled by the bios on resume */
522	if (amdgpu_device_is_px(drm_dev)) {
523		pm_runtime_disable(dev);
524		pm_runtime_set_active(dev);
525		pm_runtime_enable(dev);
526	}
527
528	return amdgpu_device_resume(drm_dev, true, true);
529}
530
531static int amdgpu_pmops_freeze(struct device *dev)
532{
533	struct pci_dev *pdev = to_pci_dev(dev);
534
535	struct drm_device *drm_dev = pci_get_drvdata(pdev);
536	return amdgpu_device_suspend(drm_dev, false, true);
537}
538
539static int amdgpu_pmops_thaw(struct device *dev)
540{
541	struct pci_dev *pdev = to_pci_dev(dev);
542
543	struct drm_device *drm_dev = pci_get_drvdata(pdev);
544	return amdgpu_device_resume(drm_dev, false, true);
545}
546
547static int amdgpu_pmops_poweroff(struct device *dev)
548{
549	struct pci_dev *pdev = to_pci_dev(dev);
550
551	struct drm_device *drm_dev = pci_get_drvdata(pdev);
552	return amdgpu_device_suspend(drm_dev, true, true);
553}
554
555static int amdgpu_pmops_restore(struct device *dev)
556{
557	struct pci_dev *pdev = to_pci_dev(dev);
558
559	struct drm_device *drm_dev = pci_get_drvdata(pdev);
560	return amdgpu_device_resume(drm_dev, false, true);
561}
562
563static int amdgpu_pmops_runtime_suspend(struct device *dev)
564{
565	struct pci_dev *pdev = to_pci_dev(dev);
566	struct drm_device *drm_dev = pci_get_drvdata(pdev);
567	int ret;
568
569	if (!amdgpu_device_is_px(drm_dev)) {
570		pm_runtime_forbid(dev);
571		return -EBUSY;
572	}
573
574	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
575	drm_kms_helper_poll_disable(drm_dev);
576	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
577
578	ret = amdgpu_device_suspend(drm_dev, false, false);
579	pci_save_state(pdev);
580	pci_disable_device(pdev);
581	pci_ignore_hotplug(pdev);
582	if (amdgpu_is_atpx_hybrid())
583		pci_set_power_state(pdev, PCI_D3cold);
584	else if (!amdgpu_has_atpx_dgpu_power_cntl())
585		pci_set_power_state(pdev, PCI_D3hot);
586	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
587
588	return 0;
589}
590
591static int amdgpu_pmops_runtime_resume(struct device *dev)
592{
593	struct pci_dev *pdev = to_pci_dev(dev);
594	struct drm_device *drm_dev = pci_get_drvdata(pdev);
595	int ret;
596
597	if (!amdgpu_device_is_px(drm_dev))
598		return -EINVAL;
599
600	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
601
602	if (amdgpu_is_atpx_hybrid() ||
603	    !amdgpu_has_atpx_dgpu_power_cntl())
604		pci_set_power_state(pdev, PCI_D0);
605	pci_restore_state(pdev);
606	ret = pci_enable_device(pdev);
607	if (ret)
608		return ret;
609	pci_set_master(pdev);
610
611	ret = amdgpu_device_resume(drm_dev, false, false);
612	drm_kms_helper_poll_enable(drm_dev);
613	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
614	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
615	return 0;
616}
617
618static int amdgpu_pmops_runtime_idle(struct device *dev)
619{
620	struct pci_dev *pdev = to_pci_dev(dev);
621	struct drm_device *drm_dev = pci_get_drvdata(pdev);
622	struct drm_crtc *crtc;
623
624	if (!amdgpu_device_is_px(drm_dev)) {
625		pm_runtime_forbid(dev);
626		return -EBUSY;
627	}
628
629	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
630		if (crtc->enabled) {
631			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
632			return -EBUSY;
633		}
634	}
635
636	pm_runtime_mark_last_busy(dev);
637	pm_runtime_autosuspend(dev);
638	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
639	return 1;
640}
641
642long amdgpu_drm_ioctl(struct file *filp,
643		      unsigned int cmd, unsigned long arg)
644{
645	struct drm_file *file_priv = filp->private_data;
646	struct drm_device *dev;
647	long ret;
648	dev = file_priv->minor->dev;
649	ret = pm_runtime_get_sync(dev->dev);
650	if (ret < 0)
651		return ret;
652
653	ret = drm_ioctl(filp, cmd, arg);
654
655	pm_runtime_mark_last_busy(dev->dev);
656	pm_runtime_put_autosuspend(dev->dev);
657	return ret;
658}
659
660static const struct dev_pm_ops amdgpu_pm_ops = {
661	.suspend = amdgpu_pmops_suspend,
662	.resume = amdgpu_pmops_resume,
663	.freeze = amdgpu_pmops_freeze,
664	.thaw = amdgpu_pmops_thaw,
665	.poweroff = amdgpu_pmops_poweroff,
666	.restore = amdgpu_pmops_restore,
667	.runtime_suspend = amdgpu_pmops_runtime_suspend,
668	.runtime_resume = amdgpu_pmops_runtime_resume,
669	.runtime_idle = amdgpu_pmops_runtime_idle,
670};
671
672static const struct file_operations amdgpu_driver_kms_fops = {
673	.owner = THIS_MODULE,
674	.open = drm_open,
675	.release = drm_release,
676	.unlocked_ioctl = amdgpu_drm_ioctl,
677	.mmap = amdgpu_mmap,
678	.poll = drm_poll,
679	.read = drm_read,
680#ifdef CONFIG_COMPAT
681	.compat_ioctl = amdgpu_kms_compat_ioctl,
682#endif
683};
684
685static struct drm_driver kms_driver = {
686	.driver_features =
687	    DRIVER_USE_AGP |
688	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
689	    DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET,
690	.dev_priv_size = 0,
691	.load = amdgpu_driver_load_kms,
692	.open = amdgpu_driver_open_kms,
693	.preclose = amdgpu_driver_preclose_kms,
694	.postclose = amdgpu_driver_postclose_kms,
695	.lastclose = amdgpu_driver_lastclose_kms,
696	.set_busid = drm_pci_set_busid,
697	.unload = amdgpu_driver_unload_kms,
698	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
699	.enable_vblank = amdgpu_enable_vblank_kms,
700	.disable_vblank = amdgpu_disable_vblank_kms,
701	.get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
702	.get_scanout_position = amdgpu_get_crtc_scanoutpos,
703#if defined(CONFIG_DEBUG_FS)
704	.debugfs_init = amdgpu_debugfs_init,
705	.debugfs_cleanup = amdgpu_debugfs_cleanup,
706#endif
707	.irq_preinstall = amdgpu_irq_preinstall,
708	.irq_postinstall = amdgpu_irq_postinstall,
709	.irq_uninstall = amdgpu_irq_uninstall,
710	.irq_handler = amdgpu_irq_handler,
711	.ioctls = amdgpu_ioctls_kms,
712	.gem_free_object_unlocked = amdgpu_gem_object_free,
713	.gem_open_object = amdgpu_gem_object_open,
714	.gem_close_object = amdgpu_gem_object_close,
715	.dumb_create = amdgpu_mode_dumb_create,
716	.dumb_map_offset = amdgpu_mode_dumb_mmap,
717	.dumb_destroy = drm_gem_dumb_destroy,
718	.fops = &amdgpu_driver_kms_fops,
719
720	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
721	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
722	.gem_prime_export = amdgpu_gem_prime_export,
723	.gem_prime_import = drm_gem_prime_import,
724	.gem_prime_pin = amdgpu_gem_prime_pin,
725	.gem_prime_unpin = amdgpu_gem_prime_unpin,
726	.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
727	.gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
728	.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
729	.gem_prime_vmap = amdgpu_gem_prime_vmap,
730	.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
731
732	.name = DRIVER_NAME,
733	.desc = DRIVER_DESC,
734	.date = DRIVER_DATE,
735	.major = KMS_DRIVER_MAJOR,
736	.minor = KMS_DRIVER_MINOR,
737	.patchlevel = KMS_DRIVER_PATCHLEVEL,
738};
739
740static struct drm_driver *driver;
741static struct pci_driver *pdriver;
742
743static struct pci_driver amdgpu_kms_pci_driver = {
744	.name = DRIVER_NAME,
745	.id_table = pciidlist,
746	.probe = amdgpu_pci_probe,
747	.remove = amdgpu_pci_remove,
748	.shutdown = amdgpu_pci_shutdown,
749	.driver.pm = &amdgpu_pm_ops,
750};
751
752
753
754static int __init amdgpu_init(void)
755{
756	int r;
757
758	r = amdgpu_sync_init();
759	if (r)
760		goto error_sync;
761
762	r = amdgpu_fence_slab_init();
763	if (r)
764		goto error_fence;
765
766	r = amd_sched_fence_slab_init();
767	if (r)
768		goto error_sched;
769
770	if (vgacon_text_force()) {
771		DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
772		return -EINVAL;
773	}
774	DRM_INFO("amdgpu kernel modesetting enabled.\n");
775	driver = &kms_driver;
776	pdriver = &amdgpu_kms_pci_driver;
777	driver->num_ioctls = amdgpu_max_kms_ioctl;
778	amdgpu_register_atpx_handler();
779	/* let modprobe override vga console setting */
780	return drm_pci_init(driver, pdriver);
781
782error_sched:
783	amdgpu_fence_slab_fini();
784
785error_fence:
786	amdgpu_sync_fini();
787
788error_sync:
789	return r;
790}
791
792static void __exit amdgpu_exit(void)
793{
794	amdgpu_amdkfd_fini();
795	drm_pci_exit(driver, pdriver);
796	amdgpu_unregister_atpx_handler();
797	amdgpu_sync_fini();
798	amd_sched_fence_slab_fini();
799	amdgpu_fence_slab_fini();
800}
801
802module_init(amdgpu_init);
803module_exit(amdgpu_exit);
804
805MODULE_AUTHOR(DRIVER_AUTHOR);
806MODULE_DESCRIPTION(DRIVER_DESC);
807MODULE_LICENSE("GPL and additional rights");