Loading...
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/config-language.txt.
4#
5
6config OPENRISC
7 def_bool y
8 select OF
9 select OF_EARLY_FLATTREE
10 select HAVE_MEMBLOCK
11 select ARCH_WANT_OPTIONAL_GPIOLIB
12 select HAVE_ARCH_TRACEHOOK
13 select HAVE_GENERIC_HARDIRQS
14 select GENERIC_IRQ_CHIP
15 select GENERIC_IRQ_PROBE
16 select GENERIC_IRQ_SHOW
17 select GENERIC_IOMAP
18
19config MMU
20 def_bool y
21
22config WISHBONE_BUS_BIG_ENDIAN
23 def_bool y
24
25config SYMBOL_PREFIX
26 string
27 default ""
28
29config HAVE_DMA_ATTRS
30 def_bool y
31
32config UID16
33 def_bool y
34
35config RWSEM_GENERIC_SPINLOCK
36 def_bool y
37
38config RWSEM_XCHGADD_ALGORITHM
39 def_bool n
40
41config GENERIC_HWEIGHT
42 def_bool y
43
44config GENERIC_IOMAP
45 def_bool y
46
47config NO_IOPORT
48 def_bool y
49
50config GENERIC_GPIO
51 def_bool y
52
53config GENERIC_CLOCKEVENTS
54 def_bool y
55
56config TRACE_IRQFLAGS_SUPPORT
57 def_bool y
58
59# For now, use generic checksum functions
60#These can be reimplemented in assembly later if so inclined
61config GENERIC_CSUM
62 def_bool y
63
64config GENERIC_FIND_NEXT_BIT
65 def_bool y
66
67source "init/Kconfig"
68
69
70menu "Processor type and features"
71
72choice
73 prompt "Subarchitecture"
74 default OR1K_1200
75
76config OR1K_1200
77 bool "OR1200"
78 help
79 Generic OpenRISC 1200 architecture
80
81endchoice
82
83config OPENRISC_BUILTIN_DTB
84 string "Builtin DTB"
85 default ""
86
87menu "Class II Instructions"
88
89config OPENRISC_HAVE_INST_FF1
90 bool "Have instruction l.ff1"
91 default y
92 help
93 Select this if your implementation has the Class II instruction l.ff1
94
95config OPENRISC_HAVE_INST_FL1
96 bool "Have instruction l.fl1"
97 default y
98 help
99 Select this if your implementation has the Class II instruction l.fl1
100
101config OPENRISC_HAVE_INST_MUL
102 bool "Have instruction l.mul for hardware multiply"
103 default y
104 help
105 Select this if your implementation has a hardware multiply instruction
106
107config OPENRISC_HAVE_INST_DIV
108 bool "Have instruction l.div for hardware divide"
109 default y
110 help
111 Select this if your implementation has a hardware divide instruction
112endmenu
113
114
115source "kernel/time/Kconfig"
116source kernel/Kconfig.hz
117source kernel/Kconfig.preempt
118source "mm/Kconfig"
119
120config OPENRISC_NO_SPR_SR_DSX
121 bool "use SPR_SR_DSX software emulation" if OR1K_1200
122 default y
123 help
124 SPR_SR_DSX bit is status register bit indicating whether
125 the last exception has happened in delay slot.
126
127 OpenRISC architecture makes it optional to have it implemented
128 in hardware and the OR1200 does not have it.
129
130 Say N here if you know that your OpenRISC processor has
131 SPR_SR_DSX bit implemented. Say Y if you are unsure.
132
133config CMDLINE
134 string "Default kernel command string"
135 default ""
136 help
137 On some architectures there is currently no way for the boot loader
138 to pass arguments to the kernel. For these architectures, you should
139 supply some command-line options at build time by entering them
140 here.
141
142menu "Debugging options"
143
144config DEBUG_STACKOVERFLOW
145 bool "Check for kernel stack overflow"
146 default y
147 help
148 Make extra checks for space avaliable on stack in some
149 critical functions. This will cause kernel to run a bit slower,
150 but will catch most of kernel stack overruns and exit gracefuly.
151
152 Say Y if you are unsure.
153
154config JUMP_UPON_UNHANDLED_EXCEPTION
155 bool "Try to die gracefully"
156 default y
157 help
158 Now this puts kernel into infinite loop after first oops. Till
159 your kernel crashes this doesn't have any influence.
160
161 Say Y if you are unsure.
162
163config OPENRISC_EXCEPTION_DEBUG
164 bool "Print processor state at each exception"
165 default n
166 help
167 This option will make your kernel unusable for all but kernel
168 debugging.
169
170 Say N if you are unsure.
171
172config OPENRISC_ESR_EXCEPTION_BUG_CHECK
173 bool "Check for possible ESR exception bug"
174 default n
175 help
176 This option enables some checks that might expose some problems
177 in kernel.
178
179 Say N if you are unsure.
180
181endmenu
182
183endmenu
184
185menu "Executable file formats"
186
187source "fs/Kconfig.binfmt"
188
189endmenu
190
191source "net/Kconfig"
192
193source "drivers/Kconfig"
194
195source "fs/Kconfig"
196
197source "security/Kconfig"
198
199source "crypto/Kconfig"
200
201source "lib/Kconfig"
202
203menu "Kernel hacking"
204
205source "lib/Kconfig.debug"
206
207endmenu
1# SPDX-License-Identifier: GPL-2.0
2#
3# For a description of the syntax of this configuration file,
4# see Documentation/kbuild/kconfig-language.rst.
5#
6
7config OPENRISC
8 def_bool y
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
11 select OF
12 select OF_EARLY_FLATTREE
13 select IRQ_DOMAIN
14 select HANDLE_DOMAIN_IRQ
15 select GPIOLIB
16 select HAVE_ARCH_TRACEHOOK
17 select SPARSE_IRQ
18 select GENERIC_IRQ_CHIP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_IOMAP
22 select GENERIC_CPU_DEVICES
23 select HAVE_UID16
24 select GENERIC_ATOMIC64
25 select GENERIC_CLOCKEVENTS
26 select GENERIC_CLOCKEVENTS_BROADCAST
27 select GENERIC_STRNCPY_FROM_USER
28 select GENERIC_STRNLEN_USER
29 select GENERIC_SMP_IDLE_THREAD
30 select MODULES_USE_ELF_RELA
31 select HAVE_DEBUG_STACKOVERFLOW
32 select OR1K_PIC
33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
34 select ARCH_USE_QUEUED_SPINLOCKS
35 select ARCH_USE_QUEUED_RWLOCKS
36 select OMPIC if SMP
37 select ARCH_WANT_FRAME_POINTERS
38 select GENERIC_IRQ_MULTI_HANDLER
39 select MMU_GATHER_NO_RANGE if MMU
40
41config CPU_BIG_ENDIAN
42 def_bool y
43
44config MMU
45 def_bool y
46
47config GENERIC_HWEIGHT
48 def_bool y
49
50config NO_IOPORT_MAP
51 def_bool y
52
53config TRACE_IRQFLAGS_SUPPORT
54 def_bool y
55
56# For now, use generic checksum functions
57#These can be reimplemented in assembly later if so inclined
58config GENERIC_CSUM
59 def_bool y
60
61config STACKTRACE_SUPPORT
62 def_bool y
63
64config LOCKDEP_SUPPORT
65 def_bool y
66
67menu "Processor type and features"
68
69choice
70 prompt "Subarchitecture"
71 default OR1K_1200
72
73config OR1K_1200
74 bool "OR1200"
75 help
76 Generic OpenRISC 1200 architecture
77
78endchoice
79
80config DCACHE_WRITETHROUGH
81 bool "Have write through data caches"
82 default n
83 help
84 Select this if your implementation features write through data caches.
85 Selecting 'N' here will allow the kernel to force flushing of data
86 caches at relevant times. Most OpenRISC implementations support write-
87 through data caches.
88
89 If unsure say N here
90
91config OPENRISC_BUILTIN_DTB
92 string "Builtin DTB"
93 default ""
94
95menu "Class II Instructions"
96
97config OPENRISC_HAVE_INST_FF1
98 bool "Have instruction l.ff1"
99 default y
100 help
101 Select this if your implementation has the Class II instruction l.ff1
102
103config OPENRISC_HAVE_INST_FL1
104 bool "Have instruction l.fl1"
105 default y
106 help
107 Select this if your implementation has the Class II instruction l.fl1
108
109config OPENRISC_HAVE_INST_MUL
110 bool "Have instruction l.mul for hardware multiply"
111 default y
112 help
113 Select this if your implementation has a hardware multiply instruction
114
115config OPENRISC_HAVE_INST_DIV
116 bool "Have instruction l.div for hardware divide"
117 default y
118 help
119 Select this if your implementation has a hardware divide instruction
120endmenu
121
122config NR_CPUS
123 int "Maximum number of CPUs (2-32)"
124 range 2 32
125 depends on SMP
126 default "2"
127
128config SMP
129 bool "Symmetric Multi-Processing support"
130 help
131 This enables support for systems with more than one CPU. If you have
132 a system with only one CPU, say N. If you have a system with more
133 than one CPU, say Y.
134
135 If you don't know what to do here, say N.
136
137source "kernel/Kconfig.hz"
138
139config OPENRISC_NO_SPR_SR_DSX
140 bool "use SPR_SR_DSX software emulation" if OR1K_1200
141 default y
142 help
143 SPR_SR_DSX bit is status register bit indicating whether
144 the last exception has happened in delay slot.
145
146 OpenRISC architecture makes it optional to have it implemented
147 in hardware and the OR1200 does not have it.
148
149 Say N here if you know that your OpenRISC processor has
150 SPR_SR_DSX bit implemented. Say Y if you are unsure.
151
152config OPENRISC_HAVE_SHADOW_GPRS
153 bool "Support for shadow gpr files" if !SMP
154 default y if SMP
155 help
156 Say Y here if your OpenRISC processor features shadowed
157 register files. They will in such case be used as a
158 scratch reg storage on exception entry.
159
160 On SMP systems, this feature is mandatory.
161 On a unicore system it's safe to say N here if you are unsure.
162
163config CMDLINE
164 string "Default kernel command string"
165 default ""
166 help
167 On some architectures there is currently no way for the boot loader
168 to pass arguments to the kernel. For these architectures, you should
169 supply some command-line options at build time by entering them
170 here.
171
172menu "Debugging options"
173
174config JUMP_UPON_UNHANDLED_EXCEPTION
175 bool "Try to die gracefully"
176 default y
177 help
178 Now this puts kernel into infinite loop after first oops. Till
179 your kernel crashes this doesn't have any influence.
180
181 Say Y if you are unsure.
182
183config OPENRISC_ESR_EXCEPTION_BUG_CHECK
184 bool "Check for possible ESR exception bug"
185 default n
186 help
187 This option enables some checks that might expose some problems
188 in kernel.
189
190 Say N if you are unsure.
191
192endmenu
193
194endmenu