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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36/* conversion functions */
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71/* forward declaration of functions */
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74/**
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
77 *
78 * Return true if we're using DMA.
79 *
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
84 * not 32bit aligned.
85 *
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
90 *
91 * g_using_dma is set depending on dts flag.
92 */
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98/*
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
101 *
102 * Return true if we're using descriptor DMA.
103 */
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109/**
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
112 *
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 */
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
122 } else {
123 hs_ep->frame_overrun = false;
124 }
125}
126
127/**
128 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
129 * by one.
130 * @hs_ep: The endpoint.
131 *
132 * This function used in service interval based scheduling flow to calculate
133 * descriptor frame number filed value. For service interval mode frame
134 * number in descriptor should point to last (u)frame in the interval.
135 *
136 */
137static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
138{
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
141 else
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
143}
144
145/**
146 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
147 * @hsotg: The device state
148 * @ints: A bitmask of the interrupts to enable
149 */
150static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
151{
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
153 u32 new_gsintmsk;
154
155 new_gsintmsk = gsintmsk | ints;
156
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
160 }
161}
162
163/**
164 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
165 * @hsotg: The device state
166 * @ints: A bitmask of the interrupts to enable
167 */
168static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
169{
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
171 u32 new_gsintmsk;
172
173 new_gsintmsk = gsintmsk & ~ints;
174
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
177}
178
179/**
180 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
181 * @hsotg: The device state
182 * @ep: The endpoint index
183 * @dir_in: True if direction is in.
184 * @en: The enable value, true to enable
185 *
186 * Set or clear the mask for an individual endpoint's interrupt
187 * request.
188 */
189static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
191 unsigned int en)
192{
193 unsigned long flags;
194 u32 bit = 1 << ep;
195 u32 daint;
196
197 if (!dir_in)
198 bit <<= 16;
199
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
202 if (en)
203 daint |= bit;
204 else
205 daint &= ~bit;
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
208}
209
210/**
211 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
212 *
213 * @hsotg: Programming view of the DWC_otg controller
214 */
215int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
216{
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218 /* In dedicated FIFO mode we need count of IN EPs */
219 return hsotg->hw_params.num_dev_in_eps;
220 else
221 /* In shared FIFO mode we need count of Periodic IN EPs */
222 return hsotg->hw_params.num_dev_perio_in_ep;
223}
224
225/**
226 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
227 * device mode TX FIFOs
228 *
229 * @hsotg: Programming view of the DWC_otg controller
230 */
231int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
232{
233 int addr;
234 int tx_addr_max;
235 u32 np_tx_fifo_size;
236
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
239
240 /* Get Endpoint Info Control block size in DWORDs. */
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
242
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
245 return 0;
246
247 return tx_addr_max - addr;
248}
249
250/**
251 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
252 *
253 * @hsotg: Programming view of the DWC_otg controller
254 *
255 */
256static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
257{
258 u32 gintsts2;
259 u32 gintmsk2;
260
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
263
264 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
265 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
266 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
267 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
268 }
269}
270
271/**
272 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
273 * TX FIFOs
274 *
275 * @hsotg: Programming view of the DWC_otg controller
276 */
277int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
278{
279 int tx_fifo_count;
280 int tx_fifo_depth;
281
282 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
283
284 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
285
286 if (!tx_fifo_count)
287 return tx_fifo_depth;
288 else
289 return tx_fifo_depth / tx_fifo_count;
290}
291
292/**
293 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
294 * @hsotg: The device instance.
295 */
296static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
297{
298 unsigned int ep;
299 unsigned int addr;
300 int timeout;
301
302 u32 val;
303 u32 *txfsz = hsotg->params.g_tx_fifo_size;
304
305 /* Reset fifo map if not correctly cleared during previous session */
306 WARN_ON(hsotg->fifo_map);
307 hsotg->fifo_map = 0;
308
309 /* set RX/NPTX FIFO sizes */
310 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
311 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
312 FIFOSIZE_STARTADDR_SHIFT) |
313 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
314 GNPTXFSIZ);
315
316 /*
317 * arange all the rest of the TX FIFOs, as some versions of this
318 * block have overlapping default addresses. This also ensures
319 * that if the settings have been changed, then they are set to
320 * known values.
321 */
322
323 /* start at the end of the GNPTXFSIZ, rounded up */
324 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
325
326 /*
327 * Configure fifos sizes from provided configuration and assign
328 * them to endpoints dynamically according to maxpacket size value of
329 * given endpoint.
330 */
331 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
332 if (!txfsz[ep])
333 continue;
334 val = addr;
335 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
336 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
337 "insufficient fifo memory");
338 addr += txfsz[ep];
339
340 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
341 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
342 }
343
344 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
345 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
346 GDFIFOCFG);
347 /*
348 * according to p428 of the design guide, we need to ensure that
349 * all fifos are flushed before continuing
350 */
351
352 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
353 GRSTCTL_RXFFLSH, GRSTCTL);
354
355 /* wait until the fifos are both flushed */
356 timeout = 100;
357 while (1) {
358 val = dwc2_readl(hsotg, GRSTCTL);
359
360 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
361 break;
362
363 if (--timeout == 0) {
364 dev_err(hsotg->dev,
365 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
366 __func__, val);
367 break;
368 }
369
370 udelay(1);
371 }
372
373 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
374}
375
376/**
377 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
378 * @ep: USB endpoint to allocate request for.
379 * @flags: Allocation flags
380 *
381 * Allocate a new USB request structure appropriate for the specified endpoint
382 */
383static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
384 gfp_t flags)
385{
386 struct dwc2_hsotg_req *req;
387
388 req = kzalloc(sizeof(*req), flags);
389 if (!req)
390 return NULL;
391
392 INIT_LIST_HEAD(&req->queue);
393
394 return &req->req;
395}
396
397/**
398 * is_ep_periodic - return true if the endpoint is in periodic mode.
399 * @hs_ep: The endpoint to query.
400 *
401 * Returns true if the endpoint is in periodic mode, meaning it is being
402 * used for an Interrupt or ISO transfer.
403 */
404static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
405{
406 return hs_ep->periodic;
407}
408
409/**
410 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
411 * @hsotg: The device state.
412 * @hs_ep: The endpoint for the request
413 * @hs_req: The request being processed.
414 *
415 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
416 * of a request to ensure the buffer is ready for access by the caller.
417 */
418static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
419 struct dwc2_hsotg_ep *hs_ep,
420 struct dwc2_hsotg_req *hs_req)
421{
422 struct usb_request *req = &hs_req->req;
423
424 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
425}
426
427/*
428 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
429 * for Control endpoint
430 * @hsotg: The device state.
431 *
432 * This function will allocate 4 descriptor chains for EP 0: 2 for
433 * Setup stage, per one for IN and OUT data/status transactions.
434 */
435static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
436{
437 hsotg->setup_desc[0] =
438 dmam_alloc_coherent(hsotg->dev,
439 sizeof(struct dwc2_dma_desc),
440 &hsotg->setup_desc_dma[0],
441 GFP_KERNEL);
442 if (!hsotg->setup_desc[0])
443 goto fail;
444
445 hsotg->setup_desc[1] =
446 dmam_alloc_coherent(hsotg->dev,
447 sizeof(struct dwc2_dma_desc),
448 &hsotg->setup_desc_dma[1],
449 GFP_KERNEL);
450 if (!hsotg->setup_desc[1])
451 goto fail;
452
453 hsotg->ctrl_in_desc =
454 dmam_alloc_coherent(hsotg->dev,
455 sizeof(struct dwc2_dma_desc),
456 &hsotg->ctrl_in_desc_dma,
457 GFP_KERNEL);
458 if (!hsotg->ctrl_in_desc)
459 goto fail;
460
461 hsotg->ctrl_out_desc =
462 dmam_alloc_coherent(hsotg->dev,
463 sizeof(struct dwc2_dma_desc),
464 &hsotg->ctrl_out_desc_dma,
465 GFP_KERNEL);
466 if (!hsotg->ctrl_out_desc)
467 goto fail;
468
469 return 0;
470
471fail:
472 return -ENOMEM;
473}
474
475/**
476 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
477 * @hsotg: The controller state.
478 * @hs_ep: The endpoint we're going to write for.
479 * @hs_req: The request to write data for.
480 *
481 * This is called when the TxFIFO has some space in it to hold a new
482 * transmission and we have something to give it. The actual setup of
483 * the data size is done elsewhere, so all we have to do is to actually
484 * write the data.
485 *
486 * The return value is zero if there is more space (or nothing was done)
487 * otherwise -ENOSPC is returned if the FIFO space was used up.
488 *
489 * This routine is only needed for PIO
490 */
491static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
492 struct dwc2_hsotg_ep *hs_ep,
493 struct dwc2_hsotg_req *hs_req)
494{
495 bool periodic = is_ep_periodic(hs_ep);
496 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
497 int buf_pos = hs_req->req.actual;
498 int to_write = hs_ep->size_loaded;
499 void *data;
500 int can_write;
501 int pkt_round;
502 int max_transfer;
503
504 to_write -= (buf_pos - hs_ep->last_load);
505
506 /* if there's nothing to write, get out early */
507 if (to_write == 0)
508 return 0;
509
510 if (periodic && !hsotg->dedicated_fifos) {
511 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
512 int size_left;
513 int size_done;
514
515 /*
516 * work out how much data was loaded so we can calculate
517 * how much data is left in the fifo.
518 */
519
520 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
521
522 /*
523 * if shared fifo, we cannot write anything until the
524 * previous data has been completely sent.
525 */
526 if (hs_ep->fifo_load != 0) {
527 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
528 return -ENOSPC;
529 }
530
531 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
532 __func__, size_left,
533 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
534
535 /* how much of the data has moved */
536 size_done = hs_ep->size_loaded - size_left;
537
538 /* how much data is left in the fifo */
539 can_write = hs_ep->fifo_load - size_done;
540 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
541 __func__, can_write);
542
543 can_write = hs_ep->fifo_size - can_write;
544 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
545 __func__, can_write);
546
547 if (can_write <= 0) {
548 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
549 return -ENOSPC;
550 }
551 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
552 can_write = dwc2_readl(hsotg,
553 DTXFSTS(hs_ep->fifo_index));
554
555 can_write &= 0xffff;
556 can_write *= 4;
557 } else {
558 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
559 dev_dbg(hsotg->dev,
560 "%s: no queue slots available (0x%08x)\n",
561 __func__, gnptxsts);
562
563 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
564 return -ENOSPC;
565 }
566
567 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
568 can_write *= 4; /* fifo size is in 32bit quantities. */
569 }
570
571 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
572
573 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
574 __func__, gnptxsts, can_write, to_write, max_transfer);
575
576 /*
577 * limit to 512 bytes of data, it seems at least on the non-periodic
578 * FIFO, requests of >512 cause the endpoint to get stuck with a
579 * fragment of the end of the transfer in it.
580 */
581 if (can_write > 512 && !periodic)
582 can_write = 512;
583
584 /*
585 * limit the write to one max-packet size worth of data, but allow
586 * the transfer to return that it did not run out of fifo space
587 * doing it.
588 */
589 if (to_write > max_transfer) {
590 to_write = max_transfer;
591
592 /* it's needed only when we do not use dedicated fifos */
593 if (!hsotg->dedicated_fifos)
594 dwc2_hsotg_en_gsint(hsotg,
595 periodic ? GINTSTS_PTXFEMP :
596 GINTSTS_NPTXFEMP);
597 }
598
599 /* see if we can write data */
600
601 if (to_write > can_write) {
602 to_write = can_write;
603 pkt_round = to_write % max_transfer;
604
605 /*
606 * Round the write down to an
607 * exact number of packets.
608 *
609 * Note, we do not currently check to see if we can ever
610 * write a full packet or not to the FIFO.
611 */
612
613 if (pkt_round)
614 to_write -= pkt_round;
615
616 /*
617 * enable correct FIFO interrupt to alert us when there
618 * is more room left.
619 */
620
621 /* it's needed only when we do not use dedicated fifos */
622 if (!hsotg->dedicated_fifos)
623 dwc2_hsotg_en_gsint(hsotg,
624 periodic ? GINTSTS_PTXFEMP :
625 GINTSTS_NPTXFEMP);
626 }
627
628 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
629 to_write, hs_req->req.length, can_write, buf_pos);
630
631 if (to_write <= 0)
632 return -ENOSPC;
633
634 hs_req->req.actual = buf_pos + to_write;
635 hs_ep->total_data += to_write;
636
637 if (periodic)
638 hs_ep->fifo_load += to_write;
639
640 to_write = DIV_ROUND_UP(to_write, 4);
641 data = hs_req->req.buf + buf_pos;
642
643 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
644
645 return (to_write >= can_write) ? -ENOSPC : 0;
646}
647
648/**
649 * get_ep_limit - get the maximum data legnth for this endpoint
650 * @hs_ep: The endpoint
651 *
652 * Return the maximum data that can be queued in one go on a given endpoint
653 * so that transfers that are too long can be split.
654 */
655static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
656{
657 int index = hs_ep->index;
658 unsigned int maxsize;
659 unsigned int maxpkt;
660
661 if (index != 0) {
662 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
663 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
664 } else {
665 maxsize = 64 + 64;
666 if (hs_ep->dir_in)
667 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
668 else
669 maxpkt = 2;
670 }
671
672 /* we made the constant loading easier above by using +1 */
673 maxpkt--;
674 maxsize--;
675
676 /*
677 * constrain by packet count if maxpkts*pktsize is greater
678 * than the length register size.
679 */
680
681 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
682 maxsize = maxpkt * hs_ep->ep.maxpacket;
683
684 return maxsize;
685}
686
687/**
688 * dwc2_hsotg_read_frameno - read current frame number
689 * @hsotg: The device instance
690 *
691 * Return the current frame number
692 */
693static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
694{
695 u32 dsts;
696
697 dsts = dwc2_readl(hsotg, DSTS);
698 dsts &= DSTS_SOFFN_MASK;
699 dsts >>= DSTS_SOFFN_SHIFT;
700
701 return dsts;
702}
703
704/**
705 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
706 * DMA descriptor chain prepared for specific endpoint
707 * @hs_ep: The endpoint
708 *
709 * Return the maximum data that can be queued in one go on a given endpoint
710 * depending on its descriptor chain capacity so that transfers that
711 * are too long can be split.
712 */
713static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
714{
715 int is_isoc = hs_ep->isochronous;
716 unsigned int maxsize;
717
718 if (is_isoc)
719 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
720 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
721 MAX_DMA_DESC_NUM_HS_ISOC;
722 else
723 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
724
725 return maxsize;
726}
727
728/*
729 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
730 * @hs_ep: The endpoint
731 * @mask: RX/TX bytes mask to be defined
732 *
733 * Returns maximum data payload for one descriptor after analyzing endpoint
734 * characteristics.
735 * DMA descriptor transfer bytes limit depends on EP type:
736 * Control out - MPS,
737 * Isochronous - descriptor rx/tx bytes bitfield limit,
738 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
739 * have concatenations from various descriptors within one packet.
740 *
741 * Selects corresponding mask for RX/TX bytes as well.
742 */
743static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
744{
745 u32 mps = hs_ep->ep.maxpacket;
746 int dir_in = hs_ep->dir_in;
747 u32 desc_size = 0;
748
749 if (!hs_ep->index && !dir_in) {
750 desc_size = mps;
751 *mask = DEV_DMA_NBYTES_MASK;
752 } else if (hs_ep->isochronous) {
753 if (dir_in) {
754 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
755 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
756 } else {
757 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
758 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
759 }
760 } else {
761 desc_size = DEV_DMA_NBYTES_LIMIT;
762 *mask = DEV_DMA_NBYTES_MASK;
763
764 /* Round down desc_size to be mps multiple */
765 desc_size -= desc_size % mps;
766 }
767
768 return desc_size;
769}
770
771static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
772 struct dwc2_dma_desc **desc,
773 dma_addr_t dma_buff,
774 unsigned int len,
775 bool true_last)
776{
777 int dir_in = hs_ep->dir_in;
778 u32 mps = hs_ep->ep.maxpacket;
779 u32 maxsize = 0;
780 u32 offset = 0;
781 u32 mask = 0;
782 int i;
783
784 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
785
786 hs_ep->desc_count = (len / maxsize) +
787 ((len % maxsize) ? 1 : 0);
788 if (len == 0)
789 hs_ep->desc_count = 1;
790
791 for (i = 0; i < hs_ep->desc_count; ++i) {
792 (*desc)->status = 0;
793 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
794 << DEV_DMA_BUFF_STS_SHIFT);
795
796 if (len > maxsize) {
797 if (!hs_ep->index && !dir_in)
798 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
799
800 (*desc)->status |=
801 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
802 (*desc)->buf = dma_buff + offset;
803
804 len -= maxsize;
805 offset += maxsize;
806 } else {
807 if (true_last)
808 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
809
810 if (dir_in)
811 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
812 ((hs_ep->send_zlp && true_last) ?
813 DEV_DMA_SHORT : 0);
814
815 (*desc)->status |=
816 len << DEV_DMA_NBYTES_SHIFT & mask;
817 (*desc)->buf = dma_buff + offset;
818 }
819
820 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
821 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
822 << DEV_DMA_BUFF_STS_SHIFT);
823 (*desc)++;
824 }
825}
826
827/*
828 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
829 * @hs_ep: The endpoint
830 * @ureq: Request to transfer
831 * @offset: offset in bytes
832 * @len: Length of the transfer
833 *
834 * This function will iterate over descriptor chain and fill its entries
835 * with corresponding information based on transfer data.
836 */
837static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
838 dma_addr_t dma_buff,
839 unsigned int len)
840{
841 struct usb_request *ureq = NULL;
842 struct dwc2_dma_desc *desc = hs_ep->desc_list;
843 struct scatterlist *sg;
844 int i;
845 u8 desc_count = 0;
846
847 if (hs_ep->req)
848 ureq = &hs_ep->req->req;
849
850 /* non-DMA sg buffer */
851 if (!ureq || !ureq->num_sgs) {
852 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
853 dma_buff, len, true);
854 return;
855 }
856
857 /* DMA sg buffer */
858 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
859 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
860 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
861 sg_is_last(sg));
862 desc_count += hs_ep->desc_count;
863 }
864
865 hs_ep->desc_count = desc_count;
866}
867
868/*
869 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
870 * @hs_ep: The isochronous endpoint.
871 * @dma_buff: usb requests dma buffer.
872 * @len: usb request transfer length.
873 *
874 * Fills next free descriptor with the data of the arrived usb request,
875 * frame info, sets Last and IOC bits increments next_desc. If filled
876 * descriptor is not the first one, removes L bit from the previous descriptor
877 * status.
878 */
879static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
880 dma_addr_t dma_buff, unsigned int len)
881{
882 struct dwc2_dma_desc *desc;
883 struct dwc2_hsotg *hsotg = hs_ep->parent;
884 u32 index;
885 u32 maxsize = 0;
886 u32 mask = 0;
887 u8 pid = 0;
888
889 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
890
891 index = hs_ep->next_desc;
892 desc = &hs_ep->desc_list[index];
893
894 /* Check if descriptor chain full */
895 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
896 DEV_DMA_BUFF_STS_HREADY) {
897 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
898 return 1;
899 }
900
901 /* Clear L bit of previous desc if more than one entries in the chain */
902 if (hs_ep->next_desc)
903 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
904
905 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
906 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
907
908 desc->status = 0;
909 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
910
911 desc->buf = dma_buff;
912 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
913 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
914
915 if (hs_ep->dir_in) {
916 if (len)
917 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
918 else
919 pid = 1;
920 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
921 DEV_DMA_ISOC_PID_MASK) |
922 ((len % hs_ep->ep.maxpacket) ?
923 DEV_DMA_SHORT : 0) |
924 ((hs_ep->target_frame <<
925 DEV_DMA_ISOC_FRNUM_SHIFT) &
926 DEV_DMA_ISOC_FRNUM_MASK);
927 }
928
929 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
930 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
931
932 /* Increment frame number by interval for IN */
933 if (hs_ep->dir_in)
934 dwc2_gadget_incr_frame_num(hs_ep);
935
936 /* Update index of last configured entry in the chain */
937 hs_ep->next_desc++;
938 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
939 hs_ep->next_desc = 0;
940
941 return 0;
942}
943
944/*
945 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
946 * @hs_ep: The isochronous endpoint.
947 *
948 * Prepare descriptor chain for isochronous endpoints. Afterwards
949 * write DMA address to HW and enable the endpoint.
950 */
951static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
952{
953 struct dwc2_hsotg *hsotg = hs_ep->parent;
954 struct dwc2_hsotg_req *hs_req, *treq;
955 int index = hs_ep->index;
956 int ret;
957 int i;
958 u32 dma_reg;
959 u32 depctl;
960 u32 ctrl;
961 struct dwc2_dma_desc *desc;
962
963 if (list_empty(&hs_ep->queue)) {
964 hs_ep->target_frame = TARGET_FRAME_INITIAL;
965 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
966 return;
967 }
968
969 /* Initialize descriptor chain by Host Busy status */
970 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
971 desc = &hs_ep->desc_list[i];
972 desc->status = 0;
973 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
974 << DEV_DMA_BUFF_STS_SHIFT);
975 }
976
977 hs_ep->next_desc = 0;
978 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
979 dma_addr_t dma_addr = hs_req->req.dma;
980
981 if (hs_req->req.num_sgs) {
982 WARN_ON(hs_req->req.num_sgs > 1);
983 dma_addr = sg_dma_address(hs_req->req.sg);
984 }
985 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
986 hs_req->req.length);
987 if (ret)
988 break;
989 }
990
991 hs_ep->compl_desc = 0;
992 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
993 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
994
995 /* write descriptor chain address to control register */
996 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
997
998 ctrl = dwc2_readl(hsotg, depctl);
999 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1000 dwc2_writel(hsotg, ctrl, depctl);
1001}
1002
1003/**
1004 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1005 * @hsotg: The controller state.
1006 * @hs_ep: The endpoint to process a request for
1007 * @hs_req: The request to start.
1008 * @continuing: True if we are doing more for the current request.
1009 *
1010 * Start the given request running by setting the endpoint registers
1011 * appropriately, and writing any data to the FIFOs.
1012 */
1013static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1014 struct dwc2_hsotg_ep *hs_ep,
1015 struct dwc2_hsotg_req *hs_req,
1016 bool continuing)
1017{
1018 struct usb_request *ureq = &hs_req->req;
1019 int index = hs_ep->index;
1020 int dir_in = hs_ep->dir_in;
1021 u32 epctrl_reg;
1022 u32 epsize_reg;
1023 u32 epsize;
1024 u32 ctrl;
1025 unsigned int length;
1026 unsigned int packets;
1027 unsigned int maxreq;
1028 unsigned int dma_reg;
1029
1030 if (index != 0) {
1031 if (hs_ep->req && !continuing) {
1032 dev_err(hsotg->dev, "%s: active request\n", __func__);
1033 WARN_ON(1);
1034 return;
1035 } else if (hs_ep->req != hs_req && continuing) {
1036 dev_err(hsotg->dev,
1037 "%s: continue different req\n", __func__);
1038 WARN_ON(1);
1039 return;
1040 }
1041 }
1042
1043 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1044 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1045 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1046
1047 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1048 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1049 hs_ep->dir_in ? "in" : "out");
1050
1051 /* If endpoint is stalled, we will restart request later */
1052 ctrl = dwc2_readl(hsotg, epctrl_reg);
1053
1054 if (index && ctrl & DXEPCTL_STALL) {
1055 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1056 return;
1057 }
1058
1059 length = ureq->length - ureq->actual;
1060 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1061 ureq->length, ureq->actual);
1062
1063 if (!using_desc_dma(hsotg))
1064 maxreq = get_ep_limit(hs_ep);
1065 else
1066 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1067
1068 if (length > maxreq) {
1069 int round = maxreq % hs_ep->ep.maxpacket;
1070
1071 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1072 __func__, length, maxreq, round);
1073
1074 /* round down to multiple of packets */
1075 if (round)
1076 maxreq -= round;
1077
1078 length = maxreq;
1079 }
1080
1081 if (length)
1082 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1083 else
1084 packets = 1; /* send one packet if length is zero. */
1085
1086 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1087 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1088 return;
1089 }
1090
1091 if (dir_in && index != 0)
1092 if (hs_ep->isochronous)
1093 epsize = DXEPTSIZ_MC(packets);
1094 else
1095 epsize = DXEPTSIZ_MC(1);
1096 else
1097 epsize = 0;
1098
1099 /*
1100 * zero length packet should be programmed on its own and should not
1101 * be counted in DIEPTSIZ.PktCnt with other packets.
1102 */
1103 if (dir_in && ureq->zero && !continuing) {
1104 /* Test if zlp is actually required. */
1105 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1106 !(ureq->length % hs_ep->ep.maxpacket))
1107 hs_ep->send_zlp = 1;
1108 }
1109
1110 epsize |= DXEPTSIZ_PKTCNT(packets);
1111 epsize |= DXEPTSIZ_XFERSIZE(length);
1112
1113 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1114 __func__, packets, length, ureq->length, epsize, epsize_reg);
1115
1116 /* store the request as the current one we're doing */
1117 hs_ep->req = hs_req;
1118
1119 if (using_desc_dma(hsotg)) {
1120 u32 offset = 0;
1121 u32 mps = hs_ep->ep.maxpacket;
1122
1123 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1124 if (!dir_in) {
1125 if (!index)
1126 length = mps;
1127 else if (length % mps)
1128 length += (mps - (length % mps));
1129 }
1130
1131 /*
1132 * If more data to send, adjust DMA for EP0 out data stage.
1133 * ureq->dma stays unchanged, hence increment it by already
1134 * passed passed data count before starting new transaction.
1135 */
1136 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1137 continuing)
1138 offset = ureq->actual;
1139
1140 /* Fill DDMA chain entries */
1141 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1142 length);
1143
1144 /* write descriptor chain address to control register */
1145 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1146
1147 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1148 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1149 } else {
1150 /* write size / packets */
1151 dwc2_writel(hsotg, epsize, epsize_reg);
1152
1153 if (using_dma(hsotg) && !continuing && (length != 0)) {
1154 /*
1155 * write DMA address to control register, buffer
1156 * already synced by dwc2_hsotg_ep_queue().
1157 */
1158
1159 dwc2_writel(hsotg, ureq->dma, dma_reg);
1160
1161 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1162 __func__, &ureq->dma, dma_reg);
1163 }
1164 }
1165
1166 if (hs_ep->isochronous && hs_ep->interval == 1) {
1167 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1168 dwc2_gadget_incr_frame_num(hs_ep);
1169
1170 if (hs_ep->target_frame & 0x1)
1171 ctrl |= DXEPCTL_SETODDFR;
1172 else
1173 ctrl |= DXEPCTL_SETEVENFR;
1174 }
1175
1176 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1177
1178 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1179
1180 /* For Setup request do not clear NAK */
1181 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1182 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1183
1184 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1185 dwc2_writel(hsotg, ctrl, epctrl_reg);
1186
1187 /*
1188 * set these, it seems that DMA support increments past the end
1189 * of the packet buffer so we need to calculate the length from
1190 * this information.
1191 */
1192 hs_ep->size_loaded = length;
1193 hs_ep->last_load = ureq->actual;
1194
1195 if (dir_in && !using_dma(hsotg)) {
1196 /* set these anyway, we may need them for non-periodic in */
1197 hs_ep->fifo_load = 0;
1198
1199 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1200 }
1201
1202 /*
1203 * Note, trying to clear the NAK here causes problems with transmit
1204 * on the S3C6400 ending up with the TXFIFO becoming full.
1205 */
1206
1207 /* check ep is enabled */
1208 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1209 dev_dbg(hsotg->dev,
1210 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1211 index, dwc2_readl(hsotg, epctrl_reg));
1212
1213 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1214 __func__, dwc2_readl(hsotg, epctrl_reg));
1215
1216 /* enable ep interrupts */
1217 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1218}
1219
1220/**
1221 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1222 * @hsotg: The device state.
1223 * @hs_ep: The endpoint the request is on.
1224 * @req: The request being processed.
1225 *
1226 * We've been asked to queue a request, so ensure that the memory buffer
1227 * is correctly setup for DMA. If we've been passed an extant DMA address
1228 * then ensure the buffer has been synced to memory. If our buffer has no
1229 * DMA memory, then we map the memory and mark our request to allow us to
1230 * cleanup on completion.
1231 */
1232static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1233 struct dwc2_hsotg_ep *hs_ep,
1234 struct usb_request *req)
1235{
1236 int ret;
1237
1238 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1239 if (ret)
1240 goto dma_error;
1241
1242 return 0;
1243
1244dma_error:
1245 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1246 __func__, req->buf, req->length);
1247
1248 return -EIO;
1249}
1250
1251static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1252 struct dwc2_hsotg_ep *hs_ep,
1253 struct dwc2_hsotg_req *hs_req)
1254{
1255 void *req_buf = hs_req->req.buf;
1256
1257 /* If dma is not being used or buffer is aligned */
1258 if (!using_dma(hsotg) || !((long)req_buf & 3))
1259 return 0;
1260
1261 WARN_ON(hs_req->saved_req_buf);
1262
1263 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1264 hs_ep->ep.name, req_buf, hs_req->req.length);
1265
1266 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1267 if (!hs_req->req.buf) {
1268 hs_req->req.buf = req_buf;
1269 dev_err(hsotg->dev,
1270 "%s: unable to allocate memory for bounce buffer\n",
1271 __func__);
1272 return -ENOMEM;
1273 }
1274
1275 /* Save actual buffer */
1276 hs_req->saved_req_buf = req_buf;
1277
1278 if (hs_ep->dir_in)
1279 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1280 return 0;
1281}
1282
1283static void
1284dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1285 struct dwc2_hsotg_ep *hs_ep,
1286 struct dwc2_hsotg_req *hs_req)
1287{
1288 /* If dma is not being used or buffer was aligned */
1289 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1290 return;
1291
1292 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1293 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1294
1295 /* Copy data from bounce buffer on successful out transfer */
1296 if (!hs_ep->dir_in && !hs_req->req.status)
1297 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1298 hs_req->req.actual);
1299
1300 /* Free bounce buffer */
1301 kfree(hs_req->req.buf);
1302
1303 hs_req->req.buf = hs_req->saved_req_buf;
1304 hs_req->saved_req_buf = NULL;
1305}
1306
1307/**
1308 * dwc2_gadget_target_frame_elapsed - Checks target frame
1309 * @hs_ep: The driver endpoint to check
1310 *
1311 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1312 * corresponding transfer.
1313 */
1314static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1315{
1316 struct dwc2_hsotg *hsotg = hs_ep->parent;
1317 u32 target_frame = hs_ep->target_frame;
1318 u32 current_frame = hsotg->frame_number;
1319 bool frame_overrun = hs_ep->frame_overrun;
1320
1321 if (!frame_overrun && current_frame >= target_frame)
1322 return true;
1323
1324 if (frame_overrun && current_frame >= target_frame &&
1325 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1326 return true;
1327
1328 return false;
1329}
1330
1331/*
1332 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1333 * @hsotg: The driver state
1334 * @hs_ep: the ep descriptor chain is for
1335 *
1336 * Called to update EP0 structure's pointers depend on stage of
1337 * control transfer.
1338 */
1339static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1340 struct dwc2_hsotg_ep *hs_ep)
1341{
1342 switch (hsotg->ep0_state) {
1343 case DWC2_EP0_SETUP:
1344 case DWC2_EP0_STATUS_OUT:
1345 hs_ep->desc_list = hsotg->setup_desc[0];
1346 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1347 break;
1348 case DWC2_EP0_DATA_IN:
1349 case DWC2_EP0_STATUS_IN:
1350 hs_ep->desc_list = hsotg->ctrl_in_desc;
1351 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1352 break;
1353 case DWC2_EP0_DATA_OUT:
1354 hs_ep->desc_list = hsotg->ctrl_out_desc;
1355 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1356 break;
1357 default:
1358 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1359 hsotg->ep0_state);
1360 return -EINVAL;
1361 }
1362
1363 return 0;
1364}
1365
1366static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1367 gfp_t gfp_flags)
1368{
1369 struct dwc2_hsotg_req *hs_req = our_req(req);
1370 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1371 struct dwc2_hsotg *hs = hs_ep->parent;
1372 bool first;
1373 int ret;
1374 u32 maxsize = 0;
1375 u32 mask = 0;
1376
1377
1378 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1379 ep->name, req, req->length, req->buf, req->no_interrupt,
1380 req->zero, req->short_not_ok);
1381
1382 /* Prevent new request submission when controller is suspended */
1383 if (hs->lx_state != DWC2_L0) {
1384 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1385 __func__);
1386 return -EAGAIN;
1387 }
1388
1389 /* initialise status of the request */
1390 INIT_LIST_HEAD(&hs_req->queue);
1391 req->actual = 0;
1392 req->status = -EINPROGRESS;
1393
1394 /* In DDMA mode for ISOC's don't queue request if length greater
1395 * than descriptor limits.
1396 */
1397 if (using_desc_dma(hs) && hs_ep->isochronous) {
1398 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1399 if (hs_ep->dir_in && req->length > maxsize) {
1400 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1401 req->length, maxsize);
1402 return -EINVAL;
1403 }
1404
1405 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1406 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1407 req->length, hs_ep->ep.maxpacket);
1408 return -EINVAL;
1409 }
1410 }
1411
1412 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1413 if (ret)
1414 return ret;
1415
1416 /* if we're using DMA, sync the buffers as necessary */
1417 if (using_dma(hs)) {
1418 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1419 if (ret)
1420 return ret;
1421 }
1422 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1423 if (using_desc_dma(hs) && !hs_ep->index) {
1424 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1425 if (ret)
1426 return ret;
1427 }
1428
1429 first = list_empty(&hs_ep->queue);
1430 list_add_tail(&hs_req->queue, &hs_ep->queue);
1431
1432 /*
1433 * Handle DDMA isochronous transfers separately - just add new entry
1434 * to the descriptor chain.
1435 * Transfer will be started once SW gets either one of NAK or
1436 * OutTknEpDis interrupts.
1437 */
1438 if (using_desc_dma(hs) && hs_ep->isochronous) {
1439 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1440 dma_addr_t dma_addr = hs_req->req.dma;
1441
1442 if (hs_req->req.num_sgs) {
1443 WARN_ON(hs_req->req.num_sgs > 1);
1444 dma_addr = sg_dma_address(hs_req->req.sg);
1445 }
1446 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1447 hs_req->req.length);
1448 }
1449 return 0;
1450 }
1451
1452 /* Change EP direction if status phase request is after data out */
1453 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1454 hs->ep0_state == DWC2_EP0_DATA_OUT)
1455 hs_ep->dir_in = 1;
1456
1457 if (first) {
1458 if (!hs_ep->isochronous) {
1459 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1460 return 0;
1461 }
1462
1463 /* Update current frame number value. */
1464 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1465 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1466 dwc2_gadget_incr_frame_num(hs_ep);
1467 /* Update current frame number value once more as it
1468 * changes here.
1469 */
1470 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1471 }
1472
1473 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1474 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1475 }
1476 return 0;
1477}
1478
1479static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1480 gfp_t gfp_flags)
1481{
1482 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1483 struct dwc2_hsotg *hs = hs_ep->parent;
1484 unsigned long flags = 0;
1485 int ret = 0;
1486
1487 spin_lock_irqsave(&hs->lock, flags);
1488 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1489 spin_unlock_irqrestore(&hs->lock, flags);
1490
1491 return ret;
1492}
1493
1494static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1495 struct usb_request *req)
1496{
1497 struct dwc2_hsotg_req *hs_req = our_req(req);
1498
1499 kfree(hs_req);
1500}
1501
1502/**
1503 * dwc2_hsotg_complete_oursetup - setup completion callback
1504 * @ep: The endpoint the request was on.
1505 * @req: The request completed.
1506 *
1507 * Called on completion of any requests the driver itself
1508 * submitted that need cleaning up.
1509 */
1510static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1511 struct usb_request *req)
1512{
1513 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1514 struct dwc2_hsotg *hsotg = hs_ep->parent;
1515
1516 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1517
1518 dwc2_hsotg_ep_free_request(ep, req);
1519}
1520
1521/**
1522 * ep_from_windex - convert control wIndex value to endpoint
1523 * @hsotg: The driver state.
1524 * @windex: The control request wIndex field (in host order).
1525 *
1526 * Convert the given wIndex into a pointer to an driver endpoint
1527 * structure, or return NULL if it is not a valid endpoint.
1528 */
1529static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1530 u32 windex)
1531{
1532 struct dwc2_hsotg_ep *ep;
1533 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1534 int idx = windex & 0x7F;
1535
1536 if (windex >= 0x100)
1537 return NULL;
1538
1539 if (idx > hsotg->num_of_eps)
1540 return NULL;
1541
1542 ep = index_to_ep(hsotg, idx, dir);
1543
1544 if (idx && ep->dir_in != dir)
1545 return NULL;
1546
1547 return ep;
1548}
1549
1550/**
1551 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1552 * @hsotg: The driver state.
1553 * @testmode: requested usb test mode
1554 * Enable usb Test Mode requested by the Host.
1555 */
1556int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1557{
1558 int dctl = dwc2_readl(hsotg, DCTL);
1559
1560 dctl &= ~DCTL_TSTCTL_MASK;
1561 switch (testmode) {
1562 case TEST_J:
1563 case TEST_K:
1564 case TEST_SE0_NAK:
1565 case TEST_PACKET:
1566 case TEST_FORCE_EN:
1567 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1568 break;
1569 default:
1570 return -EINVAL;
1571 }
1572 dwc2_writel(hsotg, dctl, DCTL);
1573 return 0;
1574}
1575
1576/**
1577 * dwc2_hsotg_send_reply - send reply to control request
1578 * @hsotg: The device state
1579 * @ep: Endpoint 0
1580 * @buff: Buffer for request
1581 * @length: Length of reply.
1582 *
1583 * Create a request and queue it on the given endpoint. This is useful as
1584 * an internal method of sending replies to certain control requests, etc.
1585 */
1586static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1587 struct dwc2_hsotg_ep *ep,
1588 void *buff,
1589 int length)
1590{
1591 struct usb_request *req;
1592 int ret;
1593
1594 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1595
1596 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1597 hsotg->ep0_reply = req;
1598 if (!req) {
1599 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1600 return -ENOMEM;
1601 }
1602
1603 req->buf = hsotg->ep0_buff;
1604 req->length = length;
1605 /*
1606 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1607 * STATUS stage.
1608 */
1609 req->zero = 0;
1610 req->complete = dwc2_hsotg_complete_oursetup;
1611
1612 if (length)
1613 memcpy(req->buf, buff, length);
1614
1615 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1616 if (ret) {
1617 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1618 return ret;
1619 }
1620
1621 return 0;
1622}
1623
1624/**
1625 * dwc2_hsotg_process_req_status - process request GET_STATUS
1626 * @hsotg: The device state
1627 * @ctrl: USB control request
1628 */
1629static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1630 struct usb_ctrlrequest *ctrl)
1631{
1632 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1633 struct dwc2_hsotg_ep *ep;
1634 __le16 reply;
1635 int ret;
1636
1637 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1638
1639 if (!ep0->dir_in) {
1640 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1641 return -EINVAL;
1642 }
1643
1644 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1645 case USB_RECIP_DEVICE:
1646 /*
1647 * bit 0 => self powered
1648 * bit 1 => remote wakeup
1649 */
1650 reply = cpu_to_le16(0);
1651 break;
1652
1653 case USB_RECIP_INTERFACE:
1654 /* currently, the data result should be zero */
1655 reply = cpu_to_le16(0);
1656 break;
1657
1658 case USB_RECIP_ENDPOINT:
1659 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1660 if (!ep)
1661 return -ENOENT;
1662
1663 reply = cpu_to_le16(ep->halted ? 1 : 0);
1664 break;
1665
1666 default:
1667 return 0;
1668 }
1669
1670 if (le16_to_cpu(ctrl->wLength) != 2)
1671 return -EINVAL;
1672
1673 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1674 if (ret) {
1675 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1676 return ret;
1677 }
1678
1679 return 1;
1680}
1681
1682static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1683
1684/**
1685 * get_ep_head - return the first request on the endpoint
1686 * @hs_ep: The controller endpoint to get
1687 *
1688 * Get the first request on the endpoint.
1689 */
1690static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1691{
1692 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1693 queue);
1694}
1695
1696/**
1697 * dwc2_gadget_start_next_request - Starts next request from ep queue
1698 * @hs_ep: Endpoint structure
1699 *
1700 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1701 * in its handler. Hence we need to unmask it here to be able to do
1702 * resynchronization.
1703 */
1704static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1705{
1706 u32 mask;
1707 struct dwc2_hsotg *hsotg = hs_ep->parent;
1708 int dir_in = hs_ep->dir_in;
1709 struct dwc2_hsotg_req *hs_req;
1710 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1711
1712 if (!list_empty(&hs_ep->queue)) {
1713 hs_req = get_ep_head(hs_ep);
1714 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1715 return;
1716 }
1717 if (!hs_ep->isochronous)
1718 return;
1719
1720 if (dir_in) {
1721 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1722 __func__);
1723 } else {
1724 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1725 __func__);
1726 mask = dwc2_readl(hsotg, epmsk_reg);
1727 mask |= DOEPMSK_OUTTKNEPDISMSK;
1728 dwc2_writel(hsotg, mask, epmsk_reg);
1729 }
1730}
1731
1732/**
1733 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1734 * @hsotg: The device state
1735 * @ctrl: USB control request
1736 */
1737static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1738 struct usb_ctrlrequest *ctrl)
1739{
1740 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1741 struct dwc2_hsotg_req *hs_req;
1742 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1743 struct dwc2_hsotg_ep *ep;
1744 int ret;
1745 bool halted;
1746 u32 recip;
1747 u32 wValue;
1748 u32 wIndex;
1749
1750 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1751 __func__, set ? "SET" : "CLEAR");
1752
1753 wValue = le16_to_cpu(ctrl->wValue);
1754 wIndex = le16_to_cpu(ctrl->wIndex);
1755 recip = ctrl->bRequestType & USB_RECIP_MASK;
1756
1757 switch (recip) {
1758 case USB_RECIP_DEVICE:
1759 switch (wValue) {
1760 case USB_DEVICE_REMOTE_WAKEUP:
1761 hsotg->remote_wakeup_allowed = 1;
1762 break;
1763
1764 case USB_DEVICE_TEST_MODE:
1765 if ((wIndex & 0xff) != 0)
1766 return -EINVAL;
1767 if (!set)
1768 return -EINVAL;
1769
1770 hsotg->test_mode = wIndex >> 8;
1771 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1772 if (ret) {
1773 dev_err(hsotg->dev,
1774 "%s: failed to send reply\n", __func__);
1775 return ret;
1776 }
1777 break;
1778 default:
1779 return -ENOENT;
1780 }
1781 break;
1782
1783 case USB_RECIP_ENDPOINT:
1784 ep = ep_from_windex(hsotg, wIndex);
1785 if (!ep) {
1786 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1787 __func__, wIndex);
1788 return -ENOENT;
1789 }
1790
1791 switch (wValue) {
1792 case USB_ENDPOINT_HALT:
1793 halted = ep->halted;
1794
1795 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1796
1797 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1798 if (ret) {
1799 dev_err(hsotg->dev,
1800 "%s: failed to send reply\n", __func__);
1801 return ret;
1802 }
1803
1804 /*
1805 * we have to complete all requests for ep if it was
1806 * halted, and the halt was cleared by CLEAR_FEATURE
1807 */
1808
1809 if (!set && halted) {
1810 /*
1811 * If we have request in progress,
1812 * then complete it
1813 */
1814 if (ep->req) {
1815 hs_req = ep->req;
1816 ep->req = NULL;
1817 list_del_init(&hs_req->queue);
1818 if (hs_req->req.complete) {
1819 spin_unlock(&hsotg->lock);
1820 usb_gadget_giveback_request(
1821 &ep->ep, &hs_req->req);
1822 spin_lock(&hsotg->lock);
1823 }
1824 }
1825
1826 /* If we have pending request, then start it */
1827 if (!ep->req)
1828 dwc2_gadget_start_next_request(ep);
1829 }
1830
1831 break;
1832
1833 default:
1834 return -ENOENT;
1835 }
1836 break;
1837 default:
1838 return -ENOENT;
1839 }
1840 return 1;
1841}
1842
1843static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1844
1845/**
1846 * dwc2_hsotg_stall_ep0 - stall ep0
1847 * @hsotg: The device state
1848 *
1849 * Set stall for ep0 as response for setup request.
1850 */
1851static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1852{
1853 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1854 u32 reg;
1855 u32 ctrl;
1856
1857 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1858 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1859
1860 /*
1861 * DxEPCTL_Stall will be cleared by EP once it has
1862 * taken effect, so no need to clear later.
1863 */
1864
1865 ctrl = dwc2_readl(hsotg, reg);
1866 ctrl |= DXEPCTL_STALL;
1867 ctrl |= DXEPCTL_CNAK;
1868 dwc2_writel(hsotg, ctrl, reg);
1869
1870 dev_dbg(hsotg->dev,
1871 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1872 ctrl, reg, dwc2_readl(hsotg, reg));
1873
1874 /*
1875 * complete won't be called, so we enqueue
1876 * setup request here
1877 */
1878 dwc2_hsotg_enqueue_setup(hsotg);
1879}
1880
1881/**
1882 * dwc2_hsotg_process_control - process a control request
1883 * @hsotg: The device state
1884 * @ctrl: The control request received
1885 *
1886 * The controller has received the SETUP phase of a control request, and
1887 * needs to work out what to do next (and whether to pass it on to the
1888 * gadget driver).
1889 */
1890static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1891 struct usb_ctrlrequest *ctrl)
1892{
1893 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1894 int ret = 0;
1895 u32 dcfg;
1896
1897 dev_dbg(hsotg->dev,
1898 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1899 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1900 ctrl->wIndex, ctrl->wLength);
1901
1902 if (ctrl->wLength == 0) {
1903 ep0->dir_in = 1;
1904 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1905 } else if (ctrl->bRequestType & USB_DIR_IN) {
1906 ep0->dir_in = 1;
1907 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1908 } else {
1909 ep0->dir_in = 0;
1910 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1911 }
1912
1913 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1914 switch (ctrl->bRequest) {
1915 case USB_REQ_SET_ADDRESS:
1916 hsotg->connected = 1;
1917 dcfg = dwc2_readl(hsotg, DCFG);
1918 dcfg &= ~DCFG_DEVADDR_MASK;
1919 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1920 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1921 dwc2_writel(hsotg, dcfg, DCFG);
1922
1923 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1924
1925 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1926 return;
1927
1928 case USB_REQ_GET_STATUS:
1929 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1930 break;
1931
1932 case USB_REQ_CLEAR_FEATURE:
1933 case USB_REQ_SET_FEATURE:
1934 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1935 break;
1936 }
1937 }
1938
1939 /* as a fallback, try delivering it to the driver to deal with */
1940
1941 if (ret == 0 && hsotg->driver) {
1942 spin_unlock(&hsotg->lock);
1943 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1944 spin_lock(&hsotg->lock);
1945 if (ret < 0)
1946 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1947 }
1948
1949 hsotg->delayed_status = false;
1950 if (ret == USB_GADGET_DELAYED_STATUS)
1951 hsotg->delayed_status = true;
1952
1953 /*
1954 * the request is either unhandlable, or is not formatted correctly
1955 * so respond with a STALL for the status stage to indicate failure.
1956 */
1957
1958 if (ret < 0)
1959 dwc2_hsotg_stall_ep0(hsotg);
1960}
1961
1962/**
1963 * dwc2_hsotg_complete_setup - completion of a setup transfer
1964 * @ep: The endpoint the request was on.
1965 * @req: The request completed.
1966 *
1967 * Called on completion of any requests the driver itself submitted for
1968 * EP0 setup packets
1969 */
1970static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1971 struct usb_request *req)
1972{
1973 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1974 struct dwc2_hsotg *hsotg = hs_ep->parent;
1975
1976 if (req->status < 0) {
1977 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1978 return;
1979 }
1980
1981 spin_lock(&hsotg->lock);
1982 if (req->actual == 0)
1983 dwc2_hsotg_enqueue_setup(hsotg);
1984 else
1985 dwc2_hsotg_process_control(hsotg, req->buf);
1986 spin_unlock(&hsotg->lock);
1987}
1988
1989/**
1990 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1991 * @hsotg: The device state.
1992 *
1993 * Enqueue a request on EP0 if necessary to received any SETUP packets
1994 * received from the host.
1995 */
1996static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1997{
1998 struct usb_request *req = hsotg->ctrl_req;
1999 struct dwc2_hsotg_req *hs_req = our_req(req);
2000 int ret;
2001
2002 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2003
2004 req->zero = 0;
2005 req->length = 8;
2006 req->buf = hsotg->ctrl_buff;
2007 req->complete = dwc2_hsotg_complete_setup;
2008
2009 if (!list_empty(&hs_req->queue)) {
2010 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2011 return;
2012 }
2013
2014 hsotg->eps_out[0]->dir_in = 0;
2015 hsotg->eps_out[0]->send_zlp = 0;
2016 hsotg->ep0_state = DWC2_EP0_SETUP;
2017
2018 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2019 if (ret < 0) {
2020 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2021 /*
2022 * Don't think there's much we can do other than watch the
2023 * driver fail.
2024 */
2025 }
2026}
2027
2028static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2029 struct dwc2_hsotg_ep *hs_ep)
2030{
2031 u32 ctrl;
2032 u8 index = hs_ep->index;
2033 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2034 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2035
2036 if (hs_ep->dir_in)
2037 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2038 index);
2039 else
2040 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2041 index);
2042 if (using_desc_dma(hsotg)) {
2043 /* Not specific buffer needed for ep0 ZLP */
2044 dma_addr_t dma = hs_ep->desc_list_dma;
2045
2046 if (!index)
2047 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2048
2049 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2050 } else {
2051 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2052 DXEPTSIZ_XFERSIZE(0),
2053 epsiz_reg);
2054 }
2055
2056 ctrl = dwc2_readl(hsotg, epctl_reg);
2057 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2058 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2059 ctrl |= DXEPCTL_USBACTEP;
2060 dwc2_writel(hsotg, ctrl, epctl_reg);
2061}
2062
2063/**
2064 * dwc2_hsotg_complete_request - complete a request given to us
2065 * @hsotg: The device state.
2066 * @hs_ep: The endpoint the request was on.
2067 * @hs_req: The request to complete.
2068 * @result: The result code (0 => Ok, otherwise errno)
2069 *
2070 * The given request has finished, so call the necessary completion
2071 * if it has one and then look to see if we can start a new request
2072 * on the endpoint.
2073 *
2074 * Note, expects the ep to already be locked as appropriate.
2075 */
2076static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2077 struct dwc2_hsotg_ep *hs_ep,
2078 struct dwc2_hsotg_req *hs_req,
2079 int result)
2080{
2081 if (!hs_req) {
2082 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2083 return;
2084 }
2085
2086 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2087 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2088
2089 /*
2090 * only replace the status if we've not already set an error
2091 * from a previous transaction
2092 */
2093
2094 if (hs_req->req.status == -EINPROGRESS)
2095 hs_req->req.status = result;
2096
2097 if (using_dma(hsotg))
2098 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2099
2100 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2101
2102 hs_ep->req = NULL;
2103 list_del_init(&hs_req->queue);
2104
2105 /*
2106 * call the complete request with the locks off, just in case the
2107 * request tries to queue more work for this endpoint.
2108 */
2109
2110 if (hs_req->req.complete) {
2111 spin_unlock(&hsotg->lock);
2112 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2113 spin_lock(&hsotg->lock);
2114 }
2115
2116 /* In DDMA don't need to proceed to starting of next ISOC request */
2117 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2118 return;
2119
2120 /*
2121 * Look to see if there is anything else to do. Note, the completion
2122 * of the previous request may have caused a new request to be started
2123 * so be careful when doing this.
2124 */
2125
2126 if (!hs_ep->req && result >= 0)
2127 dwc2_gadget_start_next_request(hs_ep);
2128}
2129
2130/*
2131 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2132 * @hs_ep: The endpoint the request was on.
2133 *
2134 * Get first request from the ep queue, determine descriptor on which complete
2135 * happened. SW discovers which descriptor currently in use by HW, adjusts
2136 * dma_address and calculates index of completed descriptor based on the value
2137 * of DEPDMA register. Update actual length of request, giveback to gadget.
2138 */
2139static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2140{
2141 struct dwc2_hsotg *hsotg = hs_ep->parent;
2142 struct dwc2_hsotg_req *hs_req;
2143 struct usb_request *ureq;
2144 u32 desc_sts;
2145 u32 mask;
2146
2147 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2148
2149 /* Process only descriptors with buffer status set to DMA done */
2150 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2151 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2152
2153 hs_req = get_ep_head(hs_ep);
2154 if (!hs_req) {
2155 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2156 return;
2157 }
2158 ureq = &hs_req->req;
2159
2160 /* Check completion status */
2161 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2162 DEV_DMA_STS_SUCC) {
2163 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2164 DEV_DMA_ISOC_RX_NBYTES_MASK;
2165 ureq->actual = ureq->length - ((desc_sts & mask) >>
2166 DEV_DMA_ISOC_NBYTES_SHIFT);
2167
2168 /* Adjust actual len for ISOC Out if len is
2169 * not align of 4
2170 */
2171 if (!hs_ep->dir_in && ureq->length & 0x3)
2172 ureq->actual += 4 - (ureq->length & 0x3);
2173
2174 /* Set actual frame number for completed transfers */
2175 ureq->frame_number =
2176 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2177 DEV_DMA_ISOC_FRNUM_SHIFT;
2178 }
2179
2180 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2181
2182 hs_ep->compl_desc++;
2183 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2184 hs_ep->compl_desc = 0;
2185 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2186 }
2187}
2188
2189/*
2190 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2191 * @hs_ep: The isochronous endpoint.
2192 *
2193 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2194 * interrupt. Reset target frame and next_desc to allow to start
2195 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2196 * interrupt for OUT direction.
2197 */
2198static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2199{
2200 struct dwc2_hsotg *hsotg = hs_ep->parent;
2201
2202 if (!hs_ep->dir_in)
2203 dwc2_flush_rx_fifo(hsotg);
2204 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2205
2206 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2207 hs_ep->next_desc = 0;
2208 hs_ep->compl_desc = 0;
2209}
2210
2211/**
2212 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2213 * @hsotg: The device state.
2214 * @ep_idx: The endpoint index for the data
2215 * @size: The size of data in the fifo, in bytes
2216 *
2217 * The FIFO status shows there is data to read from the FIFO for a given
2218 * endpoint, so sort out whether we need to read the data into a request
2219 * that has been made for that endpoint.
2220 */
2221static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2222{
2223 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2224 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2225 int to_read;
2226 int max_req;
2227 int read_ptr;
2228
2229 if (!hs_req) {
2230 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2231 int ptr;
2232
2233 dev_dbg(hsotg->dev,
2234 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2235 __func__, size, ep_idx, epctl);
2236
2237 /* dump the data from the FIFO, we've nothing we can do */
2238 for (ptr = 0; ptr < size; ptr += 4)
2239 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2240
2241 return;
2242 }
2243
2244 to_read = size;
2245 read_ptr = hs_req->req.actual;
2246 max_req = hs_req->req.length - read_ptr;
2247
2248 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2249 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2250
2251 if (to_read > max_req) {
2252 /*
2253 * more data appeared than we where willing
2254 * to deal with in this request.
2255 */
2256
2257 /* currently we don't deal this */
2258 WARN_ON_ONCE(1);
2259 }
2260
2261 hs_ep->total_data += to_read;
2262 hs_req->req.actual += to_read;
2263 to_read = DIV_ROUND_UP(to_read, 4);
2264
2265 /*
2266 * note, we might over-write the buffer end by 3 bytes depending on
2267 * alignment of the data.
2268 */
2269 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2270 hs_req->req.buf + read_ptr, to_read);
2271}
2272
2273/**
2274 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2275 * @hsotg: The device instance
2276 * @dir_in: If IN zlp
2277 *
2278 * Generate a zero-length IN packet request for terminating a SETUP
2279 * transaction.
2280 *
2281 * Note, since we don't write any data to the TxFIFO, then it is
2282 * currently believed that we do not need to wait for any space in
2283 * the TxFIFO.
2284 */
2285static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2286{
2287 /* eps_out[0] is used in both directions */
2288 hsotg->eps_out[0]->dir_in = dir_in;
2289 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2290
2291 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2292}
2293
2294static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2295 u32 epctl_reg)
2296{
2297 u32 ctrl;
2298
2299 ctrl = dwc2_readl(hsotg, epctl_reg);
2300 if (ctrl & DXEPCTL_EOFRNUM)
2301 ctrl |= DXEPCTL_SETEVENFR;
2302 else
2303 ctrl |= DXEPCTL_SETODDFR;
2304 dwc2_writel(hsotg, ctrl, epctl_reg);
2305}
2306
2307/*
2308 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2309 * @hs_ep - The endpoint on which transfer went
2310 *
2311 * Iterate over endpoints descriptor chain and get info on bytes remained
2312 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2313 */
2314static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2315{
2316 struct dwc2_hsotg *hsotg = hs_ep->parent;
2317 unsigned int bytes_rem = 0;
2318 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2319 int i;
2320 u32 status;
2321
2322 if (!desc)
2323 return -EINVAL;
2324
2325 for (i = 0; i < hs_ep->desc_count; ++i) {
2326 status = desc->status;
2327 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2328
2329 if (status & DEV_DMA_STS_MASK)
2330 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2331 i, status & DEV_DMA_STS_MASK);
2332 desc++;
2333 }
2334
2335 return bytes_rem;
2336}
2337
2338/**
2339 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2340 * @hsotg: The device instance
2341 * @epnum: The endpoint received from
2342 *
2343 * The RXFIFO has delivered an OutDone event, which means that the data
2344 * transfer for an OUT endpoint has been completed, either by a short
2345 * packet or by the finish of a transfer.
2346 */
2347static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2348{
2349 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2350 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2351 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2352 struct usb_request *req = &hs_req->req;
2353 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2354 int result = 0;
2355
2356 if (!hs_req) {
2357 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2358 return;
2359 }
2360
2361 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2362 dev_dbg(hsotg->dev, "zlp packet received\n");
2363 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2364 dwc2_hsotg_enqueue_setup(hsotg);
2365 return;
2366 }
2367
2368 if (using_desc_dma(hsotg))
2369 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2370
2371 if (using_dma(hsotg)) {
2372 unsigned int size_done;
2373
2374 /*
2375 * Calculate the size of the transfer by checking how much
2376 * is left in the endpoint size register and then working it
2377 * out from the amount we loaded for the transfer.
2378 *
2379 * We need to do this as DMA pointers are always 32bit aligned
2380 * so may overshoot/undershoot the transfer.
2381 */
2382
2383 size_done = hs_ep->size_loaded - size_left;
2384 size_done += hs_ep->last_load;
2385
2386 req->actual = size_done;
2387 }
2388
2389 /* if there is more request to do, schedule new transfer */
2390 if (req->actual < req->length && size_left == 0) {
2391 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2392 return;
2393 }
2394
2395 if (req->actual < req->length && req->short_not_ok) {
2396 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2397 __func__, req->actual, req->length);
2398
2399 /*
2400 * todo - what should we return here? there's no one else
2401 * even bothering to check the status.
2402 */
2403 }
2404
2405 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2406 if (!using_desc_dma(hsotg) && epnum == 0 &&
2407 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2408 /* Move to STATUS IN */
2409 if (!hsotg->delayed_status)
2410 dwc2_hsotg_ep0_zlp(hsotg, true);
2411 }
2412
2413 /*
2414 * Slave mode OUT transfers do not go through XferComplete so
2415 * adjust the ISOC parity here.
2416 */
2417 if (!using_dma(hsotg)) {
2418 if (hs_ep->isochronous && hs_ep->interval == 1)
2419 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2420 else if (hs_ep->isochronous && hs_ep->interval > 1)
2421 dwc2_gadget_incr_frame_num(hs_ep);
2422 }
2423
2424 /* Set actual frame number for completed transfers */
2425 if (!using_desc_dma(hsotg) && hs_ep->isochronous)
2426 req->frame_number = hsotg->frame_number;
2427
2428 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2429}
2430
2431/**
2432 * dwc2_hsotg_handle_rx - RX FIFO has data
2433 * @hsotg: The device instance
2434 *
2435 * The IRQ handler has detected that the RX FIFO has some data in it
2436 * that requires processing, so find out what is in there and do the
2437 * appropriate read.
2438 *
2439 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2440 * chunks, so if you have x packets received on an endpoint you'll get x
2441 * FIFO events delivered, each with a packet's worth of data in it.
2442 *
2443 * When using DMA, we should not be processing events from the RXFIFO
2444 * as the actual data should be sent to the memory directly and we turn
2445 * on the completion interrupts to get notifications of transfer completion.
2446 */
2447static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2448{
2449 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2450 u32 epnum, status, size;
2451
2452 WARN_ON(using_dma(hsotg));
2453
2454 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2455 status = grxstsr & GRXSTS_PKTSTS_MASK;
2456
2457 size = grxstsr & GRXSTS_BYTECNT_MASK;
2458 size >>= GRXSTS_BYTECNT_SHIFT;
2459
2460 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2461 __func__, grxstsr, size, epnum);
2462
2463 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2464 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2465 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2466 break;
2467
2468 case GRXSTS_PKTSTS_OUTDONE:
2469 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2470 dwc2_hsotg_read_frameno(hsotg));
2471
2472 if (!using_dma(hsotg))
2473 dwc2_hsotg_handle_outdone(hsotg, epnum);
2474 break;
2475
2476 case GRXSTS_PKTSTS_SETUPDONE:
2477 dev_dbg(hsotg->dev,
2478 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2479 dwc2_hsotg_read_frameno(hsotg),
2480 dwc2_readl(hsotg, DOEPCTL(0)));
2481 /*
2482 * Call dwc2_hsotg_handle_outdone here if it was not called from
2483 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2484 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2485 */
2486 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2487 dwc2_hsotg_handle_outdone(hsotg, epnum);
2488 break;
2489
2490 case GRXSTS_PKTSTS_OUTRX:
2491 dwc2_hsotg_rx_data(hsotg, epnum, size);
2492 break;
2493
2494 case GRXSTS_PKTSTS_SETUPRX:
2495 dev_dbg(hsotg->dev,
2496 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2497 dwc2_hsotg_read_frameno(hsotg),
2498 dwc2_readl(hsotg, DOEPCTL(0)));
2499
2500 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2501
2502 dwc2_hsotg_rx_data(hsotg, epnum, size);
2503 break;
2504
2505 default:
2506 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2507 __func__, grxstsr);
2508
2509 dwc2_hsotg_dump(hsotg);
2510 break;
2511 }
2512}
2513
2514/**
2515 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2516 * @mps: The maximum packet size in bytes.
2517 */
2518static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2519{
2520 switch (mps) {
2521 case 64:
2522 return D0EPCTL_MPS_64;
2523 case 32:
2524 return D0EPCTL_MPS_32;
2525 case 16:
2526 return D0EPCTL_MPS_16;
2527 case 8:
2528 return D0EPCTL_MPS_8;
2529 }
2530
2531 /* bad max packet size, warn and return invalid result */
2532 WARN_ON(1);
2533 return (u32)-1;
2534}
2535
2536/**
2537 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2538 * @hsotg: The driver state.
2539 * @ep: The index number of the endpoint
2540 * @mps: The maximum packet size in bytes
2541 * @mc: The multicount value
2542 * @dir_in: True if direction is in.
2543 *
2544 * Configure the maximum packet size for the given endpoint, updating
2545 * the hardware control registers to reflect this.
2546 */
2547static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2548 unsigned int ep, unsigned int mps,
2549 unsigned int mc, unsigned int dir_in)
2550{
2551 struct dwc2_hsotg_ep *hs_ep;
2552 u32 reg;
2553
2554 hs_ep = index_to_ep(hsotg, ep, dir_in);
2555 if (!hs_ep)
2556 return;
2557
2558 if (ep == 0) {
2559 u32 mps_bytes = mps;
2560
2561 /* EP0 is a special case */
2562 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2563 if (mps > 3)
2564 goto bad_mps;
2565 hs_ep->ep.maxpacket = mps_bytes;
2566 hs_ep->mc = 1;
2567 } else {
2568 if (mps > 1024)
2569 goto bad_mps;
2570 hs_ep->mc = mc;
2571 if (mc > 3)
2572 goto bad_mps;
2573 hs_ep->ep.maxpacket = mps;
2574 }
2575
2576 if (dir_in) {
2577 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2578 reg &= ~DXEPCTL_MPS_MASK;
2579 reg |= mps;
2580 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2581 } else {
2582 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2583 reg &= ~DXEPCTL_MPS_MASK;
2584 reg |= mps;
2585 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2586 }
2587
2588 return;
2589
2590bad_mps:
2591 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2592}
2593
2594/**
2595 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2596 * @hsotg: The driver state
2597 * @idx: The index for the endpoint (0..15)
2598 */
2599static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2600{
2601 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2602 GRSTCTL);
2603
2604 /* wait until the fifo is flushed */
2605 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2606 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2607 __func__);
2608}
2609
2610/**
2611 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2612 * @hsotg: The driver state
2613 * @hs_ep: The driver endpoint to check.
2614 *
2615 * Check to see if there is a request that has data to send, and if so
2616 * make an attempt to write data into the FIFO.
2617 */
2618static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2619 struct dwc2_hsotg_ep *hs_ep)
2620{
2621 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2622
2623 if (!hs_ep->dir_in || !hs_req) {
2624 /**
2625 * if request is not enqueued, we disable interrupts
2626 * for endpoints, excepting ep0
2627 */
2628 if (hs_ep->index != 0)
2629 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2630 hs_ep->dir_in, 0);
2631 return 0;
2632 }
2633
2634 if (hs_req->req.actual < hs_req->req.length) {
2635 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2636 hs_ep->index);
2637 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2638 }
2639
2640 return 0;
2641}
2642
2643/**
2644 * dwc2_hsotg_complete_in - complete IN transfer
2645 * @hsotg: The device state.
2646 * @hs_ep: The endpoint that has just completed.
2647 *
2648 * An IN transfer has been completed, update the transfer's state and then
2649 * call the relevant completion routines.
2650 */
2651static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2652 struct dwc2_hsotg_ep *hs_ep)
2653{
2654 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2655 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2656 int size_left, size_done;
2657
2658 if (!hs_req) {
2659 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2660 return;
2661 }
2662
2663 /* Finish ZLP handling for IN EP0 transactions */
2664 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2665 dev_dbg(hsotg->dev, "zlp packet sent\n");
2666
2667 /*
2668 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2669 * changed to IN. Change back to complete OUT transfer request
2670 */
2671 hs_ep->dir_in = 0;
2672
2673 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2674 if (hsotg->test_mode) {
2675 int ret;
2676
2677 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2678 if (ret < 0) {
2679 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2680 hsotg->test_mode);
2681 dwc2_hsotg_stall_ep0(hsotg);
2682 return;
2683 }
2684 }
2685 dwc2_hsotg_enqueue_setup(hsotg);
2686 return;
2687 }
2688
2689 /*
2690 * Calculate the size of the transfer by checking how much is left
2691 * in the endpoint size register and then working it out from
2692 * the amount we loaded for the transfer.
2693 *
2694 * We do this even for DMA, as the transfer may have incremented
2695 * past the end of the buffer (DMA transfers are always 32bit
2696 * aligned).
2697 */
2698 if (using_desc_dma(hsotg)) {
2699 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2700 if (size_left < 0)
2701 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2702 size_left);
2703 } else {
2704 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2705 }
2706
2707 size_done = hs_ep->size_loaded - size_left;
2708 size_done += hs_ep->last_load;
2709
2710 if (hs_req->req.actual != size_done)
2711 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2712 __func__, hs_req->req.actual, size_done);
2713
2714 hs_req->req.actual = size_done;
2715 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2716 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2717
2718 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2719 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2720 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2721 return;
2722 }
2723
2724 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2725 if (hs_ep->send_zlp) {
2726 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2727 hs_ep->send_zlp = 0;
2728 /* transfer will be completed on next complete interrupt */
2729 return;
2730 }
2731
2732 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2733 /* Move to STATUS OUT */
2734 dwc2_hsotg_ep0_zlp(hsotg, false);
2735 return;
2736 }
2737
2738 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2739}
2740
2741/**
2742 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2743 * @hsotg: The device state.
2744 * @idx: Index of ep.
2745 * @dir_in: Endpoint direction 1-in 0-out.
2746 *
2747 * Reads for endpoint with given index and direction, by masking
2748 * epint_reg with coresponding mask.
2749 */
2750static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2751 unsigned int idx, int dir_in)
2752{
2753 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2754 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2755 u32 ints;
2756 u32 mask;
2757 u32 diepempmsk;
2758
2759 mask = dwc2_readl(hsotg, epmsk_reg);
2760 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2761 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2762 mask |= DXEPINT_SETUP_RCVD;
2763
2764 ints = dwc2_readl(hsotg, epint_reg);
2765 ints &= mask;
2766 return ints;
2767}
2768
2769/**
2770 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2771 * @hs_ep: The endpoint on which interrupt is asserted.
2772 *
2773 * This interrupt indicates that the endpoint has been disabled per the
2774 * application's request.
2775 *
2776 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2777 * in case of ISOC completes current request.
2778 *
2779 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2780 * request starts it.
2781 */
2782static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2783{
2784 struct dwc2_hsotg *hsotg = hs_ep->parent;
2785 struct dwc2_hsotg_req *hs_req;
2786 unsigned char idx = hs_ep->index;
2787 int dir_in = hs_ep->dir_in;
2788 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2789 int dctl = dwc2_readl(hsotg, DCTL);
2790
2791 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2792
2793 if (dir_in) {
2794 int epctl = dwc2_readl(hsotg, epctl_reg);
2795
2796 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2797
2798 if (hs_ep->isochronous) {
2799 dwc2_hsotg_complete_in(hsotg, hs_ep);
2800 return;
2801 }
2802
2803 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2804 int dctl = dwc2_readl(hsotg, DCTL);
2805
2806 dctl |= DCTL_CGNPINNAK;
2807 dwc2_writel(hsotg, dctl, DCTL);
2808 }
2809 return;
2810 }
2811
2812 if (dctl & DCTL_GOUTNAKSTS) {
2813 dctl |= DCTL_CGOUTNAK;
2814 dwc2_writel(hsotg, dctl, DCTL);
2815 }
2816
2817 if (!hs_ep->isochronous)
2818 return;
2819
2820 if (list_empty(&hs_ep->queue)) {
2821 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2822 __func__, hs_ep);
2823 return;
2824 }
2825
2826 do {
2827 hs_req = get_ep_head(hs_ep);
2828 if (hs_req)
2829 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2830 -ENODATA);
2831 dwc2_gadget_incr_frame_num(hs_ep);
2832 /* Update current frame number value. */
2833 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2834 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2835
2836 dwc2_gadget_start_next_request(hs_ep);
2837}
2838
2839/**
2840 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2841 * @ep: The endpoint on which interrupt is asserted.
2842 *
2843 * This is starting point for ISOC-OUT transfer, synchronization done with
2844 * first out token received from host while corresponding EP is disabled.
2845 *
2846 * Device does not know initial frame in which out token will come. For this
2847 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2848 * getting this interrupt SW starts calculation for next transfer frame.
2849 */
2850static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2851{
2852 struct dwc2_hsotg *hsotg = ep->parent;
2853 int dir_in = ep->dir_in;
2854 u32 doepmsk;
2855
2856 if (dir_in || !ep->isochronous)
2857 return;
2858
2859 if (using_desc_dma(hsotg)) {
2860 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2861 /* Start first ISO Out */
2862 ep->target_frame = hsotg->frame_number;
2863 dwc2_gadget_start_isoc_ddma(ep);
2864 }
2865 return;
2866 }
2867
2868 if (ep->interval > 1 &&
2869 ep->target_frame == TARGET_FRAME_INITIAL) {
2870 u32 ctrl;
2871
2872 ep->target_frame = hsotg->frame_number;
2873 dwc2_gadget_incr_frame_num(ep);
2874
2875 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2876 if (ep->target_frame & 0x1)
2877 ctrl |= DXEPCTL_SETODDFR;
2878 else
2879 ctrl |= DXEPCTL_SETEVENFR;
2880
2881 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2882 }
2883
2884 dwc2_gadget_start_next_request(ep);
2885 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2886 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2887 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2888}
2889
2890/**
2891 * dwc2_gadget_handle_nak - handle NAK interrupt
2892 * @hs_ep: The endpoint on which interrupt is asserted.
2893 *
2894 * This is starting point for ISOC-IN transfer, synchronization done with
2895 * first IN token received from host while corresponding EP is disabled.
2896 *
2897 * Device does not know when first one token will arrive from host. On first
2898 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2899 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2900 * sent in response to that as there was no data in FIFO. SW is basing on this
2901 * interrupt to obtain frame in which token has come and then based on the
2902 * interval calculates next frame for transfer.
2903 */
2904static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2905{
2906 struct dwc2_hsotg *hsotg = hs_ep->parent;
2907 int dir_in = hs_ep->dir_in;
2908
2909 if (!dir_in || !hs_ep->isochronous)
2910 return;
2911
2912 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2913
2914 if (using_desc_dma(hsotg)) {
2915 hs_ep->target_frame = hsotg->frame_number;
2916 dwc2_gadget_incr_frame_num(hs_ep);
2917
2918 /* In service interval mode target_frame must
2919 * be set to last (u)frame of the service interval.
2920 */
2921 if (hsotg->params.service_interval) {
2922 /* Set target_frame to the first (u)frame of
2923 * the service interval
2924 */
2925 hs_ep->target_frame &= ~hs_ep->interval + 1;
2926
2927 /* Set target_frame to the last (u)frame of
2928 * the service interval
2929 */
2930 dwc2_gadget_incr_frame_num(hs_ep);
2931 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2932 }
2933
2934 dwc2_gadget_start_isoc_ddma(hs_ep);
2935 return;
2936 }
2937
2938 hs_ep->target_frame = hsotg->frame_number;
2939 if (hs_ep->interval > 1) {
2940 u32 ctrl = dwc2_readl(hsotg,
2941 DIEPCTL(hs_ep->index));
2942 if (hs_ep->target_frame & 0x1)
2943 ctrl |= DXEPCTL_SETODDFR;
2944 else
2945 ctrl |= DXEPCTL_SETEVENFR;
2946
2947 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2948 }
2949
2950 dwc2_hsotg_complete_request(hsotg, hs_ep,
2951 get_ep_head(hs_ep), 0);
2952 }
2953
2954 if (!using_desc_dma(hsotg))
2955 dwc2_gadget_incr_frame_num(hs_ep);
2956}
2957
2958/**
2959 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2960 * @hsotg: The driver state
2961 * @idx: The index for the endpoint (0..15)
2962 * @dir_in: Set if this is an IN endpoint
2963 *
2964 * Process and clear any interrupt pending for an individual endpoint
2965 */
2966static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2967 int dir_in)
2968{
2969 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2970 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2971 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2972 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2973 u32 ints;
2974 u32 ctrl;
2975
2976 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2977 ctrl = dwc2_readl(hsotg, epctl_reg);
2978
2979 /* Clear endpoint interrupts */
2980 dwc2_writel(hsotg, ints, epint_reg);
2981
2982 if (!hs_ep) {
2983 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2984 __func__, idx, dir_in ? "in" : "out");
2985 return;
2986 }
2987
2988 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2989 __func__, idx, dir_in ? "in" : "out", ints);
2990
2991 /* Don't process XferCompl interrupt if it is a setup packet */
2992 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2993 ints &= ~DXEPINT_XFERCOMPL;
2994
2995 /*
2996 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2997 * stage and xfercomplete was generated without SETUP phase done
2998 * interrupt. SW should parse received setup packet only after host's
2999 * exit from setup phase of control transfer.
3000 */
3001 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3002 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3003 ints &= ~DXEPINT_XFERCOMPL;
3004
3005 if (ints & DXEPINT_XFERCOMPL) {
3006 dev_dbg(hsotg->dev,
3007 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3008 __func__, dwc2_readl(hsotg, epctl_reg),
3009 dwc2_readl(hsotg, epsiz_reg));
3010
3011 /* In DDMA handle isochronous requests separately */
3012 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3013 /* XferCompl set along with BNA */
3014 if (!(ints & DXEPINT_BNAINTR))
3015 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3016 } else if (dir_in) {
3017 /*
3018 * We get OutDone from the FIFO, so we only
3019 * need to look at completing IN requests here
3020 * if operating slave mode
3021 */
3022 if (hs_ep->isochronous && hs_ep->interval > 1)
3023 dwc2_gadget_incr_frame_num(hs_ep);
3024
3025 dwc2_hsotg_complete_in(hsotg, hs_ep);
3026 if (ints & DXEPINT_NAKINTRPT)
3027 ints &= ~DXEPINT_NAKINTRPT;
3028
3029 if (idx == 0 && !hs_ep->req)
3030 dwc2_hsotg_enqueue_setup(hsotg);
3031 } else if (using_dma(hsotg)) {
3032 /*
3033 * We're using DMA, we need to fire an OutDone here
3034 * as we ignore the RXFIFO.
3035 */
3036 if (hs_ep->isochronous && hs_ep->interval > 1)
3037 dwc2_gadget_incr_frame_num(hs_ep);
3038
3039 dwc2_hsotg_handle_outdone(hsotg, idx);
3040 }
3041 }
3042
3043 if (ints & DXEPINT_EPDISBLD)
3044 dwc2_gadget_handle_ep_disabled(hs_ep);
3045
3046 if (ints & DXEPINT_OUTTKNEPDIS)
3047 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3048
3049 if (ints & DXEPINT_NAKINTRPT)
3050 dwc2_gadget_handle_nak(hs_ep);
3051
3052 if (ints & DXEPINT_AHBERR)
3053 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3054
3055 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3056 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3057
3058 if (using_dma(hsotg) && idx == 0) {
3059 /*
3060 * this is the notification we've received a
3061 * setup packet. In non-DMA mode we'd get this
3062 * from the RXFIFO, instead we need to process
3063 * the setup here.
3064 */
3065
3066 if (dir_in)
3067 WARN_ON_ONCE(1);
3068 else
3069 dwc2_hsotg_handle_outdone(hsotg, 0);
3070 }
3071 }
3072
3073 if (ints & DXEPINT_STSPHSERCVD) {
3074 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3075
3076 /* Safety check EP0 state when STSPHSERCVD asserted */
3077 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3078 /* Move to STATUS IN for DDMA */
3079 if (using_desc_dma(hsotg)) {
3080 if (!hsotg->delayed_status)
3081 dwc2_hsotg_ep0_zlp(hsotg, true);
3082 else
3083 /* In case of 3 stage Control Write with delayed
3084 * status, when Status IN transfer started
3085 * before STSPHSERCVD asserted, NAKSTS bit not
3086 * cleared by CNAK in dwc2_hsotg_start_req()
3087 * function. Clear now NAKSTS to allow complete
3088 * transfer.
3089 */
3090 dwc2_set_bit(hsotg, DIEPCTL(0),
3091 DXEPCTL_CNAK);
3092 }
3093 }
3094
3095 }
3096
3097 if (ints & DXEPINT_BACK2BACKSETUP)
3098 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3099
3100 if (ints & DXEPINT_BNAINTR) {
3101 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3102 if (hs_ep->isochronous)
3103 dwc2_gadget_handle_isoc_bna(hs_ep);
3104 }
3105
3106 if (dir_in && !hs_ep->isochronous) {
3107 /* not sure if this is important, but we'll clear it anyway */
3108 if (ints & DXEPINT_INTKNTXFEMP) {
3109 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3110 __func__, idx);
3111 }
3112
3113 /* this probably means something bad is happening */
3114 if (ints & DXEPINT_INTKNEPMIS) {
3115 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3116 __func__, idx);
3117 }
3118
3119 /* FIFO has space or is empty (see GAHBCFG) */
3120 if (hsotg->dedicated_fifos &&
3121 ints & DXEPINT_TXFEMP) {
3122 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3123 __func__, idx);
3124 if (!using_dma(hsotg))
3125 dwc2_hsotg_trytx(hsotg, hs_ep);
3126 }
3127 }
3128}
3129
3130/**
3131 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3132 * @hsotg: The device state.
3133 *
3134 * Handle updating the device settings after the enumeration phase has
3135 * been completed.
3136 */
3137static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3138{
3139 u32 dsts = dwc2_readl(hsotg, DSTS);
3140 int ep0_mps = 0, ep_mps = 8;
3141
3142 /*
3143 * This should signal the finish of the enumeration phase
3144 * of the USB handshaking, so we should now know what rate
3145 * we connected at.
3146 */
3147
3148 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3149
3150 /*
3151 * note, since we're limited by the size of transfer on EP0, and
3152 * it seems IN transfers must be a even number of packets we do
3153 * not advertise a 64byte MPS on EP0.
3154 */
3155
3156 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3157 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3158 case DSTS_ENUMSPD_FS:
3159 case DSTS_ENUMSPD_FS48:
3160 hsotg->gadget.speed = USB_SPEED_FULL;
3161 ep0_mps = EP0_MPS_LIMIT;
3162 ep_mps = 1023;
3163 break;
3164
3165 case DSTS_ENUMSPD_HS:
3166 hsotg->gadget.speed = USB_SPEED_HIGH;
3167 ep0_mps = EP0_MPS_LIMIT;
3168 ep_mps = 1024;
3169 break;
3170
3171 case DSTS_ENUMSPD_LS:
3172 hsotg->gadget.speed = USB_SPEED_LOW;
3173 ep0_mps = 8;
3174 ep_mps = 8;
3175 /*
3176 * note, we don't actually support LS in this driver at the
3177 * moment, and the documentation seems to imply that it isn't
3178 * supported by the PHYs on some of the devices.
3179 */
3180 break;
3181 }
3182 dev_info(hsotg->dev, "new device is %s\n",
3183 usb_speed_string(hsotg->gadget.speed));
3184
3185 /*
3186 * we should now know the maximum packet size for an
3187 * endpoint, so set the endpoints to a default value.
3188 */
3189
3190 if (ep0_mps) {
3191 int i;
3192 /* Initialize ep0 for both in and out directions */
3193 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3194 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3195 for (i = 1; i < hsotg->num_of_eps; i++) {
3196 if (hsotg->eps_in[i])
3197 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3198 0, 1);
3199 if (hsotg->eps_out[i])
3200 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3201 0, 0);
3202 }
3203 }
3204
3205 /* ensure after enumeration our EP0 is active */
3206
3207 dwc2_hsotg_enqueue_setup(hsotg);
3208
3209 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3210 dwc2_readl(hsotg, DIEPCTL0),
3211 dwc2_readl(hsotg, DOEPCTL0));
3212}
3213
3214/**
3215 * kill_all_requests - remove all requests from the endpoint's queue
3216 * @hsotg: The device state.
3217 * @ep: The endpoint the requests may be on.
3218 * @result: The result code to use.
3219 *
3220 * Go through the requests on the given endpoint and mark them
3221 * completed with the given result code.
3222 */
3223static void kill_all_requests(struct dwc2_hsotg *hsotg,
3224 struct dwc2_hsotg_ep *ep,
3225 int result)
3226{
3227 unsigned int size;
3228
3229 ep->req = NULL;
3230
3231 while (!list_empty(&ep->queue)) {
3232 struct dwc2_hsotg_req *req = get_ep_head(ep);
3233
3234 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3235 }
3236
3237 if (!hsotg->dedicated_fifos)
3238 return;
3239 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3240 if (size < ep->fifo_size)
3241 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3242}
3243
3244/**
3245 * dwc2_hsotg_disconnect - disconnect service
3246 * @hsotg: The device state.
3247 *
3248 * The device has been disconnected. Remove all current
3249 * transactions and signal the gadget driver that this
3250 * has happened.
3251 */
3252void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3253{
3254 unsigned int ep;
3255
3256 if (!hsotg->connected)
3257 return;
3258
3259 hsotg->connected = 0;
3260 hsotg->test_mode = 0;
3261
3262 /* all endpoints should be shutdown */
3263 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3264 if (hsotg->eps_in[ep])
3265 kill_all_requests(hsotg, hsotg->eps_in[ep],
3266 -ESHUTDOWN);
3267 if (hsotg->eps_out[ep])
3268 kill_all_requests(hsotg, hsotg->eps_out[ep],
3269 -ESHUTDOWN);
3270 }
3271
3272 call_gadget(hsotg, disconnect);
3273 hsotg->lx_state = DWC2_L3;
3274
3275 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3276}
3277
3278/**
3279 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3280 * @hsotg: The device state:
3281 * @periodic: True if this is a periodic FIFO interrupt
3282 */
3283static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3284{
3285 struct dwc2_hsotg_ep *ep;
3286 int epno, ret;
3287
3288 /* look through for any more data to transmit */
3289 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3290 ep = index_to_ep(hsotg, epno, 1);
3291
3292 if (!ep)
3293 continue;
3294
3295 if (!ep->dir_in)
3296 continue;
3297
3298 if ((periodic && !ep->periodic) ||
3299 (!periodic && ep->periodic))
3300 continue;
3301
3302 ret = dwc2_hsotg_trytx(hsotg, ep);
3303 if (ret < 0)
3304 break;
3305 }
3306}
3307
3308/* IRQ flags which will trigger a retry around the IRQ loop */
3309#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3310 GINTSTS_PTXFEMP | \
3311 GINTSTS_RXFLVL)
3312
3313static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3314/**
3315 * dwc2_hsotg_core_init - issue softreset to the core
3316 * @hsotg: The device state
3317 * @is_usb_reset: Usb resetting flag
3318 *
3319 * Issue a soft reset to the core, and await the core finishing it.
3320 */
3321void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3322 bool is_usb_reset)
3323{
3324 u32 intmsk;
3325 u32 val;
3326 u32 usbcfg;
3327 u32 dcfg = 0;
3328 int ep;
3329
3330 /* Kill any ep0 requests as controller will be reinitialized */
3331 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3332
3333 if (!is_usb_reset) {
3334 if (dwc2_core_reset(hsotg, true))
3335 return;
3336 } else {
3337 /* all endpoints should be shutdown */
3338 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3339 if (hsotg->eps_in[ep])
3340 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3341 if (hsotg->eps_out[ep])
3342 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3343 }
3344 }
3345
3346 /*
3347 * we must now enable ep0 ready for host detection and then
3348 * set configuration.
3349 */
3350
3351 /* keep other bits untouched (so e.g. forced modes are not lost) */
3352 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3353 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3354 usbcfg |= GUSBCFG_TOUTCAL(7);
3355
3356 /* remove the HNP/SRP and set the PHY */
3357 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3358 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3359
3360 dwc2_phy_init(hsotg, true);
3361
3362 dwc2_hsotg_init_fifo(hsotg);
3363
3364 if (!is_usb_reset)
3365 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3366
3367 dcfg |= DCFG_EPMISCNT(1);
3368
3369 switch (hsotg->params.speed) {
3370 case DWC2_SPEED_PARAM_LOW:
3371 dcfg |= DCFG_DEVSPD_LS;
3372 break;
3373 case DWC2_SPEED_PARAM_FULL:
3374 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3375 dcfg |= DCFG_DEVSPD_FS48;
3376 else
3377 dcfg |= DCFG_DEVSPD_FS;
3378 break;
3379 default:
3380 dcfg |= DCFG_DEVSPD_HS;
3381 }
3382
3383 if (hsotg->params.ipg_isoc_en)
3384 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3385
3386 dwc2_writel(hsotg, dcfg, DCFG);
3387
3388 /* Clear any pending OTG interrupts */
3389 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3390
3391 /* Clear any pending interrupts */
3392 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3393 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3394 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3395 GINTSTS_USBRST | GINTSTS_RESETDET |
3396 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3397 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3398 GINTSTS_LPMTRANRCVD;
3399
3400 if (!using_desc_dma(hsotg))
3401 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3402
3403 if (!hsotg->params.external_id_pin_ctl)
3404 intmsk |= GINTSTS_CONIDSTSCHNG;
3405
3406 dwc2_writel(hsotg, intmsk, GINTMSK);
3407
3408 if (using_dma(hsotg)) {
3409 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3410 hsotg->params.ahbcfg,
3411 GAHBCFG);
3412
3413 /* Set DDMA mode support in the core if needed */
3414 if (using_desc_dma(hsotg))
3415 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3416
3417 } else {
3418 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3419 (GAHBCFG_NP_TXF_EMP_LVL |
3420 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3421 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3422 }
3423
3424 /*
3425 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3426 * when we have no data to transfer. Otherwise we get being flooded by
3427 * interrupts.
3428 */
3429
3430 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3431 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3432 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3433 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3434 DIEPMSK);
3435
3436 /*
3437 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3438 * DMA mode we may need this and StsPhseRcvd.
3439 */
3440 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3441 DOEPMSK_STSPHSERCVDMSK) : 0) |
3442 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3443 DOEPMSK_SETUPMSK,
3444 DOEPMSK);
3445
3446 /* Enable BNA interrupt for DDMA */
3447 if (using_desc_dma(hsotg)) {
3448 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3449 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3450 }
3451
3452 /* Enable Service Interval mode if supported */
3453 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3454 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3455
3456 dwc2_writel(hsotg, 0, DAINTMSK);
3457
3458 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3459 dwc2_readl(hsotg, DIEPCTL0),
3460 dwc2_readl(hsotg, DOEPCTL0));
3461
3462 /* enable in and out endpoint interrupts */
3463 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3464
3465 /*
3466 * Enable the RXFIFO when in slave mode, as this is how we collect
3467 * the data. In DMA mode, we get events from the FIFO but also
3468 * things we cannot process, so do not use it.
3469 */
3470 if (!using_dma(hsotg))
3471 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3472
3473 /* Enable interrupts for EP0 in and out */
3474 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3475 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3476
3477 if (!is_usb_reset) {
3478 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3479 udelay(10); /* see openiboot */
3480 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3481 }
3482
3483 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3484
3485 /*
3486 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3487 * writing to the EPCTL register..
3488 */
3489
3490 /* set to read 1 8byte packet */
3491 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3492 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3493
3494 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3495 DXEPCTL_CNAK | DXEPCTL_EPENA |
3496 DXEPCTL_USBACTEP,
3497 DOEPCTL0);
3498
3499 /* enable, but don't activate EP0in */
3500 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3501 DXEPCTL_USBACTEP, DIEPCTL0);
3502
3503 /* clear global NAKs */
3504 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3505 if (!is_usb_reset)
3506 val |= DCTL_SFTDISCON;
3507 dwc2_set_bit(hsotg, DCTL, val);
3508
3509 /* configure the core to support LPM */
3510 dwc2_gadget_init_lpm(hsotg);
3511
3512 /* program GREFCLK register if needed */
3513 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3514 dwc2_gadget_program_ref_clk(hsotg);
3515
3516 /* must be at-least 3ms to allow bus to see disconnect */
3517 mdelay(3);
3518
3519 hsotg->lx_state = DWC2_L0;
3520
3521 dwc2_hsotg_enqueue_setup(hsotg);
3522
3523 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3524 dwc2_readl(hsotg, DIEPCTL0),
3525 dwc2_readl(hsotg, DOEPCTL0));
3526}
3527
3528static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3529{
3530 /* set the soft-disconnect bit */
3531 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3532}
3533
3534void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3535{
3536 /* remove the soft-disconnect and let's go */
3537 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3538}
3539
3540/**
3541 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3542 * @hsotg: The device state:
3543 *
3544 * This interrupt indicates one of the following conditions occurred while
3545 * transmitting an ISOC transaction.
3546 * - Corrupted IN Token for ISOC EP.
3547 * - Packet not complete in FIFO.
3548 *
3549 * The following actions will be taken:
3550 * - Determine the EP
3551 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3552 */
3553static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3554{
3555 struct dwc2_hsotg_ep *hs_ep;
3556 u32 epctrl;
3557 u32 daintmsk;
3558 u32 idx;
3559
3560 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3561
3562 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3563
3564 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3565 hs_ep = hsotg->eps_in[idx];
3566 /* Proceed only unmasked ISOC EPs */
3567 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3568 continue;
3569
3570 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3571 if ((epctrl & DXEPCTL_EPENA) &&
3572 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3573 epctrl |= DXEPCTL_SNAK;
3574 epctrl |= DXEPCTL_EPDIS;
3575 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3576 }
3577 }
3578
3579 /* Clear interrupt */
3580 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3581}
3582
3583/**
3584 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3585 * @hsotg: The device state:
3586 *
3587 * This interrupt indicates one of the following conditions occurred while
3588 * transmitting an ISOC transaction.
3589 * - Corrupted OUT Token for ISOC EP.
3590 * - Packet not complete in FIFO.
3591 *
3592 * The following actions will be taken:
3593 * - Determine the EP
3594 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3595 */
3596static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3597{
3598 u32 gintsts;
3599 u32 gintmsk;
3600 u32 daintmsk;
3601 u32 epctrl;
3602 struct dwc2_hsotg_ep *hs_ep;
3603 int idx;
3604
3605 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3606
3607 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3608 daintmsk >>= DAINT_OUTEP_SHIFT;
3609
3610 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3611 hs_ep = hsotg->eps_out[idx];
3612 /* Proceed only unmasked ISOC EPs */
3613 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3614 continue;
3615
3616 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3617 if ((epctrl & DXEPCTL_EPENA) &&
3618 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3619 /* Unmask GOUTNAKEFF interrupt */
3620 gintmsk = dwc2_readl(hsotg, GINTMSK);
3621 gintmsk |= GINTSTS_GOUTNAKEFF;
3622 dwc2_writel(hsotg, gintmsk, GINTMSK);
3623
3624 gintsts = dwc2_readl(hsotg, GINTSTS);
3625 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3626 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3627 break;
3628 }
3629 }
3630 }
3631
3632 /* Clear interrupt */
3633 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3634}
3635
3636/**
3637 * dwc2_hsotg_irq - handle device interrupt
3638 * @irq: The IRQ number triggered
3639 * @pw: The pw value when registered the handler.
3640 */
3641static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3642{
3643 struct dwc2_hsotg *hsotg = pw;
3644 int retry_count = 8;
3645 u32 gintsts;
3646 u32 gintmsk;
3647
3648 if (!dwc2_is_device_mode(hsotg))
3649 return IRQ_NONE;
3650
3651 spin_lock(&hsotg->lock);
3652irq_retry:
3653 gintsts = dwc2_readl(hsotg, GINTSTS);
3654 gintmsk = dwc2_readl(hsotg, GINTMSK);
3655
3656 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3657 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3658
3659 gintsts &= gintmsk;
3660
3661 if (gintsts & GINTSTS_RESETDET) {
3662 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3663
3664 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3665
3666 /* This event must be used only if controller is suspended */
3667 if (hsotg->lx_state == DWC2_L2) {
3668 dwc2_exit_partial_power_down(hsotg, true);
3669 hsotg->lx_state = DWC2_L0;
3670 }
3671 }
3672
3673 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3674 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3675 u32 connected = hsotg->connected;
3676
3677 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3678 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3679 dwc2_readl(hsotg, GNPTXSTS));
3680
3681 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3682
3683 /* Report disconnection if it is not already done. */
3684 dwc2_hsotg_disconnect(hsotg);
3685
3686 /* Reset device address to zero */
3687 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3688
3689 if (usb_status & GOTGCTL_BSESVLD && connected)
3690 dwc2_hsotg_core_init_disconnected(hsotg, true);
3691 }
3692
3693 if (gintsts & GINTSTS_ENUMDONE) {
3694 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3695
3696 dwc2_hsotg_irq_enumdone(hsotg);
3697 }
3698
3699 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3700 u32 daint = dwc2_readl(hsotg, DAINT);
3701 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3702 u32 daint_out, daint_in;
3703 int ep;
3704
3705 daint &= daintmsk;
3706 daint_out = daint >> DAINT_OUTEP_SHIFT;
3707 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3708
3709 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3710
3711 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3712 ep++, daint_out >>= 1) {
3713 if (daint_out & 1)
3714 dwc2_hsotg_epint(hsotg, ep, 0);
3715 }
3716
3717 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3718 ep++, daint_in >>= 1) {
3719 if (daint_in & 1)
3720 dwc2_hsotg_epint(hsotg, ep, 1);
3721 }
3722 }
3723
3724 /* check both FIFOs */
3725
3726 if (gintsts & GINTSTS_NPTXFEMP) {
3727 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3728
3729 /*
3730 * Disable the interrupt to stop it happening again
3731 * unless one of these endpoint routines decides that
3732 * it needs re-enabling
3733 */
3734
3735 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3736 dwc2_hsotg_irq_fifoempty(hsotg, false);
3737 }
3738
3739 if (gintsts & GINTSTS_PTXFEMP) {
3740 dev_dbg(hsotg->dev, "PTxFEmp\n");
3741
3742 /* See note in GINTSTS_NPTxFEmp */
3743
3744 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3745 dwc2_hsotg_irq_fifoempty(hsotg, true);
3746 }
3747
3748 if (gintsts & GINTSTS_RXFLVL) {
3749 /*
3750 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3751 * we need to retry dwc2_hsotg_handle_rx if this is still
3752 * set.
3753 */
3754
3755 dwc2_hsotg_handle_rx(hsotg);
3756 }
3757
3758 if (gintsts & GINTSTS_ERLYSUSP) {
3759 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3760 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3761 }
3762
3763 /*
3764 * these next two seem to crop-up occasionally causing the core
3765 * to shutdown the USB transfer, so try clearing them and logging
3766 * the occurrence.
3767 */
3768
3769 if (gintsts & GINTSTS_GOUTNAKEFF) {
3770 u8 idx;
3771 u32 epctrl;
3772 u32 gintmsk;
3773 u32 daintmsk;
3774 struct dwc2_hsotg_ep *hs_ep;
3775
3776 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3777 daintmsk >>= DAINT_OUTEP_SHIFT;
3778 /* Mask this interrupt */
3779 gintmsk = dwc2_readl(hsotg, GINTMSK);
3780 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3781 dwc2_writel(hsotg, gintmsk, GINTMSK);
3782
3783 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3784 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3785 hs_ep = hsotg->eps_out[idx];
3786 /* Proceed only unmasked ISOC EPs */
3787 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3788 continue;
3789
3790 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3791
3792 if (epctrl & DXEPCTL_EPENA) {
3793 epctrl |= DXEPCTL_SNAK;
3794 epctrl |= DXEPCTL_EPDIS;
3795 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3796 }
3797 }
3798
3799 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3800 }
3801
3802 if (gintsts & GINTSTS_GINNAKEFF) {
3803 dev_info(hsotg->dev, "GINNakEff triggered\n");
3804
3805 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3806
3807 dwc2_hsotg_dump(hsotg);
3808 }
3809
3810 if (gintsts & GINTSTS_INCOMPL_SOIN)
3811 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3812
3813 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3814 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3815
3816 /*
3817 * if we've had fifo events, we should try and go around the
3818 * loop again to see if there's any point in returning yet.
3819 */
3820
3821 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3822 goto irq_retry;
3823
3824 /* Check WKUP_ALERT interrupt*/
3825 if (hsotg->params.service_interval)
3826 dwc2_gadget_wkup_alert_handler(hsotg);
3827
3828 spin_unlock(&hsotg->lock);
3829
3830 return IRQ_HANDLED;
3831}
3832
3833static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3834 struct dwc2_hsotg_ep *hs_ep)
3835{
3836 u32 epctrl_reg;
3837 u32 epint_reg;
3838
3839 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3840 DOEPCTL(hs_ep->index);
3841 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3842 DOEPINT(hs_ep->index);
3843
3844 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3845 hs_ep->name);
3846
3847 if (hs_ep->dir_in) {
3848 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3849 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3850 /* Wait for Nak effect */
3851 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3852 DXEPINT_INEPNAKEFF, 100))
3853 dev_warn(hsotg->dev,
3854 "%s: timeout DIEPINT.NAKEFF\n",
3855 __func__);
3856 } else {
3857 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3858 /* Wait for Nak effect */
3859 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3860 GINTSTS_GINNAKEFF, 100))
3861 dev_warn(hsotg->dev,
3862 "%s: timeout GINTSTS.GINNAKEFF\n",
3863 __func__);
3864 }
3865 } else {
3866 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3867 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3868
3869 /* Wait for global nak to take effect */
3870 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3871 GINTSTS_GOUTNAKEFF, 100))
3872 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3873 __func__);
3874 }
3875
3876 /* Disable ep */
3877 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3878
3879 /* Wait for ep to be disabled */
3880 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3881 dev_warn(hsotg->dev,
3882 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3883
3884 /* Clear EPDISBLD interrupt */
3885 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3886
3887 if (hs_ep->dir_in) {
3888 unsigned short fifo_index;
3889
3890 if (hsotg->dedicated_fifos || hs_ep->periodic)
3891 fifo_index = hs_ep->fifo_index;
3892 else
3893 fifo_index = 0;
3894
3895 /* Flush TX FIFO */
3896 dwc2_flush_tx_fifo(hsotg, fifo_index);
3897
3898 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3899 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3900 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3901
3902 } else {
3903 /* Remove global NAKs */
3904 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3905 }
3906}
3907
3908/**
3909 * dwc2_hsotg_ep_enable - enable the given endpoint
3910 * @ep: The USB endpint to configure
3911 * @desc: The USB endpoint descriptor to configure with.
3912 *
3913 * This is called from the USB gadget code's usb_ep_enable().
3914 */
3915static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3916 const struct usb_endpoint_descriptor *desc)
3917{
3918 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3919 struct dwc2_hsotg *hsotg = hs_ep->parent;
3920 unsigned long flags;
3921 unsigned int index = hs_ep->index;
3922 u32 epctrl_reg;
3923 u32 epctrl;
3924 u32 mps;
3925 u32 mc;
3926 u32 mask;
3927 unsigned int dir_in;
3928 unsigned int i, val, size;
3929 int ret = 0;
3930 unsigned char ep_type;
3931 int desc_num;
3932
3933 dev_dbg(hsotg->dev,
3934 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3935 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3936 desc->wMaxPacketSize, desc->bInterval);
3937
3938 /* not to be called for EP0 */
3939 if (index == 0) {
3940 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3941 return -EINVAL;
3942 }
3943
3944 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3945 if (dir_in != hs_ep->dir_in) {
3946 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3947 return -EINVAL;
3948 }
3949
3950 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3951 mps = usb_endpoint_maxp(desc);
3952 mc = usb_endpoint_maxp_mult(desc);
3953
3954 /* ISOC IN in DDMA supported bInterval up to 10 */
3955 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3956 dir_in && desc->bInterval > 10) {
3957 dev_err(hsotg->dev,
3958 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3959 return -EINVAL;
3960 }
3961
3962 /* High bandwidth ISOC OUT in DDMA not supported */
3963 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3964 !dir_in && mc > 1) {
3965 dev_err(hsotg->dev,
3966 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
3967 return -EINVAL;
3968 }
3969
3970 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3971
3972 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3973 epctrl = dwc2_readl(hsotg, epctrl_reg);
3974
3975 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3976 __func__, epctrl, epctrl_reg);
3977
3978 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
3979 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
3980 else
3981 desc_num = MAX_DMA_DESC_NUM_GENERIC;
3982
3983 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3984 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3985 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3986 desc_num * sizeof(struct dwc2_dma_desc),
3987 &hs_ep->desc_list_dma, GFP_ATOMIC);
3988 if (!hs_ep->desc_list) {
3989 ret = -ENOMEM;
3990 goto error2;
3991 }
3992 }
3993
3994 spin_lock_irqsave(&hsotg->lock, flags);
3995
3996 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3997 epctrl |= DXEPCTL_MPS(mps);
3998
3999 /*
4000 * mark the endpoint as active, otherwise the core may ignore
4001 * transactions entirely for this endpoint
4002 */
4003 epctrl |= DXEPCTL_USBACTEP;
4004
4005 /* update the endpoint state */
4006 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4007
4008 /* default, set to non-periodic */
4009 hs_ep->isochronous = 0;
4010 hs_ep->periodic = 0;
4011 hs_ep->halted = 0;
4012 hs_ep->interval = desc->bInterval;
4013
4014 switch (ep_type) {
4015 case USB_ENDPOINT_XFER_ISOC:
4016 epctrl |= DXEPCTL_EPTYPE_ISO;
4017 epctrl |= DXEPCTL_SETEVENFR;
4018 hs_ep->isochronous = 1;
4019 hs_ep->interval = 1 << (desc->bInterval - 1);
4020 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4021 hs_ep->next_desc = 0;
4022 hs_ep->compl_desc = 0;
4023 if (dir_in) {
4024 hs_ep->periodic = 1;
4025 mask = dwc2_readl(hsotg, DIEPMSK);
4026 mask |= DIEPMSK_NAKMSK;
4027 dwc2_writel(hsotg, mask, DIEPMSK);
4028 } else {
4029 mask = dwc2_readl(hsotg, DOEPMSK);
4030 mask |= DOEPMSK_OUTTKNEPDISMSK;
4031 dwc2_writel(hsotg, mask, DOEPMSK);
4032 }
4033 break;
4034
4035 case USB_ENDPOINT_XFER_BULK:
4036 epctrl |= DXEPCTL_EPTYPE_BULK;
4037 break;
4038
4039 case USB_ENDPOINT_XFER_INT:
4040 if (dir_in)
4041 hs_ep->periodic = 1;
4042
4043 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4044 hs_ep->interval = 1 << (desc->bInterval - 1);
4045
4046 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4047 break;
4048
4049 case USB_ENDPOINT_XFER_CONTROL:
4050 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4051 break;
4052 }
4053
4054 /*
4055 * if the hardware has dedicated fifos, we must give each IN EP
4056 * a unique tx-fifo even if it is non-periodic.
4057 */
4058 if (dir_in && hsotg->dedicated_fifos) {
4059 u32 fifo_index = 0;
4060 u32 fifo_size = UINT_MAX;
4061
4062 size = hs_ep->ep.maxpacket * hs_ep->mc;
4063 for (i = 1; i < hsotg->num_of_eps; ++i) {
4064 if (hsotg->fifo_map & (1 << i))
4065 continue;
4066 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4067 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4068 if (val < size)
4069 continue;
4070 /* Search for smallest acceptable fifo */
4071 if (val < fifo_size) {
4072 fifo_size = val;
4073 fifo_index = i;
4074 }
4075 }
4076 if (!fifo_index) {
4077 dev_err(hsotg->dev,
4078 "%s: No suitable fifo found\n", __func__);
4079 ret = -ENOMEM;
4080 goto error1;
4081 }
4082 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4083 hsotg->fifo_map |= 1 << fifo_index;
4084 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4085 hs_ep->fifo_index = fifo_index;
4086 hs_ep->fifo_size = fifo_size;
4087 }
4088
4089 /* for non control endpoints, set PID to D0 */
4090 if (index && !hs_ep->isochronous)
4091 epctrl |= DXEPCTL_SETD0PID;
4092
4093 /* WA for Full speed ISOC IN in DDMA mode.
4094 * By Clear NAK status of EP, core will send ZLP
4095 * to IN token and assert NAK interrupt relying
4096 * on TxFIFO status only
4097 */
4098
4099 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4100 hs_ep->isochronous && dir_in) {
4101 /* The WA applies only to core versions from 2.72a
4102 * to 4.00a (including both). Also for FS_IOT_1.00a
4103 * and HS_IOT_1.00a.
4104 */
4105 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4106
4107 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4108 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4109 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4110 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4111 epctrl |= DXEPCTL_CNAK;
4112 }
4113
4114 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4115 __func__, epctrl);
4116
4117 dwc2_writel(hsotg, epctrl, epctrl_reg);
4118 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4119 __func__, dwc2_readl(hsotg, epctrl_reg));
4120
4121 /* enable the endpoint interrupt */
4122 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4123
4124error1:
4125 spin_unlock_irqrestore(&hsotg->lock, flags);
4126
4127error2:
4128 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4129 dmam_free_coherent(hsotg->dev, desc_num *
4130 sizeof(struct dwc2_dma_desc),
4131 hs_ep->desc_list, hs_ep->desc_list_dma);
4132 hs_ep->desc_list = NULL;
4133 }
4134
4135 return ret;
4136}
4137
4138/**
4139 * dwc2_hsotg_ep_disable - disable given endpoint
4140 * @ep: The endpoint to disable.
4141 */
4142static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4143{
4144 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4145 struct dwc2_hsotg *hsotg = hs_ep->parent;
4146 int dir_in = hs_ep->dir_in;
4147 int index = hs_ep->index;
4148 u32 epctrl_reg;
4149 u32 ctrl;
4150
4151 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4152
4153 if (ep == &hsotg->eps_out[0]->ep) {
4154 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4155 return -EINVAL;
4156 }
4157
4158 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4159 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4160 return -EINVAL;
4161 }
4162
4163 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4164
4165 ctrl = dwc2_readl(hsotg, epctrl_reg);
4166
4167 if (ctrl & DXEPCTL_EPENA)
4168 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4169
4170 ctrl &= ~DXEPCTL_EPENA;
4171 ctrl &= ~DXEPCTL_USBACTEP;
4172 ctrl |= DXEPCTL_SNAK;
4173
4174 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4175 dwc2_writel(hsotg, ctrl, epctrl_reg);
4176
4177 /* disable endpoint interrupts */
4178 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4179
4180 /* terminate all requests with shutdown */
4181 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4182
4183 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4184 hs_ep->fifo_index = 0;
4185 hs_ep->fifo_size = 0;
4186
4187 return 0;
4188}
4189
4190static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4191{
4192 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4193 struct dwc2_hsotg *hsotg = hs_ep->parent;
4194 unsigned long flags;
4195 int ret;
4196
4197 spin_lock_irqsave(&hsotg->lock, flags);
4198 ret = dwc2_hsotg_ep_disable(ep);
4199 spin_unlock_irqrestore(&hsotg->lock, flags);
4200 return ret;
4201}
4202
4203/**
4204 * on_list - check request is on the given endpoint
4205 * @ep: The endpoint to check.
4206 * @test: The request to test if it is on the endpoint.
4207 */
4208static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4209{
4210 struct dwc2_hsotg_req *req, *treq;
4211
4212 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4213 if (req == test)
4214 return true;
4215 }
4216
4217 return false;
4218}
4219
4220/**
4221 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4222 * @ep: The endpoint to dequeue.
4223 * @req: The request to be removed from a queue.
4224 */
4225static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4226{
4227 struct dwc2_hsotg_req *hs_req = our_req(req);
4228 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4229 struct dwc2_hsotg *hs = hs_ep->parent;
4230 unsigned long flags;
4231
4232 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4233
4234 spin_lock_irqsave(&hs->lock, flags);
4235
4236 if (!on_list(hs_ep, hs_req)) {
4237 spin_unlock_irqrestore(&hs->lock, flags);
4238 return -EINVAL;
4239 }
4240
4241 /* Dequeue already started request */
4242 if (req == &hs_ep->req->req)
4243 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4244
4245 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4246 spin_unlock_irqrestore(&hs->lock, flags);
4247
4248 return 0;
4249}
4250
4251/**
4252 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4253 * @ep: The endpoint to set halt.
4254 * @value: Set or unset the halt.
4255 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4256 * the endpoint is busy processing requests.
4257 *
4258 * We need to stall the endpoint immediately if request comes from set_feature
4259 * protocol command handler.
4260 */
4261static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4262{
4263 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4264 struct dwc2_hsotg *hs = hs_ep->parent;
4265 int index = hs_ep->index;
4266 u32 epreg;
4267 u32 epctl;
4268 u32 xfertype;
4269
4270 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4271
4272 if (index == 0) {
4273 if (value)
4274 dwc2_hsotg_stall_ep0(hs);
4275 else
4276 dev_warn(hs->dev,
4277 "%s: can't clear halt on ep0\n", __func__);
4278 return 0;
4279 }
4280
4281 if (hs_ep->isochronous) {
4282 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4283 return -EINVAL;
4284 }
4285
4286 if (!now && value && !list_empty(&hs_ep->queue)) {
4287 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4288 ep->name);
4289 return -EAGAIN;
4290 }
4291
4292 if (hs_ep->dir_in) {
4293 epreg = DIEPCTL(index);
4294 epctl = dwc2_readl(hs, epreg);
4295
4296 if (value) {
4297 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4298 if (epctl & DXEPCTL_EPENA)
4299 epctl |= DXEPCTL_EPDIS;
4300 } else {
4301 epctl &= ~DXEPCTL_STALL;
4302 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4303 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4304 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4305 epctl |= DXEPCTL_SETD0PID;
4306 }
4307 dwc2_writel(hs, epctl, epreg);
4308 } else {
4309 epreg = DOEPCTL(index);
4310 epctl = dwc2_readl(hs, epreg);
4311
4312 if (value) {
4313 epctl |= DXEPCTL_STALL;
4314 } else {
4315 epctl &= ~DXEPCTL_STALL;
4316 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4317 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4318 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4319 epctl |= DXEPCTL_SETD0PID;
4320 }
4321 dwc2_writel(hs, epctl, epreg);
4322 }
4323
4324 hs_ep->halted = value;
4325
4326 return 0;
4327}
4328
4329/**
4330 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4331 * @ep: The endpoint to set halt.
4332 * @value: Set or unset the halt.
4333 */
4334static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4335{
4336 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4337 struct dwc2_hsotg *hs = hs_ep->parent;
4338 unsigned long flags = 0;
4339 int ret = 0;
4340
4341 spin_lock_irqsave(&hs->lock, flags);
4342 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4343 spin_unlock_irqrestore(&hs->lock, flags);
4344
4345 return ret;
4346}
4347
4348static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4349 .enable = dwc2_hsotg_ep_enable,
4350 .disable = dwc2_hsotg_ep_disable_lock,
4351 .alloc_request = dwc2_hsotg_ep_alloc_request,
4352 .free_request = dwc2_hsotg_ep_free_request,
4353 .queue = dwc2_hsotg_ep_queue_lock,
4354 .dequeue = dwc2_hsotg_ep_dequeue,
4355 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4356 /* note, don't believe we have any call for the fifo routines */
4357};
4358
4359/**
4360 * dwc2_hsotg_init - initialize the usb core
4361 * @hsotg: The driver state
4362 */
4363static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4364{
4365 /* unmask subset of endpoint interrupts */
4366
4367 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4368 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4369 DIEPMSK);
4370
4371 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4372 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4373 DOEPMSK);
4374
4375 dwc2_writel(hsotg, 0, DAINTMSK);
4376
4377 /* Be in disconnected state until gadget is registered */
4378 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4379
4380 /* setup fifos */
4381
4382 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4383 dwc2_readl(hsotg, GRXFSIZ),
4384 dwc2_readl(hsotg, GNPTXFSIZ));
4385
4386 dwc2_hsotg_init_fifo(hsotg);
4387
4388 if (using_dma(hsotg))
4389 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4390}
4391
4392/**
4393 * dwc2_hsotg_udc_start - prepare the udc for work
4394 * @gadget: The usb gadget state
4395 * @driver: The usb gadget driver
4396 *
4397 * Perform initialization to prepare udc device and driver
4398 * to work.
4399 */
4400static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4401 struct usb_gadget_driver *driver)
4402{
4403 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4404 unsigned long flags;
4405 int ret;
4406
4407 if (!hsotg) {
4408 pr_err("%s: called with no device\n", __func__);
4409 return -ENODEV;
4410 }
4411
4412 if (!driver) {
4413 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4414 return -EINVAL;
4415 }
4416
4417 if (driver->max_speed < USB_SPEED_FULL)
4418 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4419
4420 if (!driver->setup) {
4421 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4422 return -EINVAL;
4423 }
4424
4425 WARN_ON(hsotg->driver);
4426
4427 driver->driver.bus = NULL;
4428 hsotg->driver = driver;
4429 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4430 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4431
4432 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4433 ret = dwc2_lowlevel_hw_enable(hsotg);
4434 if (ret)
4435 goto err;
4436 }
4437
4438 if (!IS_ERR_OR_NULL(hsotg->uphy))
4439 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4440
4441 spin_lock_irqsave(&hsotg->lock, flags);
4442 if (dwc2_hw_is_device(hsotg)) {
4443 dwc2_hsotg_init(hsotg);
4444 dwc2_hsotg_core_init_disconnected(hsotg, false);
4445 }
4446
4447 hsotg->enabled = 0;
4448 spin_unlock_irqrestore(&hsotg->lock, flags);
4449
4450 gadget->sg_supported = using_desc_dma(hsotg);
4451 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4452
4453 return 0;
4454
4455err:
4456 hsotg->driver = NULL;
4457 return ret;
4458}
4459
4460/**
4461 * dwc2_hsotg_udc_stop - stop the udc
4462 * @gadget: The usb gadget state
4463 *
4464 * Stop udc hw block and stay tunned for future transmissions
4465 */
4466static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4467{
4468 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4469 unsigned long flags = 0;
4470 int ep;
4471
4472 if (!hsotg)
4473 return -ENODEV;
4474
4475 /* all endpoints should be shutdown */
4476 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4477 if (hsotg->eps_in[ep])
4478 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4479 if (hsotg->eps_out[ep])
4480 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4481 }
4482
4483 spin_lock_irqsave(&hsotg->lock, flags);
4484
4485 hsotg->driver = NULL;
4486 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4487 hsotg->enabled = 0;
4488
4489 spin_unlock_irqrestore(&hsotg->lock, flags);
4490
4491 if (!IS_ERR_OR_NULL(hsotg->uphy))
4492 otg_set_peripheral(hsotg->uphy->otg, NULL);
4493
4494 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4495 dwc2_lowlevel_hw_disable(hsotg);
4496
4497 return 0;
4498}
4499
4500/**
4501 * dwc2_hsotg_gadget_getframe - read the frame number
4502 * @gadget: The usb gadget state
4503 *
4504 * Read the {micro} frame number
4505 */
4506static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4507{
4508 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4509}
4510
4511/**
4512 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4513 * @gadget: The usb gadget state
4514 * @is_on: Current state of the USB PHY
4515 *
4516 * Connect/Disconnect the USB PHY pullup
4517 */
4518static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4519{
4520 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4521 unsigned long flags = 0;
4522
4523 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4524 hsotg->op_state);
4525
4526 /* Don't modify pullup state while in host mode */
4527 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4528 hsotg->enabled = is_on;
4529 return 0;
4530 }
4531
4532 spin_lock_irqsave(&hsotg->lock, flags);
4533 if (is_on) {
4534 hsotg->enabled = 1;
4535 dwc2_hsotg_core_init_disconnected(hsotg, false);
4536 /* Enable ACG feature in device mode,if supported */
4537 dwc2_enable_acg(hsotg);
4538 dwc2_hsotg_core_connect(hsotg);
4539 } else {
4540 dwc2_hsotg_core_disconnect(hsotg);
4541 dwc2_hsotg_disconnect(hsotg);
4542 hsotg->enabled = 0;
4543 }
4544
4545 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4546 spin_unlock_irqrestore(&hsotg->lock, flags);
4547
4548 return 0;
4549}
4550
4551static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4552{
4553 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4554 unsigned long flags;
4555
4556 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4557 spin_lock_irqsave(&hsotg->lock, flags);
4558
4559 /*
4560 * If controller is hibernated, it must exit from power_down
4561 * before being initialized / de-initialized
4562 */
4563 if (hsotg->lx_state == DWC2_L2)
4564 dwc2_exit_partial_power_down(hsotg, false);
4565
4566 if (is_active) {
4567 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4568
4569 dwc2_hsotg_core_init_disconnected(hsotg, false);
4570 if (hsotg->enabled) {
4571 /* Enable ACG feature in device mode,if supported */
4572 dwc2_enable_acg(hsotg);
4573 dwc2_hsotg_core_connect(hsotg);
4574 }
4575 } else {
4576 dwc2_hsotg_core_disconnect(hsotg);
4577 dwc2_hsotg_disconnect(hsotg);
4578 }
4579
4580 spin_unlock_irqrestore(&hsotg->lock, flags);
4581 return 0;
4582}
4583
4584/**
4585 * dwc2_hsotg_vbus_draw - report bMaxPower field
4586 * @gadget: The usb gadget state
4587 * @mA: Amount of current
4588 *
4589 * Report how much power the device may consume to the phy.
4590 */
4591static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4592{
4593 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4594
4595 if (IS_ERR_OR_NULL(hsotg->uphy))
4596 return -ENOTSUPP;
4597 return usb_phy_set_power(hsotg->uphy, mA);
4598}
4599
4600static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4601 .get_frame = dwc2_hsotg_gadget_getframe,
4602 .udc_start = dwc2_hsotg_udc_start,
4603 .udc_stop = dwc2_hsotg_udc_stop,
4604 .pullup = dwc2_hsotg_pullup,
4605 .vbus_session = dwc2_hsotg_vbus_session,
4606 .vbus_draw = dwc2_hsotg_vbus_draw,
4607};
4608
4609/**
4610 * dwc2_hsotg_initep - initialise a single endpoint
4611 * @hsotg: The device state.
4612 * @hs_ep: The endpoint to be initialised.
4613 * @epnum: The endpoint number
4614 * @dir_in: True if direction is in.
4615 *
4616 * Initialise the given endpoint (as part of the probe and device state
4617 * creation) to give to the gadget driver. Setup the endpoint name, any
4618 * direction information and other state that may be required.
4619 */
4620static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4621 struct dwc2_hsotg_ep *hs_ep,
4622 int epnum,
4623 bool dir_in)
4624{
4625 char *dir;
4626
4627 if (epnum == 0)
4628 dir = "";
4629 else if (dir_in)
4630 dir = "in";
4631 else
4632 dir = "out";
4633
4634 hs_ep->dir_in = dir_in;
4635 hs_ep->index = epnum;
4636
4637 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4638
4639 INIT_LIST_HEAD(&hs_ep->queue);
4640 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4641
4642 /* add to the list of endpoints known by the gadget driver */
4643 if (epnum)
4644 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4645
4646 hs_ep->parent = hsotg;
4647 hs_ep->ep.name = hs_ep->name;
4648
4649 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4650 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4651 else
4652 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4653 epnum ? 1024 : EP0_MPS_LIMIT);
4654 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4655
4656 if (epnum == 0) {
4657 hs_ep->ep.caps.type_control = true;
4658 } else {
4659 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4660 hs_ep->ep.caps.type_iso = true;
4661 hs_ep->ep.caps.type_bulk = true;
4662 }
4663 hs_ep->ep.caps.type_int = true;
4664 }
4665
4666 if (dir_in)
4667 hs_ep->ep.caps.dir_in = true;
4668 else
4669 hs_ep->ep.caps.dir_out = true;
4670
4671 /*
4672 * if we're using dma, we need to set the next-endpoint pointer
4673 * to be something valid.
4674 */
4675
4676 if (using_dma(hsotg)) {
4677 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4678
4679 if (dir_in)
4680 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4681 else
4682 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4683 }
4684}
4685
4686/**
4687 * dwc2_hsotg_hw_cfg - read HW configuration registers
4688 * @hsotg: Programming view of the DWC_otg controller
4689 *
4690 * Read the USB core HW configuration registers
4691 */
4692static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4693{
4694 u32 cfg;
4695 u32 ep_type;
4696 u32 i;
4697
4698 /* check hardware configuration */
4699
4700 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4701
4702 /* Add ep0 */
4703 hsotg->num_of_eps++;
4704
4705 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4706 sizeof(struct dwc2_hsotg_ep),
4707 GFP_KERNEL);
4708 if (!hsotg->eps_in[0])
4709 return -ENOMEM;
4710 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4711 hsotg->eps_out[0] = hsotg->eps_in[0];
4712
4713 cfg = hsotg->hw_params.dev_ep_dirs;
4714 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4715 ep_type = cfg & 3;
4716 /* Direction in or both */
4717 if (!(ep_type & 2)) {
4718 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4719 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4720 if (!hsotg->eps_in[i])
4721 return -ENOMEM;
4722 }
4723 /* Direction out or both */
4724 if (!(ep_type & 1)) {
4725 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4726 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4727 if (!hsotg->eps_out[i])
4728 return -ENOMEM;
4729 }
4730 }
4731
4732 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4733 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4734
4735 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4736 hsotg->num_of_eps,
4737 hsotg->dedicated_fifos ? "dedicated" : "shared",
4738 hsotg->fifo_mem);
4739 return 0;
4740}
4741
4742/**
4743 * dwc2_hsotg_dump - dump state of the udc
4744 * @hsotg: Programming view of the DWC_otg controller
4745 *
4746 */
4747static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4748{
4749#ifdef DEBUG
4750 struct device *dev = hsotg->dev;
4751 u32 val;
4752 int idx;
4753
4754 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4755 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4756 dwc2_readl(hsotg, DIEPMSK));
4757
4758 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4759 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4760
4761 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4762 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4763
4764 /* show periodic fifo settings */
4765
4766 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4767 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4768 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4769 val >> FIFOSIZE_DEPTH_SHIFT,
4770 val & FIFOSIZE_STARTADDR_MASK);
4771 }
4772
4773 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4774 dev_info(dev,
4775 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4776 dwc2_readl(hsotg, DIEPCTL(idx)),
4777 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4778 dwc2_readl(hsotg, DIEPDMA(idx)));
4779
4780 val = dwc2_readl(hsotg, DOEPCTL(idx));
4781 dev_info(dev,
4782 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4783 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4784 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4785 dwc2_readl(hsotg, DOEPDMA(idx)));
4786 }
4787
4788 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4789 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4790#endif
4791}
4792
4793/**
4794 * dwc2_gadget_init - init function for gadget
4795 * @hsotg: Programming view of the DWC_otg controller
4796 *
4797 */
4798int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4799{
4800 struct device *dev = hsotg->dev;
4801 int epnum;
4802 int ret;
4803
4804 /* Dump fifo information */
4805 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4806 hsotg->params.g_np_tx_fifo_size);
4807 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4808
4809 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4810 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4811 hsotg->gadget.name = dev_name(dev);
4812 hsotg->remote_wakeup_allowed = 0;
4813
4814 if (hsotg->params.lpm)
4815 hsotg->gadget.lpm_capable = true;
4816
4817 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4818 hsotg->gadget.is_otg = 1;
4819 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4820 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4821
4822 ret = dwc2_hsotg_hw_cfg(hsotg);
4823 if (ret) {
4824 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4825 return ret;
4826 }
4827
4828 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4829 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4830 if (!hsotg->ctrl_buff)
4831 return -ENOMEM;
4832
4833 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4834 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4835 if (!hsotg->ep0_buff)
4836 return -ENOMEM;
4837
4838 if (using_desc_dma(hsotg)) {
4839 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4840 if (ret < 0)
4841 return ret;
4842 }
4843
4844 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4845 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4846 if (ret < 0) {
4847 dev_err(dev, "cannot claim IRQ for gadget\n");
4848 return ret;
4849 }
4850
4851 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4852
4853 if (hsotg->num_of_eps == 0) {
4854 dev_err(dev, "wrong number of EPs (zero)\n");
4855 return -EINVAL;
4856 }
4857
4858 /* setup endpoint information */
4859
4860 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4861 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4862
4863 /* allocate EP0 request */
4864
4865 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4866 GFP_KERNEL);
4867 if (!hsotg->ctrl_req) {
4868 dev_err(dev, "failed to allocate ctrl req\n");
4869 return -ENOMEM;
4870 }
4871
4872 /* initialise the endpoints now the core has been initialised */
4873 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4874 if (hsotg->eps_in[epnum])
4875 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4876 epnum, 1);
4877 if (hsotg->eps_out[epnum])
4878 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4879 epnum, 0);
4880 }
4881
4882 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4883 if (ret) {
4884 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep,
4885 hsotg->ctrl_req);
4886 return ret;
4887 }
4888 dwc2_hsotg_dump(hsotg);
4889
4890 return 0;
4891}
4892
4893/**
4894 * dwc2_hsotg_remove - remove function for hsotg driver
4895 * @hsotg: Programming view of the DWC_otg controller
4896 *
4897 */
4898int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4899{
4900 usb_del_gadget_udc(&hsotg->gadget);
4901 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4902
4903 return 0;
4904}
4905
4906int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4907{
4908 unsigned long flags;
4909
4910 if (hsotg->lx_state != DWC2_L0)
4911 return 0;
4912
4913 if (hsotg->driver) {
4914 int ep;
4915
4916 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4917 hsotg->driver->driver.name);
4918
4919 spin_lock_irqsave(&hsotg->lock, flags);
4920 if (hsotg->enabled)
4921 dwc2_hsotg_core_disconnect(hsotg);
4922 dwc2_hsotg_disconnect(hsotg);
4923 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4924 spin_unlock_irqrestore(&hsotg->lock, flags);
4925
4926 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4927 if (hsotg->eps_in[ep])
4928 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4929 if (hsotg->eps_out[ep])
4930 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4931 }
4932 }
4933
4934 return 0;
4935}
4936
4937int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4938{
4939 unsigned long flags;
4940
4941 if (hsotg->lx_state == DWC2_L2)
4942 return 0;
4943
4944 if (hsotg->driver) {
4945 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4946 hsotg->driver->driver.name);
4947
4948 spin_lock_irqsave(&hsotg->lock, flags);
4949 dwc2_hsotg_core_init_disconnected(hsotg, false);
4950 if (hsotg->enabled) {
4951 /* Enable ACG feature in device mode,if supported */
4952 dwc2_enable_acg(hsotg);
4953 dwc2_hsotg_core_connect(hsotg);
4954 }
4955 spin_unlock_irqrestore(&hsotg->lock, flags);
4956 }
4957
4958 return 0;
4959}
4960
4961/**
4962 * dwc2_backup_device_registers() - Backup controller device registers.
4963 * When suspending usb bus, registers needs to be backuped
4964 * if controller power is disabled once suspended.
4965 *
4966 * @hsotg: Programming view of the DWC_otg controller
4967 */
4968int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4969{
4970 struct dwc2_dregs_backup *dr;
4971 int i;
4972
4973 dev_dbg(hsotg->dev, "%s\n", __func__);
4974
4975 /* Backup dev regs */
4976 dr = &hsotg->dr_backup;
4977
4978 dr->dcfg = dwc2_readl(hsotg, DCFG);
4979 dr->dctl = dwc2_readl(hsotg, DCTL);
4980 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
4981 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
4982 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
4983
4984 for (i = 0; i < hsotg->num_of_eps; i++) {
4985 /* Backup IN EPs */
4986 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
4987
4988 /* Ensure DATA PID is correctly configured */
4989 if (dr->diepctl[i] & DXEPCTL_DPID)
4990 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4991 else
4992 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4993
4994 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
4995 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
4996
4997 /* Backup OUT EPs */
4998 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
4999
5000 /* Ensure DATA PID is correctly configured */
5001 if (dr->doepctl[i] & DXEPCTL_DPID)
5002 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5003 else
5004 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5005
5006 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5007 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5008 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5009 }
5010 dr->valid = true;
5011 return 0;
5012}
5013
5014/**
5015 * dwc2_restore_device_registers() - Restore controller device registers.
5016 * When resuming usb bus, device registers needs to be restored
5017 * if controller power were disabled.
5018 *
5019 * @hsotg: Programming view of the DWC_otg controller
5020 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5021 *
5022 * Return: 0 if successful, negative error code otherwise
5023 */
5024int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5025{
5026 struct dwc2_dregs_backup *dr;
5027 int i;
5028
5029 dev_dbg(hsotg->dev, "%s\n", __func__);
5030
5031 /* Restore dev regs */
5032 dr = &hsotg->dr_backup;
5033 if (!dr->valid) {
5034 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5035 __func__);
5036 return -EINVAL;
5037 }
5038 dr->valid = false;
5039
5040 if (!remote_wakeup)
5041 dwc2_writel(hsotg, dr->dctl, DCTL);
5042
5043 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5044 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5045 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5046
5047 for (i = 0; i < hsotg->num_of_eps; i++) {
5048 /* Restore IN EPs */
5049 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5050 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5051 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5052 /** WA for enabled EPx's IN in DDMA mode. On entering to
5053 * hibernation wrong value read and saved from DIEPDMAx,
5054 * as result BNA interrupt asserted on hibernation exit
5055 * by restoring from saved area.
5056 */
5057 if (hsotg->params.g_dma_desc &&
5058 (dr->diepctl[i] & DXEPCTL_EPENA))
5059 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5060 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5061 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5062 /* Restore OUT EPs */
5063 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5064 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5065 * hibernation wrong value read and saved from DOEPDMAx,
5066 * as result BNA interrupt asserted on hibernation exit
5067 * by restoring from saved area.
5068 */
5069 if (hsotg->params.g_dma_desc &&
5070 (dr->doepctl[i] & DXEPCTL_EPENA))
5071 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5072 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5073 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5074 }
5075
5076 return 0;
5077}
5078
5079/**
5080 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5081 *
5082 * @hsotg: Programming view of DWC_otg controller
5083 *
5084 */
5085void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5086{
5087 u32 val;
5088
5089 if (!hsotg->params.lpm)
5090 return;
5091
5092 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5093 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5094 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5095 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5096 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5097 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5098 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5099 dwc2_writel(hsotg, val, GLPMCFG);
5100 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5101
5102 /* Unmask WKUP_ALERT Interrupt */
5103 if (hsotg->params.service_interval)
5104 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5105}
5106
5107/**
5108 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5109 *
5110 * @hsotg: Programming view of DWC_otg controller
5111 *
5112 */
5113void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5114{
5115 u32 val = 0;
5116
5117 val |= GREFCLK_REF_CLK_MODE;
5118 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5119 val |= hsotg->params.sof_cnt_wkup_alert <<
5120 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5121
5122 dwc2_writel(hsotg, val, GREFCLK);
5123 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5124}
5125
5126/**
5127 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5128 *
5129 * @hsotg: Programming view of the DWC_otg controller
5130 *
5131 * Return non-zero if failed to enter to hibernation.
5132 */
5133int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5134{
5135 u32 gpwrdn;
5136 int ret = 0;
5137
5138 /* Change to L2(suspend) state */
5139 hsotg->lx_state = DWC2_L2;
5140 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5141 ret = dwc2_backup_global_registers(hsotg);
5142 if (ret) {
5143 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5144 __func__);
5145 return ret;
5146 }
5147 ret = dwc2_backup_device_registers(hsotg);
5148 if (ret) {
5149 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5150 __func__);
5151 return ret;
5152 }
5153
5154 gpwrdn = GPWRDN_PWRDNRSTN;
5155 gpwrdn |= GPWRDN_PMUACTV;
5156 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5157 udelay(10);
5158
5159 /* Set flag to indicate that we are in hibernation */
5160 hsotg->hibernated = 1;
5161
5162 /* Enable interrupts from wake up logic */
5163 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5164 gpwrdn |= GPWRDN_PMUINTSEL;
5165 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5166 udelay(10);
5167
5168 /* Unmask device mode interrupts in GPWRDN */
5169 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5170 gpwrdn |= GPWRDN_RST_DET_MSK;
5171 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5172 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5173 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5174 udelay(10);
5175
5176 /* Enable Power Down Clamp */
5177 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5178 gpwrdn |= GPWRDN_PWRDNCLMP;
5179 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5180 udelay(10);
5181
5182 /* Switch off VDD */
5183 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5184 gpwrdn |= GPWRDN_PWRDNSWTCH;
5185 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5186 udelay(10);
5187
5188 /* Save gpwrdn register for further usage if stschng interrupt */
5189 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5190 dev_dbg(hsotg->dev, "Hibernation completed\n");
5191
5192 return ret;
5193}
5194
5195/**
5196 * dwc2_gadget_exit_hibernation()
5197 * This function is for exiting from Device mode hibernation by host initiated
5198 * resume/reset and device initiated remote-wakeup.
5199 *
5200 * @hsotg: Programming view of the DWC_otg controller
5201 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5202 * @reset: indicates whether resume is initiated by Reset.
5203 *
5204 * Return non-zero if failed to exit from hibernation.
5205 */
5206int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5207 int rem_wakeup, int reset)
5208{
5209 u32 pcgcctl;
5210 u32 gpwrdn;
5211 u32 dctl;
5212 int ret = 0;
5213 struct dwc2_gregs_backup *gr;
5214 struct dwc2_dregs_backup *dr;
5215
5216 gr = &hsotg->gr_backup;
5217 dr = &hsotg->dr_backup;
5218
5219 if (!hsotg->hibernated) {
5220 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5221 return 1;
5222 }
5223 dev_dbg(hsotg->dev,
5224 "%s: called with rem_wakeup = %d reset = %d\n",
5225 __func__, rem_wakeup, reset);
5226
5227 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5228
5229 if (!reset) {
5230 /* Clear all pending interupts */
5231 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5232 }
5233
5234 /* De-assert Restore */
5235 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5236 gpwrdn &= ~GPWRDN_RESTORE;
5237 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5238 udelay(10);
5239
5240 if (!rem_wakeup) {
5241 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5242 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5243 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5244 }
5245
5246 /* Restore GUSBCFG, DCFG and DCTL */
5247 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5248 dwc2_writel(hsotg, dr->dcfg, DCFG);
5249 dwc2_writel(hsotg, dr->dctl, DCTL);
5250
5251 /* De-assert Wakeup Logic */
5252 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5253 gpwrdn &= ~GPWRDN_PMUACTV;
5254 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5255
5256 if (rem_wakeup) {
5257 udelay(10);
5258 /* Start Remote Wakeup Signaling */
5259 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5260 } else {
5261 udelay(50);
5262 /* Set Device programming done bit */
5263 dctl = dwc2_readl(hsotg, DCTL);
5264 dctl |= DCTL_PWRONPRGDONE;
5265 dwc2_writel(hsotg, dctl, DCTL);
5266 }
5267 /* Wait for interrupts which must be cleared */
5268 mdelay(2);
5269 /* Clear all pending interupts */
5270 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5271
5272 /* Restore global registers */
5273 ret = dwc2_restore_global_registers(hsotg);
5274 if (ret) {
5275 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5276 __func__);
5277 return ret;
5278 }
5279
5280 /* Restore device registers */
5281 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5282 if (ret) {
5283 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5284 __func__);
5285 return ret;
5286 }
5287
5288 if (rem_wakeup) {
5289 mdelay(10);
5290 dctl = dwc2_readl(hsotg, DCTL);
5291 dctl &= ~DCTL_RMTWKUPSIG;
5292 dwc2_writel(hsotg, dctl, DCTL);
5293 }
5294
5295 hsotg->hibernated = 0;
5296 hsotg->lx_state = DWC2_L0;
5297 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5298
5299 return ret;
5300}