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1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/mutex.h>
24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/of_platform.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/phy.h>
33
34#include "core.h"
35#include "hw.h"
36
37/* conversion functions */
38static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39{
40 return container_of(req, struct dwc2_hsotg_req, req);
41}
42
43static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44{
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
46}
47
48static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49{
50 return container_of(gadget, struct dwc2_hsotg, gadget);
51}
52
53static inline void __orr32(void __iomem *ptr, u32 val)
54{
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
56}
57
58static inline void __bic32(void __iomem *ptr, u32 val)
59{
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
61}
62
63static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
65{
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70}
71
72/* forward declaration of functions */
73static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74
75/**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
92 * g_using_dma is set depending on dts flag.
93 */
94static inline bool using_dma(struct dwc2_hsotg *hsotg)
95{
96 return hsotg->g_using_dma;
97}
98
99/**
100 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
101 * @hsotg: The device state
102 * @ints: A bitmask of the interrupts to enable
103 */
104static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
105{
106 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
107 u32 new_gsintmsk;
108
109 new_gsintmsk = gsintmsk | ints;
110
111 if (new_gsintmsk != gsintmsk) {
112 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
113 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
114 }
115}
116
117/**
118 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
119 * @hsotg: The device state
120 * @ints: A bitmask of the interrupts to enable
121 */
122static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
123{
124 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
125 u32 new_gsintmsk;
126
127 new_gsintmsk = gsintmsk & ~ints;
128
129 if (new_gsintmsk != gsintmsk)
130 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
131}
132
133/**
134 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
135 * @hsotg: The device state
136 * @ep: The endpoint index
137 * @dir_in: True if direction is in.
138 * @en: The enable value, true to enable
139 *
140 * Set or clear the mask for an individual endpoint's interrupt
141 * request.
142 */
143static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
144 unsigned int ep, unsigned int dir_in,
145 unsigned int en)
146{
147 unsigned long flags;
148 u32 bit = 1 << ep;
149 u32 daint;
150
151 if (!dir_in)
152 bit <<= 16;
153
154 local_irq_save(flags);
155 daint = dwc2_readl(hsotg->regs + DAINTMSK);
156 if (en)
157 daint |= bit;
158 else
159 daint &= ~bit;
160 dwc2_writel(daint, hsotg->regs + DAINTMSK);
161 local_irq_restore(flags);
162}
163
164/**
165 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
166 * @hsotg: The device instance.
167 */
168static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
169{
170 unsigned int ep;
171 unsigned int addr;
172 int timeout;
173 u32 val;
174
175 /* Reset fifo map if not correctly cleared during previous session */
176 WARN_ON(hsotg->fifo_map);
177 hsotg->fifo_map = 0;
178
179 /* set RX/NPTX FIFO sizes */
180 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
181 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
182 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
183 hsotg->regs + GNPTXFSIZ);
184
185 /*
186 * arange all the rest of the TX FIFOs, as some versions of this
187 * block have overlapping default addresses. This also ensures
188 * that if the settings have been changed, then they are set to
189 * known values.
190 */
191
192 /* start at the end of the GNPTXFSIZ, rounded up */
193 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
194
195 /*
196 * Configure fifos sizes from provided configuration and assign
197 * them to endpoints dynamically according to maxpacket size value of
198 * given endpoint.
199 */
200 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
201 if (!hsotg->g_tx_fifo_sz[ep])
202 continue;
203 val = addr;
204 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
205 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
206 "insufficient fifo memory");
207 addr += hsotg->g_tx_fifo_sz[ep];
208
209 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
210 }
211
212 /*
213 * according to p428 of the design guide, we need to ensure that
214 * all fifos are flushed before continuing
215 */
216
217 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
218 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
219
220 /* wait until the fifos are both flushed */
221 timeout = 100;
222 while (1) {
223 val = dwc2_readl(hsotg->regs + GRSTCTL);
224
225 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
226 break;
227
228 if (--timeout == 0) {
229 dev_err(hsotg->dev,
230 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
231 __func__, val);
232 break;
233 }
234
235 udelay(1);
236 }
237
238 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
239}
240
241/**
242 * @ep: USB endpoint to allocate request for.
243 * @flags: Allocation flags
244 *
245 * Allocate a new USB request structure appropriate for the specified endpoint
246 */
247static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
248 gfp_t flags)
249{
250 struct dwc2_hsotg_req *req;
251
252 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
253 if (!req)
254 return NULL;
255
256 INIT_LIST_HEAD(&req->queue);
257
258 return &req->req;
259}
260
261/**
262 * is_ep_periodic - return true if the endpoint is in periodic mode.
263 * @hs_ep: The endpoint to query.
264 *
265 * Returns true if the endpoint is in periodic mode, meaning it is being
266 * used for an Interrupt or ISO transfer.
267 */
268static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
269{
270 return hs_ep->periodic;
271}
272
273/**
274 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
275 * @hsotg: The device state.
276 * @hs_ep: The endpoint for the request
277 * @hs_req: The request being processed.
278 *
279 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
280 * of a request to ensure the buffer is ready for access by the caller.
281 */
282static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
283 struct dwc2_hsotg_ep *hs_ep,
284 struct dwc2_hsotg_req *hs_req)
285{
286 struct usb_request *req = &hs_req->req;
287
288 /* ignore this if we're not moving any data */
289 if (hs_req->req.length == 0)
290 return;
291
292 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
293}
294
295/**
296 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
297 * @hsotg: The controller state.
298 * @hs_ep: The endpoint we're going to write for.
299 * @hs_req: The request to write data for.
300 *
301 * This is called when the TxFIFO has some space in it to hold a new
302 * transmission and we have something to give it. The actual setup of
303 * the data size is done elsewhere, so all we have to do is to actually
304 * write the data.
305 *
306 * The return value is zero if there is more space (or nothing was done)
307 * otherwise -ENOSPC is returned if the FIFO space was used up.
308 *
309 * This routine is only needed for PIO
310 */
311static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
312 struct dwc2_hsotg_ep *hs_ep,
313 struct dwc2_hsotg_req *hs_req)
314{
315 bool periodic = is_ep_periodic(hs_ep);
316 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
317 int buf_pos = hs_req->req.actual;
318 int to_write = hs_ep->size_loaded;
319 void *data;
320 int can_write;
321 int pkt_round;
322 int max_transfer;
323
324 to_write -= (buf_pos - hs_ep->last_load);
325
326 /* if there's nothing to write, get out early */
327 if (to_write == 0)
328 return 0;
329
330 if (periodic && !hsotg->dedicated_fifos) {
331 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
332 int size_left;
333 int size_done;
334
335 /*
336 * work out how much data was loaded so we can calculate
337 * how much data is left in the fifo.
338 */
339
340 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
341
342 /*
343 * if shared fifo, we cannot write anything until the
344 * previous data has been completely sent.
345 */
346 if (hs_ep->fifo_load != 0) {
347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
348 return -ENOSPC;
349 }
350
351 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
352 __func__, size_left,
353 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
354
355 /* how much of the data has moved */
356 size_done = hs_ep->size_loaded - size_left;
357
358 /* how much data is left in the fifo */
359 can_write = hs_ep->fifo_load - size_done;
360 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
361 __func__, can_write);
362
363 can_write = hs_ep->fifo_size - can_write;
364 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
365 __func__, can_write);
366
367 if (can_write <= 0) {
368 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
369 return -ENOSPC;
370 }
371 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
372 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
373
374 can_write &= 0xffff;
375 can_write *= 4;
376 } else {
377 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
378 dev_dbg(hsotg->dev,
379 "%s: no queue slots available (0x%08x)\n",
380 __func__, gnptxsts);
381
382 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
383 return -ENOSPC;
384 }
385
386 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
387 can_write *= 4; /* fifo size is in 32bit quantities. */
388 }
389
390 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
391
392 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
393 __func__, gnptxsts, can_write, to_write, max_transfer);
394
395 /*
396 * limit to 512 bytes of data, it seems at least on the non-periodic
397 * FIFO, requests of >512 cause the endpoint to get stuck with a
398 * fragment of the end of the transfer in it.
399 */
400 if (can_write > 512 && !periodic)
401 can_write = 512;
402
403 /*
404 * limit the write to one max-packet size worth of data, but allow
405 * the transfer to return that it did not run out of fifo space
406 * doing it.
407 */
408 if (to_write > max_transfer) {
409 to_write = max_transfer;
410
411 /* it's needed only when we do not use dedicated fifos */
412 if (!hsotg->dedicated_fifos)
413 dwc2_hsotg_en_gsint(hsotg,
414 periodic ? GINTSTS_PTXFEMP :
415 GINTSTS_NPTXFEMP);
416 }
417
418 /* see if we can write data */
419
420 if (to_write > can_write) {
421 to_write = can_write;
422 pkt_round = to_write % max_transfer;
423
424 /*
425 * Round the write down to an
426 * exact number of packets.
427 *
428 * Note, we do not currently check to see if we can ever
429 * write a full packet or not to the FIFO.
430 */
431
432 if (pkt_round)
433 to_write -= pkt_round;
434
435 /*
436 * enable correct FIFO interrupt to alert us when there
437 * is more room left.
438 */
439
440 /* it's needed only when we do not use dedicated fifos */
441 if (!hsotg->dedicated_fifos)
442 dwc2_hsotg_en_gsint(hsotg,
443 periodic ? GINTSTS_PTXFEMP :
444 GINTSTS_NPTXFEMP);
445 }
446
447 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
448 to_write, hs_req->req.length, can_write, buf_pos);
449
450 if (to_write <= 0)
451 return -ENOSPC;
452
453 hs_req->req.actual = buf_pos + to_write;
454 hs_ep->total_data += to_write;
455
456 if (periodic)
457 hs_ep->fifo_load += to_write;
458
459 to_write = DIV_ROUND_UP(to_write, 4);
460 data = hs_req->req.buf + buf_pos;
461
462 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
463
464 return (to_write >= can_write) ? -ENOSPC : 0;
465}
466
467/**
468 * get_ep_limit - get the maximum data legnth for this endpoint
469 * @hs_ep: The endpoint
470 *
471 * Return the maximum data that can be queued in one go on a given endpoint
472 * so that transfers that are too long can be split.
473 */
474static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
475{
476 int index = hs_ep->index;
477 unsigned maxsize;
478 unsigned maxpkt;
479
480 if (index != 0) {
481 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
482 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
483 } else {
484 maxsize = 64+64;
485 if (hs_ep->dir_in)
486 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
487 else
488 maxpkt = 2;
489 }
490
491 /* we made the constant loading easier above by using +1 */
492 maxpkt--;
493 maxsize--;
494
495 /*
496 * constrain by packet count if maxpkts*pktsize is greater
497 * than the length register size.
498 */
499
500 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
501 maxsize = maxpkt * hs_ep->ep.maxpacket;
502
503 return maxsize;
504}
505
506/**
507 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
508 * @hsotg: The controller state.
509 * @hs_ep: The endpoint to process a request for
510 * @hs_req: The request to start.
511 * @continuing: True if we are doing more for the current request.
512 *
513 * Start the given request running by setting the endpoint registers
514 * appropriately, and writing any data to the FIFOs.
515 */
516static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
517 struct dwc2_hsotg_ep *hs_ep,
518 struct dwc2_hsotg_req *hs_req,
519 bool continuing)
520{
521 struct usb_request *ureq = &hs_req->req;
522 int index = hs_ep->index;
523 int dir_in = hs_ep->dir_in;
524 u32 epctrl_reg;
525 u32 epsize_reg;
526 u32 epsize;
527 u32 ctrl;
528 unsigned length;
529 unsigned packets;
530 unsigned maxreq;
531
532 if (index != 0) {
533 if (hs_ep->req && !continuing) {
534 dev_err(hsotg->dev, "%s: active request\n", __func__);
535 WARN_ON(1);
536 return;
537 } else if (hs_ep->req != hs_req && continuing) {
538 dev_err(hsotg->dev,
539 "%s: continue different req\n", __func__);
540 WARN_ON(1);
541 return;
542 }
543 }
544
545 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
546 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
547
548 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
549 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
550 hs_ep->dir_in ? "in" : "out");
551
552 /* If endpoint is stalled, we will restart request later */
553 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
554
555 if (index && ctrl & DXEPCTL_STALL) {
556 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
557 return;
558 }
559
560 length = ureq->length - ureq->actual;
561 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
562 ureq->length, ureq->actual);
563
564 maxreq = get_ep_limit(hs_ep);
565 if (length > maxreq) {
566 int round = maxreq % hs_ep->ep.maxpacket;
567
568 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
569 __func__, length, maxreq, round);
570
571 /* round down to multiple of packets */
572 if (round)
573 maxreq -= round;
574
575 length = maxreq;
576 }
577
578 if (length)
579 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
580 else
581 packets = 1; /* send one packet if length is zero. */
582
583 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
584 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
585 return;
586 }
587
588 if (dir_in && index != 0)
589 if (hs_ep->isochronous)
590 epsize = DXEPTSIZ_MC(packets);
591 else
592 epsize = DXEPTSIZ_MC(1);
593 else
594 epsize = 0;
595
596 /*
597 * zero length packet should be programmed on its own and should not
598 * be counted in DIEPTSIZ.PktCnt with other packets.
599 */
600 if (dir_in && ureq->zero && !continuing) {
601 /* Test if zlp is actually required. */
602 if ((ureq->length >= hs_ep->ep.maxpacket) &&
603 !(ureq->length % hs_ep->ep.maxpacket))
604 hs_ep->send_zlp = 1;
605 }
606
607 epsize |= DXEPTSIZ_PKTCNT(packets);
608 epsize |= DXEPTSIZ_XFERSIZE(length);
609
610 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
611 __func__, packets, length, ureq->length, epsize, epsize_reg);
612
613 /* store the request as the current one we're doing */
614 hs_ep->req = hs_req;
615
616 /* write size / packets */
617 dwc2_writel(epsize, hsotg->regs + epsize_reg);
618
619 if (using_dma(hsotg) && !continuing) {
620 unsigned int dma_reg;
621
622 /*
623 * write DMA address to control register, buffer already
624 * synced by dwc2_hsotg_ep_queue().
625 */
626
627 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
628 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
629
630 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
631 __func__, &ureq->dma, dma_reg);
632 }
633
634 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
635 ctrl |= DXEPCTL_USBACTEP;
636
637 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
638
639 /* For Setup request do not clear NAK */
640 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
641 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
642
643 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
644 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
645
646 /*
647 * set these, it seems that DMA support increments past the end
648 * of the packet buffer so we need to calculate the length from
649 * this information.
650 */
651 hs_ep->size_loaded = length;
652 hs_ep->last_load = ureq->actual;
653
654 if (dir_in && !using_dma(hsotg)) {
655 /* set these anyway, we may need them for non-periodic in */
656 hs_ep->fifo_load = 0;
657
658 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
659 }
660
661 /*
662 * clear the INTknTXFEmpMsk when we start request, more as a aide
663 * to debugging to see what is going on.
664 */
665 if (dir_in)
666 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
667 hsotg->regs + DIEPINT(index));
668
669 /*
670 * Note, trying to clear the NAK here causes problems with transmit
671 * on the S3C6400 ending up with the TXFIFO becoming full.
672 */
673
674 /* check ep is enabled */
675 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
676 dev_dbg(hsotg->dev,
677 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
678 index, dwc2_readl(hsotg->regs + epctrl_reg));
679
680 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
681 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
682
683 /* enable ep interrupts */
684 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
685}
686
687/**
688 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
689 * @hsotg: The device state.
690 * @hs_ep: The endpoint the request is on.
691 * @req: The request being processed.
692 *
693 * We've been asked to queue a request, so ensure that the memory buffer
694 * is correctly setup for DMA. If we've been passed an extant DMA address
695 * then ensure the buffer has been synced to memory. If our buffer has no
696 * DMA memory, then we map the memory and mark our request to allow us to
697 * cleanup on completion.
698 */
699static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
700 struct dwc2_hsotg_ep *hs_ep,
701 struct usb_request *req)
702{
703 struct dwc2_hsotg_req *hs_req = our_req(req);
704 int ret;
705
706 /* if the length is zero, ignore the DMA data */
707 if (hs_req->req.length == 0)
708 return 0;
709
710 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
711 if (ret)
712 goto dma_error;
713
714 return 0;
715
716dma_error:
717 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
718 __func__, req->buf, req->length);
719
720 return -EIO;
721}
722
723static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
724 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
725{
726 void *req_buf = hs_req->req.buf;
727
728 /* If dma is not being used or buffer is aligned */
729 if (!using_dma(hsotg) || !((long)req_buf & 3))
730 return 0;
731
732 WARN_ON(hs_req->saved_req_buf);
733
734 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
735 hs_ep->ep.name, req_buf, hs_req->req.length);
736
737 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
738 if (!hs_req->req.buf) {
739 hs_req->req.buf = req_buf;
740 dev_err(hsotg->dev,
741 "%s: unable to allocate memory for bounce buffer\n",
742 __func__);
743 return -ENOMEM;
744 }
745
746 /* Save actual buffer */
747 hs_req->saved_req_buf = req_buf;
748
749 if (hs_ep->dir_in)
750 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
751 return 0;
752}
753
754static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
755 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
756{
757 /* If dma is not being used or buffer was aligned */
758 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
759 return;
760
761 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
762 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
763
764 /* Copy data from bounce buffer on successful out transfer */
765 if (!hs_ep->dir_in && !hs_req->req.status)
766 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
767 hs_req->req.actual);
768
769 /* Free bounce buffer */
770 kfree(hs_req->req.buf);
771
772 hs_req->req.buf = hs_req->saved_req_buf;
773 hs_req->saved_req_buf = NULL;
774}
775
776static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
777 gfp_t gfp_flags)
778{
779 struct dwc2_hsotg_req *hs_req = our_req(req);
780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
781 struct dwc2_hsotg *hs = hs_ep->parent;
782 bool first;
783 int ret;
784
785 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
786 ep->name, req, req->length, req->buf, req->no_interrupt,
787 req->zero, req->short_not_ok);
788
789 /* Prevent new request submission when controller is suspended */
790 if (hs->lx_state == DWC2_L2) {
791 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
792 __func__);
793 return -EAGAIN;
794 }
795
796 /* initialise status of the request */
797 INIT_LIST_HEAD(&hs_req->queue);
798 req->actual = 0;
799 req->status = -EINPROGRESS;
800
801 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
802 if (ret)
803 return ret;
804
805 /* if we're using DMA, sync the buffers as necessary */
806 if (using_dma(hs)) {
807 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
808 if (ret)
809 return ret;
810 }
811
812 first = list_empty(&hs_ep->queue);
813 list_add_tail(&hs_req->queue, &hs_ep->queue);
814
815 if (first)
816 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
817
818 return 0;
819}
820
821static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
822 gfp_t gfp_flags)
823{
824 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
825 struct dwc2_hsotg *hs = hs_ep->parent;
826 unsigned long flags = 0;
827 int ret = 0;
828
829 spin_lock_irqsave(&hs->lock, flags);
830 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
831 spin_unlock_irqrestore(&hs->lock, flags);
832
833 return ret;
834}
835
836static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
838{
839 struct dwc2_hsotg_req *hs_req = our_req(req);
840
841 kfree(hs_req);
842}
843
844/**
845 * dwc2_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
848 *
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
851 */
852static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
854{
855 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
856 struct dwc2_hsotg *hsotg = hs_ep->parent;
857
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
859
860 dwc2_hsotg_ep_free_request(ep, req);
861}
862
863/**
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
867 *
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
870 */
871static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
872 u32 windex)
873{
874 struct dwc2_hsotg_ep *ep;
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
877
878 if (windex >= 0x100)
879 return NULL;
880
881 if (idx > hsotg->num_of_eps)
882 return NULL;
883
884 ep = index_to_ep(hsotg, idx, dir);
885
886 if (idx && ep->dir_in != dir)
887 return NULL;
888
889 return ep;
890}
891
892/**
893 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
894 * @hsotg: The driver state.
895 * @testmode: requested usb test mode
896 * Enable usb Test Mode requested by the Host.
897 */
898int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
899{
900 int dctl = dwc2_readl(hsotg->regs + DCTL);
901
902 dctl &= ~DCTL_TSTCTL_MASK;
903 switch (testmode) {
904 case TEST_J:
905 case TEST_K:
906 case TEST_SE0_NAK:
907 case TEST_PACKET:
908 case TEST_FORCE_EN:
909 dctl |= testmode << DCTL_TSTCTL_SHIFT;
910 break;
911 default:
912 return -EINVAL;
913 }
914 dwc2_writel(dctl, hsotg->regs + DCTL);
915 return 0;
916}
917
918/**
919 * dwc2_hsotg_send_reply - send reply to control request
920 * @hsotg: The device state
921 * @ep: Endpoint 0
922 * @buff: Buffer for request
923 * @length: Length of reply.
924 *
925 * Create a request and queue it on the given endpoint. This is useful as
926 * an internal method of sending replies to certain control requests, etc.
927 */
928static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
929 struct dwc2_hsotg_ep *ep,
930 void *buff,
931 int length)
932{
933 struct usb_request *req;
934 int ret;
935
936 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
937
938 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
939 hsotg->ep0_reply = req;
940 if (!req) {
941 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
942 return -ENOMEM;
943 }
944
945 req->buf = hsotg->ep0_buff;
946 req->length = length;
947 /*
948 * zero flag is for sending zlp in DATA IN stage. It has no impact on
949 * STATUS stage.
950 */
951 req->zero = 0;
952 req->complete = dwc2_hsotg_complete_oursetup;
953
954 if (length)
955 memcpy(req->buf, buff, length);
956
957 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
958 if (ret) {
959 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
960 return ret;
961 }
962
963 return 0;
964}
965
966/**
967 * dwc2_hsotg_process_req_status - process request GET_STATUS
968 * @hsotg: The device state
969 * @ctrl: USB control request
970 */
971static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
973{
974 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
975 struct dwc2_hsotg_ep *ep;
976 __le16 reply;
977 int ret;
978
979 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
980
981 if (!ep0->dir_in) {
982 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
983 return -EINVAL;
984 }
985
986 switch (ctrl->bRequestType & USB_RECIP_MASK) {
987 case USB_RECIP_DEVICE:
988 reply = cpu_to_le16(0); /* bit 0 => self powered,
989 * bit 1 => remote wakeup */
990 break;
991
992 case USB_RECIP_INTERFACE:
993 /* currently, the data result should be zero */
994 reply = cpu_to_le16(0);
995 break;
996
997 case USB_RECIP_ENDPOINT:
998 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
999 if (!ep)
1000 return -ENOENT;
1001
1002 reply = cpu_to_le16(ep->halted ? 1 : 0);
1003 break;
1004
1005 default:
1006 return 0;
1007 }
1008
1009 if (le16_to_cpu(ctrl->wLength) != 2)
1010 return -EINVAL;
1011
1012 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1013 if (ret) {
1014 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1015 return ret;
1016 }
1017
1018 return 1;
1019}
1020
1021static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1022
1023/**
1024 * get_ep_head - return the first request on the endpoint
1025 * @hs_ep: The controller endpoint to get
1026 *
1027 * Get the first request on the endpoint.
1028 */
1029static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1030{
1031 if (list_empty(&hs_ep->queue))
1032 return NULL;
1033
1034 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1035}
1036
1037/**
1038 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1041 */
1042static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1043 struct usb_ctrlrequest *ctrl)
1044{
1045 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1046 struct dwc2_hsotg_req *hs_req;
1047 bool restart;
1048 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1049 struct dwc2_hsotg_ep *ep;
1050 int ret;
1051 bool halted;
1052 u32 recip;
1053 u32 wValue;
1054 u32 wIndex;
1055
1056 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1057 __func__, set ? "SET" : "CLEAR");
1058
1059 wValue = le16_to_cpu(ctrl->wValue);
1060 wIndex = le16_to_cpu(ctrl->wIndex);
1061 recip = ctrl->bRequestType & USB_RECIP_MASK;
1062
1063 switch (recip) {
1064 case USB_RECIP_DEVICE:
1065 switch (wValue) {
1066 case USB_DEVICE_TEST_MODE:
1067 if ((wIndex & 0xff) != 0)
1068 return -EINVAL;
1069 if (!set)
1070 return -EINVAL;
1071
1072 hsotg->test_mode = wIndex >> 8;
1073 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1074 if (ret) {
1075 dev_err(hsotg->dev,
1076 "%s: failed to send reply\n", __func__);
1077 return ret;
1078 }
1079 break;
1080 default:
1081 return -ENOENT;
1082 }
1083 break;
1084
1085 case USB_RECIP_ENDPOINT:
1086 ep = ep_from_windex(hsotg, wIndex);
1087 if (!ep) {
1088 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1089 __func__, wIndex);
1090 return -ENOENT;
1091 }
1092
1093 switch (wValue) {
1094 case USB_ENDPOINT_HALT:
1095 halted = ep->halted;
1096
1097 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1098
1099 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1100 if (ret) {
1101 dev_err(hsotg->dev,
1102 "%s: failed to send reply\n", __func__);
1103 return ret;
1104 }
1105
1106 /*
1107 * we have to complete all requests for ep if it was
1108 * halted, and the halt was cleared by CLEAR_FEATURE
1109 */
1110
1111 if (!set && halted) {
1112 /*
1113 * If we have request in progress,
1114 * then complete it
1115 */
1116 if (ep->req) {
1117 hs_req = ep->req;
1118 ep->req = NULL;
1119 list_del_init(&hs_req->queue);
1120 if (hs_req->req.complete) {
1121 spin_unlock(&hsotg->lock);
1122 usb_gadget_giveback_request(
1123 &ep->ep, &hs_req->req);
1124 spin_lock(&hsotg->lock);
1125 }
1126 }
1127
1128 /* If we have pending request, then start it */
1129 if (!ep->req) {
1130 restart = !list_empty(&ep->queue);
1131 if (restart) {
1132 hs_req = get_ep_head(ep);
1133 dwc2_hsotg_start_req(hsotg, ep,
1134 hs_req, false);
1135 }
1136 }
1137 }
1138
1139 break;
1140
1141 default:
1142 return -ENOENT;
1143 }
1144 break;
1145 default:
1146 return -ENOENT;
1147 }
1148 return 1;
1149}
1150
1151static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1152
1153/**
1154 * dwc2_hsotg_stall_ep0 - stall ep0
1155 * @hsotg: The device state
1156 *
1157 * Set stall for ep0 as response for setup request.
1158 */
1159static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1160{
1161 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1162 u32 reg;
1163 u32 ctrl;
1164
1165 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1166 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1167
1168 /*
1169 * DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later.
1171 */
1172
1173 ctrl = dwc2_readl(hsotg->regs + reg);
1174 ctrl |= DXEPCTL_STALL;
1175 ctrl |= DXEPCTL_CNAK;
1176 dwc2_writel(ctrl, hsotg->regs + reg);
1177
1178 dev_dbg(hsotg->dev,
1179 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1180 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1181
1182 /*
1183 * complete won't be called, so we enqueue
1184 * setup request here
1185 */
1186 dwc2_hsotg_enqueue_setup(hsotg);
1187}
1188
1189/**
1190 * dwc2_hsotg_process_control - process a control request
1191 * @hsotg: The device state
1192 * @ctrl: The control request received
1193 *
1194 * The controller has received the SETUP phase of a control request, and
1195 * needs to work out what to do next (and whether to pass it on to the
1196 * gadget driver).
1197 */
1198static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1199 struct usb_ctrlrequest *ctrl)
1200{
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1202 int ret = 0;
1203 u32 dcfg;
1204
1205 dev_dbg(hsotg->dev,
1206 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1207 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1208 ctrl->wIndex, ctrl->wLength);
1209
1210 if (ctrl->wLength == 0) {
1211 ep0->dir_in = 1;
1212 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1213 } else if (ctrl->bRequestType & USB_DIR_IN) {
1214 ep0->dir_in = 1;
1215 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1216 } else {
1217 ep0->dir_in = 0;
1218 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1219 }
1220
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 hsotg->connected = 1;
1225 dcfg = dwc2_readl(hsotg->regs + DCFG);
1226 dcfg &= ~DCFG_DEVADDR_MASK;
1227 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1228 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1229 dwc2_writel(dcfg, hsotg->regs + DCFG);
1230
1231 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1232
1233 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 return;
1235
1236 case USB_REQ_GET_STATUS:
1237 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1238 break;
1239
1240 case USB_REQ_CLEAR_FEATURE:
1241 case USB_REQ_SET_FEATURE:
1242 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1243 break;
1244 }
1245 }
1246
1247 /* as a fallback, try delivering it to the driver to deal with */
1248
1249 if (ret == 0 && hsotg->driver) {
1250 spin_unlock(&hsotg->lock);
1251 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1252 spin_lock(&hsotg->lock);
1253 if (ret < 0)
1254 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1255 }
1256
1257 /*
1258 * the request is either unhandlable, or is not formatted correctly
1259 * so respond with a STALL for the status stage to indicate failure.
1260 */
1261
1262 if (ret < 0)
1263 dwc2_hsotg_stall_ep0(hsotg);
1264}
1265
1266/**
1267 * dwc2_hsotg_complete_setup - completion of a setup transfer
1268 * @ep: The endpoint the request was on.
1269 * @req: The request completed.
1270 *
1271 * Called on completion of any requests the driver itself submitted for
1272 * EP0 setup packets
1273 */
1274static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1275 struct usb_request *req)
1276{
1277 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1278 struct dwc2_hsotg *hsotg = hs_ep->parent;
1279
1280 if (req->status < 0) {
1281 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1282 return;
1283 }
1284
1285 spin_lock(&hsotg->lock);
1286 if (req->actual == 0)
1287 dwc2_hsotg_enqueue_setup(hsotg);
1288 else
1289 dwc2_hsotg_process_control(hsotg, req->buf);
1290 spin_unlock(&hsotg->lock);
1291}
1292
1293/**
1294 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1295 * @hsotg: The device state.
1296 *
1297 * Enqueue a request on EP0 if necessary to received any SETUP packets
1298 * received from the host.
1299 */
1300static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1301{
1302 struct usb_request *req = hsotg->ctrl_req;
1303 struct dwc2_hsotg_req *hs_req = our_req(req);
1304 int ret;
1305
1306 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1307
1308 req->zero = 0;
1309 req->length = 8;
1310 req->buf = hsotg->ctrl_buff;
1311 req->complete = dwc2_hsotg_complete_setup;
1312
1313 if (!list_empty(&hs_req->queue)) {
1314 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1315 return;
1316 }
1317
1318 hsotg->eps_out[0]->dir_in = 0;
1319 hsotg->eps_out[0]->send_zlp = 0;
1320 hsotg->ep0_state = DWC2_EP0_SETUP;
1321
1322 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1323 if (ret < 0) {
1324 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1325 /*
1326 * Don't think there's much we can do other than watch the
1327 * driver fail.
1328 */
1329 }
1330}
1331
1332static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1333 struct dwc2_hsotg_ep *hs_ep)
1334{
1335 u32 ctrl;
1336 u8 index = hs_ep->index;
1337 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1338 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1339
1340 if (hs_ep->dir_in)
1341 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1342 index);
1343 else
1344 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1345 index);
1346
1347 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1348 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1349 epsiz_reg);
1350
1351 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1352 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1353 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1354 ctrl |= DXEPCTL_USBACTEP;
1355 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1356}
1357
1358/**
1359 * dwc2_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1364 *
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1367 * on the endpoint.
1368 *
1369 * Note, expects the ep to already be locked as appropriate.
1370 */
1371static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1372 struct dwc2_hsotg_ep *hs_ep,
1373 struct dwc2_hsotg_req *hs_req,
1374 int result)
1375{
1376 bool restart;
1377
1378 if (!hs_req) {
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1380 return;
1381 }
1382
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1385
1386 /*
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1389 */
1390
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1393
1394 if (using_dma(hsotg))
1395 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1396
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1398
1399 hs_ep->req = NULL;
1400 list_del_init(&hs_req->queue);
1401
1402 /*
1403 * call the complete request with the locks off, just in case the
1404 * request tries to queue more work for this endpoint.
1405 */
1406
1407 if (hs_req->req.complete) {
1408 spin_unlock(&hsotg->lock);
1409 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1410 spin_lock(&hsotg->lock);
1411 }
1412
1413 /*
1414 * Look to see if there is anything else to do. Note, the completion
1415 * of the previous request may have caused a new request to be started
1416 * so be careful when doing this.
1417 */
1418
1419 if (!hs_ep->req && result >= 0) {
1420 restart = !list_empty(&hs_ep->queue);
1421 if (restart) {
1422 hs_req = get_ep_head(hs_ep);
1423 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1424 }
1425 }
1426}
1427
1428/**
1429 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1430 * @hsotg: The device state.
1431 * @ep_idx: The endpoint index for the data
1432 * @size: The size of data in the fifo, in bytes
1433 *
1434 * The FIFO status shows there is data to read from the FIFO for a given
1435 * endpoint, so sort out whether we need to read the data into a request
1436 * that has been made for that endpoint.
1437 */
1438static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1439{
1440 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1441 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 int to_read;
1444 int max_req;
1445 int read_ptr;
1446
1447
1448 if (!hs_req) {
1449 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1450 int ptr;
1451
1452 dev_dbg(hsotg->dev,
1453 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1454 __func__, size, ep_idx, epctl);
1455
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr = 0; ptr < size; ptr += 4)
1458 (void)dwc2_readl(fifo);
1459
1460 return;
1461 }
1462
1463 to_read = size;
1464 read_ptr = hs_req->req.actual;
1465 max_req = hs_req->req.length - read_ptr;
1466
1467 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1468 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1469
1470 if (to_read > max_req) {
1471 /*
1472 * more data appeared than we where willing
1473 * to deal with in this request.
1474 */
1475
1476 /* currently we don't deal this */
1477 WARN_ON_ONCE(1);
1478 }
1479
1480 hs_ep->total_data += to_read;
1481 hs_req->req.actual += to_read;
1482 to_read = DIV_ROUND_UP(to_read, 4);
1483
1484 /*
1485 * note, we might over-write the buffer end by 3 bytes depending on
1486 * alignment of the data.
1487 */
1488 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1489}
1490
1491/**
1492 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1493 * @hsotg: The device instance
1494 * @dir_in: If IN zlp
1495 *
1496 * Generate a zero-length IN packet request for terminating a SETUP
1497 * transaction.
1498 *
1499 * Note, since we don't write any data to the TxFIFO, then it is
1500 * currently believed that we do not need to wait for any space in
1501 * the TxFIFO.
1502 */
1503static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1504{
1505 /* eps_out[0] is used in both directions */
1506 hsotg->eps_out[0]->dir_in = dir_in;
1507 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1508
1509 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1510}
1511
1512static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1513 u32 epctl_reg)
1514{
1515 u32 ctrl;
1516
1517 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1518 if (ctrl & DXEPCTL_EOFRNUM)
1519 ctrl |= DXEPCTL_SETEVENFR;
1520 else
1521 ctrl |= DXEPCTL_SETODDFR;
1522 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1523}
1524
1525/**
1526 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1527 * @hsotg: The device instance
1528 * @epnum: The endpoint received from
1529 *
1530 * The RXFIFO has delivered an OutDone event, which means that the data
1531 * transfer for an OUT endpoint has been completed, either by a short
1532 * packet or by the finish of a transfer.
1533 */
1534static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1535{
1536 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 struct usb_request *req = &hs_req->req;
1540 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1541 int result = 0;
1542
1543 if (!hs_req) {
1544 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1545 return;
1546 }
1547
1548 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1549 dev_dbg(hsotg->dev, "zlp packet received\n");
1550 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1551 dwc2_hsotg_enqueue_setup(hsotg);
1552 return;
1553 }
1554
1555 if (using_dma(hsotg)) {
1556 unsigned size_done;
1557
1558 /*
1559 * Calculate the size of the transfer by checking how much
1560 * is left in the endpoint size register and then working it
1561 * out from the amount we loaded for the transfer.
1562 *
1563 * We need to do this as DMA pointers are always 32bit aligned
1564 * so may overshoot/undershoot the transfer.
1565 */
1566
1567 size_done = hs_ep->size_loaded - size_left;
1568 size_done += hs_ep->last_load;
1569
1570 req->actual = size_done;
1571 }
1572
1573 /* if there is more request to do, schedule new transfer */
1574 if (req->actual < req->length && size_left == 0) {
1575 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1576 return;
1577 }
1578
1579 if (req->actual < req->length && req->short_not_ok) {
1580 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1581 __func__, req->actual, req->length);
1582
1583 /*
1584 * todo - what should we return here? there's no one else
1585 * even bothering to check the status.
1586 */
1587 }
1588
1589 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1590 /* Move to STATUS IN */
1591 dwc2_hsotg_ep0_zlp(hsotg, true);
1592 return;
1593 }
1594
1595 /*
1596 * Slave mode OUT transfers do not go through XferComplete so
1597 * adjust the ISOC parity here.
1598 */
1599 if (!using_dma(hsotg)) {
1600 hs_ep->has_correct_parity = 1;
1601 if (hs_ep->isochronous && hs_ep->interval == 1)
1602 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1603 }
1604
1605 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1606}
1607
1608/**
1609 * dwc2_hsotg_read_frameno - read current frame number
1610 * @hsotg: The device instance
1611 *
1612 * Return the current frame number
1613 */
1614static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1615{
1616 u32 dsts;
1617
1618 dsts = dwc2_readl(hsotg->regs + DSTS);
1619 dsts &= DSTS_SOFFN_MASK;
1620 dsts >>= DSTS_SOFFN_SHIFT;
1621
1622 return dsts;
1623}
1624
1625/**
1626 * dwc2_hsotg_handle_rx - RX FIFO has data
1627 * @hsotg: The device instance
1628 *
1629 * The IRQ handler has detected that the RX FIFO has some data in it
1630 * that requires processing, so find out what is in there and do the
1631 * appropriate read.
1632 *
1633 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1634 * chunks, so if you have x packets received on an endpoint you'll get x
1635 * FIFO events delivered, each with a packet's worth of data in it.
1636 *
1637 * When using DMA, we should not be processing events from the RXFIFO
1638 * as the actual data should be sent to the memory directly and we turn
1639 * on the completion interrupts to get notifications of transfer completion.
1640 */
1641static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1642{
1643 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1644 u32 epnum, status, size;
1645
1646 WARN_ON(using_dma(hsotg));
1647
1648 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1649 status = grxstsr & GRXSTS_PKTSTS_MASK;
1650
1651 size = grxstsr & GRXSTS_BYTECNT_MASK;
1652 size >>= GRXSTS_BYTECNT_SHIFT;
1653
1654 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1655 __func__, grxstsr, size, epnum);
1656
1657 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1658 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1659 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1660 break;
1661
1662 case GRXSTS_PKTSTS_OUTDONE:
1663 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1664 dwc2_hsotg_read_frameno(hsotg));
1665
1666 if (!using_dma(hsotg))
1667 dwc2_hsotg_handle_outdone(hsotg, epnum);
1668 break;
1669
1670 case GRXSTS_PKTSTS_SETUPDONE:
1671 dev_dbg(hsotg->dev,
1672 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1673 dwc2_hsotg_read_frameno(hsotg),
1674 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1675 /*
1676 * Call dwc2_hsotg_handle_outdone here if it was not called from
1677 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1678 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1679 */
1680 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1681 dwc2_hsotg_handle_outdone(hsotg, epnum);
1682 break;
1683
1684 case GRXSTS_PKTSTS_OUTRX:
1685 dwc2_hsotg_rx_data(hsotg, epnum, size);
1686 break;
1687
1688 case GRXSTS_PKTSTS_SETUPRX:
1689 dev_dbg(hsotg->dev,
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 dwc2_hsotg_read_frameno(hsotg),
1692 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1693
1694 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1695
1696 dwc2_hsotg_rx_data(hsotg, epnum, size);
1697 break;
1698
1699 default:
1700 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1701 __func__, grxstsr);
1702
1703 dwc2_hsotg_dump(hsotg);
1704 break;
1705 }
1706}
1707
1708/**
1709 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1710 * @mps: The maximum packet size in bytes.
1711 */
1712static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1713{
1714 switch (mps) {
1715 case 64:
1716 return D0EPCTL_MPS_64;
1717 case 32:
1718 return D0EPCTL_MPS_32;
1719 case 16:
1720 return D0EPCTL_MPS_16;
1721 case 8:
1722 return D0EPCTL_MPS_8;
1723 }
1724
1725 /* bad max packet size, warn and return invalid result */
1726 WARN_ON(1);
1727 return (u32)-1;
1728}
1729
1730/**
1731 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1732 * @hsotg: The driver state.
1733 * @ep: The index number of the endpoint
1734 * @mps: The maximum packet size in bytes
1735 *
1736 * Configure the maximum packet size for the given endpoint, updating
1737 * the hardware control registers to reflect this.
1738 */
1739static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1740 unsigned int ep, unsigned int mps, unsigned int dir_in)
1741{
1742 struct dwc2_hsotg_ep *hs_ep;
1743 void __iomem *regs = hsotg->regs;
1744 u32 mpsval;
1745 u32 mcval;
1746 u32 reg;
1747
1748 hs_ep = index_to_ep(hsotg, ep, dir_in);
1749 if (!hs_ep)
1750 return;
1751
1752 if (ep == 0) {
1753 /* EP0 is a special case */
1754 mpsval = dwc2_hsotg_ep0_mps(mps);
1755 if (mpsval > 3)
1756 goto bad_mps;
1757 hs_ep->ep.maxpacket = mps;
1758 hs_ep->mc = 1;
1759 } else {
1760 mpsval = mps & DXEPCTL_MPS_MASK;
1761 if (mpsval > 1024)
1762 goto bad_mps;
1763 mcval = ((mps >> 11) & 0x3) + 1;
1764 hs_ep->mc = mcval;
1765 if (mcval > 3)
1766 goto bad_mps;
1767 hs_ep->ep.maxpacket = mpsval;
1768 }
1769
1770 if (dir_in) {
1771 reg = dwc2_readl(regs + DIEPCTL(ep));
1772 reg &= ~DXEPCTL_MPS_MASK;
1773 reg |= mpsval;
1774 dwc2_writel(reg, regs + DIEPCTL(ep));
1775 } else {
1776 reg = dwc2_readl(regs + DOEPCTL(ep));
1777 reg &= ~DXEPCTL_MPS_MASK;
1778 reg |= mpsval;
1779 dwc2_writel(reg, regs + DOEPCTL(ep));
1780 }
1781
1782 return;
1783
1784bad_mps:
1785 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1786}
1787
1788/**
1789 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1790 * @hsotg: The driver state
1791 * @idx: The index for the endpoint (0..15)
1792 */
1793static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1794{
1795 int timeout;
1796 int val;
1797
1798 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1799 hsotg->regs + GRSTCTL);
1800
1801 /* wait until the fifo is flushed */
1802 timeout = 100;
1803
1804 while (1) {
1805 val = dwc2_readl(hsotg->regs + GRSTCTL);
1806
1807 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1808 break;
1809
1810 if (--timeout == 0) {
1811 dev_err(hsotg->dev,
1812 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1813 __func__, val);
1814 break;
1815 }
1816
1817 udelay(1);
1818 }
1819}
1820
1821/**
1822 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1823 * @hsotg: The driver state
1824 * @hs_ep: The driver endpoint to check.
1825 *
1826 * Check to see if there is a request that has data to send, and if so
1827 * make an attempt to write data into the FIFO.
1828 */
1829static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1830 struct dwc2_hsotg_ep *hs_ep)
1831{
1832 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1833
1834 if (!hs_ep->dir_in || !hs_req) {
1835 /**
1836 * if request is not enqueued, we disable interrupts
1837 * for endpoints, excepting ep0
1838 */
1839 if (hs_ep->index != 0)
1840 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1841 hs_ep->dir_in, 0);
1842 return 0;
1843 }
1844
1845 if (hs_req->req.actual < hs_req->req.length) {
1846 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1847 hs_ep->index);
1848 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1849 }
1850
1851 return 0;
1852}
1853
1854/**
1855 * dwc2_hsotg_complete_in - complete IN transfer
1856 * @hsotg: The device state.
1857 * @hs_ep: The endpoint that has just completed.
1858 *
1859 * An IN transfer has been completed, update the transfer's state and then
1860 * call the relevant completion routines.
1861 */
1862static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hsotg_ep *hs_ep)
1864{
1865 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1866 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1867 int size_left, size_done;
1868
1869 if (!hs_req) {
1870 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1871 return;
1872 }
1873
1874 /* Finish ZLP handling for IN EP0 transactions */
1875 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1876 dev_dbg(hsotg->dev, "zlp packet sent\n");
1877 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1878 if (hsotg->test_mode) {
1879 int ret;
1880
1881 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1882 if (ret < 0) {
1883 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1884 hsotg->test_mode);
1885 dwc2_hsotg_stall_ep0(hsotg);
1886 return;
1887 }
1888 }
1889 dwc2_hsotg_enqueue_setup(hsotg);
1890 return;
1891 }
1892
1893 /*
1894 * Calculate the size of the transfer by checking how much is left
1895 * in the endpoint size register and then working it out from
1896 * the amount we loaded for the transfer.
1897 *
1898 * We do this even for DMA, as the transfer may have incremented
1899 * past the end of the buffer (DMA transfers are always 32bit
1900 * aligned).
1901 */
1902
1903 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1904
1905 size_done = hs_ep->size_loaded - size_left;
1906 size_done += hs_ep->last_load;
1907
1908 if (hs_req->req.actual != size_done)
1909 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1910 __func__, hs_req->req.actual, size_done);
1911
1912 hs_req->req.actual = size_done;
1913 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1914 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1915
1916 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1917 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1918 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1919 return;
1920 }
1921
1922 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1923 if (hs_ep->send_zlp) {
1924 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1925 hs_ep->send_zlp = 0;
1926 /* transfer will be completed on next complete interrupt */
1927 return;
1928 }
1929
1930 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1931 /* Move to STATUS OUT */
1932 dwc2_hsotg_ep0_zlp(hsotg, false);
1933 return;
1934 }
1935
1936 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1937}
1938
1939/**
1940 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1941 * @hsotg: The driver state
1942 * @idx: The index for the endpoint (0..15)
1943 * @dir_in: Set if this is an IN endpoint
1944 *
1945 * Process and clear any interrupt pending for an individual endpoint
1946 */
1947static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1948 int dir_in)
1949{
1950 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1951 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1954 u32 ints;
1955 u32 ctrl;
1956
1957 ints = dwc2_readl(hsotg->regs + epint_reg);
1958 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1959
1960 /* Clear endpoint interrupts */
1961 dwc2_writel(ints, hsotg->regs + epint_reg);
1962
1963 if (!hs_ep) {
1964 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1965 __func__, idx, dir_in ? "in" : "out");
1966 return;
1967 }
1968
1969 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1970 __func__, idx, dir_in ? "in" : "out", ints);
1971
1972 /* Don't process XferCompl interrupt if it is a setup packet */
1973 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1974 ints &= ~DXEPINT_XFERCOMPL;
1975
1976 if (ints & DXEPINT_XFERCOMPL) {
1977 hs_ep->has_correct_parity = 1;
1978 if (hs_ep->isochronous && hs_ep->interval == 1)
1979 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1980
1981 dev_dbg(hsotg->dev,
1982 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1983 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1984 dwc2_readl(hsotg->regs + epsiz_reg));
1985
1986 /*
1987 * we get OutDone from the FIFO, so we only need to look
1988 * at completing IN requests here
1989 */
1990 if (dir_in) {
1991 dwc2_hsotg_complete_in(hsotg, hs_ep);
1992
1993 if (idx == 0 && !hs_ep->req)
1994 dwc2_hsotg_enqueue_setup(hsotg);
1995 } else if (using_dma(hsotg)) {
1996 /*
1997 * We're using DMA, we need to fire an OutDone here
1998 * as we ignore the RXFIFO.
1999 */
2000
2001 dwc2_hsotg_handle_outdone(hsotg, idx);
2002 }
2003 }
2004
2005 if (ints & DXEPINT_EPDISBLD) {
2006 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2007
2008 if (dir_in) {
2009 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2010
2011 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2012
2013 if ((epctl & DXEPCTL_STALL) &&
2014 (epctl & DXEPCTL_EPTYPE_BULK)) {
2015 int dctl = dwc2_readl(hsotg->regs + DCTL);
2016
2017 dctl |= DCTL_CGNPINNAK;
2018 dwc2_writel(dctl, hsotg->regs + DCTL);
2019 }
2020 }
2021 }
2022
2023 if (ints & DXEPINT_AHBERR)
2024 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2025
2026 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2027 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2028
2029 if (using_dma(hsotg) && idx == 0) {
2030 /*
2031 * this is the notification we've received a
2032 * setup packet. In non-DMA mode we'd get this
2033 * from the RXFIFO, instead we need to process
2034 * the setup here.
2035 */
2036
2037 if (dir_in)
2038 WARN_ON_ONCE(1);
2039 else
2040 dwc2_hsotg_handle_outdone(hsotg, 0);
2041 }
2042 }
2043
2044 if (ints & DXEPINT_BACK2BACKSETUP)
2045 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2046
2047 if (dir_in && !hs_ep->isochronous) {
2048 /* not sure if this is important, but we'll clear it anyway */
2049 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2050 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2051 __func__, idx);
2052 }
2053
2054 /* this probably means something bad is happening */
2055 if (ints & DIEPMSK_INTKNEPMISMSK) {
2056 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2057 __func__, idx);
2058 }
2059
2060 /* FIFO has space or is empty (see GAHBCFG) */
2061 if (hsotg->dedicated_fifos &&
2062 ints & DIEPMSK_TXFIFOEMPTY) {
2063 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2064 __func__, idx);
2065 if (!using_dma(hsotg))
2066 dwc2_hsotg_trytx(hsotg, hs_ep);
2067 }
2068 }
2069}
2070
2071/**
2072 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2073 * @hsotg: The device state.
2074 *
2075 * Handle updating the device settings after the enumeration phase has
2076 * been completed.
2077 */
2078static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2079{
2080 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2081 int ep0_mps = 0, ep_mps = 8;
2082
2083 /*
2084 * This should signal the finish of the enumeration phase
2085 * of the USB handshaking, so we should now know what rate
2086 * we connected at.
2087 */
2088
2089 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2090
2091 /*
2092 * note, since we're limited by the size of transfer on EP0, and
2093 * it seems IN transfers must be a even number of packets we do
2094 * not advertise a 64byte MPS on EP0.
2095 */
2096
2097 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2098 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2099 case DSTS_ENUMSPD_FS:
2100 case DSTS_ENUMSPD_FS48:
2101 hsotg->gadget.speed = USB_SPEED_FULL;
2102 ep0_mps = EP0_MPS_LIMIT;
2103 ep_mps = 1023;
2104 break;
2105
2106 case DSTS_ENUMSPD_HS:
2107 hsotg->gadget.speed = USB_SPEED_HIGH;
2108 ep0_mps = EP0_MPS_LIMIT;
2109 ep_mps = 1024;
2110 break;
2111
2112 case DSTS_ENUMSPD_LS:
2113 hsotg->gadget.speed = USB_SPEED_LOW;
2114 /*
2115 * note, we don't actually support LS in this driver at the
2116 * moment, and the documentation seems to imply that it isn't
2117 * supported by the PHYs on some of the devices.
2118 */
2119 break;
2120 }
2121 dev_info(hsotg->dev, "new device is %s\n",
2122 usb_speed_string(hsotg->gadget.speed));
2123
2124 /*
2125 * we should now know the maximum packet size for an
2126 * endpoint, so set the endpoints to a default value.
2127 */
2128
2129 if (ep0_mps) {
2130 int i;
2131 /* Initialize ep0 for both in and out directions */
2132 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2133 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2134 for (i = 1; i < hsotg->num_of_eps; i++) {
2135 if (hsotg->eps_in[i])
2136 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2137 if (hsotg->eps_out[i])
2138 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2139 }
2140 }
2141
2142 /* ensure after enumeration our EP0 is active */
2143
2144 dwc2_hsotg_enqueue_setup(hsotg);
2145
2146 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2147 dwc2_readl(hsotg->regs + DIEPCTL0),
2148 dwc2_readl(hsotg->regs + DOEPCTL0));
2149}
2150
2151/**
2152 * kill_all_requests - remove all requests from the endpoint's queue
2153 * @hsotg: The device state.
2154 * @ep: The endpoint the requests may be on.
2155 * @result: The result code to use.
2156 *
2157 * Go through the requests on the given endpoint and mark them
2158 * completed with the given result code.
2159 */
2160static void kill_all_requests(struct dwc2_hsotg *hsotg,
2161 struct dwc2_hsotg_ep *ep,
2162 int result)
2163{
2164 struct dwc2_hsotg_req *req, *treq;
2165 unsigned size;
2166
2167 ep->req = NULL;
2168
2169 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2170 dwc2_hsotg_complete_request(hsotg, ep, req,
2171 result);
2172
2173 if (!hsotg->dedicated_fifos)
2174 return;
2175 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2176 if (size < ep->fifo_size)
2177 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2178}
2179
2180/**
2181 * dwc2_hsotg_disconnect - disconnect service
2182 * @hsotg: The device state.
2183 *
2184 * The device has been disconnected. Remove all current
2185 * transactions and signal the gadget driver that this
2186 * has happened.
2187 */
2188void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2189{
2190 unsigned ep;
2191
2192 if (!hsotg->connected)
2193 return;
2194
2195 hsotg->connected = 0;
2196 hsotg->test_mode = 0;
2197
2198 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2199 if (hsotg->eps_in[ep])
2200 kill_all_requests(hsotg, hsotg->eps_in[ep],
2201 -ESHUTDOWN);
2202 if (hsotg->eps_out[ep])
2203 kill_all_requests(hsotg, hsotg->eps_out[ep],
2204 -ESHUTDOWN);
2205 }
2206
2207 call_gadget(hsotg, disconnect);
2208 hsotg->lx_state = DWC2_L3;
2209}
2210
2211/**
2212 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2213 * @hsotg: The device state:
2214 * @periodic: True if this is a periodic FIFO interrupt
2215 */
2216static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2217{
2218 struct dwc2_hsotg_ep *ep;
2219 int epno, ret;
2220
2221 /* look through for any more data to transmit */
2222 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2223 ep = index_to_ep(hsotg, epno, 1);
2224
2225 if (!ep)
2226 continue;
2227
2228 if (!ep->dir_in)
2229 continue;
2230
2231 if ((periodic && !ep->periodic) ||
2232 (!periodic && ep->periodic))
2233 continue;
2234
2235 ret = dwc2_hsotg_trytx(hsotg, ep);
2236 if (ret < 0)
2237 break;
2238 }
2239}
2240
2241/* IRQ flags which will trigger a retry around the IRQ loop */
2242#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2243 GINTSTS_PTXFEMP | \
2244 GINTSTS_RXFLVL)
2245
2246/**
2247 * dwc2_hsotg_core_init - issue softreset to the core
2248 * @hsotg: The device state
2249 *
2250 * Issue a soft reset to the core, and await the core finishing it.
2251 */
2252void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2253 bool is_usb_reset)
2254{
2255 u32 intmsk;
2256 u32 val;
2257 u32 usbcfg;
2258
2259 /* Kill any ep0 requests as controller will be reinitialized */
2260 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2261
2262 if (!is_usb_reset)
2263 if (dwc2_core_reset(hsotg))
2264 return;
2265
2266 /*
2267 * we must now enable ep0 ready for host detection and then
2268 * set configuration.
2269 */
2270
2271 /* keep other bits untouched (so e.g. forced modes are not lost) */
2272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2273 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2274 GUSBCFG_HNPCAP);
2275
2276 /* set the PLL on, remove the HNP/SRP and set the PHY */
2277 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2278 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2279 (val << GUSBCFG_USBTRDTIM_SHIFT);
2280 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2281
2282 dwc2_hsotg_init_fifo(hsotg);
2283
2284 if (!is_usb_reset)
2285 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2286
2287 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2288
2289 /* Clear any pending OTG interrupts */
2290 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2291
2292 /* Clear any pending interrupts */
2293 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2294 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2295 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2296 GINTSTS_USBRST | GINTSTS_RESETDET |
2297 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2298 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2299 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2300
2301 if (hsotg->core_params->external_id_pin_ctl <= 0)
2302 intmsk |= GINTSTS_CONIDSTSCHNG;
2303
2304 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2305
2306 if (using_dma(hsotg))
2307 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2308 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2309 hsotg->regs + GAHBCFG);
2310 else
2311 dwc2_writel(((hsotg->dedicated_fifos) ?
2312 (GAHBCFG_NP_TXF_EMP_LVL |
2313 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2314 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2315
2316 /*
2317 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2318 * when we have no data to transfer. Otherwise we get being flooded by
2319 * interrupts.
2320 */
2321
2322 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2323 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2324 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2325 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2326 DIEPMSK_INTKNEPMISMSK,
2327 hsotg->regs + DIEPMSK);
2328
2329 /*
2330 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2331 * DMA mode we may need this.
2332 */
2333 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2334 DIEPMSK_TIMEOUTMSK) : 0) |
2335 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2336 DOEPMSK_SETUPMSK,
2337 hsotg->regs + DOEPMSK);
2338
2339 dwc2_writel(0, hsotg->regs + DAINTMSK);
2340
2341 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2342 dwc2_readl(hsotg->regs + DIEPCTL0),
2343 dwc2_readl(hsotg->regs + DOEPCTL0));
2344
2345 /* enable in and out endpoint interrupts */
2346 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2347
2348 /*
2349 * Enable the RXFIFO when in slave mode, as this is how we collect
2350 * the data. In DMA mode, we get events from the FIFO but also
2351 * things we cannot process, so do not use it.
2352 */
2353 if (!using_dma(hsotg))
2354 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2355
2356 /* Enable interrupts for EP0 in and out */
2357 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2358 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2359
2360 if (!is_usb_reset) {
2361 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2362 udelay(10); /* see openiboot */
2363 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2364 }
2365
2366 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2367
2368 /*
2369 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2370 * writing to the EPCTL register..
2371 */
2372
2373 /* set to read 1 8byte packet */
2374 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2375 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2376
2377 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2378 DXEPCTL_CNAK | DXEPCTL_EPENA |
2379 DXEPCTL_USBACTEP,
2380 hsotg->regs + DOEPCTL0);
2381
2382 /* enable, but don't activate EP0in */
2383 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2384 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2385
2386 dwc2_hsotg_enqueue_setup(hsotg);
2387
2388 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2389 dwc2_readl(hsotg->regs + DIEPCTL0),
2390 dwc2_readl(hsotg->regs + DOEPCTL0));
2391
2392 /* clear global NAKs */
2393 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2394 if (!is_usb_reset)
2395 val |= DCTL_SFTDISCON;
2396 __orr32(hsotg->regs + DCTL, val);
2397
2398 /* must be at-least 3ms to allow bus to see disconnect */
2399 mdelay(3);
2400
2401 hsotg->lx_state = DWC2_L0;
2402}
2403
2404static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2405{
2406 /* set the soft-disconnect bit */
2407 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2408}
2409
2410void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2411{
2412 /* remove the soft-disconnect and let's go */
2413 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2414}
2415
2416/**
2417 * dwc2_hsotg_irq - handle device interrupt
2418 * @irq: The IRQ number triggered
2419 * @pw: The pw value when registered the handler.
2420 */
2421static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2422{
2423 struct dwc2_hsotg *hsotg = pw;
2424 int retry_count = 8;
2425 u32 gintsts;
2426 u32 gintmsk;
2427
2428 spin_lock(&hsotg->lock);
2429irq_retry:
2430 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2431 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2432
2433 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2434 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2435
2436 gintsts &= gintmsk;
2437
2438 if (gintsts & GINTSTS_RESETDET) {
2439 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2440
2441 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2442
2443 /* This event must be used only if controller is suspended */
2444 if (hsotg->lx_state == DWC2_L2) {
2445 dwc2_exit_hibernation(hsotg, true);
2446 hsotg->lx_state = DWC2_L0;
2447 }
2448 }
2449
2450 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2451
2452 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2453 u32 connected = hsotg->connected;
2454
2455 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2456 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2457 dwc2_readl(hsotg->regs + GNPTXSTS));
2458
2459 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2460
2461 /* Report disconnection if it is not already done. */
2462 dwc2_hsotg_disconnect(hsotg);
2463
2464 if (usb_status & GOTGCTL_BSESVLD && connected)
2465 dwc2_hsotg_core_init_disconnected(hsotg, true);
2466 }
2467
2468 if (gintsts & GINTSTS_ENUMDONE) {
2469 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2470
2471 dwc2_hsotg_irq_enumdone(hsotg);
2472 }
2473
2474 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2475 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2476 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2477 u32 daint_out, daint_in;
2478 int ep;
2479
2480 daint &= daintmsk;
2481 daint_out = daint >> DAINT_OUTEP_SHIFT;
2482 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2483
2484 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2485
2486 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2487 ep++, daint_out >>= 1) {
2488 if (daint_out & 1)
2489 dwc2_hsotg_epint(hsotg, ep, 0);
2490 }
2491
2492 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2493 ep++, daint_in >>= 1) {
2494 if (daint_in & 1)
2495 dwc2_hsotg_epint(hsotg, ep, 1);
2496 }
2497 }
2498
2499 /* check both FIFOs */
2500
2501 if (gintsts & GINTSTS_NPTXFEMP) {
2502 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2503
2504 /*
2505 * Disable the interrupt to stop it happening again
2506 * unless one of these endpoint routines decides that
2507 * it needs re-enabling
2508 */
2509
2510 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2511 dwc2_hsotg_irq_fifoempty(hsotg, false);
2512 }
2513
2514 if (gintsts & GINTSTS_PTXFEMP) {
2515 dev_dbg(hsotg->dev, "PTxFEmp\n");
2516
2517 /* See note in GINTSTS_NPTxFEmp */
2518
2519 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2520 dwc2_hsotg_irq_fifoempty(hsotg, true);
2521 }
2522
2523 if (gintsts & GINTSTS_RXFLVL) {
2524 /*
2525 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2526 * we need to retry dwc2_hsotg_handle_rx if this is still
2527 * set.
2528 */
2529
2530 dwc2_hsotg_handle_rx(hsotg);
2531 }
2532
2533 if (gintsts & GINTSTS_ERLYSUSP) {
2534 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2535 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2536 }
2537
2538 /*
2539 * these next two seem to crop-up occasionally causing the core
2540 * to shutdown the USB transfer, so try clearing them and logging
2541 * the occurrence.
2542 */
2543
2544 if (gintsts & GINTSTS_GOUTNAKEFF) {
2545 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2546
2547 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2548
2549 dwc2_hsotg_dump(hsotg);
2550 }
2551
2552 if (gintsts & GINTSTS_GINNAKEFF) {
2553 dev_info(hsotg->dev, "GINNakEff triggered\n");
2554
2555 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2556
2557 dwc2_hsotg_dump(hsotg);
2558 }
2559
2560 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2561 u32 idx, epctl_reg;
2562 struct dwc2_hsotg_ep *hs_ep;
2563
2564 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2565 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2566 hs_ep = hsotg->eps_in[idx];
2567
2568 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2569 continue;
2570
2571 epctl_reg = DIEPCTL(idx);
2572 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2573 }
2574 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2575 }
2576
2577 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2578 u32 idx, epctl_reg;
2579 struct dwc2_hsotg_ep *hs_ep;
2580
2581 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2582 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2583 hs_ep = hsotg->eps_out[idx];
2584
2585 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2586 continue;
2587
2588 epctl_reg = DOEPCTL(idx);
2589 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2590 }
2591 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2592 }
2593
2594 /*
2595 * if we've had fifo events, we should try and go around the
2596 * loop again to see if there's any point in returning yet.
2597 */
2598
2599 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2600 goto irq_retry;
2601
2602 spin_unlock(&hsotg->lock);
2603
2604 return IRQ_HANDLED;
2605}
2606
2607/**
2608 * dwc2_hsotg_ep_enable - enable the given endpoint
2609 * @ep: The USB endpint to configure
2610 * @desc: The USB endpoint descriptor to configure with.
2611 *
2612 * This is called from the USB gadget code's usb_ep_enable().
2613 */
2614static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2615 const struct usb_endpoint_descriptor *desc)
2616{
2617 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2618 struct dwc2_hsotg *hsotg = hs_ep->parent;
2619 unsigned long flags;
2620 unsigned int index = hs_ep->index;
2621 u32 epctrl_reg;
2622 u32 epctrl;
2623 u32 mps;
2624 unsigned int dir_in;
2625 unsigned int i, val, size;
2626 int ret = 0;
2627
2628 dev_dbg(hsotg->dev,
2629 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2630 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2631 desc->wMaxPacketSize, desc->bInterval);
2632
2633 /* not to be called for EP0 */
2634 WARN_ON(index == 0);
2635
2636 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2637 if (dir_in != hs_ep->dir_in) {
2638 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2639 return -EINVAL;
2640 }
2641
2642 mps = usb_endpoint_maxp(desc);
2643
2644 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2645
2646 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2647 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2648
2649 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2650 __func__, epctrl, epctrl_reg);
2651
2652 spin_lock_irqsave(&hsotg->lock, flags);
2653
2654 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2655 epctrl |= DXEPCTL_MPS(mps);
2656
2657 /*
2658 * mark the endpoint as active, otherwise the core may ignore
2659 * transactions entirely for this endpoint
2660 */
2661 epctrl |= DXEPCTL_USBACTEP;
2662
2663 /*
2664 * set the NAK status on the endpoint, otherwise we might try and
2665 * do something with data that we've yet got a request to process
2666 * since the RXFIFO will take data for an endpoint even if the
2667 * size register hasn't been set.
2668 */
2669
2670 epctrl |= DXEPCTL_SNAK;
2671
2672 /* update the endpoint state */
2673 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2674
2675 /* default, set to non-periodic */
2676 hs_ep->isochronous = 0;
2677 hs_ep->periodic = 0;
2678 hs_ep->halted = 0;
2679 hs_ep->interval = desc->bInterval;
2680 hs_ep->has_correct_parity = 0;
2681
2682 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2683 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2684
2685 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2686 case USB_ENDPOINT_XFER_ISOC:
2687 epctrl |= DXEPCTL_EPTYPE_ISO;
2688 epctrl |= DXEPCTL_SETEVENFR;
2689 hs_ep->isochronous = 1;
2690 if (dir_in)
2691 hs_ep->periodic = 1;
2692 break;
2693
2694 case USB_ENDPOINT_XFER_BULK:
2695 epctrl |= DXEPCTL_EPTYPE_BULK;
2696 break;
2697
2698 case USB_ENDPOINT_XFER_INT:
2699 if (dir_in)
2700 hs_ep->periodic = 1;
2701
2702 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2703 break;
2704
2705 case USB_ENDPOINT_XFER_CONTROL:
2706 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2707 break;
2708 }
2709
2710 /* If fifo is already allocated for this ep */
2711 if (hs_ep->fifo_index) {
2712 size = hs_ep->ep.maxpacket * hs_ep->mc;
2713 /* If bigger fifo is required deallocate current one */
2714 if (size > hs_ep->fifo_size) {
2715 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2716 hs_ep->fifo_index = 0;
2717 hs_ep->fifo_size = 0;
2718 }
2719 }
2720
2721 /*
2722 * if the hardware has dedicated fifos, we must give each IN EP
2723 * a unique tx-fifo even if it is non-periodic.
2724 */
2725 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2726 u32 fifo_index = 0;
2727 u32 fifo_size = UINT_MAX;
2728 size = hs_ep->ep.maxpacket*hs_ep->mc;
2729 for (i = 1; i < hsotg->num_of_eps; ++i) {
2730 if (hsotg->fifo_map & (1<<i))
2731 continue;
2732 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2733 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2734 if (val < size)
2735 continue;
2736 /* Search for smallest acceptable fifo */
2737 if (val < fifo_size) {
2738 fifo_size = val;
2739 fifo_index = i;
2740 }
2741 }
2742 if (!fifo_index) {
2743 dev_err(hsotg->dev,
2744 "%s: No suitable fifo found\n", __func__);
2745 ret = -ENOMEM;
2746 goto error;
2747 }
2748 hsotg->fifo_map |= 1 << fifo_index;
2749 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2750 hs_ep->fifo_index = fifo_index;
2751 hs_ep->fifo_size = fifo_size;
2752 }
2753
2754 /* for non control endpoints, set PID to D0 */
2755 if (index)
2756 epctrl |= DXEPCTL_SETD0PID;
2757
2758 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2759 __func__, epctrl);
2760
2761 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2762 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2763 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2764
2765 /* enable the endpoint interrupt */
2766 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2767
2768error:
2769 spin_unlock_irqrestore(&hsotg->lock, flags);
2770 return ret;
2771}
2772
2773/**
2774 * dwc2_hsotg_ep_disable - disable given endpoint
2775 * @ep: The endpoint to disable.
2776 */
2777static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2778{
2779 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2780 struct dwc2_hsotg *hsotg = hs_ep->parent;
2781 int dir_in = hs_ep->dir_in;
2782 int index = hs_ep->index;
2783 unsigned long flags;
2784 u32 epctrl_reg;
2785 u32 ctrl;
2786
2787 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2788
2789 if (ep == &hsotg->eps_out[0]->ep) {
2790 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2791 return -EINVAL;
2792 }
2793
2794 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2795
2796 spin_lock_irqsave(&hsotg->lock, flags);
2797
2798 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2799 hs_ep->fifo_index = 0;
2800 hs_ep->fifo_size = 0;
2801
2802 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2803 ctrl &= ~DXEPCTL_EPENA;
2804 ctrl &= ~DXEPCTL_USBACTEP;
2805 ctrl |= DXEPCTL_SNAK;
2806
2807 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2808 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2809
2810 /* disable endpoint interrupts */
2811 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2812
2813 /* terminate all requests with shutdown */
2814 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2815
2816 spin_unlock_irqrestore(&hsotg->lock, flags);
2817 return 0;
2818}
2819
2820/**
2821 * on_list - check request is on the given endpoint
2822 * @ep: The endpoint to check.
2823 * @test: The request to test if it is on the endpoint.
2824 */
2825static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2826{
2827 struct dwc2_hsotg_req *req, *treq;
2828
2829 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2830 if (req == test)
2831 return true;
2832 }
2833
2834 return false;
2835}
2836
2837static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2838 u32 bit, u32 timeout)
2839{
2840 u32 i;
2841
2842 for (i = 0; i < timeout; i++) {
2843 if (dwc2_readl(hs_otg->regs + reg) & bit)
2844 return 0;
2845 udelay(1);
2846 }
2847
2848 return -ETIMEDOUT;
2849}
2850
2851static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2852 struct dwc2_hsotg_ep *hs_ep)
2853{
2854 u32 epctrl_reg;
2855 u32 epint_reg;
2856
2857 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2858 DOEPCTL(hs_ep->index);
2859 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2860 DOEPINT(hs_ep->index);
2861
2862 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2863 hs_ep->name);
2864 if (hs_ep->dir_in) {
2865 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2866 /* Wait for Nak effect */
2867 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2868 DXEPINT_INEPNAKEFF, 100))
2869 dev_warn(hsotg->dev,
2870 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2871 } else {
2872 /* Clear any pending nak effect interrupt */
2873 dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS);
2874
2875 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2876
2877 /* Wait for global nak to take effect */
2878 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
2879 GINTSTS_GOUTNAKEFF, 100))
2880 dev_warn(hsotg->dev,
2881 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
2882 }
2883
2884 /* Disable ep */
2885 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2886
2887 /* Wait for ep to be disabled */
2888 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2889 dev_warn(hsotg->dev,
2890 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2891
2892 if (hs_ep->dir_in) {
2893 if (hsotg->dedicated_fifos) {
2894 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2895 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2896 /* Wait for fifo flush */
2897 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2898 GRSTCTL_TXFFLSH, 100))
2899 dev_warn(hsotg->dev,
2900 "%s: timeout flushing fifos\n",
2901 __func__);
2902 }
2903 /* TODO: Flush shared tx fifo */
2904 } else {
2905 /* Remove global NAKs */
2906 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2907 }
2908}
2909
2910/**
2911 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2912 * @ep: The endpoint to dequeue.
2913 * @req: The request to be removed from a queue.
2914 */
2915static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2916{
2917 struct dwc2_hsotg_req *hs_req = our_req(req);
2918 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2919 struct dwc2_hsotg *hs = hs_ep->parent;
2920 unsigned long flags;
2921
2922 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2923
2924 spin_lock_irqsave(&hs->lock, flags);
2925
2926 if (!on_list(hs_ep, hs_req)) {
2927 spin_unlock_irqrestore(&hs->lock, flags);
2928 return -EINVAL;
2929 }
2930
2931 /* Dequeue already started request */
2932 if (req == &hs_ep->req->req)
2933 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2934
2935 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2936 spin_unlock_irqrestore(&hs->lock, flags);
2937
2938 return 0;
2939}
2940
2941/**
2942 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2943 * @ep: The endpoint to set halt.
2944 * @value: Set or unset the halt.
2945 */
2946static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2947{
2948 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2949 struct dwc2_hsotg *hs = hs_ep->parent;
2950 int index = hs_ep->index;
2951 u32 epreg;
2952 u32 epctl;
2953 u32 xfertype;
2954
2955 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2956
2957 if (index == 0) {
2958 if (value)
2959 dwc2_hsotg_stall_ep0(hs);
2960 else
2961 dev_warn(hs->dev,
2962 "%s: can't clear halt on ep0\n", __func__);
2963 return 0;
2964 }
2965
2966 if (hs_ep->dir_in) {
2967 epreg = DIEPCTL(index);
2968 epctl = dwc2_readl(hs->regs + epreg);
2969
2970 if (value) {
2971 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2972 if (epctl & DXEPCTL_EPENA)
2973 epctl |= DXEPCTL_EPDIS;
2974 } else {
2975 epctl &= ~DXEPCTL_STALL;
2976 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2977 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2978 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2979 epctl |= DXEPCTL_SETD0PID;
2980 }
2981 dwc2_writel(epctl, hs->regs + epreg);
2982 } else {
2983
2984 epreg = DOEPCTL(index);
2985 epctl = dwc2_readl(hs->regs + epreg);
2986
2987 if (value)
2988 epctl |= DXEPCTL_STALL;
2989 else {
2990 epctl &= ~DXEPCTL_STALL;
2991 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2992 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2993 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2994 epctl |= DXEPCTL_SETD0PID;
2995 }
2996 dwc2_writel(epctl, hs->regs + epreg);
2997 }
2998
2999 hs_ep->halted = value;
3000
3001 return 0;
3002}
3003
3004/**
3005 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3006 * @ep: The endpoint to set halt.
3007 * @value: Set or unset the halt.
3008 */
3009static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3010{
3011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3012 struct dwc2_hsotg *hs = hs_ep->parent;
3013 unsigned long flags = 0;
3014 int ret = 0;
3015
3016 spin_lock_irqsave(&hs->lock, flags);
3017 ret = dwc2_hsotg_ep_sethalt(ep, value);
3018 spin_unlock_irqrestore(&hs->lock, flags);
3019
3020 return ret;
3021}
3022
3023static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3024 .enable = dwc2_hsotg_ep_enable,
3025 .disable = dwc2_hsotg_ep_disable,
3026 .alloc_request = dwc2_hsotg_ep_alloc_request,
3027 .free_request = dwc2_hsotg_ep_free_request,
3028 .queue = dwc2_hsotg_ep_queue_lock,
3029 .dequeue = dwc2_hsotg_ep_dequeue,
3030 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3031 /* note, don't believe we have any call for the fifo routines */
3032};
3033
3034/**
3035 * dwc2_hsotg_init - initalize the usb core
3036 * @hsotg: The driver state
3037 */
3038static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3039{
3040 u32 trdtim;
3041 u32 usbcfg;
3042 /* unmask subset of endpoint interrupts */
3043
3044 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3045 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3046 hsotg->regs + DIEPMSK);
3047
3048 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3049 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3050 hsotg->regs + DOEPMSK);
3051
3052 dwc2_writel(0, hsotg->regs + DAINTMSK);
3053
3054 /* Be in disconnected state until gadget is registered */
3055 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3056
3057 /* setup fifos */
3058
3059 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3060 dwc2_readl(hsotg->regs + GRXFSIZ),
3061 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3062
3063 dwc2_hsotg_init_fifo(hsotg);
3064
3065 /* keep other bits untouched (so e.g. forced modes are not lost) */
3066 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3067 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3068 GUSBCFG_HNPCAP);
3069
3070 /* set the PLL on, remove the HNP/SRP and set the PHY */
3071 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3072 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3073 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3074 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3075
3076 if (using_dma(hsotg))
3077 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3078}
3079
3080/**
3081 * dwc2_hsotg_udc_start - prepare the udc for work
3082 * @gadget: The usb gadget state
3083 * @driver: The usb gadget driver
3084 *
3085 * Perform initialization to prepare udc device and driver
3086 * to work.
3087 */
3088static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3089 struct usb_gadget_driver *driver)
3090{
3091 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3092 unsigned long flags;
3093 int ret;
3094
3095 if (!hsotg) {
3096 pr_err("%s: called with no device\n", __func__);
3097 return -ENODEV;
3098 }
3099
3100 if (!driver) {
3101 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3102 return -EINVAL;
3103 }
3104
3105 if (driver->max_speed < USB_SPEED_FULL)
3106 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3107
3108 if (!driver->setup) {
3109 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3110 return -EINVAL;
3111 }
3112
3113 WARN_ON(hsotg->driver);
3114
3115 driver->driver.bus = NULL;
3116 hsotg->driver = driver;
3117 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3118 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3119
3120 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3121 ret = dwc2_lowlevel_hw_enable(hsotg);
3122 if (ret)
3123 goto err;
3124 }
3125
3126 if (!IS_ERR_OR_NULL(hsotg->uphy))
3127 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3128
3129 spin_lock_irqsave(&hsotg->lock, flags);
3130 dwc2_hsotg_init(hsotg);
3131 dwc2_hsotg_core_init_disconnected(hsotg, false);
3132 hsotg->enabled = 0;
3133 spin_unlock_irqrestore(&hsotg->lock, flags);
3134
3135 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3136
3137 return 0;
3138
3139err:
3140 hsotg->driver = NULL;
3141 return ret;
3142}
3143
3144/**
3145 * dwc2_hsotg_udc_stop - stop the udc
3146 * @gadget: The usb gadget state
3147 * @driver: The usb gadget driver
3148 *
3149 * Stop udc hw block and stay tunned for future transmissions
3150 */
3151static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3152{
3153 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3154 unsigned long flags = 0;
3155 int ep;
3156
3157 if (!hsotg)
3158 return -ENODEV;
3159
3160 /* all endpoints should be shutdown */
3161 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3162 if (hsotg->eps_in[ep])
3163 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3164 if (hsotg->eps_out[ep])
3165 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3166 }
3167
3168 spin_lock_irqsave(&hsotg->lock, flags);
3169
3170 hsotg->driver = NULL;
3171 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3172 hsotg->enabled = 0;
3173
3174 spin_unlock_irqrestore(&hsotg->lock, flags);
3175
3176 if (!IS_ERR_OR_NULL(hsotg->uphy))
3177 otg_set_peripheral(hsotg->uphy->otg, NULL);
3178
3179 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3180 dwc2_lowlevel_hw_disable(hsotg);
3181
3182 return 0;
3183}
3184
3185/**
3186 * dwc2_hsotg_gadget_getframe - read the frame number
3187 * @gadget: The usb gadget state
3188 *
3189 * Read the {micro} frame number
3190 */
3191static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3192{
3193 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3194}
3195
3196/**
3197 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3198 * @gadget: The usb gadget state
3199 * @is_on: Current state of the USB PHY
3200 *
3201 * Connect/Disconnect the USB PHY pullup
3202 */
3203static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3204{
3205 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3206 unsigned long flags = 0;
3207
3208 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3209 hsotg->op_state);
3210
3211 /* Don't modify pullup state while in host mode */
3212 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3213 hsotg->enabled = is_on;
3214 return 0;
3215 }
3216
3217 spin_lock_irqsave(&hsotg->lock, flags);
3218 if (is_on) {
3219 hsotg->enabled = 1;
3220 dwc2_hsotg_core_init_disconnected(hsotg, false);
3221 dwc2_hsotg_core_connect(hsotg);
3222 } else {
3223 dwc2_hsotg_core_disconnect(hsotg);
3224 dwc2_hsotg_disconnect(hsotg);
3225 hsotg->enabled = 0;
3226 }
3227
3228 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3229 spin_unlock_irqrestore(&hsotg->lock, flags);
3230
3231 return 0;
3232}
3233
3234static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3235{
3236 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3237 unsigned long flags;
3238
3239 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3240 spin_lock_irqsave(&hsotg->lock, flags);
3241
3242 /*
3243 * If controller is hibernated, it must exit from hibernation
3244 * before being initialized / de-initialized
3245 */
3246 if (hsotg->lx_state == DWC2_L2)
3247 dwc2_exit_hibernation(hsotg, false);
3248
3249 if (is_active) {
3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3251
3252 dwc2_hsotg_core_init_disconnected(hsotg, false);
3253 if (hsotg->enabled)
3254 dwc2_hsotg_core_connect(hsotg);
3255 } else {
3256 dwc2_hsotg_core_disconnect(hsotg);
3257 dwc2_hsotg_disconnect(hsotg);
3258 }
3259
3260 spin_unlock_irqrestore(&hsotg->lock, flags);
3261 return 0;
3262}
3263
3264/**
3265 * dwc2_hsotg_vbus_draw - report bMaxPower field
3266 * @gadget: The usb gadget state
3267 * @mA: Amount of current
3268 *
3269 * Report how much power the device may consume to the phy.
3270 */
3271static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3272{
3273 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3274
3275 if (IS_ERR_OR_NULL(hsotg->uphy))
3276 return -ENOTSUPP;
3277 return usb_phy_set_power(hsotg->uphy, mA);
3278}
3279
3280static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3281 .get_frame = dwc2_hsotg_gadget_getframe,
3282 .udc_start = dwc2_hsotg_udc_start,
3283 .udc_stop = dwc2_hsotg_udc_stop,
3284 .pullup = dwc2_hsotg_pullup,
3285 .vbus_session = dwc2_hsotg_vbus_session,
3286 .vbus_draw = dwc2_hsotg_vbus_draw,
3287};
3288
3289/**
3290 * dwc2_hsotg_initep - initialise a single endpoint
3291 * @hsotg: The device state.
3292 * @hs_ep: The endpoint to be initialised.
3293 * @epnum: The endpoint number
3294 *
3295 * Initialise the given endpoint (as part of the probe and device state
3296 * creation) to give to the gadget driver. Setup the endpoint name, any
3297 * direction information and other state that may be required.
3298 */
3299static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3300 struct dwc2_hsotg_ep *hs_ep,
3301 int epnum,
3302 bool dir_in)
3303{
3304 char *dir;
3305
3306 if (epnum == 0)
3307 dir = "";
3308 else if (dir_in)
3309 dir = "in";
3310 else
3311 dir = "out";
3312
3313 hs_ep->dir_in = dir_in;
3314 hs_ep->index = epnum;
3315
3316 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3317
3318 INIT_LIST_HEAD(&hs_ep->queue);
3319 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3320
3321 /* add to the list of endpoints known by the gadget driver */
3322 if (epnum)
3323 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3324
3325 hs_ep->parent = hsotg;
3326 hs_ep->ep.name = hs_ep->name;
3327 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3328 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3329
3330 if (epnum == 0) {
3331 hs_ep->ep.caps.type_control = true;
3332 } else {
3333 hs_ep->ep.caps.type_iso = true;
3334 hs_ep->ep.caps.type_bulk = true;
3335 hs_ep->ep.caps.type_int = true;
3336 }
3337
3338 if (dir_in)
3339 hs_ep->ep.caps.dir_in = true;
3340 else
3341 hs_ep->ep.caps.dir_out = true;
3342
3343 /*
3344 * if we're using dma, we need to set the next-endpoint pointer
3345 * to be something valid.
3346 */
3347
3348 if (using_dma(hsotg)) {
3349 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3350 if (dir_in)
3351 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3352 else
3353 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3354 }
3355}
3356
3357/**
3358 * dwc2_hsotg_hw_cfg - read HW configuration registers
3359 * @param: The device state
3360 *
3361 * Read the USB core HW configuration registers
3362 */
3363static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3364{
3365 u32 cfg;
3366 u32 ep_type;
3367 u32 i;
3368
3369 /* check hardware configuration */
3370
3371 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3372
3373 /* Add ep0 */
3374 hsotg->num_of_eps++;
3375
3376 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3377 GFP_KERNEL);
3378 if (!hsotg->eps_in[0])
3379 return -ENOMEM;
3380 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3381 hsotg->eps_out[0] = hsotg->eps_in[0];
3382
3383 cfg = hsotg->hw_params.dev_ep_dirs;
3384 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3385 ep_type = cfg & 3;
3386 /* Direction in or both */
3387 if (!(ep_type & 2)) {
3388 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3389 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3390 if (!hsotg->eps_in[i])
3391 return -ENOMEM;
3392 }
3393 /* Direction out or both */
3394 if (!(ep_type & 1)) {
3395 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3396 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3397 if (!hsotg->eps_out[i])
3398 return -ENOMEM;
3399 }
3400 }
3401
3402 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3403 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3404
3405 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3406 hsotg->num_of_eps,
3407 hsotg->dedicated_fifos ? "dedicated" : "shared",
3408 hsotg->fifo_mem);
3409 return 0;
3410}
3411
3412/**
3413 * dwc2_hsotg_dump - dump state of the udc
3414 * @param: The device state
3415 */
3416static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3417{
3418#ifdef DEBUG
3419 struct device *dev = hsotg->dev;
3420 void __iomem *regs = hsotg->regs;
3421 u32 val;
3422 int idx;
3423
3424 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3425 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3426 dwc2_readl(regs + DIEPMSK));
3427
3428 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3429 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3430
3431 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3432 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3433
3434 /* show periodic fifo settings */
3435
3436 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3437 val = dwc2_readl(regs + DPTXFSIZN(idx));
3438 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3439 val >> FIFOSIZE_DEPTH_SHIFT,
3440 val & FIFOSIZE_STARTADDR_MASK);
3441 }
3442
3443 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3444 dev_info(dev,
3445 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3446 dwc2_readl(regs + DIEPCTL(idx)),
3447 dwc2_readl(regs + DIEPTSIZ(idx)),
3448 dwc2_readl(regs + DIEPDMA(idx)));
3449
3450 val = dwc2_readl(regs + DOEPCTL(idx));
3451 dev_info(dev,
3452 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3453 idx, dwc2_readl(regs + DOEPCTL(idx)),
3454 dwc2_readl(regs + DOEPTSIZ(idx)),
3455 dwc2_readl(regs + DOEPDMA(idx)));
3456
3457 }
3458
3459 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3460 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3461#endif
3462}
3463
3464#ifdef CONFIG_OF
3465static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3466{
3467 struct device_node *np = hsotg->dev->of_node;
3468 u32 len = 0;
3469 u32 i = 0;
3470
3471 /* Enable dma if requested in device tree */
3472 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3473
3474 /*
3475 * Register TX periodic fifo size per endpoint.
3476 * EP0 is excluded since it has no fifo configuration.
3477 */
3478 if (!of_find_property(np, "g-tx-fifo-size", &len))
3479 goto rx_fifo;
3480
3481 len /= sizeof(u32);
3482
3483 /* Read tx fifo sizes other than ep0 */
3484 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3485 &hsotg->g_tx_fifo_sz[1], len))
3486 goto rx_fifo;
3487
3488 /* Add ep0 */
3489 len++;
3490
3491 /* Make remaining TX fifos unavailable */
3492 if (len < MAX_EPS_CHANNELS) {
3493 for (i = len; i < MAX_EPS_CHANNELS; i++)
3494 hsotg->g_tx_fifo_sz[i] = 0;
3495 }
3496
3497rx_fifo:
3498 /* Register RX fifo size */
3499 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3500
3501 /* Register NPTX fifo size */
3502 of_property_read_u32(np, "g-np-tx-fifo-size",
3503 &hsotg->g_np_g_tx_fifo_sz);
3504}
3505#else
3506static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3507#endif
3508
3509/**
3510 * dwc2_gadget_init - init function for gadget
3511 * @dwc2: The data structure for the DWC2 driver.
3512 * @irq: The IRQ number for the controller.
3513 */
3514int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3515{
3516 struct device *dev = hsotg->dev;
3517 int epnum;
3518 int ret;
3519 int i;
3520 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3521
3522 /* Initialize to legacy fifo configuration values */
3523 hsotg->g_rx_fifo_sz = 2048;
3524 hsotg->g_np_g_tx_fifo_sz = 1024;
3525 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3526 /* Device tree specific probe */
3527 dwc2_hsotg_of_probe(hsotg);
3528
3529 /* Check against largest possible value. */
3530 if (hsotg->g_np_g_tx_fifo_sz >
3531 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3532 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3533 hsotg->g_np_g_tx_fifo_sz,
3534 hsotg->hw_params.dev_nperio_tx_fifo_size);
3535 hsotg->g_np_g_tx_fifo_sz =
3536 hsotg->hw_params.dev_nperio_tx_fifo_size;
3537 }
3538
3539 /* Dump fifo information */
3540 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3541 hsotg->g_np_g_tx_fifo_sz);
3542 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3543 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3544 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3545 hsotg->g_tx_fifo_sz[i]);
3546
3547 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3548 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3549 hsotg->gadget.name = dev_name(dev);
3550 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3551 hsotg->gadget.is_otg = 1;
3552 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3553 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3554
3555 ret = dwc2_hsotg_hw_cfg(hsotg);
3556 if (ret) {
3557 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3558 return ret;
3559 }
3560
3561 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3562 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3563 if (!hsotg->ctrl_buff) {
3564 dev_err(dev, "failed to allocate ctrl request buff\n");
3565 return -ENOMEM;
3566 }
3567
3568 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3569 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3570 if (!hsotg->ep0_buff) {
3571 dev_err(dev, "failed to allocate ctrl reply buff\n");
3572 return -ENOMEM;
3573 }
3574
3575 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3576 dev_name(hsotg->dev), hsotg);
3577 if (ret < 0) {
3578 dev_err(dev, "cannot claim IRQ for gadget\n");
3579 return ret;
3580 }
3581
3582 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3583
3584 if (hsotg->num_of_eps == 0) {
3585 dev_err(dev, "wrong number of EPs (zero)\n");
3586 return -EINVAL;
3587 }
3588
3589 /* setup endpoint information */
3590
3591 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3592 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3593
3594 /* allocate EP0 request */
3595
3596 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3597 GFP_KERNEL);
3598 if (!hsotg->ctrl_req) {
3599 dev_err(dev, "failed to allocate ctrl req\n");
3600 return -ENOMEM;
3601 }
3602
3603 /* initialise the endpoints now the core has been initialised */
3604 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3605 if (hsotg->eps_in[epnum])
3606 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3607 epnum, 1);
3608 if (hsotg->eps_out[epnum])
3609 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3610 epnum, 0);
3611 }
3612
3613 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3614 if (ret)
3615 return ret;
3616
3617 dwc2_hsotg_dump(hsotg);
3618
3619 return 0;
3620}
3621
3622/**
3623 * dwc2_hsotg_remove - remove function for hsotg driver
3624 * @pdev: The platform information for the driver
3625 */
3626int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3627{
3628 usb_del_gadget_udc(&hsotg->gadget);
3629
3630 return 0;
3631}
3632
3633int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3634{
3635 unsigned long flags;
3636
3637 if (hsotg->lx_state != DWC2_L0)
3638 return 0;
3639
3640 if (hsotg->driver) {
3641 int ep;
3642
3643 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3644 hsotg->driver->driver.name);
3645
3646 spin_lock_irqsave(&hsotg->lock, flags);
3647 if (hsotg->enabled)
3648 dwc2_hsotg_core_disconnect(hsotg);
3649 dwc2_hsotg_disconnect(hsotg);
3650 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3651 spin_unlock_irqrestore(&hsotg->lock, flags);
3652
3653 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3654 if (hsotg->eps_in[ep])
3655 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3656 if (hsotg->eps_out[ep])
3657 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3658 }
3659 }
3660
3661 return 0;
3662}
3663
3664int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3665{
3666 unsigned long flags;
3667
3668 if (hsotg->lx_state == DWC2_L2)
3669 return 0;
3670
3671 if (hsotg->driver) {
3672 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3673 hsotg->driver->driver.name);
3674
3675 spin_lock_irqsave(&hsotg->lock, flags);
3676 dwc2_hsotg_core_init_disconnected(hsotg, false);
3677 if (hsotg->enabled)
3678 dwc2_hsotg_core_connect(hsotg);
3679 spin_unlock_irqrestore(&hsotg->lock, flags);
3680 }
3681
3682 return 0;
3683}
3684
3685/**
3686 * dwc2_backup_device_registers() - Backup controller device registers.
3687 * When suspending usb bus, registers needs to be backuped
3688 * if controller power is disabled once suspended.
3689 *
3690 * @hsotg: Programming view of the DWC_otg controller
3691 */
3692int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3693{
3694 struct dwc2_dregs_backup *dr;
3695 int i;
3696
3697 dev_dbg(hsotg->dev, "%s\n", __func__);
3698
3699 /* Backup dev regs */
3700 dr = &hsotg->dr_backup;
3701
3702 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3703 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3704 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3705 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3706 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3707
3708 for (i = 0; i < hsotg->num_of_eps; i++) {
3709 /* Backup IN EPs */
3710 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3711
3712 /* Ensure DATA PID is correctly configured */
3713 if (dr->diepctl[i] & DXEPCTL_DPID)
3714 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3715 else
3716 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3717
3718 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3719 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3720
3721 /* Backup OUT EPs */
3722 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3723
3724 /* Ensure DATA PID is correctly configured */
3725 if (dr->doepctl[i] & DXEPCTL_DPID)
3726 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3727 else
3728 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3729
3730 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3731 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3732 }
3733 dr->valid = true;
3734 return 0;
3735}
3736
3737/**
3738 * dwc2_restore_device_registers() - Restore controller device registers.
3739 * When resuming usb bus, device registers needs to be restored
3740 * if controller power were disabled.
3741 *
3742 * @hsotg: Programming view of the DWC_otg controller
3743 */
3744int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3745{
3746 struct dwc2_dregs_backup *dr;
3747 u32 dctl;
3748 int i;
3749
3750 dev_dbg(hsotg->dev, "%s\n", __func__);
3751
3752 /* Restore dev regs */
3753 dr = &hsotg->dr_backup;
3754 if (!dr->valid) {
3755 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3756 __func__);
3757 return -EINVAL;
3758 }
3759 dr->valid = false;
3760
3761 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3762 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3763 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3764 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3765 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3766
3767 for (i = 0; i < hsotg->num_of_eps; i++) {
3768 /* Restore IN EPs */
3769 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3770 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3771 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3772
3773 /* Restore OUT EPs */
3774 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3775 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3776 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3777 }
3778
3779 /* Set the Power-On Programming done bit */
3780 dctl = dwc2_readl(hsotg->regs + DCTL);
3781 dctl |= DCTL_PWRONPRGDONE;
3782 dwc2_writel(dctl, hsotg->regs + DCTL);
3783
3784 return 0;
3785}