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1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/of_spi.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <sysdev/fsl_soc.h>
24
25#include "spi-fsl-lib.h"
26
27/* eSPI Controller registers */
28struct fsl_espi_reg {
29 __be32 mode; /* 0x000 - eSPI mode register */
30 __be32 event; /* 0x004 - eSPI event register */
31 __be32 mask; /* 0x008 - eSPI mask register */
32 __be32 command; /* 0x00c - eSPI command register */
33 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
34 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
35 u8 res[8]; /* 0x018 - 0x01c reserved */
36 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
37};
38
39struct fsl_espi_transfer {
40 const void *tx_buf;
41 void *rx_buf;
42 unsigned len;
43 unsigned n_tx;
44 unsigned n_rx;
45 unsigned actual_length;
46 int status;
47};
48
49/* eSPI Controller mode register definitions */
50#define SPMODE_ENABLE (1 << 31)
51#define SPMODE_LOOP (1 << 30)
52#define SPMODE_TXTHR(x) ((x) << 8)
53#define SPMODE_RXTHR(x) ((x) << 0)
54
55/* eSPI Controller CS mode register definitions */
56#define CSMODE_CI_INACTIVEHIGH (1 << 31)
57#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
58#define CSMODE_REV (1 << 29)
59#define CSMODE_DIV16 (1 << 28)
60#define CSMODE_PM(x) ((x) << 24)
61#define CSMODE_POL_1 (1 << 20)
62#define CSMODE_LEN(x) ((x) << 16)
63#define CSMODE_BEF(x) ((x) << 12)
64#define CSMODE_AFT(x) ((x) << 8)
65#define CSMODE_CG(x) ((x) << 3)
66
67/* Default mode/csmode for eSPI controller */
68#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
69#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
70 | CSMODE_AFT(0) | CSMODE_CG(1))
71
72/* SPIE register values */
73#define SPIE_NE 0x00000200 /* Not empty */
74#define SPIE_NF 0x00000100 /* Not full */
75
76/* SPIM register values */
77#define SPIM_NE 0x00000200 /* Not empty */
78#define SPIM_NF 0x00000100 /* Not full */
79#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
80#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
81
82/* SPCOM register values */
83#define SPCOM_CS(x) ((x) << 30)
84#define SPCOM_TRANLEN(x) ((x) << 0)
85#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
86
87static void fsl_espi_change_mode(struct spi_device *spi)
88{
89 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
90 struct spi_mpc8xxx_cs *cs = spi->controller_state;
91 struct fsl_espi_reg *reg_base = mspi->reg_base;
92 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
93 __be32 __iomem *espi_mode = ®_base->mode;
94 u32 tmp;
95 unsigned long flags;
96
97 /* Turn off IRQs locally to minimize time that SPI is disabled. */
98 local_irq_save(flags);
99
100 /* Turn off SPI unit prior changing mode */
101 tmp = mpc8xxx_spi_read_reg(espi_mode);
102 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
103 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
104 mpc8xxx_spi_write_reg(espi_mode, tmp);
105
106 local_irq_restore(flags);
107}
108
109static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
110{
111 u32 data;
112 u16 data_h;
113 u16 data_l;
114 const u32 *tx = mpc8xxx_spi->tx;
115
116 if (!tx)
117 return 0;
118
119 data = *tx++ << mpc8xxx_spi->tx_shift;
120 data_l = data & 0xffff;
121 data_h = (data >> 16) & 0xffff;
122 swab16s(&data_l);
123 swab16s(&data_h);
124 data = data_h | data_l;
125
126 mpc8xxx_spi->tx = tx;
127 return data;
128}
129
130static int fsl_espi_setup_transfer(struct spi_device *spi,
131 struct spi_transfer *t)
132{
133 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
134 int bits_per_word = 0;
135 u8 pm;
136 u32 hz = 0;
137 struct spi_mpc8xxx_cs *cs = spi->controller_state;
138
139 if (t) {
140 bits_per_word = t->bits_per_word;
141 hz = t->speed_hz;
142 }
143
144 /* spi_transfer level calls that work per-word */
145 if (!bits_per_word)
146 bits_per_word = spi->bits_per_word;
147
148 /* Make sure its a bit width we support [4..16] */
149 if ((bits_per_word < 4) || (bits_per_word > 16))
150 return -EINVAL;
151
152 if (!hz)
153 hz = spi->max_speed_hz;
154
155 cs->rx_shift = 0;
156 cs->tx_shift = 0;
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159 if (bits_per_word <= 8) {
160 cs->rx_shift = 8 - bits_per_word;
161 } else if (bits_per_word <= 16) {
162 cs->rx_shift = 16 - bits_per_word;
163 if (spi->mode & SPI_LSB_FIRST)
164 cs->get_tx = fsl_espi_tx_buf_lsb;
165 } else {
166 return -EINVAL;
167 }
168
169 mpc8xxx_spi->rx_shift = cs->rx_shift;
170 mpc8xxx_spi->tx_shift = cs->tx_shift;
171 mpc8xxx_spi->get_rx = cs->get_rx;
172 mpc8xxx_spi->get_tx = cs->get_tx;
173
174 bits_per_word = bits_per_word - 1;
175
176 /* mask out bits we are going to set */
177 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
178
179 cs->hw_mode |= CSMODE_LEN(bits_per_word);
180
181 if ((mpc8xxx_spi->spibrg / hz) > 64) {
182 cs->hw_mode |= CSMODE_DIV16;
183 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
184
185 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
186 "Will use %d Hz instead.\n", dev_name(&spi->dev),
187 hz, mpc8xxx_spi->spibrg / 1024);
188 if (pm > 16)
189 pm = 16;
190 } else {
191 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
192 }
193 if (pm)
194 pm--;
195
196 cs->hw_mode |= CSMODE_PM(pm);
197
198 fsl_espi_change_mode(spi);
199 return 0;
200}
201
202static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
203 unsigned int len)
204{
205 u32 word;
206 struct fsl_espi_reg *reg_base = mspi->reg_base;
207
208 mspi->count = len;
209
210 /* enable rx ints */
211 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
212
213 /* transmit word */
214 word = mspi->get_tx(mspi);
215 mpc8xxx_spi_write_reg(®_base->transmit, word);
216
217 return 0;
218}
219
220static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
221{
222 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
224 unsigned int len = t->len;
225 u8 bits_per_word;
226 int ret;
227
228 bits_per_word = spi->bits_per_word;
229 if (t->bits_per_word)
230 bits_per_word = t->bits_per_word;
231
232 mpc8xxx_spi->len = t->len;
233 len = roundup(len, 4) / 4;
234
235 mpc8xxx_spi->tx = t->tx_buf;
236 mpc8xxx_spi->rx = t->rx_buf;
237
238 INIT_COMPLETION(mpc8xxx_spi->done);
239
240 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
241 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
242 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
243 " beyond the SPCOM[TRANLEN] field\n", t->len);
244 return -EINVAL;
245 }
246 mpc8xxx_spi_write_reg(®_base->command,
247 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
248
249 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
250 if (ret)
251 return ret;
252
253 wait_for_completion(&mpc8xxx_spi->done);
254
255 /* disable rx ints */
256 mpc8xxx_spi_write_reg(®_base->mask, 0);
257
258 return mpc8xxx_spi->count;
259}
260
261static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
262{
263 if (cmd) {
264 cmd[1] = (u8)(addr >> 16);
265 cmd[2] = (u8)(addr >> 8);
266 cmd[3] = (u8)(addr >> 0);
267 }
268}
269
270static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
271{
272 if (cmd)
273 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
274
275 return 0;
276}
277
278static void fsl_espi_do_trans(struct spi_message *m,
279 struct fsl_espi_transfer *tr)
280{
281 struct spi_device *spi = m->spi;
282 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
283 struct fsl_espi_transfer *espi_trans = tr;
284 struct spi_message message;
285 struct spi_transfer *t, *first, trans;
286 int status = 0;
287
288 spi_message_init(&message);
289 memset(&trans, 0, sizeof(trans));
290
291 first = list_first_entry(&m->transfers, struct spi_transfer,
292 transfer_list);
293 list_for_each_entry(t, &m->transfers, transfer_list) {
294 if ((first->bits_per_word != t->bits_per_word) ||
295 (first->speed_hz != t->speed_hz)) {
296 espi_trans->status = -EINVAL;
297 dev_err(mspi->dev, "bits_per_word/speed_hz should be"
298 " same for the same SPI transfer\n");
299 return;
300 }
301
302 trans.speed_hz = t->speed_hz;
303 trans.bits_per_word = t->bits_per_word;
304 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
305 }
306
307 trans.len = espi_trans->len;
308 trans.tx_buf = espi_trans->tx_buf;
309 trans.rx_buf = espi_trans->rx_buf;
310 spi_message_add_tail(&trans, &message);
311
312 list_for_each_entry(t, &message.transfers, transfer_list) {
313 if (t->bits_per_word || t->speed_hz) {
314 status = -EINVAL;
315
316 status = fsl_espi_setup_transfer(spi, t);
317 if (status < 0)
318 break;
319 }
320
321 if (t->len)
322 status = fsl_espi_bufs(spi, t);
323
324 if (status) {
325 status = -EMSGSIZE;
326 break;
327 }
328
329 if (t->delay_usecs)
330 udelay(t->delay_usecs);
331 }
332
333 espi_trans->status = status;
334 fsl_espi_setup_transfer(spi, NULL);
335}
336
337static void fsl_espi_cmd_trans(struct spi_message *m,
338 struct fsl_espi_transfer *trans, u8 *rx_buff)
339{
340 struct spi_transfer *t;
341 u8 *local_buf;
342 int i = 0;
343 struct fsl_espi_transfer *espi_trans = trans;
344
345 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
346 if (!local_buf) {
347 espi_trans->status = -ENOMEM;
348 return;
349 }
350
351 list_for_each_entry(t, &m->transfers, transfer_list) {
352 if (t->tx_buf) {
353 memcpy(local_buf + i, t->tx_buf, t->len);
354 i += t->len;
355 }
356 }
357
358 espi_trans->tx_buf = local_buf;
359 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
360 fsl_espi_do_trans(m, espi_trans);
361
362 espi_trans->actual_length = espi_trans->len;
363 kfree(local_buf);
364}
365
366static void fsl_espi_rw_trans(struct spi_message *m,
367 struct fsl_espi_transfer *trans, u8 *rx_buff)
368{
369 struct fsl_espi_transfer *espi_trans = trans;
370 unsigned int n_tx = espi_trans->n_tx;
371 unsigned int n_rx = espi_trans->n_rx;
372 struct spi_transfer *t;
373 u8 *local_buf;
374 u8 *rx_buf = rx_buff;
375 unsigned int trans_len;
376 unsigned int addr;
377 int i, pos, loop;
378
379 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
380 if (!local_buf) {
381 espi_trans->status = -ENOMEM;
382 return;
383 }
384
385 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
386 trans_len = n_rx - pos;
387 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
388 trans_len = SPCOM_TRANLEN_MAX - n_tx;
389
390 i = 0;
391 list_for_each_entry(t, &m->transfers, transfer_list) {
392 if (t->tx_buf) {
393 memcpy(local_buf + i, t->tx_buf, t->len);
394 i += t->len;
395 }
396 }
397
398 if (pos > 0) {
399 addr = fsl_espi_cmd2addr(local_buf);
400 addr += pos;
401 fsl_espi_addr2cmd(addr, local_buf);
402 }
403
404 espi_trans->n_tx = n_tx;
405 espi_trans->n_rx = trans_len;
406 espi_trans->len = trans_len + n_tx;
407 espi_trans->tx_buf = local_buf;
408 espi_trans->rx_buf = local_buf + n_tx;
409 fsl_espi_do_trans(m, espi_trans);
410
411 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
412
413 if (loop > 0)
414 espi_trans->actual_length += espi_trans->len - n_tx;
415 else
416 espi_trans->actual_length += espi_trans->len;
417 }
418
419 kfree(local_buf);
420}
421
422static void fsl_espi_do_one_msg(struct spi_message *m)
423{
424 struct spi_transfer *t;
425 u8 *rx_buf = NULL;
426 unsigned int n_tx = 0;
427 unsigned int n_rx = 0;
428 struct fsl_espi_transfer espi_trans;
429
430 list_for_each_entry(t, &m->transfers, transfer_list) {
431 if (t->tx_buf)
432 n_tx += t->len;
433 if (t->rx_buf) {
434 n_rx += t->len;
435 rx_buf = t->rx_buf;
436 }
437 }
438
439 espi_trans.n_tx = n_tx;
440 espi_trans.n_rx = n_rx;
441 espi_trans.len = n_tx + n_rx;
442 espi_trans.actual_length = 0;
443 espi_trans.status = 0;
444
445 if (!rx_buf)
446 fsl_espi_cmd_trans(m, &espi_trans, NULL);
447 else
448 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
449
450 m->actual_length = espi_trans.actual_length;
451 m->status = espi_trans.status;
452 m->complete(m->context);
453}
454
455static int fsl_espi_setup(struct spi_device *spi)
456{
457 struct mpc8xxx_spi *mpc8xxx_spi;
458 struct fsl_espi_reg *reg_base;
459 int retval;
460 u32 hw_mode;
461 u32 loop_mode;
462 struct spi_mpc8xxx_cs *cs = spi->controller_state;
463
464 if (!spi->max_speed_hz)
465 return -EINVAL;
466
467 if (!cs) {
468 cs = kzalloc(sizeof *cs, GFP_KERNEL);
469 if (!cs)
470 return -ENOMEM;
471 spi->controller_state = cs;
472 }
473
474 mpc8xxx_spi = spi_master_get_devdata(spi->master);
475 reg_base = mpc8xxx_spi->reg_base;
476
477 hw_mode = cs->hw_mode; /* Save original settings */
478 cs->hw_mode = mpc8xxx_spi_read_reg(
479 ®_base->csmode[spi->chip_select]);
480 /* mask out bits we are going to set */
481 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
482 | CSMODE_REV);
483
484 if (spi->mode & SPI_CPHA)
485 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
486 if (spi->mode & SPI_CPOL)
487 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
488 if (!(spi->mode & SPI_LSB_FIRST))
489 cs->hw_mode |= CSMODE_REV;
490
491 /* Handle the loop mode */
492 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
493 loop_mode &= ~SPMODE_LOOP;
494 if (spi->mode & SPI_LOOP)
495 loop_mode |= SPMODE_LOOP;
496 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
497
498 retval = fsl_espi_setup_transfer(spi, NULL);
499 if (retval < 0) {
500 cs->hw_mode = hw_mode; /* Restore settings */
501 return retval;
502 }
503 return 0;
504}
505
506void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
507{
508 struct fsl_espi_reg *reg_base = mspi->reg_base;
509
510 /* We need handle RX first */
511 if (events & SPIE_NE) {
512 u32 rx_data, tmp;
513 u8 rx_data_8;
514
515 /* Spin until RX is done */
516 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
517 cpu_relax();
518 events = mpc8xxx_spi_read_reg(®_base->event);
519 }
520
521 if (mspi->len >= 4) {
522 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
523 } else {
524 tmp = mspi->len;
525 rx_data = 0;
526 while (tmp--) {
527 rx_data_8 = in_8((u8 *)®_base->receive);
528 rx_data |= (rx_data_8 << (tmp * 8));
529 }
530
531 rx_data <<= (4 - mspi->len) * 8;
532 }
533
534 mspi->len -= 4;
535
536 if (mspi->rx)
537 mspi->get_rx(rx_data, mspi);
538 }
539
540 if (!(events & SPIE_NF)) {
541 int ret;
542
543 /* spin until TX is done */
544 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
545 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
546 if (!ret) {
547 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
548 return;
549 }
550 }
551
552 /* Clear the events */
553 mpc8xxx_spi_write_reg(®_base->event, events);
554
555 mspi->count -= 1;
556 if (mspi->count) {
557 u32 word = mspi->get_tx(mspi);
558
559 mpc8xxx_spi_write_reg(®_base->transmit, word);
560 } else {
561 complete(&mspi->done);
562 }
563}
564
565static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
566{
567 struct mpc8xxx_spi *mspi = context_data;
568 struct fsl_espi_reg *reg_base = mspi->reg_base;
569 irqreturn_t ret = IRQ_NONE;
570 u32 events;
571
572 /* Get interrupt events(tx/rx) */
573 events = mpc8xxx_spi_read_reg(®_base->event);
574 if (events)
575 ret = IRQ_HANDLED;
576
577 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
578
579 fsl_espi_cpu_irq(mspi, events);
580
581 return ret;
582}
583
584static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
585{
586 iounmap(mspi->reg_base);
587}
588
589static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
590 struct resource *mem, unsigned int irq)
591{
592 struct fsl_spi_platform_data *pdata = dev->platform_data;
593 struct spi_master *master;
594 struct mpc8xxx_spi *mpc8xxx_spi;
595 struct fsl_espi_reg *reg_base;
596 u32 regval;
597 int i, ret = 0;
598
599 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
600 if (!master) {
601 ret = -ENOMEM;
602 goto err;
603 }
604
605 dev_set_drvdata(dev, master);
606
607 ret = mpc8xxx_spi_probe(dev, mem, irq);
608 if (ret)
609 goto err_probe;
610
611 master->setup = fsl_espi_setup;
612
613 mpc8xxx_spi = spi_master_get_devdata(master);
614 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
615 mpc8xxx_spi->spi_remove = fsl_espi_remove;
616
617 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
618 if (!mpc8xxx_spi->reg_base) {
619 ret = -ENOMEM;
620 goto err_probe;
621 }
622
623 reg_base = mpc8xxx_spi->reg_base;
624
625 /* Register for SPI Interrupt */
626 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
627 0, "fsl_espi", mpc8xxx_spi);
628 if (ret)
629 goto free_irq;
630
631 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
632 mpc8xxx_spi->rx_shift = 16;
633 mpc8xxx_spi->tx_shift = 24;
634 }
635
636 /* SPI controller initializations */
637 mpc8xxx_spi_write_reg(®_base->mode, 0);
638 mpc8xxx_spi_write_reg(®_base->mask, 0);
639 mpc8xxx_spi_write_reg(®_base->command, 0);
640 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
641
642 /* Init eSPI CS mode register */
643 for (i = 0; i < pdata->max_chipselect; i++)
644 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
645
646 /* Enable SPI interface */
647 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
648
649 mpc8xxx_spi_write_reg(®_base->mode, regval);
650
651 ret = spi_register_master(master);
652 if (ret < 0)
653 goto unreg_master;
654
655 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
656
657 return master;
658
659unreg_master:
660 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
661free_irq:
662 iounmap(mpc8xxx_spi->reg_base);
663err_probe:
664 spi_master_put(master);
665err:
666 return ERR_PTR(ret);
667}
668
669static int of_fsl_espi_get_chipselects(struct device *dev)
670{
671 struct device_node *np = dev->of_node;
672 struct fsl_spi_platform_data *pdata = dev->platform_data;
673 const u32 *prop;
674 int len;
675
676 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
677 if (!prop || len < sizeof(*prop)) {
678 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
679 return -EINVAL;
680 }
681
682 pdata->max_chipselect = *prop;
683 pdata->cs_control = NULL;
684
685 return 0;
686}
687
688static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
689{
690 struct device *dev = &ofdev->dev;
691 struct device_node *np = ofdev->dev.of_node;
692 struct spi_master *master;
693 struct resource mem;
694 struct resource irq;
695 int ret = -ENOMEM;
696
697 ret = of_mpc8xxx_spi_probe(ofdev);
698 if (ret)
699 return ret;
700
701 ret = of_fsl_espi_get_chipselects(dev);
702 if (ret)
703 goto err;
704
705 ret = of_address_to_resource(np, 0, &mem);
706 if (ret)
707 goto err;
708
709 ret = of_irq_to_resource(np, 0, &irq);
710 if (!ret) {
711 ret = -EINVAL;
712 goto err;
713 }
714
715 master = fsl_espi_probe(dev, &mem, irq.start);
716 if (IS_ERR(master)) {
717 ret = PTR_ERR(master);
718 goto err;
719 }
720
721 return 0;
722
723err:
724 return ret;
725}
726
727static int __devexit of_fsl_espi_remove(struct platform_device *dev)
728{
729 return mpc8xxx_spi_remove(&dev->dev);
730}
731
732static const struct of_device_id of_fsl_espi_match[] = {
733 { .compatible = "fsl,mpc8536-espi" },
734 {}
735};
736MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
737
738static struct platform_driver fsl_espi_driver = {
739 .driver = {
740 .name = "fsl_espi",
741 .owner = THIS_MODULE,
742 .of_match_table = of_fsl_espi_match,
743 },
744 .probe = of_fsl_espi_probe,
745 .remove = __devexit_p(of_fsl_espi_remove),
746};
747
748static int __init fsl_espi_init(void)
749{
750 return platform_driver_register(&fsl_espi_driver);
751}
752module_init(fsl_espi_init);
753
754static void __exit fsl_espi_exit(void)
755{
756 platform_driver_unregister(&fsl_espi_driver);
757}
758module_exit(fsl_espi_exit);
759
760MODULE_AUTHOR("Mingkai Hu");
761MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
762MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale eSPI controller driver.
4 *
5 * Copyright 2010 Freescale Semiconductor, Inc.
6 */
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/fsl_devices.h>
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/mm.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/pm_runtime.h>
20#include <sysdev/fsl_soc.h>
21
22/* eSPI Controller registers */
23#define ESPI_SPMODE 0x00 /* eSPI mode register */
24#define ESPI_SPIE 0x04 /* eSPI event register */
25#define ESPI_SPIM 0x08 /* eSPI mask register */
26#define ESPI_SPCOM 0x0c /* eSPI command register */
27#define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
28#define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
29#define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
30
31#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
32
33/* eSPI Controller mode register definitions */
34#define SPMODE_ENABLE BIT(31)
35#define SPMODE_LOOP BIT(30)
36#define SPMODE_TXTHR(x) ((x) << 8)
37#define SPMODE_RXTHR(x) ((x) << 0)
38
39/* eSPI Controller CS mode register definitions */
40#define CSMODE_CI_INACTIVEHIGH BIT(31)
41#define CSMODE_CP_BEGIN_EDGECLK BIT(30)
42#define CSMODE_REV BIT(29)
43#define CSMODE_DIV16 BIT(28)
44#define CSMODE_PM(x) ((x) << 24)
45#define CSMODE_POL_1 BIT(20)
46#define CSMODE_LEN(x) ((x) << 16)
47#define CSMODE_BEF(x) ((x) << 12)
48#define CSMODE_AFT(x) ((x) << 8)
49#define CSMODE_CG(x) ((x) << 3)
50
51#define FSL_ESPI_FIFO_SIZE 32
52#define FSL_ESPI_RXTHR 15
53
54/* Default mode/csmode for eSPI controller */
55#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
56#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
57 | CSMODE_AFT(0) | CSMODE_CG(1))
58
59/* SPIE register values */
60#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
61#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
62#define SPIE_TXE BIT(15) /* TX FIFO empty */
63#define SPIE_DON BIT(14) /* TX done */
64#define SPIE_RXT BIT(13) /* RX FIFO threshold */
65#define SPIE_RXF BIT(12) /* RX FIFO full */
66#define SPIE_TXT BIT(11) /* TX FIFO threshold*/
67#define SPIE_RNE BIT(9) /* RX FIFO not empty */
68#define SPIE_TNF BIT(8) /* TX FIFO not full */
69
70/* SPIM register values */
71#define SPIM_TXE BIT(15) /* TX FIFO empty */
72#define SPIM_DON BIT(14) /* TX done */
73#define SPIM_RXT BIT(13) /* RX FIFO threshold */
74#define SPIM_RXF BIT(12) /* RX FIFO full */
75#define SPIM_TXT BIT(11) /* TX FIFO threshold*/
76#define SPIM_RNE BIT(9) /* RX FIFO not empty */
77#define SPIM_TNF BIT(8) /* TX FIFO not full */
78
79/* SPCOM register values */
80#define SPCOM_CS(x) ((x) << 30)
81#define SPCOM_DO BIT(28) /* Dual output */
82#define SPCOM_TO BIT(27) /* TX only */
83#define SPCOM_RXSKIP(x) ((x) << 16)
84#define SPCOM_TRANLEN(x) ((x) << 0)
85
86#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
87
88#define AUTOSUSPEND_TIMEOUT 2000
89
90struct fsl_espi {
91 struct device *dev;
92 void __iomem *reg_base;
93
94 struct list_head *m_transfers;
95 struct spi_transfer *tx_t;
96 unsigned int tx_pos;
97 bool tx_done;
98 struct spi_transfer *rx_t;
99 unsigned int rx_pos;
100 bool rx_done;
101
102 bool swab;
103 unsigned int rxskip;
104
105 spinlock_t lock;
106
107 u32 spibrg; /* SPIBRG input clock */
108
109 struct completion done;
110};
111
112struct fsl_espi_cs {
113 u32 hw_mode;
114};
115
116static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
117{
118 return ioread32be(espi->reg_base + offset);
119}
120
121static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
122{
123 return ioread16be(espi->reg_base + offset);
124}
125
126static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
127{
128 return ioread8(espi->reg_base + offset);
129}
130
131static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
132 u32 val)
133{
134 iowrite32be(val, espi->reg_base + offset);
135}
136
137static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
138 u16 val)
139{
140 iowrite16be(val, espi->reg_base + offset);
141}
142
143static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
144 u8 val)
145{
146 iowrite8(val, espi->reg_base + offset);
147}
148
149static int fsl_espi_check_message(struct spi_message *m)
150{
151 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
152 struct spi_transfer *t, *first;
153
154 if (m->frame_length > SPCOM_TRANLEN_MAX) {
155 dev_err(espi->dev, "message too long, size is %u bytes\n",
156 m->frame_length);
157 return -EMSGSIZE;
158 }
159
160 first = list_first_entry(&m->transfers, struct spi_transfer,
161 transfer_list);
162
163 list_for_each_entry(t, &m->transfers, transfer_list) {
164 if (first->bits_per_word != t->bits_per_word ||
165 first->speed_hz != t->speed_hz) {
166 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
167 return -EINVAL;
168 }
169 }
170
171 /* ESPI supports MSB-first transfers for word size 8 / 16 only */
172 if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
173 first->bits_per_word != 16) {
174 dev_err(espi->dev,
175 "MSB-first transfer not supported for wordsize %u\n",
176 first->bits_per_word);
177 return -EINVAL;
178 }
179
180 return 0;
181}
182
183static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
184{
185 struct spi_transfer *t;
186 unsigned int i = 0, rxskip = 0;
187
188 /*
189 * prerequisites for ESPI rxskip mode:
190 * - message has two transfers
191 * - first transfer is a write and second is a read
192 *
193 * In addition the current low-level transfer mechanism requires
194 * that the rxskip bytes fit into the TX FIFO. Else the transfer
195 * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
196 * the TX FIFO isn't re-filled.
197 */
198 list_for_each_entry(t, &m->transfers, transfer_list) {
199 if (i == 0) {
200 if (!t->tx_buf || t->rx_buf ||
201 t->len > FSL_ESPI_FIFO_SIZE)
202 return 0;
203 rxskip = t->len;
204 } else if (i == 1) {
205 if (t->tx_buf || !t->rx_buf)
206 return 0;
207 }
208 i++;
209 }
210
211 return i == 2 ? rxskip : 0;
212}
213
214static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
215{
216 u32 tx_fifo_avail;
217 unsigned int tx_left;
218 const void *tx_buf;
219
220 /* if events is zero transfer has not started and tx fifo is empty */
221 tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
222start:
223 tx_left = espi->tx_t->len - espi->tx_pos;
224 tx_buf = espi->tx_t->tx_buf;
225 while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
226 if (tx_left >= 4) {
227 if (!tx_buf)
228 fsl_espi_write_reg(espi, ESPI_SPITF, 0);
229 else if (espi->swab)
230 fsl_espi_write_reg(espi, ESPI_SPITF,
231 swahb32p(tx_buf + espi->tx_pos));
232 else
233 fsl_espi_write_reg(espi, ESPI_SPITF,
234 *(u32 *)(tx_buf + espi->tx_pos));
235 espi->tx_pos += 4;
236 tx_left -= 4;
237 tx_fifo_avail -= 4;
238 } else if (tx_left >= 2 && tx_buf && espi->swab) {
239 fsl_espi_write_reg16(espi, ESPI_SPITF,
240 swab16p(tx_buf + espi->tx_pos));
241 espi->tx_pos += 2;
242 tx_left -= 2;
243 tx_fifo_avail -= 2;
244 } else {
245 if (!tx_buf)
246 fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
247 else
248 fsl_espi_write_reg8(espi, ESPI_SPITF,
249 *(u8 *)(tx_buf + espi->tx_pos));
250 espi->tx_pos += 1;
251 tx_left -= 1;
252 tx_fifo_avail -= 1;
253 }
254 }
255
256 if (!tx_left) {
257 /* Last transfer finished, in rxskip mode only one is needed */
258 if (list_is_last(&espi->tx_t->transfer_list,
259 espi->m_transfers) || espi->rxskip) {
260 espi->tx_done = true;
261 return;
262 }
263 espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
264 espi->tx_pos = 0;
265 /* continue with next transfer if tx fifo is not full */
266 if (tx_fifo_avail)
267 goto start;
268 }
269}
270
271static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
272{
273 u32 rx_fifo_avail = SPIE_RXCNT(events);
274 unsigned int rx_left;
275 void *rx_buf;
276
277start:
278 rx_left = espi->rx_t->len - espi->rx_pos;
279 rx_buf = espi->rx_t->rx_buf;
280 while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
281 if (rx_left >= 4) {
282 u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
283
284 if (rx_buf && espi->swab)
285 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
286 else if (rx_buf)
287 *(u32 *)(rx_buf + espi->rx_pos) = val;
288 espi->rx_pos += 4;
289 rx_left -= 4;
290 rx_fifo_avail -= 4;
291 } else if (rx_left >= 2 && rx_buf && espi->swab) {
292 u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
293
294 *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
295 espi->rx_pos += 2;
296 rx_left -= 2;
297 rx_fifo_avail -= 2;
298 } else {
299 u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
300
301 if (rx_buf)
302 *(u8 *)(rx_buf + espi->rx_pos) = val;
303 espi->rx_pos += 1;
304 rx_left -= 1;
305 rx_fifo_avail -= 1;
306 }
307 }
308
309 if (!rx_left) {
310 if (list_is_last(&espi->rx_t->transfer_list,
311 espi->m_transfers)) {
312 espi->rx_done = true;
313 return;
314 }
315 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
316 espi->rx_pos = 0;
317 /* continue with next transfer if rx fifo is not empty */
318 if (rx_fifo_avail)
319 goto start;
320 }
321}
322
323static void fsl_espi_setup_transfer(struct spi_device *spi,
324 struct spi_transfer *t)
325{
326 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
327 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
328 u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
329 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
330 u32 hw_mode_old = cs->hw_mode;
331
332 /* mask out bits we are going to set */
333 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
334
335 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
336
337 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
338
339 if (pm > 15) {
340 cs->hw_mode |= CSMODE_DIV16;
341 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
342 }
343
344 cs->hw_mode |= CSMODE_PM(pm);
345
346 /* don't write the mode register if the mode doesn't change */
347 if (cs->hw_mode != hw_mode_old)
348 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
349 cs->hw_mode);
350}
351
352static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
353{
354 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
355 unsigned int rx_len = t->len;
356 u32 mask, spcom;
357 int ret;
358
359 reinit_completion(&espi->done);
360
361 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
362 spcom = SPCOM_CS(spi->chip_select);
363 spcom |= SPCOM_TRANLEN(t->len - 1);
364
365 /* configure RXSKIP mode */
366 if (espi->rxskip) {
367 spcom |= SPCOM_RXSKIP(espi->rxskip);
368 rx_len = t->len - espi->rxskip;
369 if (t->rx_nbits == SPI_NBITS_DUAL)
370 spcom |= SPCOM_DO;
371 }
372
373 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
374
375 /* enable interrupts */
376 mask = SPIM_DON;
377 if (rx_len > FSL_ESPI_FIFO_SIZE)
378 mask |= SPIM_RXT;
379 fsl_espi_write_reg(espi, ESPI_SPIM, mask);
380
381 /* Prevent filling the fifo from getting interrupted */
382 spin_lock_irq(&espi->lock);
383 fsl_espi_fill_tx_fifo(espi, 0);
384 spin_unlock_irq(&espi->lock);
385
386 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
387 ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
388 if (ret == 0)
389 dev_err(espi->dev, "Transfer timed out!\n");
390
391 /* disable rx ints */
392 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
393
394 return ret == 0 ? -ETIMEDOUT : 0;
395}
396
397static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
398{
399 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
400 struct spi_device *spi = m->spi;
401 int ret;
402
403 /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
404 espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
405
406 espi->m_transfers = &m->transfers;
407 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
408 transfer_list);
409 espi->tx_pos = 0;
410 espi->tx_done = false;
411 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
412 transfer_list);
413 espi->rx_pos = 0;
414 espi->rx_done = false;
415
416 espi->rxskip = fsl_espi_check_rxskip_mode(m);
417 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
418 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
419 return -EINVAL;
420 }
421
422 /* In RXSKIP mode skip first transfer for reads */
423 if (espi->rxskip)
424 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
425
426 fsl_espi_setup_transfer(spi, trans);
427
428 ret = fsl_espi_bufs(spi, trans);
429
430 if (trans->delay_usecs)
431 udelay(trans->delay_usecs);
432
433 return ret;
434}
435
436static int fsl_espi_do_one_msg(struct spi_master *master,
437 struct spi_message *m)
438{
439 unsigned int delay_usecs = 0, rx_nbits = 0;
440 struct spi_transfer *t, trans = {};
441 int ret;
442
443 ret = fsl_espi_check_message(m);
444 if (ret)
445 goto out;
446
447 list_for_each_entry(t, &m->transfers, transfer_list) {
448 if (t->delay_usecs > delay_usecs)
449 delay_usecs = t->delay_usecs;
450 if (t->rx_nbits > rx_nbits)
451 rx_nbits = t->rx_nbits;
452 }
453
454 t = list_first_entry(&m->transfers, struct spi_transfer,
455 transfer_list);
456
457 trans.len = m->frame_length;
458 trans.speed_hz = t->speed_hz;
459 trans.bits_per_word = t->bits_per_word;
460 trans.delay_usecs = delay_usecs;
461 trans.rx_nbits = rx_nbits;
462
463 if (trans.len)
464 ret = fsl_espi_trans(m, &trans);
465
466 m->actual_length = ret ? 0 : trans.len;
467out:
468 if (m->status == -EINPROGRESS)
469 m->status = ret;
470
471 spi_finalize_current_message(master);
472
473 return ret;
474}
475
476static int fsl_espi_setup(struct spi_device *spi)
477{
478 struct fsl_espi *espi;
479 u32 loop_mode;
480 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
481
482 if (!cs) {
483 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
484 if (!cs)
485 return -ENOMEM;
486 spi_set_ctldata(spi, cs);
487 }
488
489 espi = spi_master_get_devdata(spi->master);
490
491 pm_runtime_get_sync(espi->dev);
492
493 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
494 /* mask out bits we are going to set */
495 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
496 | CSMODE_REV);
497
498 if (spi->mode & SPI_CPHA)
499 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
500 if (spi->mode & SPI_CPOL)
501 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
502 if (!(spi->mode & SPI_LSB_FIRST))
503 cs->hw_mode |= CSMODE_REV;
504
505 /* Handle the loop mode */
506 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
507 loop_mode &= ~SPMODE_LOOP;
508 if (spi->mode & SPI_LOOP)
509 loop_mode |= SPMODE_LOOP;
510 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
511
512 fsl_espi_setup_transfer(spi, NULL);
513
514 pm_runtime_mark_last_busy(espi->dev);
515 pm_runtime_put_autosuspend(espi->dev);
516
517 return 0;
518}
519
520static void fsl_espi_cleanup(struct spi_device *spi)
521{
522 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
523
524 kfree(cs);
525 spi_set_ctldata(spi, NULL);
526}
527
528static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
529{
530 if (!espi->rx_done)
531 fsl_espi_read_rx_fifo(espi, events);
532
533 if (!espi->tx_done)
534 fsl_espi_fill_tx_fifo(espi, events);
535
536 if (!espi->tx_done || !espi->rx_done)
537 return;
538
539 /* we're done, but check for errors before returning */
540 events = fsl_espi_read_reg(espi, ESPI_SPIE);
541
542 if (!(events & SPIE_DON))
543 dev_err(espi->dev,
544 "Transfer done but SPIE_DON isn't set!\n");
545
546 if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
547 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
548 dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
549 SPIE_RXCNT(events), SPIE_TXCNT(events));
550 }
551
552 complete(&espi->done);
553}
554
555static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
556{
557 struct fsl_espi *espi = context_data;
558 u32 events;
559
560 spin_lock(&espi->lock);
561
562 /* Get interrupt events(tx/rx) */
563 events = fsl_espi_read_reg(espi, ESPI_SPIE);
564 if (!events) {
565 spin_unlock(&espi->lock);
566 return IRQ_NONE;
567 }
568
569 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
570
571 fsl_espi_cpu_irq(espi, events);
572
573 /* Clear the events */
574 fsl_espi_write_reg(espi, ESPI_SPIE, events);
575
576 spin_unlock(&espi->lock);
577
578 return IRQ_HANDLED;
579}
580
581#ifdef CONFIG_PM
582static int fsl_espi_runtime_suspend(struct device *dev)
583{
584 struct spi_master *master = dev_get_drvdata(dev);
585 struct fsl_espi *espi = spi_master_get_devdata(master);
586 u32 regval;
587
588 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
589 regval &= ~SPMODE_ENABLE;
590 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
591
592 return 0;
593}
594
595static int fsl_espi_runtime_resume(struct device *dev)
596{
597 struct spi_master *master = dev_get_drvdata(dev);
598 struct fsl_espi *espi = spi_master_get_devdata(master);
599 u32 regval;
600
601 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
602 regval |= SPMODE_ENABLE;
603 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
604
605 return 0;
606}
607#endif
608
609static size_t fsl_espi_max_message_size(struct spi_device *spi)
610{
611 return SPCOM_TRANLEN_MAX;
612}
613
614static void fsl_espi_init_regs(struct device *dev, bool initial)
615{
616 struct spi_master *master = dev_get_drvdata(dev);
617 struct fsl_espi *espi = spi_master_get_devdata(master);
618 struct device_node *nc;
619 u32 csmode, cs, prop;
620 int ret;
621
622 /* SPI controller initializations */
623 fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
624 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
625 fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
626 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
627
628 /* Init eSPI CS mode register */
629 for_each_available_child_of_node(master->dev.of_node, nc) {
630 /* get chip select */
631 ret = of_property_read_u32(nc, "reg", &cs);
632 if (ret || cs >= master->num_chipselect)
633 continue;
634
635 csmode = CSMODE_INIT_VAL;
636
637 /* check if CSBEF is set in device tree */
638 ret = of_property_read_u32(nc, "fsl,csbef", &prop);
639 if (!ret) {
640 csmode &= ~(CSMODE_BEF(0xf));
641 csmode |= CSMODE_BEF(prop);
642 }
643
644 /* check if CSAFT is set in device tree */
645 ret = of_property_read_u32(nc, "fsl,csaft", &prop);
646 if (!ret) {
647 csmode &= ~(CSMODE_AFT(0xf));
648 csmode |= CSMODE_AFT(prop);
649 }
650
651 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
652
653 if (initial)
654 dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
655 }
656
657 /* Enable SPI interface */
658 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
659}
660
661static int fsl_espi_probe(struct device *dev, struct resource *mem,
662 unsigned int irq, unsigned int num_cs)
663{
664 struct spi_master *master;
665 struct fsl_espi *espi;
666 int ret;
667
668 master = spi_alloc_master(dev, sizeof(struct fsl_espi));
669 if (!master)
670 return -ENOMEM;
671
672 dev_set_drvdata(dev, master);
673
674 master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
675 SPI_LSB_FIRST | SPI_LOOP;
676 master->dev.of_node = dev->of_node;
677 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
678 master->setup = fsl_espi_setup;
679 master->cleanup = fsl_espi_cleanup;
680 master->transfer_one_message = fsl_espi_do_one_msg;
681 master->auto_runtime_pm = true;
682 master->max_message_size = fsl_espi_max_message_size;
683 master->num_chipselect = num_cs;
684
685 espi = spi_master_get_devdata(master);
686 spin_lock_init(&espi->lock);
687
688 espi->dev = dev;
689 espi->spibrg = fsl_get_sys_freq();
690 if (espi->spibrg == -1) {
691 dev_err(dev, "Can't get sys frequency!\n");
692 ret = -EINVAL;
693 goto err_probe;
694 }
695 /* determined by clock divider fields DIV16/PM in register SPMODEx */
696 master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
697 master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
698
699 init_completion(&espi->done);
700
701 espi->reg_base = devm_ioremap_resource(dev, mem);
702 if (IS_ERR(espi->reg_base)) {
703 ret = PTR_ERR(espi->reg_base);
704 goto err_probe;
705 }
706
707 /* Register for SPI Interrupt */
708 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
709 if (ret)
710 goto err_probe;
711
712 fsl_espi_init_regs(dev, true);
713
714 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
715 pm_runtime_use_autosuspend(dev);
716 pm_runtime_set_active(dev);
717 pm_runtime_enable(dev);
718 pm_runtime_get_sync(dev);
719
720 ret = devm_spi_register_master(dev, master);
721 if (ret < 0)
722 goto err_pm;
723
724 dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq);
725
726 pm_runtime_mark_last_busy(dev);
727 pm_runtime_put_autosuspend(dev);
728
729 return 0;
730
731err_pm:
732 pm_runtime_put_noidle(dev);
733 pm_runtime_disable(dev);
734 pm_runtime_set_suspended(dev);
735err_probe:
736 spi_master_put(master);
737 return ret;
738}
739
740static int of_fsl_espi_get_chipselects(struct device *dev)
741{
742 struct device_node *np = dev->of_node;
743 u32 num_cs;
744 int ret;
745
746 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
747 if (ret) {
748 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
749 return 0;
750 }
751
752 return num_cs;
753}
754
755static int of_fsl_espi_probe(struct platform_device *ofdev)
756{
757 struct device *dev = &ofdev->dev;
758 struct device_node *np = ofdev->dev.of_node;
759 struct resource mem;
760 unsigned int irq, num_cs;
761 int ret;
762
763 if (of_property_read_bool(np, "mode")) {
764 dev_err(dev, "mode property is not supported on ESPI!\n");
765 return -EINVAL;
766 }
767
768 num_cs = of_fsl_espi_get_chipselects(dev);
769 if (!num_cs)
770 return -EINVAL;
771
772 ret = of_address_to_resource(np, 0, &mem);
773 if (ret)
774 return ret;
775
776 irq = irq_of_parse_and_map(np, 0);
777 if (!irq)
778 return -EINVAL;
779
780 return fsl_espi_probe(dev, &mem, irq, num_cs);
781}
782
783static int of_fsl_espi_remove(struct platform_device *dev)
784{
785 pm_runtime_disable(&dev->dev);
786
787 return 0;
788}
789
790#ifdef CONFIG_PM_SLEEP
791static int of_fsl_espi_suspend(struct device *dev)
792{
793 struct spi_master *master = dev_get_drvdata(dev);
794 int ret;
795
796 ret = spi_master_suspend(master);
797 if (ret)
798 return ret;
799
800 return pm_runtime_force_suspend(dev);
801}
802
803static int of_fsl_espi_resume(struct device *dev)
804{
805 struct spi_master *master = dev_get_drvdata(dev);
806 int ret;
807
808 fsl_espi_init_regs(dev, false);
809
810 ret = pm_runtime_force_resume(dev);
811 if (ret < 0)
812 return ret;
813
814 return spi_master_resume(master);
815}
816#endif /* CONFIG_PM_SLEEP */
817
818static const struct dev_pm_ops espi_pm = {
819 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
820 fsl_espi_runtime_resume, NULL)
821 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
822};
823
824static const struct of_device_id of_fsl_espi_match[] = {
825 { .compatible = "fsl,mpc8536-espi" },
826 {}
827};
828MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
829
830static struct platform_driver fsl_espi_driver = {
831 .driver = {
832 .name = "fsl_espi",
833 .of_match_table = of_fsl_espi_match,
834 .pm = &espi_pm,
835 },
836 .probe = of_fsl_espi_probe,
837 .remove = of_fsl_espi_remove,
838};
839module_platform_driver(fsl_espi_driver);
840
841MODULE_AUTHOR("Mingkai Hu");
842MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
843MODULE_LICENSE("GPL");