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1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/of_spi.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <sysdev/fsl_soc.h>
24
25#include "spi-fsl-lib.h"
26
27/* eSPI Controller registers */
28struct fsl_espi_reg {
29 __be32 mode; /* 0x000 - eSPI mode register */
30 __be32 event; /* 0x004 - eSPI event register */
31 __be32 mask; /* 0x008 - eSPI mask register */
32 __be32 command; /* 0x00c - eSPI command register */
33 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
34 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
35 u8 res[8]; /* 0x018 - 0x01c reserved */
36 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
37};
38
39struct fsl_espi_transfer {
40 const void *tx_buf;
41 void *rx_buf;
42 unsigned len;
43 unsigned n_tx;
44 unsigned n_rx;
45 unsigned actual_length;
46 int status;
47};
48
49/* eSPI Controller mode register definitions */
50#define SPMODE_ENABLE (1 << 31)
51#define SPMODE_LOOP (1 << 30)
52#define SPMODE_TXTHR(x) ((x) << 8)
53#define SPMODE_RXTHR(x) ((x) << 0)
54
55/* eSPI Controller CS mode register definitions */
56#define CSMODE_CI_INACTIVEHIGH (1 << 31)
57#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
58#define CSMODE_REV (1 << 29)
59#define CSMODE_DIV16 (1 << 28)
60#define CSMODE_PM(x) ((x) << 24)
61#define CSMODE_POL_1 (1 << 20)
62#define CSMODE_LEN(x) ((x) << 16)
63#define CSMODE_BEF(x) ((x) << 12)
64#define CSMODE_AFT(x) ((x) << 8)
65#define CSMODE_CG(x) ((x) << 3)
66
67/* Default mode/csmode for eSPI controller */
68#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
69#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
70 | CSMODE_AFT(0) | CSMODE_CG(1))
71
72/* SPIE register values */
73#define SPIE_NE 0x00000200 /* Not empty */
74#define SPIE_NF 0x00000100 /* Not full */
75
76/* SPIM register values */
77#define SPIM_NE 0x00000200 /* Not empty */
78#define SPIM_NF 0x00000100 /* Not full */
79#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
80#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
81
82/* SPCOM register values */
83#define SPCOM_CS(x) ((x) << 30)
84#define SPCOM_TRANLEN(x) ((x) << 0)
85#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
86
87static void fsl_espi_change_mode(struct spi_device *spi)
88{
89 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
90 struct spi_mpc8xxx_cs *cs = spi->controller_state;
91 struct fsl_espi_reg *reg_base = mspi->reg_base;
92 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
93 __be32 __iomem *espi_mode = ®_base->mode;
94 u32 tmp;
95 unsigned long flags;
96
97 /* Turn off IRQs locally to minimize time that SPI is disabled. */
98 local_irq_save(flags);
99
100 /* Turn off SPI unit prior changing mode */
101 tmp = mpc8xxx_spi_read_reg(espi_mode);
102 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
103 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
104 mpc8xxx_spi_write_reg(espi_mode, tmp);
105
106 local_irq_restore(flags);
107}
108
109static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
110{
111 u32 data;
112 u16 data_h;
113 u16 data_l;
114 const u32 *tx = mpc8xxx_spi->tx;
115
116 if (!tx)
117 return 0;
118
119 data = *tx++ << mpc8xxx_spi->tx_shift;
120 data_l = data & 0xffff;
121 data_h = (data >> 16) & 0xffff;
122 swab16s(&data_l);
123 swab16s(&data_h);
124 data = data_h | data_l;
125
126 mpc8xxx_spi->tx = tx;
127 return data;
128}
129
130static int fsl_espi_setup_transfer(struct spi_device *spi,
131 struct spi_transfer *t)
132{
133 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
134 int bits_per_word = 0;
135 u8 pm;
136 u32 hz = 0;
137 struct spi_mpc8xxx_cs *cs = spi->controller_state;
138
139 if (t) {
140 bits_per_word = t->bits_per_word;
141 hz = t->speed_hz;
142 }
143
144 /* spi_transfer level calls that work per-word */
145 if (!bits_per_word)
146 bits_per_word = spi->bits_per_word;
147
148 /* Make sure its a bit width we support [4..16] */
149 if ((bits_per_word < 4) || (bits_per_word > 16))
150 return -EINVAL;
151
152 if (!hz)
153 hz = spi->max_speed_hz;
154
155 cs->rx_shift = 0;
156 cs->tx_shift = 0;
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159 if (bits_per_word <= 8) {
160 cs->rx_shift = 8 - bits_per_word;
161 } else if (bits_per_word <= 16) {
162 cs->rx_shift = 16 - bits_per_word;
163 if (spi->mode & SPI_LSB_FIRST)
164 cs->get_tx = fsl_espi_tx_buf_lsb;
165 } else {
166 return -EINVAL;
167 }
168
169 mpc8xxx_spi->rx_shift = cs->rx_shift;
170 mpc8xxx_spi->tx_shift = cs->tx_shift;
171 mpc8xxx_spi->get_rx = cs->get_rx;
172 mpc8xxx_spi->get_tx = cs->get_tx;
173
174 bits_per_word = bits_per_word - 1;
175
176 /* mask out bits we are going to set */
177 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
178
179 cs->hw_mode |= CSMODE_LEN(bits_per_word);
180
181 if ((mpc8xxx_spi->spibrg / hz) > 64) {
182 cs->hw_mode |= CSMODE_DIV16;
183 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
184
185 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
186 "Will use %d Hz instead.\n", dev_name(&spi->dev),
187 hz, mpc8xxx_spi->spibrg / 1024);
188 if (pm > 16)
189 pm = 16;
190 } else {
191 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
192 }
193 if (pm)
194 pm--;
195
196 cs->hw_mode |= CSMODE_PM(pm);
197
198 fsl_espi_change_mode(spi);
199 return 0;
200}
201
202static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
203 unsigned int len)
204{
205 u32 word;
206 struct fsl_espi_reg *reg_base = mspi->reg_base;
207
208 mspi->count = len;
209
210 /* enable rx ints */
211 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
212
213 /* transmit word */
214 word = mspi->get_tx(mspi);
215 mpc8xxx_spi_write_reg(®_base->transmit, word);
216
217 return 0;
218}
219
220static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
221{
222 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
224 unsigned int len = t->len;
225 u8 bits_per_word;
226 int ret;
227
228 bits_per_word = spi->bits_per_word;
229 if (t->bits_per_word)
230 bits_per_word = t->bits_per_word;
231
232 mpc8xxx_spi->len = t->len;
233 len = roundup(len, 4) / 4;
234
235 mpc8xxx_spi->tx = t->tx_buf;
236 mpc8xxx_spi->rx = t->rx_buf;
237
238 INIT_COMPLETION(mpc8xxx_spi->done);
239
240 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
241 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
242 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
243 " beyond the SPCOM[TRANLEN] field\n", t->len);
244 return -EINVAL;
245 }
246 mpc8xxx_spi_write_reg(®_base->command,
247 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
248
249 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
250 if (ret)
251 return ret;
252
253 wait_for_completion(&mpc8xxx_spi->done);
254
255 /* disable rx ints */
256 mpc8xxx_spi_write_reg(®_base->mask, 0);
257
258 return mpc8xxx_spi->count;
259}
260
261static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
262{
263 if (cmd) {
264 cmd[1] = (u8)(addr >> 16);
265 cmd[2] = (u8)(addr >> 8);
266 cmd[3] = (u8)(addr >> 0);
267 }
268}
269
270static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
271{
272 if (cmd)
273 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
274
275 return 0;
276}
277
278static void fsl_espi_do_trans(struct spi_message *m,
279 struct fsl_espi_transfer *tr)
280{
281 struct spi_device *spi = m->spi;
282 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
283 struct fsl_espi_transfer *espi_trans = tr;
284 struct spi_message message;
285 struct spi_transfer *t, *first, trans;
286 int status = 0;
287
288 spi_message_init(&message);
289 memset(&trans, 0, sizeof(trans));
290
291 first = list_first_entry(&m->transfers, struct spi_transfer,
292 transfer_list);
293 list_for_each_entry(t, &m->transfers, transfer_list) {
294 if ((first->bits_per_word != t->bits_per_word) ||
295 (first->speed_hz != t->speed_hz)) {
296 espi_trans->status = -EINVAL;
297 dev_err(mspi->dev, "bits_per_word/speed_hz should be"
298 " same for the same SPI transfer\n");
299 return;
300 }
301
302 trans.speed_hz = t->speed_hz;
303 trans.bits_per_word = t->bits_per_word;
304 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
305 }
306
307 trans.len = espi_trans->len;
308 trans.tx_buf = espi_trans->tx_buf;
309 trans.rx_buf = espi_trans->rx_buf;
310 spi_message_add_tail(&trans, &message);
311
312 list_for_each_entry(t, &message.transfers, transfer_list) {
313 if (t->bits_per_word || t->speed_hz) {
314 status = -EINVAL;
315
316 status = fsl_espi_setup_transfer(spi, t);
317 if (status < 0)
318 break;
319 }
320
321 if (t->len)
322 status = fsl_espi_bufs(spi, t);
323
324 if (status) {
325 status = -EMSGSIZE;
326 break;
327 }
328
329 if (t->delay_usecs)
330 udelay(t->delay_usecs);
331 }
332
333 espi_trans->status = status;
334 fsl_espi_setup_transfer(spi, NULL);
335}
336
337static void fsl_espi_cmd_trans(struct spi_message *m,
338 struct fsl_espi_transfer *trans, u8 *rx_buff)
339{
340 struct spi_transfer *t;
341 u8 *local_buf;
342 int i = 0;
343 struct fsl_espi_transfer *espi_trans = trans;
344
345 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
346 if (!local_buf) {
347 espi_trans->status = -ENOMEM;
348 return;
349 }
350
351 list_for_each_entry(t, &m->transfers, transfer_list) {
352 if (t->tx_buf) {
353 memcpy(local_buf + i, t->tx_buf, t->len);
354 i += t->len;
355 }
356 }
357
358 espi_trans->tx_buf = local_buf;
359 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
360 fsl_espi_do_trans(m, espi_trans);
361
362 espi_trans->actual_length = espi_trans->len;
363 kfree(local_buf);
364}
365
366static void fsl_espi_rw_trans(struct spi_message *m,
367 struct fsl_espi_transfer *trans, u8 *rx_buff)
368{
369 struct fsl_espi_transfer *espi_trans = trans;
370 unsigned int n_tx = espi_trans->n_tx;
371 unsigned int n_rx = espi_trans->n_rx;
372 struct spi_transfer *t;
373 u8 *local_buf;
374 u8 *rx_buf = rx_buff;
375 unsigned int trans_len;
376 unsigned int addr;
377 int i, pos, loop;
378
379 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
380 if (!local_buf) {
381 espi_trans->status = -ENOMEM;
382 return;
383 }
384
385 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
386 trans_len = n_rx - pos;
387 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
388 trans_len = SPCOM_TRANLEN_MAX - n_tx;
389
390 i = 0;
391 list_for_each_entry(t, &m->transfers, transfer_list) {
392 if (t->tx_buf) {
393 memcpy(local_buf + i, t->tx_buf, t->len);
394 i += t->len;
395 }
396 }
397
398 if (pos > 0) {
399 addr = fsl_espi_cmd2addr(local_buf);
400 addr += pos;
401 fsl_espi_addr2cmd(addr, local_buf);
402 }
403
404 espi_trans->n_tx = n_tx;
405 espi_trans->n_rx = trans_len;
406 espi_trans->len = trans_len + n_tx;
407 espi_trans->tx_buf = local_buf;
408 espi_trans->rx_buf = local_buf + n_tx;
409 fsl_espi_do_trans(m, espi_trans);
410
411 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
412
413 if (loop > 0)
414 espi_trans->actual_length += espi_trans->len - n_tx;
415 else
416 espi_trans->actual_length += espi_trans->len;
417 }
418
419 kfree(local_buf);
420}
421
422static void fsl_espi_do_one_msg(struct spi_message *m)
423{
424 struct spi_transfer *t;
425 u8 *rx_buf = NULL;
426 unsigned int n_tx = 0;
427 unsigned int n_rx = 0;
428 struct fsl_espi_transfer espi_trans;
429
430 list_for_each_entry(t, &m->transfers, transfer_list) {
431 if (t->tx_buf)
432 n_tx += t->len;
433 if (t->rx_buf) {
434 n_rx += t->len;
435 rx_buf = t->rx_buf;
436 }
437 }
438
439 espi_trans.n_tx = n_tx;
440 espi_trans.n_rx = n_rx;
441 espi_trans.len = n_tx + n_rx;
442 espi_trans.actual_length = 0;
443 espi_trans.status = 0;
444
445 if (!rx_buf)
446 fsl_espi_cmd_trans(m, &espi_trans, NULL);
447 else
448 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
449
450 m->actual_length = espi_trans.actual_length;
451 m->status = espi_trans.status;
452 m->complete(m->context);
453}
454
455static int fsl_espi_setup(struct spi_device *spi)
456{
457 struct mpc8xxx_spi *mpc8xxx_spi;
458 struct fsl_espi_reg *reg_base;
459 int retval;
460 u32 hw_mode;
461 u32 loop_mode;
462 struct spi_mpc8xxx_cs *cs = spi->controller_state;
463
464 if (!spi->max_speed_hz)
465 return -EINVAL;
466
467 if (!cs) {
468 cs = kzalloc(sizeof *cs, GFP_KERNEL);
469 if (!cs)
470 return -ENOMEM;
471 spi->controller_state = cs;
472 }
473
474 mpc8xxx_spi = spi_master_get_devdata(spi->master);
475 reg_base = mpc8xxx_spi->reg_base;
476
477 hw_mode = cs->hw_mode; /* Save original settings */
478 cs->hw_mode = mpc8xxx_spi_read_reg(
479 ®_base->csmode[spi->chip_select]);
480 /* mask out bits we are going to set */
481 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
482 | CSMODE_REV);
483
484 if (spi->mode & SPI_CPHA)
485 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
486 if (spi->mode & SPI_CPOL)
487 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
488 if (!(spi->mode & SPI_LSB_FIRST))
489 cs->hw_mode |= CSMODE_REV;
490
491 /* Handle the loop mode */
492 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
493 loop_mode &= ~SPMODE_LOOP;
494 if (spi->mode & SPI_LOOP)
495 loop_mode |= SPMODE_LOOP;
496 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
497
498 retval = fsl_espi_setup_transfer(spi, NULL);
499 if (retval < 0) {
500 cs->hw_mode = hw_mode; /* Restore settings */
501 return retval;
502 }
503 return 0;
504}
505
506void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
507{
508 struct fsl_espi_reg *reg_base = mspi->reg_base;
509
510 /* We need handle RX first */
511 if (events & SPIE_NE) {
512 u32 rx_data, tmp;
513 u8 rx_data_8;
514
515 /* Spin until RX is done */
516 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
517 cpu_relax();
518 events = mpc8xxx_spi_read_reg(®_base->event);
519 }
520
521 if (mspi->len >= 4) {
522 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
523 } else {
524 tmp = mspi->len;
525 rx_data = 0;
526 while (tmp--) {
527 rx_data_8 = in_8((u8 *)®_base->receive);
528 rx_data |= (rx_data_8 << (tmp * 8));
529 }
530
531 rx_data <<= (4 - mspi->len) * 8;
532 }
533
534 mspi->len -= 4;
535
536 if (mspi->rx)
537 mspi->get_rx(rx_data, mspi);
538 }
539
540 if (!(events & SPIE_NF)) {
541 int ret;
542
543 /* spin until TX is done */
544 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
545 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
546 if (!ret) {
547 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
548 return;
549 }
550 }
551
552 /* Clear the events */
553 mpc8xxx_spi_write_reg(®_base->event, events);
554
555 mspi->count -= 1;
556 if (mspi->count) {
557 u32 word = mspi->get_tx(mspi);
558
559 mpc8xxx_spi_write_reg(®_base->transmit, word);
560 } else {
561 complete(&mspi->done);
562 }
563}
564
565static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
566{
567 struct mpc8xxx_spi *mspi = context_data;
568 struct fsl_espi_reg *reg_base = mspi->reg_base;
569 irqreturn_t ret = IRQ_NONE;
570 u32 events;
571
572 /* Get interrupt events(tx/rx) */
573 events = mpc8xxx_spi_read_reg(®_base->event);
574 if (events)
575 ret = IRQ_HANDLED;
576
577 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
578
579 fsl_espi_cpu_irq(mspi, events);
580
581 return ret;
582}
583
584static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
585{
586 iounmap(mspi->reg_base);
587}
588
589static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
590 struct resource *mem, unsigned int irq)
591{
592 struct fsl_spi_platform_data *pdata = dev->platform_data;
593 struct spi_master *master;
594 struct mpc8xxx_spi *mpc8xxx_spi;
595 struct fsl_espi_reg *reg_base;
596 u32 regval;
597 int i, ret = 0;
598
599 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
600 if (!master) {
601 ret = -ENOMEM;
602 goto err;
603 }
604
605 dev_set_drvdata(dev, master);
606
607 ret = mpc8xxx_spi_probe(dev, mem, irq);
608 if (ret)
609 goto err_probe;
610
611 master->setup = fsl_espi_setup;
612
613 mpc8xxx_spi = spi_master_get_devdata(master);
614 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
615 mpc8xxx_spi->spi_remove = fsl_espi_remove;
616
617 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
618 if (!mpc8xxx_spi->reg_base) {
619 ret = -ENOMEM;
620 goto err_probe;
621 }
622
623 reg_base = mpc8xxx_spi->reg_base;
624
625 /* Register for SPI Interrupt */
626 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
627 0, "fsl_espi", mpc8xxx_spi);
628 if (ret)
629 goto free_irq;
630
631 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
632 mpc8xxx_spi->rx_shift = 16;
633 mpc8xxx_spi->tx_shift = 24;
634 }
635
636 /* SPI controller initializations */
637 mpc8xxx_spi_write_reg(®_base->mode, 0);
638 mpc8xxx_spi_write_reg(®_base->mask, 0);
639 mpc8xxx_spi_write_reg(®_base->command, 0);
640 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
641
642 /* Init eSPI CS mode register */
643 for (i = 0; i < pdata->max_chipselect; i++)
644 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
645
646 /* Enable SPI interface */
647 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
648
649 mpc8xxx_spi_write_reg(®_base->mode, regval);
650
651 ret = spi_register_master(master);
652 if (ret < 0)
653 goto unreg_master;
654
655 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
656
657 return master;
658
659unreg_master:
660 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
661free_irq:
662 iounmap(mpc8xxx_spi->reg_base);
663err_probe:
664 spi_master_put(master);
665err:
666 return ERR_PTR(ret);
667}
668
669static int of_fsl_espi_get_chipselects(struct device *dev)
670{
671 struct device_node *np = dev->of_node;
672 struct fsl_spi_platform_data *pdata = dev->platform_data;
673 const u32 *prop;
674 int len;
675
676 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
677 if (!prop || len < sizeof(*prop)) {
678 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
679 return -EINVAL;
680 }
681
682 pdata->max_chipselect = *prop;
683 pdata->cs_control = NULL;
684
685 return 0;
686}
687
688static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
689{
690 struct device *dev = &ofdev->dev;
691 struct device_node *np = ofdev->dev.of_node;
692 struct spi_master *master;
693 struct resource mem;
694 struct resource irq;
695 int ret = -ENOMEM;
696
697 ret = of_mpc8xxx_spi_probe(ofdev);
698 if (ret)
699 return ret;
700
701 ret = of_fsl_espi_get_chipselects(dev);
702 if (ret)
703 goto err;
704
705 ret = of_address_to_resource(np, 0, &mem);
706 if (ret)
707 goto err;
708
709 ret = of_irq_to_resource(np, 0, &irq);
710 if (!ret) {
711 ret = -EINVAL;
712 goto err;
713 }
714
715 master = fsl_espi_probe(dev, &mem, irq.start);
716 if (IS_ERR(master)) {
717 ret = PTR_ERR(master);
718 goto err;
719 }
720
721 return 0;
722
723err:
724 return ret;
725}
726
727static int __devexit of_fsl_espi_remove(struct platform_device *dev)
728{
729 return mpc8xxx_spi_remove(&dev->dev);
730}
731
732static const struct of_device_id of_fsl_espi_match[] = {
733 { .compatible = "fsl,mpc8536-espi" },
734 {}
735};
736MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
737
738static struct platform_driver fsl_espi_driver = {
739 .driver = {
740 .name = "fsl_espi",
741 .owner = THIS_MODULE,
742 .of_match_table = of_fsl_espi_match,
743 },
744 .probe = of_fsl_espi_probe,
745 .remove = __devexit_p(of_fsl_espi_remove),
746};
747
748static int __init fsl_espi_init(void)
749{
750 return platform_driver_register(&fsl_espi_driver);
751}
752module_init(fsl_espi_init);
753
754static void __exit fsl_espi_exit(void)
755{
756 platform_driver_unregister(&fsl_espi_driver);
757}
758module_exit(fsl_espi_exit);
759
760MODULE_AUTHOR("Mingkai Hu");
761MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
762MODULE_LICENSE("GPL");
1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/interrupt.h>
21#include <linux/err.h>
22#include <sysdev/fsl_soc.h>
23
24#include "spi-fsl-lib.h"
25
26/* eSPI Controller registers */
27struct fsl_espi_reg {
28 __be32 mode; /* 0x000 - eSPI mode register */
29 __be32 event; /* 0x004 - eSPI event register */
30 __be32 mask; /* 0x008 - eSPI mask register */
31 __be32 command; /* 0x00c - eSPI command register */
32 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
33 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
34 u8 res[8]; /* 0x018 - 0x01c reserved */
35 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
36};
37
38struct fsl_espi_transfer {
39 const void *tx_buf;
40 void *rx_buf;
41 unsigned len;
42 unsigned n_tx;
43 unsigned n_rx;
44 unsigned actual_length;
45 int status;
46};
47
48/* eSPI Controller mode register definitions */
49#define SPMODE_ENABLE (1 << 31)
50#define SPMODE_LOOP (1 << 30)
51#define SPMODE_TXTHR(x) ((x) << 8)
52#define SPMODE_RXTHR(x) ((x) << 0)
53
54/* eSPI Controller CS mode register definitions */
55#define CSMODE_CI_INACTIVEHIGH (1 << 31)
56#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
57#define CSMODE_REV (1 << 29)
58#define CSMODE_DIV16 (1 << 28)
59#define CSMODE_PM(x) ((x) << 24)
60#define CSMODE_POL_1 (1 << 20)
61#define CSMODE_LEN(x) ((x) << 16)
62#define CSMODE_BEF(x) ((x) << 12)
63#define CSMODE_AFT(x) ((x) << 8)
64#define CSMODE_CG(x) ((x) << 3)
65
66/* Default mode/csmode for eSPI controller */
67#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
68#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
69 | CSMODE_AFT(0) | CSMODE_CG(1))
70
71/* SPIE register values */
72#define SPIE_NE 0x00000200 /* Not empty */
73#define SPIE_NF 0x00000100 /* Not full */
74
75/* SPIM register values */
76#define SPIM_NE 0x00000200 /* Not empty */
77#define SPIM_NF 0x00000100 /* Not full */
78#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
79#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
80
81/* SPCOM register values */
82#define SPCOM_CS(x) ((x) << 30)
83#define SPCOM_TRANLEN(x) ((x) << 0)
84#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
85
86static void fsl_espi_change_mode(struct spi_device *spi)
87{
88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
89 struct spi_mpc8xxx_cs *cs = spi->controller_state;
90 struct fsl_espi_reg *reg_base = mspi->reg_base;
91 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
92 __be32 __iomem *espi_mode = ®_base->mode;
93 u32 tmp;
94 unsigned long flags;
95
96 /* Turn off IRQs locally to minimize time that SPI is disabled. */
97 local_irq_save(flags);
98
99 /* Turn off SPI unit prior changing mode */
100 tmp = mpc8xxx_spi_read_reg(espi_mode);
101 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
102 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp);
104
105 local_irq_restore(flags);
106}
107
108static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
109{
110 u32 data;
111 u16 data_h;
112 u16 data_l;
113 const u32 *tx = mpc8xxx_spi->tx;
114
115 if (!tx)
116 return 0;
117
118 data = *tx++ << mpc8xxx_spi->tx_shift;
119 data_l = data & 0xffff;
120 data_h = (data >> 16) & 0xffff;
121 swab16s(&data_l);
122 swab16s(&data_h);
123 data = data_h | data_l;
124
125 mpc8xxx_spi->tx = tx;
126 return data;
127}
128
129static int fsl_espi_setup_transfer(struct spi_device *spi,
130 struct spi_transfer *t)
131{
132 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
133 int bits_per_word = 0;
134 u8 pm;
135 u32 hz = 0;
136 struct spi_mpc8xxx_cs *cs = spi->controller_state;
137
138 if (t) {
139 bits_per_word = t->bits_per_word;
140 hz = t->speed_hz;
141 }
142
143 /* spi_transfer level calls that work per-word */
144 if (!bits_per_word)
145 bits_per_word = spi->bits_per_word;
146
147 /* Make sure its a bit width we support [4..16] */
148 if ((bits_per_word < 4) || (bits_per_word > 16))
149 return -EINVAL;
150
151 if (!hz)
152 hz = spi->max_speed_hz;
153
154 cs->rx_shift = 0;
155 cs->tx_shift = 0;
156 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
157 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
158 if (bits_per_word <= 8) {
159 cs->rx_shift = 8 - bits_per_word;
160 } else if (bits_per_word <= 16) {
161 cs->rx_shift = 16 - bits_per_word;
162 if (spi->mode & SPI_LSB_FIRST)
163 cs->get_tx = fsl_espi_tx_buf_lsb;
164 } else {
165 return -EINVAL;
166 }
167
168 mpc8xxx_spi->rx_shift = cs->rx_shift;
169 mpc8xxx_spi->tx_shift = cs->tx_shift;
170 mpc8xxx_spi->get_rx = cs->get_rx;
171 mpc8xxx_spi->get_tx = cs->get_tx;
172
173 bits_per_word = bits_per_word - 1;
174
175 /* mask out bits we are going to set */
176 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
177
178 cs->hw_mode |= CSMODE_LEN(bits_per_word);
179
180 if ((mpc8xxx_spi->spibrg / hz) > 64) {
181 cs->hw_mode |= CSMODE_DIV16;
182 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
183
184 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
185 "Will use %d Hz instead.\n", dev_name(&spi->dev),
186 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
187 if (pm > 33)
188 pm = 33;
189 } else {
190 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
191 }
192 if (pm)
193 pm--;
194 if (pm < 2)
195 pm = 2;
196
197 cs->hw_mode |= CSMODE_PM(pm);
198
199 fsl_espi_change_mode(spi);
200 return 0;
201}
202
203static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
204 unsigned int len)
205{
206 u32 word;
207 struct fsl_espi_reg *reg_base = mspi->reg_base;
208
209 mspi->count = len;
210
211 /* enable rx ints */
212 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
213
214 /* transmit word */
215 word = mspi->get_tx(mspi);
216 mpc8xxx_spi_write_reg(®_base->transmit, word);
217
218 return 0;
219}
220
221static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
222{
223 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
224 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
225 unsigned int len = t->len;
226 u8 bits_per_word;
227 int ret;
228
229 bits_per_word = spi->bits_per_word;
230 if (t->bits_per_word)
231 bits_per_word = t->bits_per_word;
232
233 mpc8xxx_spi->len = t->len;
234 len = roundup(len, 4) / 4;
235
236 mpc8xxx_spi->tx = t->tx_buf;
237 mpc8xxx_spi->rx = t->rx_buf;
238
239 INIT_COMPLETION(mpc8xxx_spi->done);
240
241 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
242 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
243 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
244 " beyond the SPCOM[TRANLEN] field\n", t->len);
245 return -EINVAL;
246 }
247 mpc8xxx_spi_write_reg(®_base->command,
248 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
249
250 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
251 if (ret)
252 return ret;
253
254 wait_for_completion(&mpc8xxx_spi->done);
255
256 /* disable rx ints */
257 mpc8xxx_spi_write_reg(®_base->mask, 0);
258
259 return mpc8xxx_spi->count;
260}
261
262static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
263{
264 if (cmd) {
265 cmd[1] = (u8)(addr >> 16);
266 cmd[2] = (u8)(addr >> 8);
267 cmd[3] = (u8)(addr >> 0);
268 }
269}
270
271static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
272{
273 if (cmd)
274 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
275
276 return 0;
277}
278
279static void fsl_espi_do_trans(struct spi_message *m,
280 struct fsl_espi_transfer *tr)
281{
282 struct spi_device *spi = m->spi;
283 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
284 struct fsl_espi_transfer *espi_trans = tr;
285 struct spi_message message;
286 struct spi_transfer *t, *first, trans;
287 int status = 0;
288
289 spi_message_init(&message);
290 memset(&trans, 0, sizeof(trans));
291
292 first = list_first_entry(&m->transfers, struct spi_transfer,
293 transfer_list);
294 list_for_each_entry(t, &m->transfers, transfer_list) {
295 if ((first->bits_per_word != t->bits_per_word) ||
296 (first->speed_hz != t->speed_hz)) {
297 espi_trans->status = -EINVAL;
298 dev_err(mspi->dev, "bits_per_word/speed_hz should be"
299 " same for the same SPI transfer\n");
300 return;
301 }
302
303 trans.speed_hz = t->speed_hz;
304 trans.bits_per_word = t->bits_per_word;
305 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
306 }
307
308 trans.len = espi_trans->len;
309 trans.tx_buf = espi_trans->tx_buf;
310 trans.rx_buf = espi_trans->rx_buf;
311 spi_message_add_tail(&trans, &message);
312
313 list_for_each_entry(t, &message.transfers, transfer_list) {
314 if (t->bits_per_word || t->speed_hz) {
315 status = -EINVAL;
316
317 status = fsl_espi_setup_transfer(spi, t);
318 if (status < 0)
319 break;
320 }
321
322 if (t->len)
323 status = fsl_espi_bufs(spi, t);
324
325 if (status) {
326 status = -EMSGSIZE;
327 break;
328 }
329
330 if (t->delay_usecs)
331 udelay(t->delay_usecs);
332 }
333
334 espi_trans->status = status;
335 fsl_espi_setup_transfer(spi, NULL);
336}
337
338static void fsl_espi_cmd_trans(struct spi_message *m,
339 struct fsl_espi_transfer *trans, u8 *rx_buff)
340{
341 struct spi_transfer *t;
342 u8 *local_buf;
343 int i = 0;
344 struct fsl_espi_transfer *espi_trans = trans;
345
346 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
347 if (!local_buf) {
348 espi_trans->status = -ENOMEM;
349 return;
350 }
351
352 list_for_each_entry(t, &m->transfers, transfer_list) {
353 if (t->tx_buf) {
354 memcpy(local_buf + i, t->tx_buf, t->len);
355 i += t->len;
356 }
357 }
358
359 espi_trans->tx_buf = local_buf;
360 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
361 fsl_espi_do_trans(m, espi_trans);
362
363 espi_trans->actual_length = espi_trans->len;
364 kfree(local_buf);
365}
366
367static void fsl_espi_rw_trans(struct spi_message *m,
368 struct fsl_espi_transfer *trans, u8 *rx_buff)
369{
370 struct fsl_espi_transfer *espi_trans = trans;
371 unsigned int n_tx = espi_trans->n_tx;
372 unsigned int n_rx = espi_trans->n_rx;
373 struct spi_transfer *t;
374 u8 *local_buf;
375 u8 *rx_buf = rx_buff;
376 unsigned int trans_len;
377 unsigned int addr;
378 int i, pos, loop;
379
380 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
381 if (!local_buf) {
382 espi_trans->status = -ENOMEM;
383 return;
384 }
385
386 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
387 trans_len = n_rx - pos;
388 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
389 trans_len = SPCOM_TRANLEN_MAX - n_tx;
390
391 i = 0;
392 list_for_each_entry(t, &m->transfers, transfer_list) {
393 if (t->tx_buf) {
394 memcpy(local_buf + i, t->tx_buf, t->len);
395 i += t->len;
396 }
397 }
398
399 if (pos > 0) {
400 addr = fsl_espi_cmd2addr(local_buf);
401 addr += pos;
402 fsl_espi_addr2cmd(addr, local_buf);
403 }
404
405 espi_trans->n_tx = n_tx;
406 espi_trans->n_rx = trans_len;
407 espi_trans->len = trans_len + n_tx;
408 espi_trans->tx_buf = local_buf;
409 espi_trans->rx_buf = local_buf + n_tx;
410 fsl_espi_do_trans(m, espi_trans);
411
412 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
413
414 if (loop > 0)
415 espi_trans->actual_length += espi_trans->len - n_tx;
416 else
417 espi_trans->actual_length += espi_trans->len;
418 }
419
420 kfree(local_buf);
421}
422
423static void fsl_espi_do_one_msg(struct spi_message *m)
424{
425 struct spi_transfer *t;
426 u8 *rx_buf = NULL;
427 unsigned int n_tx = 0;
428 unsigned int n_rx = 0;
429 struct fsl_espi_transfer espi_trans;
430
431 list_for_each_entry(t, &m->transfers, transfer_list) {
432 if (t->tx_buf)
433 n_tx += t->len;
434 if (t->rx_buf) {
435 n_rx += t->len;
436 rx_buf = t->rx_buf;
437 }
438 }
439
440 espi_trans.n_tx = n_tx;
441 espi_trans.n_rx = n_rx;
442 espi_trans.len = n_tx + n_rx;
443 espi_trans.actual_length = 0;
444 espi_trans.status = 0;
445
446 if (!rx_buf)
447 fsl_espi_cmd_trans(m, &espi_trans, NULL);
448 else
449 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
450
451 m->actual_length = espi_trans.actual_length;
452 m->status = espi_trans.status;
453 m->complete(m->context);
454}
455
456static int fsl_espi_setup(struct spi_device *spi)
457{
458 struct mpc8xxx_spi *mpc8xxx_spi;
459 struct fsl_espi_reg *reg_base;
460 int retval;
461 u32 hw_mode;
462 u32 loop_mode;
463 struct spi_mpc8xxx_cs *cs = spi->controller_state;
464
465 if (!spi->max_speed_hz)
466 return -EINVAL;
467
468 if (!cs) {
469 cs = kzalloc(sizeof *cs, GFP_KERNEL);
470 if (!cs)
471 return -ENOMEM;
472 spi->controller_state = cs;
473 }
474
475 mpc8xxx_spi = spi_master_get_devdata(spi->master);
476 reg_base = mpc8xxx_spi->reg_base;
477
478 hw_mode = cs->hw_mode; /* Save original settings */
479 cs->hw_mode = mpc8xxx_spi_read_reg(
480 ®_base->csmode[spi->chip_select]);
481 /* mask out bits we are going to set */
482 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
483 | CSMODE_REV);
484
485 if (spi->mode & SPI_CPHA)
486 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
487 if (spi->mode & SPI_CPOL)
488 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
489 if (!(spi->mode & SPI_LSB_FIRST))
490 cs->hw_mode |= CSMODE_REV;
491
492 /* Handle the loop mode */
493 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
494 loop_mode &= ~SPMODE_LOOP;
495 if (spi->mode & SPI_LOOP)
496 loop_mode |= SPMODE_LOOP;
497 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
498
499 retval = fsl_espi_setup_transfer(spi, NULL);
500 if (retval < 0) {
501 cs->hw_mode = hw_mode; /* Restore settings */
502 return retval;
503 }
504 return 0;
505}
506
507void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
508{
509 struct fsl_espi_reg *reg_base = mspi->reg_base;
510
511 /* We need handle RX first */
512 if (events & SPIE_NE) {
513 u32 rx_data, tmp;
514 u8 rx_data_8;
515
516 /* Spin until RX is done */
517 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
518 cpu_relax();
519 events = mpc8xxx_spi_read_reg(®_base->event);
520 }
521
522 if (mspi->len >= 4) {
523 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
524 } else {
525 tmp = mspi->len;
526 rx_data = 0;
527 while (tmp--) {
528 rx_data_8 = in_8((u8 *)®_base->receive);
529 rx_data |= (rx_data_8 << (tmp * 8));
530 }
531
532 rx_data <<= (4 - mspi->len) * 8;
533 }
534
535 mspi->len -= 4;
536
537 if (mspi->rx)
538 mspi->get_rx(rx_data, mspi);
539 }
540
541 if (!(events & SPIE_NF)) {
542 int ret;
543
544 /* spin until TX is done */
545 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
546 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
547 if (!ret) {
548 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
549 return;
550 }
551 }
552
553 /* Clear the events */
554 mpc8xxx_spi_write_reg(®_base->event, events);
555
556 mspi->count -= 1;
557 if (mspi->count) {
558 u32 word = mspi->get_tx(mspi);
559
560 mpc8xxx_spi_write_reg(®_base->transmit, word);
561 } else {
562 complete(&mspi->done);
563 }
564}
565
566static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
567{
568 struct mpc8xxx_spi *mspi = context_data;
569 struct fsl_espi_reg *reg_base = mspi->reg_base;
570 irqreturn_t ret = IRQ_NONE;
571 u32 events;
572
573 /* Get interrupt events(tx/rx) */
574 events = mpc8xxx_spi_read_reg(®_base->event);
575 if (events)
576 ret = IRQ_HANDLED;
577
578 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
579
580 fsl_espi_cpu_irq(mspi, events);
581
582 return ret;
583}
584
585static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
586{
587 iounmap(mspi->reg_base);
588}
589
590static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
591 struct resource *mem, unsigned int irq)
592{
593 struct fsl_spi_platform_data *pdata = dev->platform_data;
594 struct spi_master *master;
595 struct mpc8xxx_spi *mpc8xxx_spi;
596 struct fsl_espi_reg *reg_base;
597 u32 regval;
598 int i, ret = 0;
599
600 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
601 if (!master) {
602 ret = -ENOMEM;
603 goto err;
604 }
605
606 dev_set_drvdata(dev, master);
607
608 ret = mpc8xxx_spi_probe(dev, mem, irq);
609 if (ret)
610 goto err_probe;
611
612 master->setup = fsl_espi_setup;
613
614 mpc8xxx_spi = spi_master_get_devdata(master);
615 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
616 mpc8xxx_spi->spi_remove = fsl_espi_remove;
617
618 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
619 if (!mpc8xxx_spi->reg_base) {
620 ret = -ENOMEM;
621 goto err_probe;
622 }
623
624 reg_base = mpc8xxx_spi->reg_base;
625
626 /* Register for SPI Interrupt */
627 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
628 0, "fsl_espi", mpc8xxx_spi);
629 if (ret)
630 goto free_irq;
631
632 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
633 mpc8xxx_spi->rx_shift = 16;
634 mpc8xxx_spi->tx_shift = 24;
635 }
636
637 /* SPI controller initializations */
638 mpc8xxx_spi_write_reg(®_base->mode, 0);
639 mpc8xxx_spi_write_reg(®_base->mask, 0);
640 mpc8xxx_spi_write_reg(®_base->command, 0);
641 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
642
643 /* Init eSPI CS mode register */
644 for (i = 0; i < pdata->max_chipselect; i++)
645 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
646
647 /* Enable SPI interface */
648 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
649
650 mpc8xxx_spi_write_reg(®_base->mode, regval);
651
652 ret = spi_register_master(master);
653 if (ret < 0)
654 goto unreg_master;
655
656 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
657
658 return master;
659
660unreg_master:
661 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
662free_irq:
663 iounmap(mpc8xxx_spi->reg_base);
664err_probe:
665 spi_master_put(master);
666err:
667 return ERR_PTR(ret);
668}
669
670static int of_fsl_espi_get_chipselects(struct device *dev)
671{
672 struct device_node *np = dev->of_node;
673 struct fsl_spi_platform_data *pdata = dev->platform_data;
674 const u32 *prop;
675 int len;
676
677 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
678 if (!prop || len < sizeof(*prop)) {
679 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
680 return -EINVAL;
681 }
682
683 pdata->max_chipselect = *prop;
684 pdata->cs_control = NULL;
685
686 return 0;
687}
688
689static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
690{
691 struct device *dev = &ofdev->dev;
692 struct device_node *np = ofdev->dev.of_node;
693 struct spi_master *master;
694 struct resource mem;
695 struct resource irq;
696 int ret = -ENOMEM;
697
698 ret = of_mpc8xxx_spi_probe(ofdev);
699 if (ret)
700 return ret;
701
702 ret = of_fsl_espi_get_chipselects(dev);
703 if (ret)
704 goto err;
705
706 ret = of_address_to_resource(np, 0, &mem);
707 if (ret)
708 goto err;
709
710 ret = of_irq_to_resource(np, 0, &irq);
711 if (!ret) {
712 ret = -EINVAL;
713 goto err;
714 }
715
716 master = fsl_espi_probe(dev, &mem, irq.start);
717 if (IS_ERR(master)) {
718 ret = PTR_ERR(master);
719 goto err;
720 }
721
722 return 0;
723
724err:
725 return ret;
726}
727
728static int __devexit of_fsl_espi_remove(struct platform_device *dev)
729{
730 return mpc8xxx_spi_remove(&dev->dev);
731}
732
733static const struct of_device_id of_fsl_espi_match[] = {
734 { .compatible = "fsl,mpc8536-espi" },
735 {}
736};
737MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
738
739static struct platform_driver fsl_espi_driver = {
740 .driver = {
741 .name = "fsl_espi",
742 .owner = THIS_MODULE,
743 .of_match_table = of_fsl_espi_match,
744 },
745 .probe = of_fsl_espi_probe,
746 .remove = __devexit_p(of_fsl_espi_remove),
747};
748module_platform_driver(fsl_espi_driver);
749
750MODULE_AUTHOR("Mingkai Hu");
751MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
752MODULE_LICENSE("GPL");