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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * EMIF driver
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * Aneesh V <aneesh@ti.com>
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 */
10#include <linux/err.h>
11#include <linux/kernel.h>
12#include <linux/reboot.h>
13#include <linux/platform_data/emif_plat.h>
14#include <linux/io.h>
15#include <linux/device.h>
16#include <linux/platform_device.h>
17#include <linux/interrupt.h>
18#include <linux/slab.h>
19#include <linux/of.h>
20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/pm.h>
26
27#include "emif.h"
28#include "jedec_ddr.h"
29#include "of_memory.h"
30
31/**
32 * struct emif_data - Per device static data for driver's use
33 * @duplicate: Whether the DDR devices attached to this EMIF
34 * instance are exactly same as that on EMIF1. In
35 * this case we can save some memory and processing
36 * @temperature_level: Maximum temperature of LPDDR2 devices attached
37 * to this EMIF - read from MR4 register. If there
38 * are two devices attached to this EMIF, this
39 * value is the maximum of the two temperature
40 * levels.
41 * @node: node in the device list
42 * @base: base address of memory-mapped IO registers.
43 * @dev: device pointer.
44 * @addressing table with addressing information from the spec
45 * @regs_cache: An array of 'struct emif_regs' that stores
46 * calculated register values for different
47 * frequencies, to avoid re-calculating them on
48 * each DVFS transition.
49 * @curr_regs: The set of register values used in the last
50 * frequency change (i.e. corresponding to the
51 * frequency in effect at the moment)
52 * @plat_data: Pointer to saved platform data.
53 * @debugfs_root: dentry to the root folder for EMIF in debugfs
54 * @np_ddr: Pointer to ddr device tree node
55 */
56struct emif_data {
57 u8 duplicate;
58 u8 temperature_level;
59 u8 lpmode;
60 struct list_head node;
61 unsigned long irq_state;
62 void __iomem *base;
63 struct device *dev;
64 const struct lpddr2_addressing *addressing;
65 struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
66 struct emif_regs *curr_regs;
67 struct emif_platform_data *plat_data;
68 struct dentry *debugfs_root;
69 struct device_node *np_ddr;
70};
71
72static struct emif_data *emif1;
73static spinlock_t emif_lock;
74static unsigned long irq_state;
75static u32 t_ck; /* DDR clock period in ps */
76static LIST_HEAD(device_list);
77
78#ifdef CONFIG_DEBUG_FS
79static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
80 struct emif_regs *regs)
81{
82 u32 type = emif->plat_data->device_info->type;
83 u32 ip_rev = emif->plat_data->ip_rev;
84
85 seq_printf(s, "EMIF register cache dump for %dMHz\n",
86 regs->freq/1000000);
87
88 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
89 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
90 seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
91 seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
92
93 if (ip_rev == EMIF_4D) {
94 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
95 regs->read_idle_ctrl_shdw_normal);
96 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
97 regs->read_idle_ctrl_shdw_volt_ramp);
98 } else if (ip_rev == EMIF_4D5) {
99 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
100 regs->dll_calib_ctrl_shdw_normal);
101 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
102 regs->dll_calib_ctrl_shdw_volt_ramp);
103 }
104
105 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
106 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
107 regs->ref_ctrl_shdw_derated);
108 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
109 regs->sdram_tim1_shdw_derated);
110 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
111 regs->sdram_tim3_shdw_derated);
112 }
113}
114
115static int emif_regdump_show(struct seq_file *s, void *unused)
116{
117 struct emif_data *emif = s->private;
118 struct emif_regs **regs_cache;
119 int i;
120
121 if (emif->duplicate)
122 regs_cache = emif1->regs_cache;
123 else
124 regs_cache = emif->regs_cache;
125
126 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
127 do_emif_regdump_show(s, emif, regs_cache[i]);
128 seq_putc(s, '\n');
129 }
130
131 return 0;
132}
133
134static int emif_regdump_open(struct inode *inode, struct file *file)
135{
136 return single_open(file, emif_regdump_show, inode->i_private);
137}
138
139static const struct file_operations emif_regdump_fops = {
140 .open = emif_regdump_open,
141 .read = seq_read,
142 .release = single_release,
143};
144
145static int emif_mr4_show(struct seq_file *s, void *unused)
146{
147 struct emif_data *emif = s->private;
148
149 seq_printf(s, "MR4=%d\n", emif->temperature_level);
150 return 0;
151}
152
153static int emif_mr4_open(struct inode *inode, struct file *file)
154{
155 return single_open(file, emif_mr4_show, inode->i_private);
156}
157
158static const struct file_operations emif_mr4_fops = {
159 .open = emif_mr4_open,
160 .read = seq_read,
161 .release = single_release,
162};
163
164static int __init_or_module emif_debugfs_init(struct emif_data *emif)
165{
166 struct dentry *dentry;
167 int ret;
168
169 dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
170 if (!dentry) {
171 ret = -ENOMEM;
172 goto err0;
173 }
174 emif->debugfs_root = dentry;
175
176 dentry = debugfs_create_file("regcache_dump", S_IRUGO,
177 emif->debugfs_root, emif, &emif_regdump_fops);
178 if (!dentry) {
179 ret = -ENOMEM;
180 goto err1;
181 }
182
183 dentry = debugfs_create_file("mr4", S_IRUGO,
184 emif->debugfs_root, emif, &emif_mr4_fops);
185 if (!dentry) {
186 ret = -ENOMEM;
187 goto err1;
188 }
189
190 return 0;
191err1:
192 debugfs_remove_recursive(emif->debugfs_root);
193err0:
194 return ret;
195}
196
197static void __exit emif_debugfs_exit(struct emif_data *emif)
198{
199 debugfs_remove_recursive(emif->debugfs_root);
200 emif->debugfs_root = NULL;
201}
202#else
203static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
204{
205 return 0;
206}
207
208static inline void __exit emif_debugfs_exit(struct emif_data *emif)
209{
210}
211#endif
212
213/*
214 * Calculate the period of DDR clock from frequency value
215 */
216static void set_ddr_clk_period(u32 freq)
217{
218 /* Divide 10^12 by frequency to get period in ps */
219 t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
220}
221
222/*
223 * Get bus width used by EMIF. Note that this may be different from the
224 * bus width of the DDR devices used. For instance two 16-bit DDR devices
225 * may be connected to a given CS of EMIF. In this case bus width as far
226 * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
227 */
228static u32 get_emif_bus_width(struct emif_data *emif)
229{
230 u32 width;
231 void __iomem *base = emif->base;
232
233 width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
234 >> NARROW_MODE_SHIFT;
235 width = width == 0 ? 32 : 16;
236
237 return width;
238}
239
240/*
241 * Get the CL from SDRAM_CONFIG register
242 */
243static u32 get_cl(struct emif_data *emif)
244{
245 u32 cl;
246 void __iomem *base = emif->base;
247
248 cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
249
250 return cl;
251}
252
253static void set_lpmode(struct emif_data *emif, u8 lpmode)
254{
255 u32 temp;
256 void __iomem *base = emif->base;
257
258 /*
259 * Workaround for errata i743 - LPDDR2 Power-Down State is Not
260 * Efficient
261 *
262 * i743 DESCRIPTION:
263 * The EMIF supports power-down state for low power. The EMIF
264 * automatically puts the SDRAM into power-down after the memory is
265 * not accessed for a defined number of cycles and the
266 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
267 * As the EMIF supports automatic output impedance calibration, a ZQ
268 * calibration long command is issued every time it exits active
269 * power-down and precharge power-down modes. The EMIF waits and
270 * blocks any other command during this calibration.
271 * The EMIF does not allow selective disabling of ZQ calibration upon
272 * exit of power-down mode. Due to very short periods of power-down
273 * cycles, ZQ calibration overhead creates bandwidth issues and
274 * increases overall system power consumption. On the other hand,
275 * issuing ZQ calibration long commands when exiting self-refresh is
276 * still required.
277 *
278 * WORKAROUND
279 * Because there is no power consumption benefit of the power-down due
280 * to the calibration and there is a performance risk, the guideline
281 * is to not allow power-down state and, therefore, to not have set
282 * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
283 */
284 if ((emif->plat_data->ip_rev == EMIF_4D) &&
285 (EMIF_LP_MODE_PWR_DN == lpmode)) {
286 WARN_ONCE(1,
287 "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by"
288 "erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
289 /* rollback LP_MODE to Self-refresh mode */
290 lpmode = EMIF_LP_MODE_SELF_REFRESH;
291 }
292
293 temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
294 temp &= ~LP_MODE_MASK;
295 temp |= (lpmode << LP_MODE_SHIFT);
296 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
297}
298
299static void do_freq_update(void)
300{
301 struct emif_data *emif;
302
303 /*
304 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
305 *
306 * i728 DESCRIPTION:
307 * The EMIF automatically puts the SDRAM into self-refresh mode
308 * after the EMIF has not performed accesses during
309 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
310 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
311 * to 0x2. If during a small window the following three events
312 * occur:
313 * - The SR_TIMING counter expires
314 * - And frequency change is requested
315 * - And OCP access is requested
316 * Then it causes instable clock on the DDR interface.
317 *
318 * WORKAROUND
319 * To avoid the occurrence of the three events, the workaround
320 * is to disable the self-refresh when requesting a frequency
321 * change. Before requesting a frequency change the software must
322 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
323 * frequency change has been done, the software can reprogram
324 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
325 */
326 list_for_each_entry(emif, &device_list, node) {
327 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
328 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
329 }
330
331 /*
332 * TODO: Do FREQ_UPDATE here when an API
333 * is available for this as part of the new
334 * clock framework
335 */
336
337 list_for_each_entry(emif, &device_list, node) {
338 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
339 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
340 }
341}
342
343/* Find addressing table entry based on the device's type and density */
344static const struct lpddr2_addressing *get_addressing_table(
345 const struct ddr_device_info *device_info)
346{
347 u32 index, type, density;
348
349 type = device_info->type;
350 density = device_info->density;
351
352 switch (type) {
353 case DDR_TYPE_LPDDR2_S4:
354 index = density - 1;
355 break;
356 case DDR_TYPE_LPDDR2_S2:
357 switch (density) {
358 case DDR_DENSITY_1Gb:
359 case DDR_DENSITY_2Gb:
360 index = density + 3;
361 break;
362 default:
363 index = density - 1;
364 }
365 break;
366 default:
367 return NULL;
368 }
369
370 return &lpddr2_jedec_addressing_table[index];
371}
372
373/*
374 * Find the the right timing table from the array of timing
375 * tables of the device using DDR clock frequency
376 */
377static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
378 u32 freq)
379{
380 u32 i, min, max, freq_nearest;
381 const struct lpddr2_timings *timings = NULL;
382 const struct lpddr2_timings *timings_arr = emif->plat_data->timings;
383 struct device *dev = emif->dev;
384
385 /* Start with a very high frequency - 1GHz */
386 freq_nearest = 1000000000;
387
388 /*
389 * Find the timings table such that:
390 * 1. the frequency range covers the required frequency(safe) AND
391 * 2. the max_freq is closest to the required frequency(optimal)
392 */
393 for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
394 max = timings_arr[i].max_freq;
395 min = timings_arr[i].min_freq;
396 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
397 freq_nearest = max;
398 timings = &timings_arr[i];
399 }
400 }
401
402 if (!timings)
403 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
404 __func__, freq);
405
406 dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
407 __func__, freq, freq_nearest);
408
409 return timings;
410}
411
412static u32 get_sdram_ref_ctrl_shdw(u32 freq,
413 const struct lpddr2_addressing *addressing)
414{
415 u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
416
417 /* Scale down frequency and t_refi to avoid overflow */
418 freq_khz = freq / 1000;
419 t_refi = addressing->tREFI_ns / 100;
420
421 /*
422 * refresh rate to be set is 'tREFI(in us) * freq in MHz
423 * division by 10000 to account for change in units
424 */
425 val = t_refi * freq_khz / 10000;
426 ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
427
428 return ref_ctrl_shdw;
429}
430
431static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
432 const struct lpddr2_min_tck *min_tck,
433 const struct lpddr2_addressing *addressing)
434{
435 u32 tim1 = 0, val = 0;
436
437 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
438 tim1 |= val << T_WTR_SHIFT;
439
440 if (addressing->num_banks == B8)
441 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
442 else
443 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
444 tim1 |= (val - 1) << T_RRD_SHIFT;
445
446 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
447 tim1 |= val << T_RC_SHIFT;
448
449 val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
450 tim1 |= (val - 1) << T_RAS_SHIFT;
451
452 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
453 tim1 |= val << T_WR_SHIFT;
454
455 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
456 tim1 |= val << T_RCD_SHIFT;
457
458 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
459 tim1 |= val << T_RP_SHIFT;
460
461 return tim1;
462}
463
464static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
465 const struct lpddr2_min_tck *min_tck,
466 const struct lpddr2_addressing *addressing)
467{
468 u32 tim1 = 0, val = 0;
469
470 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
471 tim1 = val << T_WTR_SHIFT;
472
473 /*
474 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
475 * to tFAW for de-rating
476 */
477 if (addressing->num_banks == B8) {
478 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
479 } else {
480 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
481 val = max(min_tck->tRRD, val) - 1;
482 }
483 tim1 |= val << T_RRD_SHIFT;
484
485 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
486 tim1 |= (val - 1) << T_RC_SHIFT;
487
488 val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
489 val = max(min_tck->tRASmin, val) - 1;
490 tim1 |= val << T_RAS_SHIFT;
491
492 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
493 tim1 |= val << T_WR_SHIFT;
494
495 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
496 tim1 |= (val - 1) << T_RCD_SHIFT;
497
498 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
499 tim1 |= (val - 1) << T_RP_SHIFT;
500
501 return tim1;
502}
503
504static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
505 const struct lpddr2_min_tck *min_tck,
506 const struct lpddr2_addressing *addressing,
507 u32 type)
508{
509 u32 tim2 = 0, val = 0;
510
511 val = min_tck->tCKE - 1;
512 tim2 |= val << T_CKE_SHIFT;
513
514 val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
515 tim2 |= val << T_RTP_SHIFT;
516
517 /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
518 val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
519 tim2 |= val << T_XSNR_SHIFT;
520
521 /* XSRD same as XSNR for LPDDR2 */
522 tim2 |= val << T_XSRD_SHIFT;
523
524 val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
525 tim2 |= val << T_XP_SHIFT;
526
527 return tim2;
528}
529
530static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
531 const struct lpddr2_min_tck *min_tck,
532 const struct lpddr2_addressing *addressing,
533 u32 type, u32 ip_rev, u32 derated)
534{
535 u32 tim3 = 0, val = 0, t_dqsck;
536
537 val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
538 val = val > 0xF ? 0xF : val;
539 tim3 |= val << T_RAS_MAX_SHIFT;
540
541 val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
542 tim3 |= val << T_RFC_SHIFT;
543
544 t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
545 timings->tDQSCK_max_derated : timings->tDQSCK_max;
546 if (ip_rev == EMIF_4D5)
547 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
548 else
549 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
550
551 tim3 |= val << T_TDQSCKMAX_SHIFT;
552
553 val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
554 tim3 |= val << ZQ_ZQCS_SHIFT;
555
556 val = DIV_ROUND_UP(timings->tCKESR, t_ck);
557 val = max(min_tck->tCKESR, val) - 1;
558 tim3 |= val << T_CKESR_SHIFT;
559
560 if (ip_rev == EMIF_4D5) {
561 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
562
563 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
564 tim3 |= val << T_PDLL_UL_SHIFT;
565 }
566
567 return tim3;
568}
569
570static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
571 bool cs1_used, bool cal_resistors_per_cs)
572{
573 u32 zq = 0, val = 0;
574
575 val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
576 zq |= val << ZQ_REFINTERVAL_SHIFT;
577
578 val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
579 zq |= val << ZQ_ZQCL_MULT_SHIFT;
580
581 val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
582 zq |= val << ZQ_ZQINIT_MULT_SHIFT;
583
584 zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
585
586 if (cal_resistors_per_cs)
587 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
588 else
589 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
590
591 zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
592
593 val = cs1_used ? 1 : 0;
594 zq |= val << ZQ_CS1EN_SHIFT;
595
596 return zq;
597}
598
599static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
600 const struct emif_custom_configs *custom_configs, bool cs1_used,
601 u32 sdram_io_width, u32 emif_bus_width)
602{
603 u32 alert = 0, interval, devcnt;
604
605 if (custom_configs && (custom_configs->mask &
606 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
607 interval = custom_configs->temp_alert_poll_interval_ms;
608 else
609 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
610
611 interval *= 1000000; /* Convert to ns */
612 interval /= addressing->tREFI_ns; /* Convert to refresh cycles */
613 alert |= (interval << TA_REFINTERVAL_SHIFT);
614
615 /*
616 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
617 * also to this form and subtract to get TA_DEVCNT, which is
618 * in log2(x) form.
619 */
620 emif_bus_width = __fls(emif_bus_width) - 1;
621 devcnt = emif_bus_width - sdram_io_width;
622 alert |= devcnt << TA_DEVCNT_SHIFT;
623
624 /* DEVWDT is in 'log2(x) - 3' form */
625 alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
626
627 alert |= 1 << TA_SFEXITEN_SHIFT;
628 alert |= 1 << TA_CS0EN_SHIFT;
629 alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
630
631 return alert;
632}
633
634static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
635{
636 u32 idle = 0, val = 0;
637
638 /*
639 * Maximum value in normal conditions and increased frequency
640 * when voltage is ramping
641 */
642 if (volt_ramp)
643 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
644 else
645 val = 0x1FF;
646
647 /*
648 * READ_IDLE_CTRL register in EMIF4D has same offset and fields
649 * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
650 */
651 idle |= val << DLL_CALIB_INTERVAL_SHIFT;
652 idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
653
654 return idle;
655}
656
657static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
658{
659 u32 calib = 0, val = 0;
660
661 if (volt_ramp == DDR_VOLTAGE_RAMPING)
662 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
663 else
664 val = 0; /* Disabled when voltage is stable */
665
666 calib |= val << DLL_CALIB_INTERVAL_SHIFT;
667 calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
668
669 return calib;
670}
671
672static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
673 u32 freq, u8 RL)
674{
675 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
676
677 val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
678 phy |= val << READ_LATENCY_SHIFT_4D;
679
680 if (freq <= 100000000)
681 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
682 else if (freq <= 200000000)
683 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
684 else
685 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
686
687 phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
688
689 return phy;
690}
691
692static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
693{
694 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
695
696 /*
697 * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
698 * half-delay is not needed else set half-delay
699 */
700 if (freq >= 265000000 && freq < 267000000)
701 half_delay = 0;
702 else
703 half_delay = 1;
704
705 phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
706 phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
707 t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
708
709 return phy;
710}
711
712static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
713{
714 u32 fifo_we_slave_ratio;
715
716 fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
717 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
718
719 return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
720 fifo_we_slave_ratio << 22;
721}
722
723static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
724{
725 u32 fifo_we_slave_ratio;
726
727 fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
728 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
729
730 return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
731 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
732}
733
734static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
735{
736 u32 fifo_we_slave_ratio;
737
738 fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
739 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
740
741 return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
742 fifo_we_slave_ratio << 13;
743}
744
745static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
746{
747 u32 pwr_mgmt_ctrl = 0, timeout;
748 u32 lpmode = EMIF_LP_MODE_SELF_REFRESH;
749 u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
750 u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER;
751 u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD;
752 u32 mask;
753 u8 shift;
754
755 struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
756
757 if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
758 lpmode = cust_cfgs->lpmode;
759 timeout_perf = cust_cfgs->lpmode_timeout_performance;
760 timeout_pwr = cust_cfgs->lpmode_timeout_power;
761 freq_threshold = cust_cfgs->lpmode_freq_threshold;
762 }
763
764 /* Timeout based on DDR frequency */
765 timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
766
767 /*
768 * The value to be set in register is "log2(timeout) - 3"
769 * if timeout < 16 load 0 in register
770 * if timeout is not a power of 2, round to next highest power of 2
771 */
772 if (timeout < 16) {
773 timeout = 0;
774 } else {
775 if (timeout & (timeout - 1))
776 timeout <<= 1;
777 timeout = __fls(timeout) - 3;
778 }
779
780 switch (lpmode) {
781 case EMIF_LP_MODE_CLOCK_STOP:
782 shift = CS_TIM_SHIFT;
783 mask = CS_TIM_MASK;
784 break;
785 case EMIF_LP_MODE_SELF_REFRESH:
786 /* Workaround for errata i735 */
787 if (timeout < 6)
788 timeout = 6;
789
790 shift = SR_TIM_SHIFT;
791 mask = SR_TIM_MASK;
792 break;
793 case EMIF_LP_MODE_PWR_DN:
794 shift = PD_TIM_SHIFT;
795 mask = PD_TIM_MASK;
796 break;
797 case EMIF_LP_MODE_DISABLE:
798 default:
799 mask = 0;
800 shift = 0;
801 break;
802 }
803 /* Round to maximum in case of overflow, BUT warn! */
804 if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
805 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
806 lpmode,
807 timeout_perf,
808 timeout_pwr,
809 freq_threshold);
810 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
811 timeout, mask >> shift);
812 timeout = mask >> shift;
813 }
814
815 /* Setup required timing */
816 pwr_mgmt_ctrl = (timeout << shift) & mask;
817 /* setup a default mask for rest of the modes */
818 pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
819 ~mask;
820
821 /* No CS_TIM in EMIF_4D5 */
822 if (ip_rev == EMIF_4D5)
823 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
824
825 pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
826
827 return pwr_mgmt_ctrl;
828}
829
830/*
831 * Get the temperature level of the EMIF instance:
832 * Reads the MR4 register of attached SDRAM parts to find out the temperature
833 * level. If there are two parts attached(one on each CS), then the temperature
834 * level for the EMIF instance is the higher of the two temperatures.
835 */
836static void get_temperature_level(struct emif_data *emif)
837{
838 u32 temp, temperature_level;
839 void __iomem *base;
840
841 base = emif->base;
842
843 /* Read mode register 4 */
844 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
845 temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
846 temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
847 MR4_SDRAM_REF_RATE_SHIFT;
848
849 if (emif->plat_data->device_info->cs1_used) {
850 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
851 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
852 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
853 >> MR4_SDRAM_REF_RATE_SHIFT;
854 temperature_level = max(temp, temperature_level);
855 }
856
857 /* treat everything less than nominal(3) in MR4 as nominal */
858 if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
859 temperature_level = SDRAM_TEMP_NOMINAL;
860
861 /* if we get reserved value in MR4 persist with the existing value */
862 if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
863 emif->temperature_level = temperature_level;
864}
865
866/*
867 * Program EMIF shadow registers that are not dependent on temperature
868 * or voltage
869 */
870static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
871{
872 void __iomem *base = emif->base;
873
874 writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
875 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
876 writel(regs->pwr_mgmt_ctrl_shdw,
877 base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
878
879 /* Settings specific for EMIF4D5 */
880 if (emif->plat_data->ip_rev != EMIF_4D5)
881 return;
882 writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
883 writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
884 writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
885}
886
887/*
888 * When voltage ramps dll calibration and forced read idle should
889 * happen more often
890 */
891static void setup_volt_sensitive_regs(struct emif_data *emif,
892 struct emif_regs *regs, u32 volt_state)
893{
894 u32 calib_ctrl;
895 void __iomem *base = emif->base;
896
897 /*
898 * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
899 * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
900 * is an alias of the respective read_idle_ctrl_shdw_* (members of
901 * a union). So, the below code takes care of both cases
902 */
903 if (volt_state == DDR_VOLTAGE_RAMPING)
904 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
905 else
906 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
907
908 writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
909}
910
911/*
912 * setup_temperature_sensitive_regs() - set the timings for temperature
913 * sensitive registers. This happens once at initialisation time based
914 * on the temperature at boot time and subsequently based on the temperature
915 * alert interrupt. Temperature alert can happen when the temperature
916 * increases or drops. So this function can have the effect of either
917 * derating the timings or going back to nominal values.
918 */
919static void setup_temperature_sensitive_regs(struct emif_data *emif,
920 struct emif_regs *regs)
921{
922 u32 tim1, tim3, ref_ctrl, type;
923 void __iomem *base = emif->base;
924 u32 temperature;
925
926 type = emif->plat_data->device_info->type;
927
928 tim1 = regs->sdram_tim1_shdw;
929 tim3 = regs->sdram_tim3_shdw;
930 ref_ctrl = regs->ref_ctrl_shdw;
931
932 /* No de-rating for non-lpddr2 devices */
933 if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
934 goto out;
935
936 temperature = emif->temperature_level;
937 if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
938 ref_ctrl = regs->ref_ctrl_shdw_derated;
939 } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
940 tim1 = regs->sdram_tim1_shdw_derated;
941 tim3 = regs->sdram_tim3_shdw_derated;
942 ref_ctrl = regs->ref_ctrl_shdw_derated;
943 }
944
945out:
946 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
947 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
948 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
949}
950
951static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
952{
953 u32 old_temp_level;
954 irqreturn_t ret = IRQ_HANDLED;
955 struct emif_custom_configs *custom_configs;
956
957 spin_lock_irqsave(&emif_lock, irq_state);
958 old_temp_level = emif->temperature_level;
959 get_temperature_level(emif);
960
961 if (unlikely(emif->temperature_level == old_temp_level)) {
962 goto out;
963 } else if (!emif->curr_regs) {
964 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
965 goto out;
966 }
967
968 custom_configs = emif->plat_data->custom_configs;
969
970 /*
971 * IF we detect higher than "nominal rating" from DDR sensor
972 * on an unsupported DDR part, shutdown system
973 */
974 if (custom_configs && !(custom_configs->mask &
975 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
976 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
977 dev_err(emif->dev,
978 "%s:NOT Extended temperature capable memory."
979 "Converting MR4=0x%02x as shutdown event\n",
980 __func__, emif->temperature_level);
981 /*
982 * Temperature far too high - do kernel_power_off()
983 * from thread context
984 */
985 emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
986 ret = IRQ_WAKE_THREAD;
987 goto out;
988 }
989 }
990
991 if (emif->temperature_level < old_temp_level ||
992 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
993 /*
994 * Temperature coming down - defer handling to thread OR
995 * Temperature far too high - do kernel_power_off() from
996 * thread context
997 */
998 ret = IRQ_WAKE_THREAD;
999 } else {
1000 /* Temperature is going up - handle immediately */
1001 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1002 do_freq_update();
1003 }
1004
1005out:
1006 spin_unlock_irqrestore(&emif_lock, irq_state);
1007 return ret;
1008}
1009
1010static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
1011{
1012 u32 interrupts;
1013 struct emif_data *emif = dev_id;
1014 void __iomem *base = emif->base;
1015 struct device *dev = emif->dev;
1016 irqreturn_t ret = IRQ_HANDLED;
1017
1018 /* Save the status and clear it */
1019 interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1020 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1021
1022 /*
1023 * Handle temperature alert
1024 * Temperature alert should be same for all ports
1025 * So, it's enough to process it only for one of the ports
1026 */
1027 if (interrupts & TA_SYS_MASK)
1028 ret = handle_temp_alert(base, emif);
1029
1030 if (interrupts & ERR_SYS_MASK)
1031 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
1032
1033 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1034 /* Save the status and clear it */
1035 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
1036 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
1037
1038 if (interrupts & ERR_LL_MASK)
1039 dev_err(dev, "Access error from LL port - %x\n",
1040 interrupts);
1041 }
1042
1043 return ret;
1044}
1045
1046static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
1047{
1048 struct emif_data *emif = dev_id;
1049
1050 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
1051 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1052
1053 /* If we have Power OFF ability, use it, else try restarting */
1054 if (pm_power_off) {
1055 kernel_power_off();
1056 } else {
1057 WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
1058 kernel_restart("SDRAM Over-temp Emergency restart");
1059 }
1060 return IRQ_HANDLED;
1061 }
1062
1063 spin_lock_irqsave(&emif_lock, irq_state);
1064
1065 if (emif->curr_regs) {
1066 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1067 do_freq_update();
1068 } else {
1069 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
1070 }
1071
1072 spin_unlock_irqrestore(&emif_lock, irq_state);
1073
1074 return IRQ_HANDLED;
1075}
1076
1077static void clear_all_interrupts(struct emif_data *emif)
1078{
1079 void __iomem *base = emif->base;
1080
1081 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
1082 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1083 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1084 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
1085 base + EMIF_LL_OCP_INTERRUPT_STATUS);
1086}
1087
1088static void disable_and_clear_all_interrupts(struct emif_data *emif)
1089{
1090 void __iomem *base = emif->base;
1091
1092 /* Disable all interrupts */
1093 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1094 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1095 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1096 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1097 base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1098
1099 /* Clear all interrupts */
1100 clear_all_interrupts(emif);
1101}
1102
1103static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1104{
1105 u32 interrupts, type;
1106 void __iomem *base = emif->base;
1107
1108 type = emif->plat_data->device_info->type;
1109
1110 clear_all_interrupts(emif);
1111
1112 /* Enable interrupts for SYS interface */
1113 interrupts = EN_ERR_SYS_MASK;
1114 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1115 interrupts |= EN_TA_SYS_MASK;
1116 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1117
1118 /* Enable interrupts for LL interface */
1119 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1120 /* TA need not be enabled for LL */
1121 interrupts = EN_ERR_LL_MASK;
1122 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1123 }
1124
1125 /* setup IRQ handlers */
1126 return devm_request_threaded_irq(emif->dev, irq,
1127 emif_interrupt_handler,
1128 emif_threaded_isr,
1129 0, dev_name(emif->dev),
1130 emif);
1131
1132}
1133
1134static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1135{
1136 u32 pwr_mgmt_ctrl, zq, temp_alert_cfg;
1137 void __iomem *base = emif->base;
1138 const struct lpddr2_addressing *addressing;
1139 const struct ddr_device_info *device_info;
1140
1141 device_info = emif->plat_data->device_info;
1142 addressing = get_addressing_table(device_info);
1143
1144 /*
1145 * Init power management settings
1146 * We don't know the frequency yet. Use a high frequency
1147 * value for a conservative timeout setting
1148 */
1149 pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1150 emif->plat_data->ip_rev);
1151 emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1152 writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1153
1154 /* Init ZQ calibration settings */
1155 zq = get_zq_config_reg(addressing, device_info->cs1_used,
1156 device_info->cal_resistors_per_cs);
1157 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1158
1159 /* Check temperature level temperature level*/
1160 get_temperature_level(emif);
1161 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1162 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1163
1164 /* Init temperature polling */
1165 temp_alert_cfg = get_temp_alert_config(addressing,
1166 emif->plat_data->custom_configs, device_info->cs1_used,
1167 device_info->io_width, get_emif_bus_width(emif));
1168 writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1169
1170 /*
1171 * Program external PHY control registers that are not frequency
1172 * dependent
1173 */
1174 if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1175 return;
1176 writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1177 writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1178 writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1179 writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1180 writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1181 writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1182 writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1183 writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1184 writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1185 writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1186 writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1187 writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1188 writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1189 writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1190 writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1191 writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1192 writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1193 writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1194 writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1195 writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1196 writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1197}
1198
1199static void get_default_timings(struct emif_data *emif)
1200{
1201 struct emif_platform_data *pd = emif->plat_data;
1202
1203 pd->timings = lpddr2_jedec_timings;
1204 pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings);
1205
1206 dev_warn(emif->dev, "%s: using default timings\n", __func__);
1207}
1208
1209static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1210 u32 ip_rev, struct device *dev)
1211{
1212 int valid;
1213
1214 valid = (type == DDR_TYPE_LPDDR2_S4 ||
1215 type == DDR_TYPE_LPDDR2_S2)
1216 && (density >= DDR_DENSITY_64Mb
1217 && density <= DDR_DENSITY_8Gb)
1218 && (io_width >= DDR_IO_WIDTH_8
1219 && io_width <= DDR_IO_WIDTH_32);
1220
1221 /* Combinations of EMIF and PHY revisions that we support today */
1222 switch (ip_rev) {
1223 case EMIF_4D:
1224 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1225 break;
1226 case EMIF_4D5:
1227 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1228 break;
1229 default:
1230 valid = 0;
1231 }
1232
1233 if (!valid)
1234 dev_err(dev, "%s: invalid DDR details\n", __func__);
1235 return valid;
1236}
1237
1238static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1239 struct device *dev)
1240{
1241 int valid = 1;
1242
1243 if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1244 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1245 valid = cust_cfgs->lpmode_freq_threshold &&
1246 cust_cfgs->lpmode_timeout_performance &&
1247 cust_cfgs->lpmode_timeout_power;
1248
1249 if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1250 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1251
1252 if (!valid)
1253 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1254
1255 return valid;
1256}
1257
1258#if defined(CONFIG_OF)
1259static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1260 struct emif_data *emif)
1261{
1262 struct emif_custom_configs *cust_cfgs = NULL;
1263 int len;
1264 const __be32 *lpmode, *poll_intvl;
1265
1266 lpmode = of_get_property(np_emif, "low-power-mode", &len);
1267 poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1268
1269 if (lpmode || poll_intvl)
1270 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1271 GFP_KERNEL);
1272
1273 if (!cust_cfgs)
1274 return;
1275
1276 if (lpmode) {
1277 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1278 cust_cfgs->lpmode = be32_to_cpup(lpmode);
1279 of_property_read_u32(np_emif,
1280 "low-power-mode-timeout-performance",
1281 &cust_cfgs->lpmode_timeout_performance);
1282 of_property_read_u32(np_emif,
1283 "low-power-mode-timeout-power",
1284 &cust_cfgs->lpmode_timeout_power);
1285 of_property_read_u32(np_emif,
1286 "low-power-mode-freq-threshold",
1287 &cust_cfgs->lpmode_freq_threshold);
1288 }
1289
1290 if (poll_intvl) {
1291 cust_cfgs->mask |=
1292 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1293 cust_cfgs->temp_alert_poll_interval_ms =
1294 be32_to_cpup(poll_intvl);
1295 }
1296
1297 if (of_find_property(np_emif, "extended-temp-part", &len))
1298 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
1299
1300 if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1301 devm_kfree(emif->dev, cust_cfgs);
1302 return;
1303 }
1304
1305 emif->plat_data->custom_configs = cust_cfgs;
1306}
1307
1308static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1309 struct device_node *np_ddr,
1310 struct ddr_device_info *dev_info)
1311{
1312 u32 density = 0, io_width = 0;
1313 int len;
1314
1315 if (of_find_property(np_emif, "cs1-used", &len))
1316 dev_info->cs1_used = true;
1317
1318 if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1319 dev_info->cal_resistors_per_cs = true;
1320
1321 if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
1322 dev_info->type = DDR_TYPE_LPDDR2_S4;
1323 else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
1324 dev_info->type = DDR_TYPE_LPDDR2_S2;
1325
1326 of_property_read_u32(np_ddr, "density", &density);
1327 of_property_read_u32(np_ddr, "io-width", &io_width);
1328
1329 /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1330 if (density & (density - 1))
1331 dev_info->density = 0;
1332 else
1333 dev_info->density = __fls(density) - 5;
1334
1335 /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1336 if (io_width & (io_width - 1))
1337 dev_info->io_width = 0;
1338 else
1339 dev_info->io_width = __fls(io_width) - 1;
1340}
1341
1342static struct emif_data * __init_or_module of_get_memory_device_details(
1343 struct device_node *np_emif, struct device *dev)
1344{
1345 struct emif_data *emif = NULL;
1346 struct ddr_device_info *dev_info = NULL;
1347 struct emif_platform_data *pd = NULL;
1348 struct device_node *np_ddr;
1349 int len;
1350
1351 np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1352 if (!np_ddr)
1353 goto error;
1354 emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1355 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1356 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1357
1358 if (!emif || !pd || !dev_info) {
1359 dev_err(dev, "%s: Out of memory!!\n",
1360 __func__);
1361 goto error;
1362 }
1363
1364 emif->plat_data = pd;
1365 pd->device_info = dev_info;
1366 emif->dev = dev;
1367 emif->np_ddr = np_ddr;
1368 emif->temperature_level = SDRAM_TEMP_NOMINAL;
1369
1370 if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1371 emif->plat_data->ip_rev = EMIF_4D;
1372 else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1373 emif->plat_data->ip_rev = EMIF_4D5;
1374
1375 of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1376
1377 if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1378 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1379
1380 of_get_ddr_info(np_emif, np_ddr, dev_info);
1381 if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1382 pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1383 emif->dev)) {
1384 dev_err(dev, "%s: invalid device data!!\n", __func__);
1385 goto error;
1386 }
1387 /*
1388 * For EMIF instances other than EMIF1 see if the devices connected
1389 * are exactly same as on EMIF1(which is typically the case). If so,
1390 * mark it as a duplicate of EMIF1. This will save some memory and
1391 * computation.
1392 */
1393 if (emif1 && emif1->np_ddr == np_ddr) {
1394 emif->duplicate = true;
1395 goto out;
1396 } else if (emif1) {
1397 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1398 __func__);
1399 }
1400
1401 of_get_custom_configs(np_emif, emif);
1402 emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1403 emif->plat_data->device_info->type,
1404 &emif->plat_data->timings_arr_size);
1405
1406 emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1407 goto out;
1408
1409error:
1410 return NULL;
1411out:
1412 return emif;
1413}
1414
1415#else
1416
1417static struct emif_data * __init_or_module of_get_memory_device_details(
1418 struct device_node *np_emif, struct device *dev)
1419{
1420 return NULL;
1421}
1422#endif
1423
1424static struct emif_data *__init_or_module get_device_details(
1425 struct platform_device *pdev)
1426{
1427 u32 size;
1428 struct emif_data *emif = NULL;
1429 struct ddr_device_info *dev_info;
1430 struct emif_custom_configs *cust_cfgs;
1431 struct emif_platform_data *pd;
1432 struct device *dev;
1433 void *temp;
1434
1435 pd = pdev->dev.platform_data;
1436 dev = &pdev->dev;
1437
1438 if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1439 pd->device_info->density, pd->device_info->io_width,
1440 pd->phy_type, pd->ip_rev, dev))) {
1441 dev_err(dev, "%s: invalid device data\n", __func__);
1442 goto error;
1443 }
1444
1445 emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1446 temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1447 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1448
1449 if (!emif || !pd || !dev_info) {
1450 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1451 goto error;
1452 }
1453
1454 memcpy(temp, pd, sizeof(*pd));
1455 pd = temp;
1456 memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1457
1458 pd->device_info = dev_info;
1459 emif->plat_data = pd;
1460 emif->dev = dev;
1461 emif->temperature_level = SDRAM_TEMP_NOMINAL;
1462
1463 /*
1464 * For EMIF instances other than EMIF1 see if the devices connected
1465 * are exactly same as on EMIF1(which is typically the case). If so,
1466 * mark it as a duplicate of EMIF1 and skip copying timings data.
1467 * This will save some memory and some computation later.
1468 */
1469 emif->duplicate = emif1 && (memcmp(dev_info,
1470 emif1->plat_data->device_info,
1471 sizeof(struct ddr_device_info)) == 0);
1472
1473 if (emif->duplicate) {
1474 pd->timings = NULL;
1475 pd->min_tck = NULL;
1476 goto out;
1477 } else if (emif1) {
1478 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1479 __func__);
1480 }
1481
1482 /*
1483 * Copy custom configs - ignore allocation error, if any, as
1484 * custom_configs is not very critical
1485 */
1486 cust_cfgs = pd->custom_configs;
1487 if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1488 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1489 if (temp)
1490 memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1491 else
1492 dev_warn(dev, "%s:%d: allocation error\n", __func__,
1493 __LINE__);
1494 pd->custom_configs = temp;
1495 }
1496
1497 /*
1498 * Copy timings and min-tck values from platform data. If it is not
1499 * available or if memory allocation fails, use JEDEC defaults
1500 */
1501 size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1502 if (pd->timings) {
1503 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1504 if (temp) {
1505 memcpy(temp, pd->timings, size);
1506 pd->timings = temp;
1507 } else {
1508 dev_warn(dev, "%s:%d: allocation error\n", __func__,
1509 __LINE__);
1510 get_default_timings(emif);
1511 }
1512 } else {
1513 get_default_timings(emif);
1514 }
1515
1516 if (pd->min_tck) {
1517 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1518 if (temp) {
1519 memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1520 pd->min_tck = temp;
1521 } else {
1522 dev_warn(dev, "%s:%d: allocation error\n", __func__,
1523 __LINE__);
1524 pd->min_tck = &lpddr2_jedec_min_tck;
1525 }
1526 } else {
1527 pd->min_tck = &lpddr2_jedec_min_tck;
1528 }
1529
1530out:
1531 return emif;
1532
1533error:
1534 return NULL;
1535}
1536
1537static int __init_or_module emif_probe(struct platform_device *pdev)
1538{
1539 struct emif_data *emif;
1540 struct resource *res;
1541 int irq;
1542
1543 if (pdev->dev.of_node)
1544 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1545 else
1546 emif = get_device_details(pdev);
1547
1548 if (!emif) {
1549 pr_err("%s: error getting device data\n", __func__);
1550 goto error;
1551 }
1552
1553 list_add(&emif->node, &device_list);
1554 emif->addressing = get_addressing_table(emif->plat_data->device_info);
1555
1556 /* Save pointers to each other in emif and device structures */
1557 emif->dev = &pdev->dev;
1558 platform_set_drvdata(pdev, emif);
1559
1560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1561 emif->base = devm_ioremap_resource(emif->dev, res);
1562 if (IS_ERR(emif->base))
1563 goto error;
1564
1565 irq = platform_get_irq(pdev, 0);
1566 if (irq < 0) {
1567 dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
1568 __func__, irq);
1569 goto error;
1570 }
1571
1572 emif_onetime_settings(emif);
1573 emif_debugfs_init(emif);
1574 disable_and_clear_all_interrupts(emif);
1575 setup_interrupts(emif, irq);
1576
1577 /* One-time actions taken on probing the first device */
1578 if (!emif1) {
1579 emif1 = emif;
1580 spin_lock_init(&emif_lock);
1581
1582 /*
1583 * TODO: register notifiers for frequency and voltage
1584 * change here once the respective frameworks are
1585 * available
1586 */
1587 }
1588
1589 dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1590 __func__, emif->base, irq);
1591
1592 return 0;
1593error:
1594 return -ENODEV;
1595}
1596
1597static int __exit emif_remove(struct platform_device *pdev)
1598{
1599 struct emif_data *emif = platform_get_drvdata(pdev);
1600
1601 emif_debugfs_exit(emif);
1602
1603 return 0;
1604}
1605
1606static void emif_shutdown(struct platform_device *pdev)
1607{
1608 struct emif_data *emif = platform_get_drvdata(pdev);
1609
1610 disable_and_clear_all_interrupts(emif);
1611}
1612
1613static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1614 struct emif_regs *regs)
1615{
1616 u32 cs1_used, ip_rev, phy_type;
1617 u32 cl, type;
1618 const struct lpddr2_timings *timings;
1619 const struct lpddr2_min_tck *min_tck;
1620 const struct ddr_device_info *device_info;
1621 const struct lpddr2_addressing *addressing;
1622 struct emif_data *emif_for_calc;
1623 struct device *dev;
1624 const struct emif_custom_configs *custom_configs;
1625
1626 dev = emif->dev;
1627 /*
1628 * If the devices on this EMIF instance is duplicate of EMIF1,
1629 * use EMIF1 details for the calculation
1630 */
1631 emif_for_calc = emif->duplicate ? emif1 : emif;
1632 timings = get_timings_table(emif_for_calc, freq);
1633 addressing = emif_for_calc->addressing;
1634 if (!timings || !addressing) {
1635 dev_err(dev, "%s: not enough data available for %dHz",
1636 __func__, freq);
1637 return -1;
1638 }
1639
1640 device_info = emif_for_calc->plat_data->device_info;
1641 type = device_info->type;
1642 cs1_used = device_info->cs1_used;
1643 ip_rev = emif_for_calc->plat_data->ip_rev;
1644 phy_type = emif_for_calc->plat_data->phy_type;
1645
1646 min_tck = emif_for_calc->plat_data->min_tck;
1647 custom_configs = emif_for_calc->plat_data->custom_configs;
1648
1649 set_ddr_clk_period(freq);
1650
1651 regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1652 regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1653 addressing);
1654 regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1655 addressing, type);
1656 regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1657 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1658
1659 cl = get_cl(emif);
1660
1661 if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1662 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1663 timings, freq, cl);
1664 } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1665 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1666 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1667 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1668 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1669 } else {
1670 return -1;
1671 }
1672
1673 /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1674 regs->pwr_mgmt_ctrl_shdw =
1675 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1676 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1677
1678 if (ip_rev & EMIF_4D) {
1679 regs->read_idle_ctrl_shdw_normal =
1680 get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1681
1682 regs->read_idle_ctrl_shdw_volt_ramp =
1683 get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1684 } else if (ip_rev & EMIF_4D5) {
1685 regs->dll_calib_ctrl_shdw_normal =
1686 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1687
1688 regs->dll_calib_ctrl_shdw_volt_ramp =
1689 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1690 }
1691
1692 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1693 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1694 addressing);
1695
1696 regs->sdram_tim1_shdw_derated =
1697 get_sdram_tim_1_shdw_derated(timings, min_tck,
1698 addressing);
1699
1700 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1701 min_tck, addressing, type, ip_rev,
1702 EMIF_DERATED_TIMINGS);
1703 }
1704
1705 regs->freq = freq;
1706
1707 return 0;
1708}
1709
1710/*
1711 * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1712 * given frequency(freq):
1713 *
1714 * As an optimisation, every EMIF instance other than EMIF1 shares the
1715 * register cache with EMIF1 if the devices connected on this instance
1716 * are same as that on EMIF1(indicated by the duplicate flag)
1717 *
1718 * If we do not have an entry corresponding to the frequency given, we
1719 * allocate a new entry and calculate the values
1720 *
1721 * Upon finding the right reg dump, save it in curr_regs. It can be
1722 * directly used for thermal de-rating and voltage ramping changes.
1723 */
1724static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1725{
1726 int i;
1727 struct emif_regs **regs_cache;
1728 struct emif_regs *regs = NULL;
1729 struct device *dev;
1730
1731 dev = emif->dev;
1732 if (emif->curr_regs && emif->curr_regs->freq == freq) {
1733 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1734 return emif->curr_regs;
1735 }
1736
1737 if (emif->duplicate)
1738 regs_cache = emif1->regs_cache;
1739 else
1740 regs_cache = emif->regs_cache;
1741
1742 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1743 if (regs_cache[i]->freq == freq) {
1744 regs = regs_cache[i];
1745 dev_dbg(dev,
1746 "%s: reg dump found in reg cache for %u Hz\n",
1747 __func__, freq);
1748 break;
1749 }
1750 }
1751
1752 /*
1753 * If we don't have an entry for this frequency in the cache create one
1754 * and calculate the values
1755 */
1756 if (!regs) {
1757 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1758 if (!regs)
1759 return NULL;
1760
1761 if (get_emif_reg_values(emif, freq, regs)) {
1762 devm_kfree(emif->dev, regs);
1763 return NULL;
1764 }
1765
1766 /*
1767 * Now look for an un-used entry in the cache and save the
1768 * newly created struct. If there are no free entries
1769 * over-write the last entry
1770 */
1771 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1772 ;
1773
1774 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1775 dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1776 __func__);
1777 i = EMIF_MAX_NUM_FREQUENCIES - 1;
1778 devm_kfree(emif->dev, regs_cache[i]);
1779 }
1780 regs_cache[i] = regs;
1781 }
1782
1783 return regs;
1784}
1785
1786static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1787{
1788 dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1789 volt_state);
1790
1791 if (!emif->curr_regs) {
1792 dev_err(emif->dev,
1793 "%s: volt-notify before registers are ready: %d\n",
1794 __func__, volt_state);
1795 return;
1796 }
1797
1798 setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1799}
1800
1801/*
1802 * TODO: voltage notify handling should be hooked up to
1803 * regulator framework as soon as the necessary support
1804 * is available in mainline kernel. This function is un-used
1805 * right now.
1806 */
1807static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1808{
1809 struct emif_data *emif;
1810
1811 spin_lock_irqsave(&emif_lock, irq_state);
1812
1813 list_for_each_entry(emif, &device_list, node)
1814 do_volt_notify_handling(emif, volt_state);
1815 do_freq_update();
1816
1817 spin_unlock_irqrestore(&emif_lock, irq_state);
1818}
1819
1820static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1821{
1822 struct emif_regs *regs;
1823
1824 regs = get_regs(emif, new_freq);
1825 if (!regs)
1826 return;
1827
1828 emif->curr_regs = regs;
1829
1830 /*
1831 * Update the shadow registers:
1832 * Temperature and voltage-ramp sensitive settings are also configured
1833 * in terms of DDR cycles. So, we need to update them too when there
1834 * is a freq change
1835 */
1836 dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1837 __func__, new_freq);
1838 setup_registers(emif, regs);
1839 setup_temperature_sensitive_regs(emif, regs);
1840 setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1841
1842 /*
1843 * Part of workaround for errata i728. See do_freq_update()
1844 * for more details
1845 */
1846 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1847 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1848}
1849
1850/*
1851 * TODO: frequency notify handling should be hooked up to
1852 * clock framework as soon as the necessary support is
1853 * available in mainline kernel. This function is un-used
1854 * right now.
1855 */
1856static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1857{
1858 struct emif_data *emif;
1859
1860 /*
1861 * NOTE: we are taking the spin-lock here and releases it
1862 * only in post-notifier. This doesn't look good and
1863 * Sparse complains about it, but this seems to be
1864 * un-avoidable. We need to lock a sequence of events
1865 * that is split between EMIF and clock framework.
1866 *
1867 * 1. EMIF driver updates EMIF timings in shadow registers in the
1868 * frequency pre-notify callback from clock framework
1869 * 2. clock framework sets up the registers for the new frequency
1870 * 3. clock framework initiates a hw-sequence that updates
1871 * the frequency EMIF timings synchronously.
1872 *
1873 * All these 3 steps should be performed as an atomic operation
1874 * vis-a-vis similar sequence in the EMIF interrupt handler
1875 * for temperature events. Otherwise, there could be race
1876 * conditions that could result in incorrect EMIF timings for
1877 * a given frequency
1878 */
1879 spin_lock_irqsave(&emif_lock, irq_state);
1880
1881 list_for_each_entry(emif, &device_list, node)
1882 do_freq_pre_notify_handling(emif, new_freq);
1883}
1884
1885static void do_freq_post_notify_handling(struct emif_data *emif)
1886{
1887 /*
1888 * Part of workaround for errata i728. See do_freq_update()
1889 * for more details
1890 */
1891 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1892 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1893}
1894
1895/*
1896 * TODO: frequency notify handling should be hooked up to
1897 * clock framework as soon as the necessary support is
1898 * available in mainline kernel. This function is un-used
1899 * right now.
1900 */
1901static void __attribute__((unused)) freq_post_notify_handling(void)
1902{
1903 struct emif_data *emif;
1904
1905 list_for_each_entry(emif, &device_list, node)
1906 do_freq_post_notify_handling(emif);
1907
1908 /*
1909 * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1910 * for more details
1911 */
1912 spin_unlock_irqrestore(&emif_lock, irq_state);
1913}
1914
1915#if defined(CONFIG_OF)
1916static const struct of_device_id emif_of_match[] = {
1917 { .compatible = "ti,emif-4d" },
1918 { .compatible = "ti,emif-4d5" },
1919 {},
1920};
1921MODULE_DEVICE_TABLE(of, emif_of_match);
1922#endif
1923
1924static struct platform_driver emif_driver = {
1925 .remove = __exit_p(emif_remove),
1926 .shutdown = emif_shutdown,
1927 .driver = {
1928 .name = "emif",
1929 .of_match_table = of_match_ptr(emif_of_match),
1930 },
1931};
1932
1933module_platform_driver_probe(emif_driver, emif_probe);
1934
1935MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1936MODULE_LICENSE("GPL");
1937MODULE_ALIAS("platform:emif");
1938MODULE_AUTHOR("Texas Instruments Inc");