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1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <mach/irqs.h>
28#include <mach/gpio.h>
29#include <asm/mach/irq.h>
30
31struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37 u32 suspend_wakeup;
38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup;
40#endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57 u32 width;
58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
62};
63
64#ifdef CONFIG_ARCH_OMAP3
65struct omap3_gpio_regs {
66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
76};
77
78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79#endif
80
81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
86
87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
89
90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92
93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94{
95 void __iomem *reg = bank->base;
96 u32 l;
97
98 reg += bank->regs->direction;
99 l = __raw_readl(reg);
100 if (is_input)
101 l |= 1 << gpio;
102 else
103 l &= ~(1 << gpio);
104 __raw_writel(l, reg);
105}
106
107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
110{
111 void __iomem *reg = bank->base;
112 u32 l = GPIO_BIT(bank, gpio);
113
114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
118
119 __raw_writel(l, reg);
120}
121
122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
124{
125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
128
129 l = __raw_readl(reg);
130 if (enable)
131 l |= gpio_bit;
132 else
133 l &= ~gpio_bit;
134 __raw_writel(l, reg);
135}
136
137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
138{
139 void __iomem *reg = bank->base + bank->regs->datain;
140
141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
142}
143
144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
145{
146 void __iomem *reg = bank->base + bank->regs->dataout;
147
148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
149}
150
151#define MOD_REG_BIT(reg, bit_mask, set) \
152do { \
153 int l = __raw_readl(base + reg); \
154 if (set) l |= bit_mask; \
155 else l &= ~bit_mask; \
156 __raw_writel(l, base + reg); \
157} while(0)
158
159/**
160 * _set_gpio_debounce - low level gpio debounce time
161 * @bank: the gpio bank we're acting upon
162 * @gpio: the gpio number on this @gpio
163 * @debounce: debounce time to use
164 *
165 * OMAP's debounce time is in 31us steps so we need
166 * to convert and round up to the closest unit.
167 */
168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
169 unsigned debounce)
170{
171 void __iomem *reg;
172 u32 val;
173 u32 l;
174
175 if (!bank->dbck_flag)
176 return;
177
178 if (debounce < 32)
179 debounce = 0x01;
180 else if (debounce > 7936)
181 debounce = 0xff;
182 else
183 debounce = (debounce / 0x1f) - 1;
184
185 l = GPIO_BIT(bank, gpio);
186
187 reg = bank->base + bank->regs->debounce;
188 __raw_writel(debounce, reg);
189
190 reg = bank->base + bank->regs->debounce_en;
191 val = __raw_readl(reg);
192
193 if (debounce) {
194 val |= l;
195 clk_enable(bank->dbck);
196 } else {
197 val &= ~l;
198 clk_disable(bank->dbck);
199 }
200 bank->dbck_enable_mask = val;
201
202 __raw_writel(val, reg);
203}
204
205#ifdef CONFIG_ARCH_OMAP2PLUS
206static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
207 int trigger)
208{
209 void __iomem *base = bank->base;
210 u32 gpio_bit = 1 << gpio;
211
212 if (cpu_is_omap44xx()) {
213 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
214 trigger & IRQ_TYPE_LEVEL_LOW);
215 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
216 trigger & IRQ_TYPE_LEVEL_HIGH);
217 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
218 trigger & IRQ_TYPE_EDGE_RISING);
219 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
220 trigger & IRQ_TYPE_EDGE_FALLING);
221 } else {
222 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
223 trigger & IRQ_TYPE_LEVEL_LOW);
224 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
225 trigger & IRQ_TYPE_LEVEL_HIGH);
226 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
227 trigger & IRQ_TYPE_EDGE_RISING);
228 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
229 trigger & IRQ_TYPE_EDGE_FALLING);
230 }
231 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
232 if (cpu_is_omap44xx()) {
233 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
234 trigger != 0);
235 } else {
236 /*
237 * GPIO wakeup request can only be generated on edge
238 * transitions
239 */
240 if (trigger & IRQ_TYPE_EDGE_BOTH)
241 __raw_writel(1 << gpio, bank->base
242 + OMAP24XX_GPIO_SETWKUENA);
243 else
244 __raw_writel(1 << gpio, bank->base
245 + OMAP24XX_GPIO_CLEARWKUENA);
246 }
247 }
248 /* This part needs to be executed always for OMAP{34xx, 44xx} */
249 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
250 (bank->non_wakeup_gpios & gpio_bit)) {
251 /*
252 * Log the edge gpio and manually trigger the IRQ
253 * after resume if the input level changes
254 * to avoid irq lost during PER RET/OFF mode
255 * Applies for omap2 non-wakeup gpio and all omap3 gpios
256 */
257 if (trigger & IRQ_TYPE_EDGE_BOTH)
258 bank->enabled_non_wakeup_gpios |= gpio_bit;
259 else
260 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
261 }
262
263 if (cpu_is_omap44xx()) {
264 bank->level_mask =
265 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
266 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
267 } else {
268 bank->level_mask =
269 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
270 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
271 }
272}
273#endif
274
275#ifdef CONFIG_ARCH_OMAP1
276/*
277 * This only applies to chips that can't do both rising and falling edge
278 * detection at once. For all other chips, this function is a noop.
279 */
280static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
281{
282 void __iomem *reg = bank->base;
283 u32 l = 0;
284
285 switch (bank->method) {
286 case METHOD_MPUIO:
287 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
288 break;
289#ifdef CONFIG_ARCH_OMAP15XX
290 case METHOD_GPIO_1510:
291 reg += OMAP1510_GPIO_INT_CONTROL;
292 break;
293#endif
294#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
295 case METHOD_GPIO_7XX:
296 reg += OMAP7XX_GPIO_INT_CONTROL;
297 break;
298#endif
299 default:
300 return;
301 }
302
303 l = __raw_readl(reg);
304 if ((l >> gpio) & 1)
305 l &= ~(1 << gpio);
306 else
307 l |= 1 << gpio;
308
309 __raw_writel(l, reg);
310}
311#endif
312
313static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
314{
315 void __iomem *reg = bank->base;
316 u32 l = 0;
317
318 switch (bank->method) {
319#ifdef CONFIG_ARCH_OMAP1
320 case METHOD_MPUIO:
321 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
322 l = __raw_readl(reg);
323 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
324 bank->toggle_mask |= 1 << gpio;
325 if (trigger & IRQ_TYPE_EDGE_RISING)
326 l |= 1 << gpio;
327 else if (trigger & IRQ_TYPE_EDGE_FALLING)
328 l &= ~(1 << gpio);
329 else
330 goto bad;
331 break;
332#endif
333#ifdef CONFIG_ARCH_OMAP15XX
334 case METHOD_GPIO_1510:
335 reg += OMAP1510_GPIO_INT_CONTROL;
336 l = __raw_readl(reg);
337 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
338 bank->toggle_mask |= 1 << gpio;
339 if (trigger & IRQ_TYPE_EDGE_RISING)
340 l |= 1 << gpio;
341 else if (trigger & IRQ_TYPE_EDGE_FALLING)
342 l &= ~(1 << gpio);
343 else
344 goto bad;
345 break;
346#endif
347#ifdef CONFIG_ARCH_OMAP16XX
348 case METHOD_GPIO_1610:
349 if (gpio & 0x08)
350 reg += OMAP1610_GPIO_EDGE_CTRL2;
351 else
352 reg += OMAP1610_GPIO_EDGE_CTRL1;
353 gpio &= 0x07;
354 l = __raw_readl(reg);
355 l &= ~(3 << (gpio << 1));
356 if (trigger & IRQ_TYPE_EDGE_RISING)
357 l |= 2 << (gpio << 1);
358 if (trigger & IRQ_TYPE_EDGE_FALLING)
359 l |= 1 << (gpio << 1);
360 if (trigger)
361 /* Enable wake-up during idle for dynamic tick */
362 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
363 else
364 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
365 break;
366#endif
367#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
368 case METHOD_GPIO_7XX:
369 reg += OMAP7XX_GPIO_INT_CONTROL;
370 l = __raw_readl(reg);
371 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
372 bank->toggle_mask |= 1 << gpio;
373 if (trigger & IRQ_TYPE_EDGE_RISING)
374 l |= 1 << gpio;
375 else if (trigger & IRQ_TYPE_EDGE_FALLING)
376 l &= ~(1 << gpio);
377 else
378 goto bad;
379 break;
380#endif
381#ifdef CONFIG_ARCH_OMAP2PLUS
382 case METHOD_GPIO_24XX:
383 case METHOD_GPIO_44XX:
384 set_24xx_gpio_triggering(bank, gpio, trigger);
385 return 0;
386#endif
387 default:
388 goto bad;
389 }
390 __raw_writel(l, reg);
391 return 0;
392bad:
393 return -EINVAL;
394}
395
396static int gpio_irq_type(struct irq_data *d, unsigned type)
397{
398 struct gpio_bank *bank;
399 unsigned gpio;
400 int retval;
401 unsigned long flags;
402
403 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
404 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
405 else
406 gpio = d->irq - IH_GPIO_BASE;
407
408 if (type & ~IRQ_TYPE_SENSE_MASK)
409 return -EINVAL;
410
411 /* OMAP1 allows only only edge triggering */
412 if (!cpu_class_is_omap2()
413 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
414 return -EINVAL;
415
416 bank = irq_data_get_irq_chip_data(d);
417 spin_lock_irqsave(&bank->lock, flags);
418 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
419 spin_unlock_irqrestore(&bank->lock, flags);
420
421 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
422 __irq_set_handler_locked(d->irq, handle_level_irq);
423 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
424 __irq_set_handler_locked(d->irq, handle_edge_irq);
425
426 return retval;
427}
428
429static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
430{
431 void __iomem *reg = bank->base;
432
433 reg += bank->regs->irqstatus;
434 __raw_writel(gpio_mask, reg);
435
436 /* Workaround for clearing DSP GPIO interrupts to allow retention */
437 if (bank->regs->irqstatus2) {
438 reg = bank->base + bank->regs->irqstatus2;
439 __raw_writel(gpio_mask, reg);
440 }
441
442 /* Flush posted write for the irq status to avoid spurious interrupts */
443 __raw_readl(reg);
444}
445
446static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
447{
448 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
449}
450
451static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
452{
453 void __iomem *reg = bank->base;
454 u32 l;
455 u32 mask = (1 << bank->width) - 1;
456
457 reg += bank->regs->irqenable;
458 l = __raw_readl(reg);
459 if (bank->regs->irqenable_inv)
460 l = ~l;
461 l &= mask;
462 return l;
463}
464
465static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
466{
467 void __iomem *reg = bank->base;
468 u32 l;
469
470 if (bank->regs->set_irqenable) {
471 reg += bank->regs->set_irqenable;
472 l = gpio_mask;
473 } else {
474 reg += bank->regs->irqenable;
475 l = __raw_readl(reg);
476 if (bank->regs->irqenable_inv)
477 l &= ~gpio_mask;
478 else
479 l |= gpio_mask;
480 }
481
482 __raw_writel(l, reg);
483}
484
485static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
486{
487 void __iomem *reg = bank->base;
488 u32 l;
489
490 if (bank->regs->clr_irqenable) {
491 reg += bank->regs->clr_irqenable;
492 l = gpio_mask;
493 } else {
494 reg += bank->regs->irqenable;
495 l = __raw_readl(reg);
496 if (bank->regs->irqenable_inv)
497 l |= gpio_mask;
498 else
499 l &= ~gpio_mask;
500 }
501
502 __raw_writel(l, reg);
503}
504
505static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
506{
507 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
508}
509
510/*
511 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
512 * 1510 does not seem to have a wake-up register. If JTAG is connected
513 * to the target, system will wake up always on GPIO events. While
514 * system is running all registered GPIO interrupts need to have wake-up
515 * enabled. When system is suspended, only selected GPIO interrupts need
516 * to have wake-up enabled.
517 */
518static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
519{
520 u32 gpio_bit = GPIO_BIT(bank, gpio);
521 unsigned long flags;
522
523 if (bank->non_wakeup_gpios & gpio_bit) {
524 dev_err(bank->dev,
525 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
526 return -EINVAL;
527 }
528
529 spin_lock_irqsave(&bank->lock, flags);
530 if (enable)
531 bank->suspend_wakeup |= gpio_bit;
532 else
533 bank->suspend_wakeup &= ~gpio_bit;
534
535 spin_unlock_irqrestore(&bank->lock, flags);
536
537 return 0;
538}
539
540static void _reset_gpio(struct gpio_bank *bank, int gpio)
541{
542 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
543 _set_gpio_irqenable(bank, gpio, 0);
544 _clear_gpio_irqstatus(bank, gpio);
545 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
546}
547
548/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
549static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
550{
551 unsigned int gpio = d->irq - IH_GPIO_BASE;
552 struct gpio_bank *bank;
553 int retval;
554
555 bank = irq_data_get_irq_chip_data(d);
556 retval = _set_gpio_wakeup(bank, gpio, enable);
557
558 return retval;
559}
560
561static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
562{
563 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
564 unsigned long flags;
565
566 spin_lock_irqsave(&bank->lock, flags);
567
568 /* Set trigger to none. You need to enable the desired trigger with
569 * request_irq() or set_irq_type().
570 */
571 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
572
573#ifdef CONFIG_ARCH_OMAP15XX
574 if (bank->method == METHOD_GPIO_1510) {
575 void __iomem *reg;
576
577 /* Claim the pin for MPU */
578 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
579 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
580 }
581#endif
582 if (!cpu_class_is_omap1()) {
583 if (!bank->mod_usage) {
584 void __iomem *reg = bank->base;
585 u32 ctrl;
586
587 if (cpu_is_omap24xx() || cpu_is_omap34xx())
588 reg += OMAP24XX_GPIO_CTRL;
589 else if (cpu_is_omap44xx())
590 reg += OMAP4_GPIO_CTRL;
591 ctrl = __raw_readl(reg);
592 /* Module is enabled, clocks are not gated */
593 ctrl &= 0xFFFFFFFE;
594 __raw_writel(ctrl, reg);
595 }
596 bank->mod_usage |= 1 << offset;
597 }
598 spin_unlock_irqrestore(&bank->lock, flags);
599
600 return 0;
601}
602
603static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
604{
605 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
606 unsigned long flags;
607
608 spin_lock_irqsave(&bank->lock, flags);
609#ifdef CONFIG_ARCH_OMAP16XX
610 if (bank->method == METHOD_GPIO_1610) {
611 /* Disable wake-up during idle for dynamic tick */
612 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
613 __raw_writel(1 << offset, reg);
614 }
615#endif
616#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
617 if (bank->method == METHOD_GPIO_24XX) {
618 /* Disable wake-up during idle for dynamic tick */
619 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
620 __raw_writel(1 << offset, reg);
621 }
622#endif
623#ifdef CONFIG_ARCH_OMAP4
624 if (bank->method == METHOD_GPIO_44XX) {
625 /* Disable wake-up during idle for dynamic tick */
626 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
627 __raw_writel(1 << offset, reg);
628 }
629#endif
630 if (!cpu_class_is_omap1()) {
631 bank->mod_usage &= ~(1 << offset);
632 if (!bank->mod_usage) {
633 void __iomem *reg = bank->base;
634 u32 ctrl;
635
636 if (cpu_is_omap24xx() || cpu_is_omap34xx())
637 reg += OMAP24XX_GPIO_CTRL;
638 else if (cpu_is_omap44xx())
639 reg += OMAP4_GPIO_CTRL;
640 ctrl = __raw_readl(reg);
641 /* Module is disabled, clocks are gated */
642 ctrl |= 1;
643 __raw_writel(ctrl, reg);
644 }
645 }
646 _reset_gpio(bank, bank->chip.base + offset);
647 spin_unlock_irqrestore(&bank->lock, flags);
648}
649
650/*
651 * We need to unmask the GPIO bank interrupt as soon as possible to
652 * avoid missing GPIO interrupts for other lines in the bank.
653 * Then we need to mask-read-clear-unmask the triggered GPIO lines
654 * in the bank to avoid missing nested interrupts for a GPIO line.
655 * If we wait to unmask individual GPIO lines in the bank after the
656 * line's interrupt handler has been run, we may miss some nested
657 * interrupts.
658 */
659static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
660{
661 void __iomem *isr_reg = NULL;
662 u32 isr;
663 unsigned int gpio_irq, gpio_index;
664 struct gpio_bank *bank;
665 u32 retrigger = 0;
666 int unmasked = 0;
667 struct irq_chip *chip = irq_desc_get_chip(desc);
668
669 chained_irq_enter(chip, desc);
670
671 bank = irq_get_handler_data(irq);
672 isr_reg = bank->base + bank->regs->irqstatus;
673
674 if (WARN_ON(!isr_reg))
675 goto exit;
676
677 while(1) {
678 u32 isr_saved, level_mask = 0;
679 u32 enabled;
680
681 enabled = _get_gpio_irqbank_mask(bank);
682 isr_saved = isr = __raw_readl(isr_reg) & enabled;
683
684 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
685 isr &= 0x0000ffff;
686
687 if (cpu_class_is_omap2()) {
688 level_mask = bank->level_mask & enabled;
689 }
690
691 /* clear edge sensitive interrupts before handler(s) are
692 called so that we don't miss any interrupt occurred while
693 executing them */
694 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
695 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
696 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
697
698 /* if there is only edge sensitive GPIO pin interrupts
699 configured, we could unmask GPIO bank interrupt immediately */
700 if (!level_mask && !unmasked) {
701 unmasked = 1;
702 chained_irq_exit(chip, desc);
703 }
704
705 isr |= retrigger;
706 retrigger = 0;
707 if (!isr)
708 break;
709
710 gpio_irq = bank->virtual_irq_start;
711 for (; isr != 0; isr >>= 1, gpio_irq++) {
712 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
713
714 if (!(isr & 1))
715 continue;
716
717#ifdef CONFIG_ARCH_OMAP1
718 /*
719 * Some chips can't respond to both rising and falling
720 * at the same time. If this irq was requested with
721 * both flags, we need to flip the ICR data for the IRQ
722 * to respond to the IRQ for the opposite direction.
723 * This will be indicated in the bank toggle_mask.
724 */
725 if (bank->toggle_mask & (1 << gpio_index))
726 _toggle_gpio_edge_triggering(bank, gpio_index);
727#endif
728
729 generic_handle_irq(gpio_irq);
730 }
731 }
732 /* if bank has any level sensitive GPIO pin interrupt
733 configured, we must unmask the bank interrupt only after
734 handler(s) are executed in order to avoid spurious bank
735 interrupt */
736exit:
737 if (!unmasked)
738 chained_irq_exit(chip, desc);
739}
740
741static void gpio_irq_shutdown(struct irq_data *d)
742{
743 unsigned int gpio = d->irq - IH_GPIO_BASE;
744 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
745 unsigned long flags;
746
747 spin_lock_irqsave(&bank->lock, flags);
748 _reset_gpio(bank, gpio);
749 spin_unlock_irqrestore(&bank->lock, flags);
750}
751
752static void gpio_ack_irq(struct irq_data *d)
753{
754 unsigned int gpio = d->irq - IH_GPIO_BASE;
755 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
756
757 _clear_gpio_irqstatus(bank, gpio);
758}
759
760static void gpio_mask_irq(struct irq_data *d)
761{
762 unsigned int gpio = d->irq - IH_GPIO_BASE;
763 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
764 unsigned long flags;
765
766 spin_lock_irqsave(&bank->lock, flags);
767 _set_gpio_irqenable(bank, gpio, 0);
768 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
769 spin_unlock_irqrestore(&bank->lock, flags);
770}
771
772static void gpio_unmask_irq(struct irq_data *d)
773{
774 unsigned int gpio = d->irq - IH_GPIO_BASE;
775 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
776 unsigned int irq_mask = GPIO_BIT(bank, gpio);
777 u32 trigger = irqd_get_trigger_type(d);
778 unsigned long flags;
779
780 spin_lock_irqsave(&bank->lock, flags);
781 if (trigger)
782 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
783
784 /* For level-triggered GPIOs, the clearing must be done after
785 * the HW source is cleared, thus after the handler has run */
786 if (bank->level_mask & irq_mask) {
787 _set_gpio_irqenable(bank, gpio, 0);
788 _clear_gpio_irqstatus(bank, gpio);
789 }
790
791 _set_gpio_irqenable(bank, gpio, 1);
792 spin_unlock_irqrestore(&bank->lock, flags);
793}
794
795static struct irq_chip gpio_irq_chip = {
796 .name = "GPIO",
797 .irq_shutdown = gpio_irq_shutdown,
798 .irq_ack = gpio_ack_irq,
799 .irq_mask = gpio_mask_irq,
800 .irq_unmask = gpio_unmask_irq,
801 .irq_set_type = gpio_irq_type,
802 .irq_set_wake = gpio_wake_enable,
803};
804
805/*---------------------------------------------------------------------*/
806
807#ifdef CONFIG_ARCH_OMAP1
808
809#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
810
811#ifdef CONFIG_ARCH_OMAP16XX
812
813#include <linux/platform_device.h>
814
815static int omap_mpuio_suspend_noirq(struct device *dev)
816{
817 struct platform_device *pdev = to_platform_device(dev);
818 struct gpio_bank *bank = platform_get_drvdata(pdev);
819 void __iomem *mask_reg = bank->base +
820 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
821 unsigned long flags;
822
823 spin_lock_irqsave(&bank->lock, flags);
824 bank->saved_wakeup = __raw_readl(mask_reg);
825 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
826 spin_unlock_irqrestore(&bank->lock, flags);
827
828 return 0;
829}
830
831static int omap_mpuio_resume_noirq(struct device *dev)
832{
833 struct platform_device *pdev = to_platform_device(dev);
834 struct gpio_bank *bank = platform_get_drvdata(pdev);
835 void __iomem *mask_reg = bank->base +
836 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
837 unsigned long flags;
838
839 spin_lock_irqsave(&bank->lock, flags);
840 __raw_writel(bank->saved_wakeup, mask_reg);
841 spin_unlock_irqrestore(&bank->lock, flags);
842
843 return 0;
844}
845
846static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
847 .suspend_noirq = omap_mpuio_suspend_noirq,
848 .resume_noirq = omap_mpuio_resume_noirq,
849};
850
851/* use platform_driver for this. */
852static struct platform_driver omap_mpuio_driver = {
853 .driver = {
854 .name = "mpuio",
855 .pm = &omap_mpuio_dev_pm_ops,
856 },
857};
858
859static struct platform_device omap_mpuio_device = {
860 .name = "mpuio",
861 .id = -1,
862 .dev = {
863 .driver = &omap_mpuio_driver.driver,
864 }
865 /* could list the /proc/iomem resources */
866};
867
868static inline void mpuio_init(void)
869{
870 struct gpio_bank *bank = &gpio_bank[0];
871 platform_set_drvdata(&omap_mpuio_device, bank);
872
873 if (platform_driver_register(&omap_mpuio_driver) == 0)
874 (void) platform_device_register(&omap_mpuio_device);
875}
876
877#else
878static inline void mpuio_init(void) {}
879#endif /* 16xx */
880
881#else
882
883#define bank_is_mpuio(bank) 0
884static inline void mpuio_init(void) {}
885
886#endif
887
888/*---------------------------------------------------------------------*/
889
890/* REVISIT these are stupid implementations! replace by ones that
891 * don't switch on METHOD_* and which mostly avoid spinlocks
892 */
893
894static int gpio_input(struct gpio_chip *chip, unsigned offset)
895{
896 struct gpio_bank *bank;
897 unsigned long flags;
898
899 bank = container_of(chip, struct gpio_bank, chip);
900 spin_lock_irqsave(&bank->lock, flags);
901 _set_gpio_direction(bank, offset, 1);
902 spin_unlock_irqrestore(&bank->lock, flags);
903 return 0;
904}
905
906static int gpio_is_input(struct gpio_bank *bank, int mask)
907{
908 void __iomem *reg = bank->base + bank->regs->direction;
909
910 return __raw_readl(reg) & mask;
911}
912
913static int gpio_get(struct gpio_chip *chip, unsigned offset)
914{
915 struct gpio_bank *bank;
916 void __iomem *reg;
917 int gpio;
918 u32 mask;
919
920 gpio = chip->base + offset;
921 bank = container_of(chip, struct gpio_bank, chip);
922 reg = bank->base;
923 mask = GPIO_BIT(bank, gpio);
924
925 if (gpio_is_input(bank, mask))
926 return _get_gpio_datain(bank, gpio);
927 else
928 return _get_gpio_dataout(bank, gpio);
929}
930
931static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
932{
933 struct gpio_bank *bank;
934 unsigned long flags;
935
936 bank = container_of(chip, struct gpio_bank, chip);
937 spin_lock_irqsave(&bank->lock, flags);
938 bank->set_dataout(bank, offset, value);
939 _set_gpio_direction(bank, offset, 0);
940 spin_unlock_irqrestore(&bank->lock, flags);
941 return 0;
942}
943
944static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
945 unsigned debounce)
946{
947 struct gpio_bank *bank;
948 unsigned long flags;
949
950 bank = container_of(chip, struct gpio_bank, chip);
951
952 if (!bank->dbck) {
953 bank->dbck = clk_get(bank->dev, "dbclk");
954 if (IS_ERR(bank->dbck))
955 dev_err(bank->dev, "Could not get gpio dbck\n");
956 }
957
958 spin_lock_irqsave(&bank->lock, flags);
959 _set_gpio_debounce(bank, offset, debounce);
960 spin_unlock_irqrestore(&bank->lock, flags);
961
962 return 0;
963}
964
965static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
966{
967 struct gpio_bank *bank;
968 unsigned long flags;
969
970 bank = container_of(chip, struct gpio_bank, chip);
971 spin_lock_irqsave(&bank->lock, flags);
972 bank->set_dataout(bank, offset, value);
973 spin_unlock_irqrestore(&bank->lock, flags);
974}
975
976static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
977{
978 struct gpio_bank *bank;
979
980 bank = container_of(chip, struct gpio_bank, chip);
981 return bank->virtual_irq_start + offset;
982}
983
984/*---------------------------------------------------------------------*/
985
986static void __init omap_gpio_show_rev(struct gpio_bank *bank)
987{
988 static bool called;
989 u32 rev;
990
991 if (called || bank->regs->revision == USHRT_MAX)
992 return;
993
994 rev = __raw_readw(bank->base + bank->regs->revision);
995 pr_info("OMAP GPIO hardware version %d.%d\n",
996 (rev >> 4) & 0x0f, rev & 0x0f);
997
998 called = true;
999}
1000
1001/* This lock class tells lockdep that GPIO irqs are in a different
1002 * category than their parents, so it won't report false recursion.
1003 */
1004static struct lock_class_key gpio_lock_class;
1005
1006static inline int init_gpio_info(struct platform_device *pdev)
1007{
1008 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1009 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1010 GFP_KERNEL);
1011 if (!gpio_bank) {
1012 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1013 return -ENOMEM;
1014 }
1015 return 0;
1016}
1017
1018/* TODO: Cleanup cpu_is_* checks */
1019static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1020{
1021 if (cpu_class_is_omap2()) {
1022 if (cpu_is_omap44xx()) {
1023 __raw_writel(0xffffffff, bank->base +
1024 OMAP4_GPIO_IRQSTATUSCLR0);
1025 __raw_writel(0x00000000, bank->base +
1026 OMAP4_GPIO_DEBOUNCENABLE);
1027 /* Initialize interface clk ungated, module enabled */
1028 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1029 } else if (cpu_is_omap34xx()) {
1030 __raw_writel(0x00000000, bank->base +
1031 OMAP24XX_GPIO_IRQENABLE1);
1032 __raw_writel(0xffffffff, bank->base +
1033 OMAP24XX_GPIO_IRQSTATUS1);
1034 __raw_writel(0x00000000, bank->base +
1035 OMAP24XX_GPIO_DEBOUNCE_EN);
1036
1037 /* Initialize interface clk ungated, module enabled */
1038 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1039 } else if (cpu_is_omap24xx()) {
1040 static const u32 non_wakeup_gpios[] = {
1041 0xe203ffc0, 0x08700040
1042 };
1043 if (id < ARRAY_SIZE(non_wakeup_gpios))
1044 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1045 }
1046 } else if (cpu_class_is_omap1()) {
1047 if (bank_is_mpuio(bank))
1048 __raw_writew(0xffff, bank->base +
1049 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1050 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1051 __raw_writew(0xffff, bank->base
1052 + OMAP1510_GPIO_INT_MASK);
1053 __raw_writew(0x0000, bank->base
1054 + OMAP1510_GPIO_INT_STATUS);
1055 }
1056 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1057 __raw_writew(0x0000, bank->base
1058 + OMAP1610_GPIO_IRQENABLE1);
1059 __raw_writew(0xffff, bank->base
1060 + OMAP1610_GPIO_IRQSTATUS1);
1061 __raw_writew(0x0014, bank->base
1062 + OMAP1610_GPIO_SYSCONFIG);
1063
1064 /*
1065 * Enable system clock for GPIO module.
1066 * The CAM_CLK_CTRL *is* really the right place.
1067 */
1068 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1069 ULPD_CAM_CLK_CTRL);
1070 }
1071 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1072 __raw_writel(0xffffffff, bank->base
1073 + OMAP7XX_GPIO_INT_MASK);
1074 __raw_writel(0x00000000, bank->base
1075 + OMAP7XX_GPIO_INT_STATUS);
1076 }
1077 }
1078}
1079
1080static __init void
1081omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1082 unsigned int num)
1083{
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086
1087 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1088 handle_simple_irq);
1089 ct = gc->chip_types;
1090
1091 /* NOTE: No ack required, reading IRQ status clears it. */
1092 ct->chip.irq_mask = irq_gc_mask_set_bit;
1093 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1094 ct->chip.irq_set_type = gpio_irq_type;
1095 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1096 if (cpu_is_omap16xx())
1097 ct->chip.irq_set_wake = gpio_wake_enable,
1098
1099 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1100 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1101 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1102}
1103
1104static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1105{
1106 int j;
1107 static int gpio;
1108
1109 bank->mod_usage = 0;
1110 /*
1111 * REVISIT eventually switch from OMAP-specific gpio structs
1112 * over to the generic ones
1113 */
1114 bank->chip.request = omap_gpio_request;
1115 bank->chip.free = omap_gpio_free;
1116 bank->chip.direction_input = gpio_input;
1117 bank->chip.get = gpio_get;
1118 bank->chip.direction_output = gpio_output;
1119 bank->chip.set_debounce = gpio_debounce;
1120 bank->chip.set = gpio_set;
1121 bank->chip.to_irq = gpio_2irq;
1122 if (bank_is_mpuio(bank)) {
1123 bank->chip.label = "mpuio";
1124#ifdef CONFIG_ARCH_OMAP16XX
1125 bank->chip.dev = &omap_mpuio_device.dev;
1126#endif
1127 bank->chip.base = OMAP_MPUIO(0);
1128 } else {
1129 bank->chip.label = "gpio";
1130 bank->chip.base = gpio;
1131 gpio += bank->width;
1132 }
1133 bank->chip.ngpio = bank->width;
1134
1135 gpiochip_add(&bank->chip);
1136
1137 for (j = bank->virtual_irq_start;
1138 j < bank->virtual_irq_start + bank->width; j++) {
1139 irq_set_lockdep_class(j, &gpio_lock_class);
1140 irq_set_chip_data(j, bank);
1141 if (bank_is_mpuio(bank)) {
1142 omap_mpuio_alloc_gc(bank, j, bank->width);
1143 } else {
1144 irq_set_chip(j, &gpio_irq_chip);
1145 irq_set_handler(j, handle_simple_irq);
1146 set_irq_flags(j, IRQF_VALID);
1147 }
1148 }
1149 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1150 irq_set_handler_data(bank->irq, bank);
1151}
1152
1153static int __devinit omap_gpio_probe(struct platform_device *pdev)
1154{
1155 static int gpio_init_done;
1156 struct omap_gpio_platform_data *pdata;
1157 struct resource *res;
1158 int id;
1159 struct gpio_bank *bank;
1160
1161 if (!pdev->dev.platform_data)
1162 return -EINVAL;
1163
1164 pdata = pdev->dev.platform_data;
1165
1166 if (!gpio_init_done) {
1167 int ret;
1168
1169 ret = init_gpio_info(pdev);
1170 if (ret)
1171 return ret;
1172 }
1173
1174 id = pdev->id;
1175 bank = &gpio_bank[id];
1176
1177 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1178 if (unlikely(!res)) {
1179 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1180 return -ENODEV;
1181 }
1182
1183 bank->irq = res->start;
1184 bank->virtual_irq_start = pdata->virtual_irq_start;
1185 bank->method = pdata->bank_type;
1186 bank->dev = &pdev->dev;
1187 bank->dbck_flag = pdata->dbck_flag;
1188 bank->stride = pdata->bank_stride;
1189 bank->width = pdata->bank_width;
1190
1191 bank->regs = pdata->regs;
1192
1193 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1194 bank->set_dataout = _set_gpio_dataout_reg;
1195 else
1196 bank->set_dataout = _set_gpio_dataout_mask;
1197
1198 spin_lock_init(&bank->lock);
1199
1200 /* Static mapping, never released */
1201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1202 if (unlikely(!res)) {
1203 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1204 return -ENODEV;
1205 }
1206
1207 bank->base = ioremap(res->start, resource_size(res));
1208 if (!bank->base) {
1209 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1210 return -ENOMEM;
1211 }
1212
1213 pm_runtime_enable(bank->dev);
1214 pm_runtime_get_sync(bank->dev);
1215
1216 omap_gpio_mod_init(bank, id);
1217 omap_gpio_chip_init(bank);
1218 omap_gpio_show_rev(bank);
1219
1220 if (!gpio_init_done)
1221 gpio_init_done = 1;
1222
1223 return 0;
1224}
1225
1226#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1227static int omap_gpio_suspend(void)
1228{
1229 int i;
1230
1231 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1232 return 0;
1233
1234 for (i = 0; i < gpio_bank_count; i++) {
1235 struct gpio_bank *bank = &gpio_bank[i];
1236 void __iomem *wake_status;
1237 void __iomem *wake_clear;
1238 void __iomem *wake_set;
1239 unsigned long flags;
1240
1241 switch (bank->method) {
1242#ifdef CONFIG_ARCH_OMAP16XX
1243 case METHOD_GPIO_1610:
1244 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1245 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1246 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1247 break;
1248#endif
1249#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1250 case METHOD_GPIO_24XX:
1251 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1252 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1253 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1254 break;
1255#endif
1256#ifdef CONFIG_ARCH_OMAP4
1257 case METHOD_GPIO_44XX:
1258 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1259 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1260 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1261 break;
1262#endif
1263 default:
1264 continue;
1265 }
1266
1267 spin_lock_irqsave(&bank->lock, flags);
1268 bank->saved_wakeup = __raw_readl(wake_status);
1269 __raw_writel(0xffffffff, wake_clear);
1270 __raw_writel(bank->suspend_wakeup, wake_set);
1271 spin_unlock_irqrestore(&bank->lock, flags);
1272 }
1273
1274 return 0;
1275}
1276
1277static void omap_gpio_resume(void)
1278{
1279 int i;
1280
1281 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1282 return;
1283
1284 for (i = 0; i < gpio_bank_count; i++) {
1285 struct gpio_bank *bank = &gpio_bank[i];
1286 void __iomem *wake_clear;
1287 void __iomem *wake_set;
1288 unsigned long flags;
1289
1290 switch (bank->method) {
1291#ifdef CONFIG_ARCH_OMAP16XX
1292 case METHOD_GPIO_1610:
1293 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1294 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1295 break;
1296#endif
1297#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1298 case METHOD_GPIO_24XX:
1299 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1300 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1301 break;
1302#endif
1303#ifdef CONFIG_ARCH_OMAP4
1304 case METHOD_GPIO_44XX:
1305 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1306 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1307 break;
1308#endif
1309 default:
1310 continue;
1311 }
1312
1313 spin_lock_irqsave(&bank->lock, flags);
1314 __raw_writel(0xffffffff, wake_clear);
1315 __raw_writel(bank->saved_wakeup, wake_set);
1316 spin_unlock_irqrestore(&bank->lock, flags);
1317 }
1318}
1319
1320static struct syscore_ops omap_gpio_syscore_ops = {
1321 .suspend = omap_gpio_suspend,
1322 .resume = omap_gpio_resume,
1323};
1324
1325#endif
1326
1327#ifdef CONFIG_ARCH_OMAP2PLUS
1328
1329static int workaround_enabled;
1330
1331void omap2_gpio_prepare_for_idle(int off_mode)
1332{
1333 int i, c = 0;
1334 int min = 0;
1335
1336 if (cpu_is_omap34xx())
1337 min = 1;
1338
1339 for (i = min; i < gpio_bank_count; i++) {
1340 struct gpio_bank *bank = &gpio_bank[i];
1341 u32 l1 = 0, l2 = 0;
1342 int j;
1343
1344 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1345 clk_disable(bank->dbck);
1346
1347 if (!off_mode)
1348 continue;
1349
1350 /* If going to OFF, remove triggering for all
1351 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1352 * generated. See OMAP2420 Errata item 1.101. */
1353 if (!(bank->enabled_non_wakeup_gpios))
1354 continue;
1355
1356 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1357 bank->saved_datain = __raw_readl(bank->base +
1358 OMAP24XX_GPIO_DATAIN);
1359 l1 = __raw_readl(bank->base +
1360 OMAP24XX_GPIO_FALLINGDETECT);
1361 l2 = __raw_readl(bank->base +
1362 OMAP24XX_GPIO_RISINGDETECT);
1363 }
1364
1365 if (cpu_is_omap44xx()) {
1366 bank->saved_datain = __raw_readl(bank->base +
1367 OMAP4_GPIO_DATAIN);
1368 l1 = __raw_readl(bank->base +
1369 OMAP4_GPIO_FALLINGDETECT);
1370 l2 = __raw_readl(bank->base +
1371 OMAP4_GPIO_RISINGDETECT);
1372 }
1373
1374 bank->saved_fallingdetect = l1;
1375 bank->saved_risingdetect = l2;
1376 l1 &= ~bank->enabled_non_wakeup_gpios;
1377 l2 &= ~bank->enabled_non_wakeup_gpios;
1378
1379 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1380 __raw_writel(l1, bank->base +
1381 OMAP24XX_GPIO_FALLINGDETECT);
1382 __raw_writel(l2, bank->base +
1383 OMAP24XX_GPIO_RISINGDETECT);
1384 }
1385
1386 if (cpu_is_omap44xx()) {
1387 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1388 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1389 }
1390
1391 c++;
1392 }
1393 if (!c) {
1394 workaround_enabled = 0;
1395 return;
1396 }
1397 workaround_enabled = 1;
1398}
1399
1400void omap2_gpio_resume_after_idle(void)
1401{
1402 int i;
1403 int min = 0;
1404
1405 if (cpu_is_omap34xx())
1406 min = 1;
1407 for (i = min; i < gpio_bank_count; i++) {
1408 struct gpio_bank *bank = &gpio_bank[i];
1409 u32 l = 0, gen, gen0, gen1;
1410 int j;
1411
1412 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1413 clk_enable(bank->dbck);
1414
1415 if (!workaround_enabled)
1416 continue;
1417
1418 if (!(bank->enabled_non_wakeup_gpios))
1419 continue;
1420
1421 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1422 __raw_writel(bank->saved_fallingdetect,
1423 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1424 __raw_writel(bank->saved_risingdetect,
1425 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1426 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1427 }
1428
1429 if (cpu_is_omap44xx()) {
1430 __raw_writel(bank->saved_fallingdetect,
1431 bank->base + OMAP4_GPIO_FALLINGDETECT);
1432 __raw_writel(bank->saved_risingdetect,
1433 bank->base + OMAP4_GPIO_RISINGDETECT);
1434 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1435 }
1436
1437 /* Check if any of the non-wakeup interrupt GPIOs have changed
1438 * state. If so, generate an IRQ by software. This is
1439 * horribly racy, but it's the best we can do to work around
1440 * this silicon bug. */
1441 l ^= bank->saved_datain;
1442 l &= bank->enabled_non_wakeup_gpios;
1443
1444 /*
1445 * No need to generate IRQs for the rising edge for gpio IRQs
1446 * configured with falling edge only; and vice versa.
1447 */
1448 gen0 = l & bank->saved_fallingdetect;
1449 gen0 &= bank->saved_datain;
1450
1451 gen1 = l & bank->saved_risingdetect;
1452 gen1 &= ~(bank->saved_datain);
1453
1454 /* FIXME: Consider GPIO IRQs with level detections properly! */
1455 gen = l & (~(bank->saved_fallingdetect) &
1456 ~(bank->saved_risingdetect));
1457 /* Consider all GPIO IRQs needed to be updated */
1458 gen |= gen0 | gen1;
1459
1460 if (gen) {
1461 u32 old0, old1;
1462
1463 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1464 old0 = __raw_readl(bank->base +
1465 OMAP24XX_GPIO_LEVELDETECT0);
1466 old1 = __raw_readl(bank->base +
1467 OMAP24XX_GPIO_LEVELDETECT1);
1468 __raw_writel(old0 | gen, bank->base +
1469 OMAP24XX_GPIO_LEVELDETECT0);
1470 __raw_writel(old1 | gen, bank->base +
1471 OMAP24XX_GPIO_LEVELDETECT1);
1472 __raw_writel(old0, bank->base +
1473 OMAP24XX_GPIO_LEVELDETECT0);
1474 __raw_writel(old1, bank->base +
1475 OMAP24XX_GPIO_LEVELDETECT1);
1476 }
1477
1478 if (cpu_is_omap44xx()) {
1479 old0 = __raw_readl(bank->base +
1480 OMAP4_GPIO_LEVELDETECT0);
1481 old1 = __raw_readl(bank->base +
1482 OMAP4_GPIO_LEVELDETECT1);
1483 __raw_writel(old0 | l, bank->base +
1484 OMAP4_GPIO_LEVELDETECT0);
1485 __raw_writel(old1 | l, bank->base +
1486 OMAP4_GPIO_LEVELDETECT1);
1487 __raw_writel(old0, bank->base +
1488 OMAP4_GPIO_LEVELDETECT0);
1489 __raw_writel(old1, bank->base +
1490 OMAP4_GPIO_LEVELDETECT1);
1491 }
1492 }
1493 }
1494
1495}
1496
1497#endif
1498
1499#ifdef CONFIG_ARCH_OMAP3
1500/* save the registers of bank 2-6 */
1501void omap_gpio_save_context(void)
1502{
1503 int i;
1504
1505 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1506 for (i = 1; i < gpio_bank_count; i++) {
1507 struct gpio_bank *bank = &gpio_bank[i];
1508 gpio_context[i].irqenable1 =
1509 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1510 gpio_context[i].irqenable2 =
1511 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1512 gpio_context[i].wake_en =
1513 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1514 gpio_context[i].ctrl =
1515 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1516 gpio_context[i].oe =
1517 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1518 gpio_context[i].leveldetect0 =
1519 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1520 gpio_context[i].leveldetect1 =
1521 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1522 gpio_context[i].risingdetect =
1523 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1524 gpio_context[i].fallingdetect =
1525 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1526 gpio_context[i].dataout =
1527 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1528 }
1529}
1530
1531/* restore the required registers of bank 2-6 */
1532void omap_gpio_restore_context(void)
1533{
1534 int i;
1535
1536 for (i = 1; i < gpio_bank_count; i++) {
1537 struct gpio_bank *bank = &gpio_bank[i];
1538 __raw_writel(gpio_context[i].irqenable1,
1539 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1540 __raw_writel(gpio_context[i].irqenable2,
1541 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1542 __raw_writel(gpio_context[i].wake_en,
1543 bank->base + OMAP24XX_GPIO_WAKE_EN);
1544 __raw_writel(gpio_context[i].ctrl,
1545 bank->base + OMAP24XX_GPIO_CTRL);
1546 __raw_writel(gpio_context[i].oe,
1547 bank->base + OMAP24XX_GPIO_OE);
1548 __raw_writel(gpio_context[i].leveldetect0,
1549 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1550 __raw_writel(gpio_context[i].leveldetect1,
1551 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1552 __raw_writel(gpio_context[i].risingdetect,
1553 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1554 __raw_writel(gpio_context[i].fallingdetect,
1555 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1556 __raw_writel(gpio_context[i].dataout,
1557 bank->base + OMAP24XX_GPIO_DATAOUT);
1558 }
1559}
1560#endif
1561
1562static struct platform_driver omap_gpio_driver = {
1563 .probe = omap_gpio_probe,
1564 .driver = {
1565 .name = "omap_gpio",
1566 },
1567};
1568
1569/*
1570 * gpio driver register needs to be done before
1571 * machine_init functions access gpio APIs.
1572 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1573 */
1574static int __init omap_gpio_drv_reg(void)
1575{
1576 return platform_driver_register(&omap_gpio_driver);
1577}
1578postcore_initcall(omap_gpio_drv_reg);
1579
1580static int __init omap_gpio_sysinit(void)
1581{
1582 mpuio_init();
1583
1584#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1585 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1586 register_syscore_ops(&omap_gpio_syscore_ops);
1587#endif
1588
1589 return 0;
1590}
1591
1592arch_initcall(omap_gpio_sysinit);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support functions for OMAP GPIO
4 *
5 * Copyright (C) 2003-2005 Nokia Corporation
6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/syscore_ops.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/cpu_pm.h>
20#include <linux/device.h>
21#include <linux/pm_runtime.h>
22#include <linux/pm.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/gpio/driver.h>
26#include <linux/bitops.h>
27#include <linux/platform_data/gpio-omap.h>
28
29#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
30
31struct gpio_regs {
32 u32 irqenable1;
33 u32 irqenable2;
34 u32 wake_en;
35 u32 ctrl;
36 u32 oe;
37 u32 leveldetect0;
38 u32 leveldetect1;
39 u32 risingdetect;
40 u32 fallingdetect;
41 u32 dataout;
42 u32 debounce;
43 u32 debounce_en;
44};
45
46struct gpio_bank {
47 void __iomem *base;
48 const struct omap_gpio_reg_offs *regs;
49
50 int irq;
51 u32 non_wakeup_gpios;
52 u32 enabled_non_wakeup_gpios;
53 struct gpio_regs context;
54 u32 saved_datain;
55 u32 level_mask;
56 u32 toggle_mask;
57 raw_spinlock_t lock;
58 raw_spinlock_t wa_lock;
59 struct gpio_chip chip;
60 struct clk *dbck;
61 struct notifier_block nb;
62 unsigned int is_suspended:1;
63 u32 mod_usage;
64 u32 irq_usage;
65 u32 dbck_enable_mask;
66 bool dbck_enabled;
67 bool is_mpuio;
68 bool dbck_flag;
69 bool loses_context;
70 bool context_valid;
71 int stride;
72 u32 width;
73 int context_loss_count;
74
75 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
76 int (*get_context_loss_count)(struct device *dev);
77};
78
79#define GPIO_MOD_CTRL_BIT BIT(0)
80
81#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
82#define LINE_USED(line, offset) (line & (BIT(offset)))
83
84static void omap_gpio_unmask_irq(struct irq_data *d);
85
86static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
87{
88 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
89 return gpiochip_get_data(chip);
90}
91
92static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
93{
94 u32 val = readl_relaxed(reg);
95
96 if (set)
97 val |= mask;
98 else
99 val &= ~mask;
100
101 writel_relaxed(val, reg);
102
103 return val;
104}
105
106static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
107 int is_input)
108{
109 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
110 BIT(gpio), is_input);
111}
112
113
114/* set data out value using dedicate set/clear register */
115static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
116 int enable)
117{
118 void __iomem *reg = bank->base;
119 u32 l = BIT(offset);
120
121 if (enable) {
122 reg += bank->regs->set_dataout;
123 bank->context.dataout |= l;
124 } else {
125 reg += bank->regs->clr_dataout;
126 bank->context.dataout &= ~l;
127 }
128
129 writel_relaxed(l, reg);
130}
131
132/* set data out value using mask register */
133static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
134 int enable)
135{
136 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
137 BIT(offset), enable);
138}
139
140static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
141{
142 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
143 clk_enable(bank->dbck);
144 bank->dbck_enabled = true;
145
146 writel_relaxed(bank->dbck_enable_mask,
147 bank->base + bank->regs->debounce_en);
148 }
149}
150
151static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
152{
153 if (bank->dbck_enable_mask && bank->dbck_enabled) {
154 /*
155 * Disable debounce before cutting it's clock. If debounce is
156 * enabled but the clock is not, GPIO module seems to be unable
157 * to detect events and generate interrupts at least on OMAP3.
158 */
159 writel_relaxed(0, bank->base + bank->regs->debounce_en);
160
161 clk_disable(bank->dbck);
162 bank->dbck_enabled = false;
163 }
164}
165
166/**
167 * omap2_set_gpio_debounce - low level gpio debounce time
168 * @bank: the gpio bank we're acting upon
169 * @offset: the gpio number on this @bank
170 * @debounce: debounce time to use
171 *
172 * OMAP's debounce time is in 31us steps
173 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
174 * so we need to convert and round up to the closest unit.
175 *
176 * Return: 0 on success, negative error otherwise.
177 */
178static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
179 unsigned debounce)
180{
181 u32 val;
182 u32 l;
183 bool enable = !!debounce;
184
185 if (!bank->dbck_flag)
186 return -ENOTSUPP;
187
188 if (enable) {
189 debounce = DIV_ROUND_UP(debounce, 31) - 1;
190 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
191 return -EINVAL;
192 }
193
194 l = BIT(offset);
195
196 clk_enable(bank->dbck);
197 writel_relaxed(debounce, bank->base + bank->regs->debounce);
198
199 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
200 bank->dbck_enable_mask = val;
201
202 clk_disable(bank->dbck);
203 /*
204 * Enable debounce clock per module.
205 * This call is mandatory because in omap_gpio_request() when
206 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
207 * runtime callbck fails to turn on dbck because dbck_enable_mask
208 * used within _gpio_dbck_enable() is still not initialized at
209 * that point. Therefore we have to enable dbck here.
210 */
211 omap_gpio_dbck_enable(bank);
212 if (bank->dbck_enable_mask) {
213 bank->context.debounce = debounce;
214 bank->context.debounce_en = val;
215 }
216
217 return 0;
218}
219
220/**
221 * omap_clear_gpio_debounce - clear debounce settings for a gpio
222 * @bank: the gpio bank we're acting upon
223 * @offset: the gpio number on this @bank
224 *
225 * If a gpio is using debounce, then clear the debounce enable bit and if
226 * this is the only gpio in this bank using debounce, then clear the debounce
227 * time too. The debounce clock will also be disabled when calling this function
228 * if this is the only gpio in the bank using debounce.
229 */
230static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
231{
232 u32 gpio_bit = BIT(offset);
233
234 if (!bank->dbck_flag)
235 return;
236
237 if (!(bank->dbck_enable_mask & gpio_bit))
238 return;
239
240 bank->dbck_enable_mask &= ~gpio_bit;
241 bank->context.debounce_en &= ~gpio_bit;
242 writel_relaxed(bank->context.debounce_en,
243 bank->base + bank->regs->debounce_en);
244
245 if (!bank->dbck_enable_mask) {
246 bank->context.debounce = 0;
247 writel_relaxed(bank->context.debounce, bank->base +
248 bank->regs->debounce);
249 clk_disable(bank->dbck);
250 bank->dbck_enabled = false;
251 }
252}
253
254/*
255 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
256 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
257 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
258 * are capable waking up the system from off mode.
259 */
260static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
261{
262 u32 no_wake = bank->non_wakeup_gpios;
263
264 if (no_wake)
265 return !!(~no_wake & gpio_mask);
266
267 return false;
268}
269
270static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
271 unsigned trigger)
272{
273 void __iomem *base = bank->base;
274 u32 gpio_bit = BIT(gpio);
275
276 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
277 trigger & IRQ_TYPE_LEVEL_LOW);
278 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
279 trigger & IRQ_TYPE_LEVEL_HIGH);
280
281 /*
282 * We need the edge detection enabled for to allow the GPIO block
283 * to be woken from idle state. Set the appropriate edge detection
284 * in addition to the level detection.
285 */
286 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
287 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
288 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
289 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
290
291 bank->context.leveldetect0 =
292 readl_relaxed(bank->base + bank->regs->leveldetect0);
293 bank->context.leveldetect1 =
294 readl_relaxed(bank->base + bank->regs->leveldetect1);
295 bank->context.risingdetect =
296 readl_relaxed(bank->base + bank->regs->risingdetect);
297 bank->context.fallingdetect =
298 readl_relaxed(bank->base + bank->regs->fallingdetect);
299
300 bank->level_mask = bank->context.leveldetect0 |
301 bank->context.leveldetect1;
302
303 /* This part needs to be executed always for OMAP{34xx, 44xx} */
304 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
305 /*
306 * Log the edge gpio and manually trigger the IRQ
307 * after resume if the input level changes
308 * to avoid irq lost during PER RET/OFF mode
309 * Applies for omap2 non-wakeup gpio and all omap3 gpios
310 */
311 if (trigger & IRQ_TYPE_EDGE_BOTH)
312 bank->enabled_non_wakeup_gpios |= gpio_bit;
313 else
314 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
315 }
316}
317
318/*
319 * This only applies to chips that can't do both rising and falling edge
320 * detection at once. For all other chips, this function is a noop.
321 */
322static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
323{
324 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
325 void __iomem *reg = bank->base + bank->regs->irqctrl;
326
327 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
328 }
329}
330
331static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
332 unsigned trigger)
333{
334 void __iomem *reg = bank->base;
335 u32 l = 0;
336
337 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
338 omap_set_gpio_trigger(bank, gpio, trigger);
339 } else if (bank->regs->irqctrl) {
340 reg += bank->regs->irqctrl;
341
342 l = readl_relaxed(reg);
343 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
344 bank->toggle_mask |= BIT(gpio);
345 if (trigger & IRQ_TYPE_EDGE_RISING)
346 l |= BIT(gpio);
347 else if (trigger & IRQ_TYPE_EDGE_FALLING)
348 l &= ~(BIT(gpio));
349 else
350 return -EINVAL;
351
352 writel_relaxed(l, reg);
353 } else if (bank->regs->edgectrl1) {
354 if (gpio & 0x08)
355 reg += bank->regs->edgectrl2;
356 else
357 reg += bank->regs->edgectrl1;
358
359 gpio &= 0x07;
360 l = readl_relaxed(reg);
361 l &= ~(3 << (gpio << 1));
362 if (trigger & IRQ_TYPE_EDGE_RISING)
363 l |= 2 << (gpio << 1);
364 if (trigger & IRQ_TYPE_EDGE_FALLING)
365 l |= BIT(gpio << 1);
366 writel_relaxed(l, reg);
367 }
368 return 0;
369}
370
371static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
372{
373 if (bank->regs->pinctrl) {
374 void __iomem *reg = bank->base + bank->regs->pinctrl;
375
376 /* Claim the pin for MPU */
377 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
378 }
379
380 if (bank->regs->ctrl && !BANK_USED(bank)) {
381 void __iomem *reg = bank->base + bank->regs->ctrl;
382 u32 ctrl;
383
384 ctrl = readl_relaxed(reg);
385 /* Module is enabled, clocks are not gated */
386 ctrl &= ~GPIO_MOD_CTRL_BIT;
387 writel_relaxed(ctrl, reg);
388 bank->context.ctrl = ctrl;
389 }
390}
391
392static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
393{
394 if (bank->regs->ctrl && !BANK_USED(bank)) {
395 void __iomem *reg = bank->base + bank->regs->ctrl;
396 u32 ctrl;
397
398 ctrl = readl_relaxed(reg);
399 /* Module is disabled, clocks are gated */
400 ctrl |= GPIO_MOD_CTRL_BIT;
401 writel_relaxed(ctrl, reg);
402 bank->context.ctrl = ctrl;
403 }
404}
405
406static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
407{
408 void __iomem *reg = bank->base + bank->regs->direction;
409
410 return readl_relaxed(reg) & BIT(offset);
411}
412
413static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
414{
415 if (!LINE_USED(bank->mod_usage, offset)) {
416 omap_enable_gpio_module(bank, offset);
417 omap_set_gpio_direction(bank, offset, 1);
418 }
419 bank->irq_usage |= BIT(offset);
420}
421
422static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
423{
424 struct gpio_bank *bank = omap_irq_data_get_bank(d);
425 int retval;
426 unsigned long flags;
427 unsigned offset = d->hwirq;
428
429 if (type & ~IRQ_TYPE_SENSE_MASK)
430 return -EINVAL;
431
432 if (!bank->regs->leveldetect0 &&
433 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
434 return -EINVAL;
435
436 raw_spin_lock_irqsave(&bank->lock, flags);
437 retval = omap_set_gpio_triggering(bank, offset, type);
438 if (retval) {
439 raw_spin_unlock_irqrestore(&bank->lock, flags);
440 goto error;
441 }
442 omap_gpio_init_irq(bank, offset);
443 if (!omap_gpio_is_input(bank, offset)) {
444 raw_spin_unlock_irqrestore(&bank->lock, flags);
445 retval = -EINVAL;
446 goto error;
447 }
448 raw_spin_unlock_irqrestore(&bank->lock, flags);
449
450 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
451 irq_set_handler_locked(d, handle_level_irq);
452 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
453 /*
454 * Edge IRQs are already cleared/acked in irq_handler and
455 * not need to be masked, as result handle_edge_irq()
456 * logic is excessed here and may cause lose of interrupts.
457 * So just use handle_simple_irq.
458 */
459 irq_set_handler_locked(d, handle_simple_irq);
460
461 return 0;
462
463error:
464 return retval;
465}
466
467static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
468{
469 void __iomem *reg = bank->base;
470
471 reg += bank->regs->irqstatus;
472 writel_relaxed(gpio_mask, reg);
473
474 /* Workaround for clearing DSP GPIO interrupts to allow retention */
475 if (bank->regs->irqstatus2) {
476 reg = bank->base + bank->regs->irqstatus2;
477 writel_relaxed(gpio_mask, reg);
478 }
479
480 /* Flush posted write for the irq status to avoid spurious interrupts */
481 readl_relaxed(reg);
482}
483
484static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
485 unsigned offset)
486{
487 omap_clear_gpio_irqbank(bank, BIT(offset));
488}
489
490static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
491{
492 void __iomem *reg = bank->base;
493 u32 l;
494 u32 mask = (BIT(bank->width)) - 1;
495
496 reg += bank->regs->irqenable;
497 l = readl_relaxed(reg);
498 if (bank->regs->irqenable_inv)
499 l = ~l;
500 l &= mask;
501 return l;
502}
503
504static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
505 unsigned offset, int enable)
506{
507 void __iomem *reg = bank->base;
508 u32 gpio_mask = BIT(offset);
509
510 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
511 if (enable) {
512 reg += bank->regs->set_irqenable;
513 bank->context.irqenable1 |= gpio_mask;
514 } else {
515 reg += bank->regs->clr_irqenable;
516 bank->context.irqenable1 &= ~gpio_mask;
517 }
518 writel_relaxed(gpio_mask, reg);
519 } else {
520 bank->context.irqenable1 =
521 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
522 enable ^ bank->regs->irqenable_inv);
523 }
524
525 /*
526 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
527 * note requiring correlation between the IRQ enable registers and
528 * the wakeup registers. In any case, we want wakeup from idle
529 * enabled for the GPIOs which support this feature.
530 */
531 if (bank->regs->wkup_en &&
532 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
533 bank->context.wake_en =
534 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
535 gpio_mask, enable);
536 }
537}
538
539/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
540static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
541{
542 struct gpio_bank *bank = omap_irq_data_get_bank(d);
543
544 return irq_set_irq_wake(bank->irq, enable);
545}
546
547/*
548 * We need to unmask the GPIO bank interrupt as soon as possible to
549 * avoid missing GPIO interrupts for other lines in the bank.
550 * Then we need to mask-read-clear-unmask the triggered GPIO lines
551 * in the bank to avoid missing nested interrupts for a GPIO line.
552 * If we wait to unmask individual GPIO lines in the bank after the
553 * line's interrupt handler has been run, we may miss some nested
554 * interrupts.
555 */
556static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
557{
558 void __iomem *isr_reg = NULL;
559 u32 enabled, isr, edge;
560 unsigned int bit;
561 struct gpio_bank *bank = gpiobank;
562 unsigned long wa_lock_flags;
563 unsigned long lock_flags;
564
565 isr_reg = bank->base + bank->regs->irqstatus;
566 if (WARN_ON(!isr_reg))
567 goto exit;
568
569 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
570 "gpio irq%i while runtime suspended?\n", irq))
571 return IRQ_NONE;
572
573 while (1) {
574 raw_spin_lock_irqsave(&bank->lock, lock_flags);
575
576 enabled = omap_get_gpio_irqbank_mask(bank);
577 isr = readl_relaxed(isr_reg) & enabled;
578
579 /*
580 * Clear edge sensitive interrupts before calling handler(s)
581 * so subsequent edge transitions are not missed while the
582 * handlers are running.
583 */
584 edge = isr & ~bank->level_mask;
585 if (edge)
586 omap_clear_gpio_irqbank(bank, edge);
587
588 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
589
590 if (!isr)
591 break;
592
593 while (isr) {
594 bit = __ffs(isr);
595 isr &= ~(BIT(bit));
596
597 raw_spin_lock_irqsave(&bank->lock, lock_flags);
598 /*
599 * Some chips can't respond to both rising and falling
600 * at the same time. If this irq was requested with
601 * both flags, we need to flip the ICR data for the IRQ
602 * to respond to the IRQ for the opposite direction.
603 * This will be indicated in the bank toggle_mask.
604 */
605 if (bank->toggle_mask & (BIT(bit)))
606 omap_toggle_gpio_edge_triggering(bank, bit);
607
608 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
609
610 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
611
612 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
613 bit));
614
615 raw_spin_unlock_irqrestore(&bank->wa_lock,
616 wa_lock_flags);
617 }
618 }
619exit:
620 return IRQ_HANDLED;
621}
622
623static unsigned int omap_gpio_irq_startup(struct irq_data *d)
624{
625 struct gpio_bank *bank = omap_irq_data_get_bank(d);
626 unsigned long flags;
627 unsigned offset = d->hwirq;
628
629 raw_spin_lock_irqsave(&bank->lock, flags);
630
631 if (!LINE_USED(bank->mod_usage, offset))
632 omap_set_gpio_direction(bank, offset, 1);
633 omap_enable_gpio_module(bank, offset);
634 bank->irq_usage |= BIT(offset);
635
636 raw_spin_unlock_irqrestore(&bank->lock, flags);
637 omap_gpio_unmask_irq(d);
638
639 return 0;
640}
641
642static void omap_gpio_irq_shutdown(struct irq_data *d)
643{
644 struct gpio_bank *bank = omap_irq_data_get_bank(d);
645 unsigned long flags;
646 unsigned offset = d->hwirq;
647
648 raw_spin_lock_irqsave(&bank->lock, flags);
649 bank->irq_usage &= ~(BIT(offset));
650 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
651 omap_clear_gpio_irqstatus(bank, offset);
652 omap_set_gpio_irqenable(bank, offset, 0);
653 if (!LINE_USED(bank->mod_usage, offset))
654 omap_clear_gpio_debounce(bank, offset);
655 omap_disable_gpio_module(bank, offset);
656 raw_spin_unlock_irqrestore(&bank->lock, flags);
657}
658
659static void omap_gpio_irq_bus_lock(struct irq_data *data)
660{
661 struct gpio_bank *bank = omap_irq_data_get_bank(data);
662
663 pm_runtime_get_sync(bank->chip.parent);
664}
665
666static void gpio_irq_bus_sync_unlock(struct irq_data *data)
667{
668 struct gpio_bank *bank = omap_irq_data_get_bank(data);
669
670 pm_runtime_put(bank->chip.parent);
671}
672
673static void omap_gpio_mask_irq(struct irq_data *d)
674{
675 struct gpio_bank *bank = omap_irq_data_get_bank(d);
676 unsigned offset = d->hwirq;
677 unsigned long flags;
678
679 raw_spin_lock_irqsave(&bank->lock, flags);
680 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
681 omap_set_gpio_irqenable(bank, offset, 0);
682 raw_spin_unlock_irqrestore(&bank->lock, flags);
683}
684
685static void omap_gpio_unmask_irq(struct irq_data *d)
686{
687 struct gpio_bank *bank = omap_irq_data_get_bank(d);
688 unsigned offset = d->hwirq;
689 u32 trigger = irqd_get_trigger_type(d);
690 unsigned long flags;
691
692 raw_spin_lock_irqsave(&bank->lock, flags);
693 omap_set_gpio_irqenable(bank, offset, 1);
694
695 /*
696 * For level-triggered GPIOs, clearing must be done after the source
697 * is cleared, thus after the handler has run. OMAP4 needs this done
698 * after enabing the interrupt to clear the wakeup status.
699 */
700 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
701 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
702 omap_clear_gpio_irqstatus(bank, offset);
703
704 if (trigger)
705 omap_set_gpio_triggering(bank, offset, trigger);
706
707 raw_spin_unlock_irqrestore(&bank->lock, flags);
708}
709
710/*---------------------------------------------------------------------*/
711
712static int omap_mpuio_suspend_noirq(struct device *dev)
713{
714 struct gpio_bank *bank = dev_get_drvdata(dev);
715 void __iomem *mask_reg = bank->base +
716 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
717 unsigned long flags;
718
719 raw_spin_lock_irqsave(&bank->lock, flags);
720 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
721 raw_spin_unlock_irqrestore(&bank->lock, flags);
722
723 return 0;
724}
725
726static int omap_mpuio_resume_noirq(struct device *dev)
727{
728 struct gpio_bank *bank = dev_get_drvdata(dev);
729 void __iomem *mask_reg = bank->base +
730 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
731 unsigned long flags;
732
733 raw_spin_lock_irqsave(&bank->lock, flags);
734 writel_relaxed(bank->context.wake_en, mask_reg);
735 raw_spin_unlock_irqrestore(&bank->lock, flags);
736
737 return 0;
738}
739
740static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
741 .suspend_noirq = omap_mpuio_suspend_noirq,
742 .resume_noirq = omap_mpuio_resume_noirq,
743};
744
745/* use platform_driver for this. */
746static struct platform_driver omap_mpuio_driver = {
747 .driver = {
748 .name = "mpuio",
749 .pm = &omap_mpuio_dev_pm_ops,
750 },
751};
752
753static struct platform_device omap_mpuio_device = {
754 .name = "mpuio",
755 .id = -1,
756 .dev = {
757 .driver = &omap_mpuio_driver.driver,
758 }
759 /* could list the /proc/iomem resources */
760};
761
762static inline void omap_mpuio_init(struct gpio_bank *bank)
763{
764 platform_set_drvdata(&omap_mpuio_device, bank);
765
766 if (platform_driver_register(&omap_mpuio_driver) == 0)
767 (void) platform_device_register(&omap_mpuio_device);
768}
769
770/*---------------------------------------------------------------------*/
771
772static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
773{
774 struct gpio_bank *bank = gpiochip_get_data(chip);
775 unsigned long flags;
776
777 pm_runtime_get_sync(chip->parent);
778
779 raw_spin_lock_irqsave(&bank->lock, flags);
780 omap_enable_gpio_module(bank, offset);
781 bank->mod_usage |= BIT(offset);
782 raw_spin_unlock_irqrestore(&bank->lock, flags);
783
784 return 0;
785}
786
787static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
788{
789 struct gpio_bank *bank = gpiochip_get_data(chip);
790 unsigned long flags;
791
792 raw_spin_lock_irqsave(&bank->lock, flags);
793 bank->mod_usage &= ~(BIT(offset));
794 if (!LINE_USED(bank->irq_usage, offset)) {
795 omap_set_gpio_direction(bank, offset, 1);
796 omap_clear_gpio_debounce(bank, offset);
797 }
798 omap_disable_gpio_module(bank, offset);
799 raw_spin_unlock_irqrestore(&bank->lock, flags);
800
801 pm_runtime_put(chip->parent);
802}
803
804static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
805{
806 struct gpio_bank *bank = gpiochip_get_data(chip);
807
808 return !!(readl_relaxed(bank->base + bank->regs->direction) &
809 BIT(offset));
810}
811
812static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
813{
814 struct gpio_bank *bank;
815 unsigned long flags;
816
817 bank = gpiochip_get_data(chip);
818 raw_spin_lock_irqsave(&bank->lock, flags);
819 omap_set_gpio_direction(bank, offset, 1);
820 raw_spin_unlock_irqrestore(&bank->lock, flags);
821 return 0;
822}
823
824static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
825{
826 struct gpio_bank *bank = gpiochip_get_data(chip);
827 void __iomem *reg;
828
829 if (omap_gpio_is_input(bank, offset))
830 reg = bank->base + bank->regs->datain;
831 else
832 reg = bank->base + bank->regs->dataout;
833
834 return (readl_relaxed(reg) & BIT(offset)) != 0;
835}
836
837static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
838{
839 struct gpio_bank *bank;
840 unsigned long flags;
841
842 bank = gpiochip_get_data(chip);
843 raw_spin_lock_irqsave(&bank->lock, flags);
844 bank->set_dataout(bank, offset, value);
845 omap_set_gpio_direction(bank, offset, 0);
846 raw_spin_unlock_irqrestore(&bank->lock, flags);
847 return 0;
848}
849
850static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
851 unsigned long *bits)
852{
853 struct gpio_bank *bank = gpiochip_get_data(chip);
854 void __iomem *base = bank->base;
855 u32 direction, m, val = 0;
856
857 direction = readl_relaxed(base + bank->regs->direction);
858
859 m = direction & *mask;
860 if (m)
861 val |= readl_relaxed(base + bank->regs->datain) & m;
862
863 m = ~direction & *mask;
864 if (m)
865 val |= readl_relaxed(base + bank->regs->dataout) & m;
866
867 *bits = val;
868
869 return 0;
870}
871
872static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
873 unsigned debounce)
874{
875 struct gpio_bank *bank;
876 unsigned long flags;
877 int ret;
878
879 bank = gpiochip_get_data(chip);
880
881 raw_spin_lock_irqsave(&bank->lock, flags);
882 ret = omap2_set_gpio_debounce(bank, offset, debounce);
883 raw_spin_unlock_irqrestore(&bank->lock, flags);
884
885 if (ret)
886 dev_info(chip->parent,
887 "Could not set line %u debounce to %u microseconds (%d)",
888 offset, debounce, ret);
889
890 return ret;
891}
892
893static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
894 unsigned long config)
895{
896 u32 debounce;
897
898 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
899 return -ENOTSUPP;
900
901 debounce = pinconf_to_config_argument(config);
902 return omap_gpio_debounce(chip, offset, debounce);
903}
904
905static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
906{
907 struct gpio_bank *bank;
908 unsigned long flags;
909
910 bank = gpiochip_get_data(chip);
911 raw_spin_lock_irqsave(&bank->lock, flags);
912 bank->set_dataout(bank, offset, value);
913 raw_spin_unlock_irqrestore(&bank->lock, flags);
914}
915
916static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
917 unsigned long *bits)
918{
919 struct gpio_bank *bank = gpiochip_get_data(chip);
920 void __iomem *reg = bank->base + bank->regs->dataout;
921 unsigned long flags;
922 u32 l;
923
924 raw_spin_lock_irqsave(&bank->lock, flags);
925 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
926 writel_relaxed(l, reg);
927 bank->context.dataout = l;
928 raw_spin_unlock_irqrestore(&bank->lock, flags);
929}
930
931/*---------------------------------------------------------------------*/
932
933static void omap_gpio_show_rev(struct gpio_bank *bank)
934{
935 static bool called;
936 u32 rev;
937
938 if (called || bank->regs->revision == USHRT_MAX)
939 return;
940
941 rev = readw_relaxed(bank->base + bank->regs->revision);
942 pr_info("OMAP GPIO hardware version %d.%d\n",
943 (rev >> 4) & 0x0f, rev & 0x0f);
944
945 called = true;
946}
947
948static void omap_gpio_mod_init(struct gpio_bank *bank)
949{
950 void __iomem *base = bank->base;
951 u32 l = 0xffffffff;
952
953 if (bank->width == 16)
954 l = 0xffff;
955
956 if (bank->is_mpuio) {
957 writel_relaxed(l, bank->base + bank->regs->irqenable);
958 return;
959 }
960
961 omap_gpio_rmw(base + bank->regs->irqenable, l,
962 bank->regs->irqenable_inv);
963 omap_gpio_rmw(base + bank->regs->irqstatus, l,
964 !bank->regs->irqenable_inv);
965 if (bank->regs->debounce_en)
966 writel_relaxed(0, base + bank->regs->debounce_en);
967
968 /* Save OE default value (0xffffffff) in the context */
969 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
970 /* Initialize interface clk ungated, module enabled */
971 if (bank->regs->ctrl)
972 writel_relaxed(0, base + bank->regs->ctrl);
973}
974
975static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
976{
977 struct gpio_irq_chip *irq;
978 static int gpio;
979 const char *label;
980 int irq_base = 0;
981 int ret;
982
983 /*
984 * REVISIT eventually switch from OMAP-specific gpio structs
985 * over to the generic ones
986 */
987 bank->chip.request = omap_gpio_request;
988 bank->chip.free = omap_gpio_free;
989 bank->chip.get_direction = omap_gpio_get_direction;
990 bank->chip.direction_input = omap_gpio_input;
991 bank->chip.get = omap_gpio_get;
992 bank->chip.get_multiple = omap_gpio_get_multiple;
993 bank->chip.direction_output = omap_gpio_output;
994 bank->chip.set_config = omap_gpio_set_config;
995 bank->chip.set = omap_gpio_set;
996 bank->chip.set_multiple = omap_gpio_set_multiple;
997 if (bank->is_mpuio) {
998 bank->chip.label = "mpuio";
999 if (bank->regs->wkup_en)
1000 bank->chip.parent = &omap_mpuio_device.dev;
1001 bank->chip.base = OMAP_MPUIO(0);
1002 } else {
1003 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1004 gpio, gpio + bank->width - 1);
1005 if (!label)
1006 return -ENOMEM;
1007 bank->chip.label = label;
1008 bank->chip.base = gpio;
1009 }
1010 bank->chip.ngpio = bank->width;
1011
1012#ifdef CONFIG_ARCH_OMAP1
1013 /*
1014 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1015 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1016 */
1017 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1018 -1, 0, bank->width, 0);
1019 if (irq_base < 0) {
1020 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1021 return -ENODEV;
1022 }
1023#endif
1024
1025 /* MPUIO is a bit different, reading IRQ status clears it */
1026 if (bank->is_mpuio && !bank->regs->wkup_en)
1027 irqc->irq_set_wake = NULL;
1028
1029 irq = &bank->chip.irq;
1030 irq->chip = irqc;
1031 irq->handler = handle_bad_irq;
1032 irq->default_type = IRQ_TYPE_NONE;
1033 irq->num_parents = 1;
1034 irq->parents = &bank->irq;
1035 irq->first = irq_base;
1036
1037 ret = gpiochip_add_data(&bank->chip, bank);
1038 if (ret) {
1039 dev_err(bank->chip.parent,
1040 "Could not register gpio chip %d\n", ret);
1041 return ret;
1042 }
1043
1044 ret = devm_request_irq(bank->chip.parent, bank->irq,
1045 omap_gpio_irq_handler,
1046 0, dev_name(bank->chip.parent), bank);
1047 if (ret)
1048 gpiochip_remove(&bank->chip);
1049
1050 if (!bank->is_mpuio)
1051 gpio += bank->width;
1052
1053 return ret;
1054}
1055
1056static void omap_gpio_init_context(struct gpio_bank *p)
1057{
1058 const struct omap_gpio_reg_offs *regs = p->regs;
1059 void __iomem *base = p->base;
1060
1061 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1062 p->context.oe = readl_relaxed(base + regs->direction);
1063 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1064 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1065 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1066 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1067 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1068 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1069 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1070 p->context.dataout = readl_relaxed(base + regs->dataout);
1071
1072 p->context_valid = true;
1073}
1074
1075static void omap_gpio_restore_context(struct gpio_bank *bank)
1076{
1077 const struct omap_gpio_reg_offs *regs = bank->regs;
1078 void __iomem *base = bank->base;
1079
1080 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1081 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1082 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1083 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1084 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1085 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1086 writel_relaxed(bank->context.dataout, base + regs->dataout);
1087 writel_relaxed(bank->context.oe, base + regs->direction);
1088
1089 if (bank->dbck_enable_mask) {
1090 writel_relaxed(bank->context.debounce, base + regs->debounce);
1091 writel_relaxed(bank->context.debounce_en,
1092 base + regs->debounce_en);
1093 }
1094
1095 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1096 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1097}
1098
1099static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1100{
1101 struct device *dev = bank->chip.parent;
1102 void __iomem *base = bank->base;
1103 u32 mask, nowake;
1104
1105 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1106
1107 if (!bank->enabled_non_wakeup_gpios)
1108 goto update_gpio_context_count;
1109
1110 /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
1111 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1112 mask &= ~bank->context.risingdetect;
1113 bank->saved_datain |= mask;
1114
1115 /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
1116 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1117 mask &= ~bank->context.fallingdetect;
1118 bank->saved_datain &= ~mask;
1119
1120 if (!may_lose_context)
1121 goto update_gpio_context_count;
1122
1123 /*
1124 * If going to OFF, remove triggering for all wkup domain
1125 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1126 * generated. See OMAP2420 Errata item 1.101.
1127 */
1128 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1129 nowake = bank->enabled_non_wakeup_gpios;
1130 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1131 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1132 }
1133
1134update_gpio_context_count:
1135 if (bank->get_context_loss_count)
1136 bank->context_loss_count =
1137 bank->get_context_loss_count(dev);
1138
1139 omap_gpio_dbck_disable(bank);
1140}
1141
1142static void omap_gpio_unidle(struct gpio_bank *bank)
1143{
1144 struct device *dev = bank->chip.parent;
1145 u32 l = 0, gen, gen0, gen1;
1146 int c;
1147
1148 /*
1149 * On the first resume during the probe, the context has not
1150 * been initialised and so initialise it now. Also initialise
1151 * the context loss count.
1152 */
1153 if (bank->loses_context && !bank->context_valid) {
1154 omap_gpio_init_context(bank);
1155
1156 if (bank->get_context_loss_count)
1157 bank->context_loss_count =
1158 bank->get_context_loss_count(dev);
1159 }
1160
1161 omap_gpio_dbck_enable(bank);
1162
1163 if (bank->loses_context) {
1164 if (!bank->get_context_loss_count) {
1165 omap_gpio_restore_context(bank);
1166 } else {
1167 c = bank->get_context_loss_count(dev);
1168 if (c != bank->context_loss_count) {
1169 omap_gpio_restore_context(bank);
1170 } else {
1171 return;
1172 }
1173 }
1174 } else {
1175 /* Restore changes done for OMAP2420 errata 1.101 */
1176 writel_relaxed(bank->context.fallingdetect,
1177 bank->base + bank->regs->fallingdetect);
1178 writel_relaxed(bank->context.risingdetect,
1179 bank->base + bank->regs->risingdetect);
1180 }
1181
1182 l = readl_relaxed(bank->base + bank->regs->datain);
1183
1184 /*
1185 * Check if any of the non-wakeup interrupt GPIOs have changed
1186 * state. If so, generate an IRQ by software. This is
1187 * horribly racy, but it's the best we can do to work around
1188 * this silicon bug.
1189 */
1190 l ^= bank->saved_datain;
1191 l &= bank->enabled_non_wakeup_gpios;
1192
1193 /*
1194 * No need to generate IRQs for the rising edge for gpio IRQs
1195 * configured with falling edge only; and vice versa.
1196 */
1197 gen0 = l & bank->context.fallingdetect;
1198 gen0 &= bank->saved_datain;
1199
1200 gen1 = l & bank->context.risingdetect;
1201 gen1 &= ~(bank->saved_datain);
1202
1203 /* FIXME: Consider GPIO IRQs with level detections properly! */
1204 gen = l & (~(bank->context.fallingdetect) &
1205 ~(bank->context.risingdetect));
1206 /* Consider all GPIO IRQs needed to be updated */
1207 gen |= gen0 | gen1;
1208
1209 if (gen) {
1210 u32 old0, old1;
1211
1212 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1213 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1214
1215 if (!bank->regs->irqstatus_raw0) {
1216 writel_relaxed(old0 | gen, bank->base +
1217 bank->regs->leveldetect0);
1218 writel_relaxed(old1 | gen, bank->base +
1219 bank->regs->leveldetect1);
1220 }
1221
1222 if (bank->regs->irqstatus_raw0) {
1223 writel_relaxed(old0 | l, bank->base +
1224 bank->regs->leveldetect0);
1225 writel_relaxed(old1 | l, bank->base +
1226 bank->regs->leveldetect1);
1227 }
1228 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1229 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1230 }
1231}
1232
1233static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1234 unsigned long cmd, void *v)
1235{
1236 struct gpio_bank *bank;
1237 unsigned long flags;
1238
1239 bank = container_of(nb, struct gpio_bank, nb);
1240
1241 raw_spin_lock_irqsave(&bank->lock, flags);
1242 switch (cmd) {
1243 case CPU_CLUSTER_PM_ENTER:
1244 if (bank->is_suspended)
1245 break;
1246 omap_gpio_idle(bank, true);
1247 break;
1248 case CPU_CLUSTER_PM_ENTER_FAILED:
1249 case CPU_CLUSTER_PM_EXIT:
1250 if (bank->is_suspended)
1251 break;
1252 omap_gpio_unidle(bank);
1253 break;
1254 }
1255 raw_spin_unlock_irqrestore(&bank->lock, flags);
1256
1257 return NOTIFY_OK;
1258}
1259
1260static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1261 .revision = OMAP24XX_GPIO_REVISION,
1262 .direction = OMAP24XX_GPIO_OE,
1263 .datain = OMAP24XX_GPIO_DATAIN,
1264 .dataout = OMAP24XX_GPIO_DATAOUT,
1265 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1266 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1267 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1268 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1269 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1270 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1271 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1272 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1273 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1274 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1275 .ctrl = OMAP24XX_GPIO_CTRL,
1276 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1277 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1278 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1279 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1280 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1281};
1282
1283static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1284 .revision = OMAP4_GPIO_REVISION,
1285 .direction = OMAP4_GPIO_OE,
1286 .datain = OMAP4_GPIO_DATAIN,
1287 .dataout = OMAP4_GPIO_DATAOUT,
1288 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1289 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1290 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1291 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1292 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1293 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1294 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1295 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1296 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1297 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1298 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1299 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1300 .ctrl = OMAP4_GPIO_CTRL,
1301 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1302 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1303 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1304 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1305 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1306};
1307
1308static const struct omap_gpio_platform_data omap2_pdata = {
1309 .regs = &omap2_gpio_regs,
1310 .bank_width = 32,
1311 .dbck_flag = false,
1312};
1313
1314static const struct omap_gpio_platform_data omap3_pdata = {
1315 .regs = &omap2_gpio_regs,
1316 .bank_width = 32,
1317 .dbck_flag = true,
1318};
1319
1320static const struct omap_gpio_platform_data omap4_pdata = {
1321 .regs = &omap4_gpio_regs,
1322 .bank_width = 32,
1323 .dbck_flag = true,
1324};
1325
1326static const struct of_device_id omap_gpio_match[] = {
1327 {
1328 .compatible = "ti,omap4-gpio",
1329 .data = &omap4_pdata,
1330 },
1331 {
1332 .compatible = "ti,omap3-gpio",
1333 .data = &omap3_pdata,
1334 },
1335 {
1336 .compatible = "ti,omap2-gpio",
1337 .data = &omap2_pdata,
1338 },
1339 { },
1340};
1341MODULE_DEVICE_TABLE(of, omap_gpio_match);
1342
1343static int omap_gpio_probe(struct platform_device *pdev)
1344{
1345 struct device *dev = &pdev->dev;
1346 struct device_node *node = dev->of_node;
1347 const struct of_device_id *match;
1348 const struct omap_gpio_platform_data *pdata;
1349 struct gpio_bank *bank;
1350 struct irq_chip *irqc;
1351 int ret;
1352
1353 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1354
1355 pdata = match ? match->data : dev_get_platdata(dev);
1356 if (!pdata)
1357 return -EINVAL;
1358
1359 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1360 if (!bank)
1361 return -ENOMEM;
1362
1363 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1364 if (!irqc)
1365 return -ENOMEM;
1366
1367 irqc->irq_startup = omap_gpio_irq_startup,
1368 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1369 irqc->irq_ack = dummy_irq_chip.irq_ack,
1370 irqc->irq_mask = omap_gpio_mask_irq,
1371 irqc->irq_unmask = omap_gpio_unmask_irq,
1372 irqc->irq_set_type = omap_gpio_irq_type,
1373 irqc->irq_set_wake = omap_gpio_wake_enable,
1374 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1375 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1376 irqc->name = dev_name(&pdev->dev);
1377 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1378 irqc->parent_device = dev;
1379
1380 bank->irq = platform_get_irq(pdev, 0);
1381 if (bank->irq <= 0) {
1382 if (!bank->irq)
1383 bank->irq = -ENXIO;
1384 if (bank->irq != -EPROBE_DEFER)
1385 dev_err(dev,
1386 "can't get irq resource ret=%d\n", bank->irq);
1387 return bank->irq;
1388 }
1389
1390 bank->chip.parent = dev;
1391 bank->chip.owner = THIS_MODULE;
1392 bank->dbck_flag = pdata->dbck_flag;
1393 bank->stride = pdata->bank_stride;
1394 bank->width = pdata->bank_width;
1395 bank->is_mpuio = pdata->is_mpuio;
1396 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1397 bank->regs = pdata->regs;
1398#ifdef CONFIG_OF_GPIO
1399 bank->chip.of_node = of_node_get(node);
1400#endif
1401
1402 if (node) {
1403 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1404 bank->loses_context = true;
1405 } else {
1406 bank->loses_context = pdata->loses_context;
1407
1408 if (bank->loses_context)
1409 bank->get_context_loss_count =
1410 pdata->get_context_loss_count;
1411 }
1412
1413 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1414 bank->set_dataout = omap_set_gpio_dataout_reg;
1415 else
1416 bank->set_dataout = omap_set_gpio_dataout_mask;
1417
1418 raw_spin_lock_init(&bank->lock);
1419 raw_spin_lock_init(&bank->wa_lock);
1420
1421 /* Static mapping, never released */
1422 bank->base = devm_platform_ioremap_resource(pdev, 0);
1423 if (IS_ERR(bank->base)) {
1424 return PTR_ERR(bank->base);
1425 }
1426
1427 if (bank->dbck_flag) {
1428 bank->dbck = devm_clk_get(dev, "dbclk");
1429 if (IS_ERR(bank->dbck)) {
1430 dev_err(dev,
1431 "Could not get gpio dbck. Disable debounce\n");
1432 bank->dbck_flag = false;
1433 } else {
1434 clk_prepare(bank->dbck);
1435 }
1436 }
1437
1438 platform_set_drvdata(pdev, bank);
1439
1440 pm_runtime_enable(dev);
1441 pm_runtime_get_sync(dev);
1442
1443 if (bank->is_mpuio)
1444 omap_mpuio_init(bank);
1445
1446 omap_gpio_mod_init(bank);
1447
1448 ret = omap_gpio_chip_init(bank, irqc);
1449 if (ret) {
1450 pm_runtime_put_sync(dev);
1451 pm_runtime_disable(dev);
1452 if (bank->dbck_flag)
1453 clk_unprepare(bank->dbck);
1454 return ret;
1455 }
1456
1457 omap_gpio_show_rev(bank);
1458
1459 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1460 cpu_pm_register_notifier(&bank->nb);
1461
1462 pm_runtime_put(dev);
1463
1464 return 0;
1465}
1466
1467static int omap_gpio_remove(struct platform_device *pdev)
1468{
1469 struct gpio_bank *bank = platform_get_drvdata(pdev);
1470
1471 cpu_pm_unregister_notifier(&bank->nb);
1472 gpiochip_remove(&bank->chip);
1473 pm_runtime_disable(&pdev->dev);
1474 if (bank->dbck_flag)
1475 clk_unprepare(bank->dbck);
1476
1477 return 0;
1478}
1479
1480static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1481{
1482 struct gpio_bank *bank = dev_get_drvdata(dev);
1483 unsigned long flags;
1484
1485 raw_spin_lock_irqsave(&bank->lock, flags);
1486 omap_gpio_idle(bank, true);
1487 bank->is_suspended = true;
1488 raw_spin_unlock_irqrestore(&bank->lock, flags);
1489
1490 return 0;
1491}
1492
1493static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1494{
1495 struct gpio_bank *bank = dev_get_drvdata(dev);
1496 unsigned long flags;
1497
1498 raw_spin_lock_irqsave(&bank->lock, flags);
1499 omap_gpio_unidle(bank);
1500 bank->is_suspended = false;
1501 raw_spin_unlock_irqrestore(&bank->lock, flags);
1502
1503 return 0;
1504}
1505
1506static const struct dev_pm_ops gpio_pm_ops = {
1507 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1508 NULL)
1509};
1510
1511static struct platform_driver omap_gpio_driver = {
1512 .probe = omap_gpio_probe,
1513 .remove = omap_gpio_remove,
1514 .driver = {
1515 .name = "omap_gpio",
1516 .pm = &gpio_pm_ops,
1517 .of_match_table = omap_gpio_match,
1518 },
1519};
1520
1521/*
1522 * gpio driver register needs to be done before
1523 * machine_init functions access gpio APIs.
1524 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1525 */
1526static int __init omap_gpio_drv_reg(void)
1527{
1528 return platform_driver_register(&omap_gpio_driver);
1529}
1530postcore_initcall(omap_gpio_drv_reg);
1531
1532static void __exit omap_gpio_exit(void)
1533{
1534 platform_driver_unregister(&omap_gpio_driver);
1535}
1536module_exit(omap_gpio_exit);
1537
1538MODULE_DESCRIPTION("omap gpio driver");
1539MODULE_ALIAS("platform:gpio-omap");
1540MODULE_LICENSE("GPL v2");