Loading...
1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <mach/irqs.h>
28#include <mach/gpio.h>
29#include <asm/mach/irq.h>
30
31struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37 u32 suspend_wakeup;
38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup;
40#endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57 u32 width;
58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
62};
63
64#ifdef CONFIG_ARCH_OMAP3
65struct omap3_gpio_regs {
66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
76};
77
78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79#endif
80
81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
86
87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
89
90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92
93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94{
95 void __iomem *reg = bank->base;
96 u32 l;
97
98 reg += bank->regs->direction;
99 l = __raw_readl(reg);
100 if (is_input)
101 l |= 1 << gpio;
102 else
103 l &= ~(1 << gpio);
104 __raw_writel(l, reg);
105}
106
107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
110{
111 void __iomem *reg = bank->base;
112 u32 l = GPIO_BIT(bank, gpio);
113
114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
118
119 __raw_writel(l, reg);
120}
121
122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
124{
125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
128
129 l = __raw_readl(reg);
130 if (enable)
131 l |= gpio_bit;
132 else
133 l &= ~gpio_bit;
134 __raw_writel(l, reg);
135}
136
137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
138{
139 void __iomem *reg = bank->base + bank->regs->datain;
140
141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
142}
143
144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
145{
146 void __iomem *reg = bank->base + bank->regs->dataout;
147
148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
149}
150
151#define MOD_REG_BIT(reg, bit_mask, set) \
152do { \
153 int l = __raw_readl(base + reg); \
154 if (set) l |= bit_mask; \
155 else l &= ~bit_mask; \
156 __raw_writel(l, base + reg); \
157} while(0)
158
159/**
160 * _set_gpio_debounce - low level gpio debounce time
161 * @bank: the gpio bank we're acting upon
162 * @gpio: the gpio number on this @gpio
163 * @debounce: debounce time to use
164 *
165 * OMAP's debounce time is in 31us steps so we need
166 * to convert and round up to the closest unit.
167 */
168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
169 unsigned debounce)
170{
171 void __iomem *reg;
172 u32 val;
173 u32 l;
174
175 if (!bank->dbck_flag)
176 return;
177
178 if (debounce < 32)
179 debounce = 0x01;
180 else if (debounce > 7936)
181 debounce = 0xff;
182 else
183 debounce = (debounce / 0x1f) - 1;
184
185 l = GPIO_BIT(bank, gpio);
186
187 reg = bank->base + bank->regs->debounce;
188 __raw_writel(debounce, reg);
189
190 reg = bank->base + bank->regs->debounce_en;
191 val = __raw_readl(reg);
192
193 if (debounce) {
194 val |= l;
195 clk_enable(bank->dbck);
196 } else {
197 val &= ~l;
198 clk_disable(bank->dbck);
199 }
200 bank->dbck_enable_mask = val;
201
202 __raw_writel(val, reg);
203}
204
205#ifdef CONFIG_ARCH_OMAP2PLUS
206static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
207 int trigger)
208{
209 void __iomem *base = bank->base;
210 u32 gpio_bit = 1 << gpio;
211
212 if (cpu_is_omap44xx()) {
213 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
214 trigger & IRQ_TYPE_LEVEL_LOW);
215 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
216 trigger & IRQ_TYPE_LEVEL_HIGH);
217 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
218 trigger & IRQ_TYPE_EDGE_RISING);
219 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
220 trigger & IRQ_TYPE_EDGE_FALLING);
221 } else {
222 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
223 trigger & IRQ_TYPE_LEVEL_LOW);
224 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
225 trigger & IRQ_TYPE_LEVEL_HIGH);
226 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
227 trigger & IRQ_TYPE_EDGE_RISING);
228 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
229 trigger & IRQ_TYPE_EDGE_FALLING);
230 }
231 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
232 if (cpu_is_omap44xx()) {
233 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
234 trigger != 0);
235 } else {
236 /*
237 * GPIO wakeup request can only be generated on edge
238 * transitions
239 */
240 if (trigger & IRQ_TYPE_EDGE_BOTH)
241 __raw_writel(1 << gpio, bank->base
242 + OMAP24XX_GPIO_SETWKUENA);
243 else
244 __raw_writel(1 << gpio, bank->base
245 + OMAP24XX_GPIO_CLEARWKUENA);
246 }
247 }
248 /* This part needs to be executed always for OMAP{34xx, 44xx} */
249 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
250 (bank->non_wakeup_gpios & gpio_bit)) {
251 /*
252 * Log the edge gpio and manually trigger the IRQ
253 * after resume if the input level changes
254 * to avoid irq lost during PER RET/OFF mode
255 * Applies for omap2 non-wakeup gpio and all omap3 gpios
256 */
257 if (trigger & IRQ_TYPE_EDGE_BOTH)
258 bank->enabled_non_wakeup_gpios |= gpio_bit;
259 else
260 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
261 }
262
263 if (cpu_is_omap44xx()) {
264 bank->level_mask =
265 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
266 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
267 } else {
268 bank->level_mask =
269 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
270 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
271 }
272}
273#endif
274
275#ifdef CONFIG_ARCH_OMAP1
276/*
277 * This only applies to chips that can't do both rising and falling edge
278 * detection at once. For all other chips, this function is a noop.
279 */
280static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
281{
282 void __iomem *reg = bank->base;
283 u32 l = 0;
284
285 switch (bank->method) {
286 case METHOD_MPUIO:
287 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
288 break;
289#ifdef CONFIG_ARCH_OMAP15XX
290 case METHOD_GPIO_1510:
291 reg += OMAP1510_GPIO_INT_CONTROL;
292 break;
293#endif
294#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
295 case METHOD_GPIO_7XX:
296 reg += OMAP7XX_GPIO_INT_CONTROL;
297 break;
298#endif
299 default:
300 return;
301 }
302
303 l = __raw_readl(reg);
304 if ((l >> gpio) & 1)
305 l &= ~(1 << gpio);
306 else
307 l |= 1 << gpio;
308
309 __raw_writel(l, reg);
310}
311#endif
312
313static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
314{
315 void __iomem *reg = bank->base;
316 u32 l = 0;
317
318 switch (bank->method) {
319#ifdef CONFIG_ARCH_OMAP1
320 case METHOD_MPUIO:
321 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
322 l = __raw_readl(reg);
323 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
324 bank->toggle_mask |= 1 << gpio;
325 if (trigger & IRQ_TYPE_EDGE_RISING)
326 l |= 1 << gpio;
327 else if (trigger & IRQ_TYPE_EDGE_FALLING)
328 l &= ~(1 << gpio);
329 else
330 goto bad;
331 break;
332#endif
333#ifdef CONFIG_ARCH_OMAP15XX
334 case METHOD_GPIO_1510:
335 reg += OMAP1510_GPIO_INT_CONTROL;
336 l = __raw_readl(reg);
337 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
338 bank->toggle_mask |= 1 << gpio;
339 if (trigger & IRQ_TYPE_EDGE_RISING)
340 l |= 1 << gpio;
341 else if (trigger & IRQ_TYPE_EDGE_FALLING)
342 l &= ~(1 << gpio);
343 else
344 goto bad;
345 break;
346#endif
347#ifdef CONFIG_ARCH_OMAP16XX
348 case METHOD_GPIO_1610:
349 if (gpio & 0x08)
350 reg += OMAP1610_GPIO_EDGE_CTRL2;
351 else
352 reg += OMAP1610_GPIO_EDGE_CTRL1;
353 gpio &= 0x07;
354 l = __raw_readl(reg);
355 l &= ~(3 << (gpio << 1));
356 if (trigger & IRQ_TYPE_EDGE_RISING)
357 l |= 2 << (gpio << 1);
358 if (trigger & IRQ_TYPE_EDGE_FALLING)
359 l |= 1 << (gpio << 1);
360 if (trigger)
361 /* Enable wake-up during idle for dynamic tick */
362 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
363 else
364 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
365 break;
366#endif
367#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
368 case METHOD_GPIO_7XX:
369 reg += OMAP7XX_GPIO_INT_CONTROL;
370 l = __raw_readl(reg);
371 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
372 bank->toggle_mask |= 1 << gpio;
373 if (trigger & IRQ_TYPE_EDGE_RISING)
374 l |= 1 << gpio;
375 else if (trigger & IRQ_TYPE_EDGE_FALLING)
376 l &= ~(1 << gpio);
377 else
378 goto bad;
379 break;
380#endif
381#ifdef CONFIG_ARCH_OMAP2PLUS
382 case METHOD_GPIO_24XX:
383 case METHOD_GPIO_44XX:
384 set_24xx_gpio_triggering(bank, gpio, trigger);
385 return 0;
386#endif
387 default:
388 goto bad;
389 }
390 __raw_writel(l, reg);
391 return 0;
392bad:
393 return -EINVAL;
394}
395
396static int gpio_irq_type(struct irq_data *d, unsigned type)
397{
398 struct gpio_bank *bank;
399 unsigned gpio;
400 int retval;
401 unsigned long flags;
402
403 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
404 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
405 else
406 gpio = d->irq - IH_GPIO_BASE;
407
408 if (type & ~IRQ_TYPE_SENSE_MASK)
409 return -EINVAL;
410
411 /* OMAP1 allows only only edge triggering */
412 if (!cpu_class_is_omap2()
413 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
414 return -EINVAL;
415
416 bank = irq_data_get_irq_chip_data(d);
417 spin_lock_irqsave(&bank->lock, flags);
418 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
419 spin_unlock_irqrestore(&bank->lock, flags);
420
421 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
422 __irq_set_handler_locked(d->irq, handle_level_irq);
423 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
424 __irq_set_handler_locked(d->irq, handle_edge_irq);
425
426 return retval;
427}
428
429static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
430{
431 void __iomem *reg = bank->base;
432
433 reg += bank->regs->irqstatus;
434 __raw_writel(gpio_mask, reg);
435
436 /* Workaround for clearing DSP GPIO interrupts to allow retention */
437 if (bank->regs->irqstatus2) {
438 reg = bank->base + bank->regs->irqstatus2;
439 __raw_writel(gpio_mask, reg);
440 }
441
442 /* Flush posted write for the irq status to avoid spurious interrupts */
443 __raw_readl(reg);
444}
445
446static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
447{
448 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
449}
450
451static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
452{
453 void __iomem *reg = bank->base;
454 u32 l;
455 u32 mask = (1 << bank->width) - 1;
456
457 reg += bank->regs->irqenable;
458 l = __raw_readl(reg);
459 if (bank->regs->irqenable_inv)
460 l = ~l;
461 l &= mask;
462 return l;
463}
464
465static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
466{
467 void __iomem *reg = bank->base;
468 u32 l;
469
470 if (bank->regs->set_irqenable) {
471 reg += bank->regs->set_irqenable;
472 l = gpio_mask;
473 } else {
474 reg += bank->regs->irqenable;
475 l = __raw_readl(reg);
476 if (bank->regs->irqenable_inv)
477 l &= ~gpio_mask;
478 else
479 l |= gpio_mask;
480 }
481
482 __raw_writel(l, reg);
483}
484
485static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
486{
487 void __iomem *reg = bank->base;
488 u32 l;
489
490 if (bank->regs->clr_irqenable) {
491 reg += bank->regs->clr_irqenable;
492 l = gpio_mask;
493 } else {
494 reg += bank->regs->irqenable;
495 l = __raw_readl(reg);
496 if (bank->regs->irqenable_inv)
497 l |= gpio_mask;
498 else
499 l &= ~gpio_mask;
500 }
501
502 __raw_writel(l, reg);
503}
504
505static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
506{
507 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
508}
509
510/*
511 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
512 * 1510 does not seem to have a wake-up register. If JTAG is connected
513 * to the target, system will wake up always on GPIO events. While
514 * system is running all registered GPIO interrupts need to have wake-up
515 * enabled. When system is suspended, only selected GPIO interrupts need
516 * to have wake-up enabled.
517 */
518static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
519{
520 u32 gpio_bit = GPIO_BIT(bank, gpio);
521 unsigned long flags;
522
523 if (bank->non_wakeup_gpios & gpio_bit) {
524 dev_err(bank->dev,
525 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
526 return -EINVAL;
527 }
528
529 spin_lock_irqsave(&bank->lock, flags);
530 if (enable)
531 bank->suspend_wakeup |= gpio_bit;
532 else
533 bank->suspend_wakeup &= ~gpio_bit;
534
535 spin_unlock_irqrestore(&bank->lock, flags);
536
537 return 0;
538}
539
540static void _reset_gpio(struct gpio_bank *bank, int gpio)
541{
542 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
543 _set_gpio_irqenable(bank, gpio, 0);
544 _clear_gpio_irqstatus(bank, gpio);
545 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
546}
547
548/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
549static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
550{
551 unsigned int gpio = d->irq - IH_GPIO_BASE;
552 struct gpio_bank *bank;
553 int retval;
554
555 bank = irq_data_get_irq_chip_data(d);
556 retval = _set_gpio_wakeup(bank, gpio, enable);
557
558 return retval;
559}
560
561static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
562{
563 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
564 unsigned long flags;
565
566 spin_lock_irqsave(&bank->lock, flags);
567
568 /* Set trigger to none. You need to enable the desired trigger with
569 * request_irq() or set_irq_type().
570 */
571 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
572
573#ifdef CONFIG_ARCH_OMAP15XX
574 if (bank->method == METHOD_GPIO_1510) {
575 void __iomem *reg;
576
577 /* Claim the pin for MPU */
578 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
579 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
580 }
581#endif
582 if (!cpu_class_is_omap1()) {
583 if (!bank->mod_usage) {
584 void __iomem *reg = bank->base;
585 u32 ctrl;
586
587 if (cpu_is_omap24xx() || cpu_is_omap34xx())
588 reg += OMAP24XX_GPIO_CTRL;
589 else if (cpu_is_omap44xx())
590 reg += OMAP4_GPIO_CTRL;
591 ctrl = __raw_readl(reg);
592 /* Module is enabled, clocks are not gated */
593 ctrl &= 0xFFFFFFFE;
594 __raw_writel(ctrl, reg);
595 }
596 bank->mod_usage |= 1 << offset;
597 }
598 spin_unlock_irqrestore(&bank->lock, flags);
599
600 return 0;
601}
602
603static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
604{
605 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
606 unsigned long flags;
607
608 spin_lock_irqsave(&bank->lock, flags);
609#ifdef CONFIG_ARCH_OMAP16XX
610 if (bank->method == METHOD_GPIO_1610) {
611 /* Disable wake-up during idle for dynamic tick */
612 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
613 __raw_writel(1 << offset, reg);
614 }
615#endif
616#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
617 if (bank->method == METHOD_GPIO_24XX) {
618 /* Disable wake-up during idle for dynamic tick */
619 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
620 __raw_writel(1 << offset, reg);
621 }
622#endif
623#ifdef CONFIG_ARCH_OMAP4
624 if (bank->method == METHOD_GPIO_44XX) {
625 /* Disable wake-up during idle for dynamic tick */
626 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
627 __raw_writel(1 << offset, reg);
628 }
629#endif
630 if (!cpu_class_is_omap1()) {
631 bank->mod_usage &= ~(1 << offset);
632 if (!bank->mod_usage) {
633 void __iomem *reg = bank->base;
634 u32 ctrl;
635
636 if (cpu_is_omap24xx() || cpu_is_omap34xx())
637 reg += OMAP24XX_GPIO_CTRL;
638 else if (cpu_is_omap44xx())
639 reg += OMAP4_GPIO_CTRL;
640 ctrl = __raw_readl(reg);
641 /* Module is disabled, clocks are gated */
642 ctrl |= 1;
643 __raw_writel(ctrl, reg);
644 }
645 }
646 _reset_gpio(bank, bank->chip.base + offset);
647 spin_unlock_irqrestore(&bank->lock, flags);
648}
649
650/*
651 * We need to unmask the GPIO bank interrupt as soon as possible to
652 * avoid missing GPIO interrupts for other lines in the bank.
653 * Then we need to mask-read-clear-unmask the triggered GPIO lines
654 * in the bank to avoid missing nested interrupts for a GPIO line.
655 * If we wait to unmask individual GPIO lines in the bank after the
656 * line's interrupt handler has been run, we may miss some nested
657 * interrupts.
658 */
659static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
660{
661 void __iomem *isr_reg = NULL;
662 u32 isr;
663 unsigned int gpio_irq, gpio_index;
664 struct gpio_bank *bank;
665 u32 retrigger = 0;
666 int unmasked = 0;
667 struct irq_chip *chip = irq_desc_get_chip(desc);
668
669 chained_irq_enter(chip, desc);
670
671 bank = irq_get_handler_data(irq);
672 isr_reg = bank->base + bank->regs->irqstatus;
673
674 if (WARN_ON(!isr_reg))
675 goto exit;
676
677 while(1) {
678 u32 isr_saved, level_mask = 0;
679 u32 enabled;
680
681 enabled = _get_gpio_irqbank_mask(bank);
682 isr_saved = isr = __raw_readl(isr_reg) & enabled;
683
684 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
685 isr &= 0x0000ffff;
686
687 if (cpu_class_is_omap2()) {
688 level_mask = bank->level_mask & enabled;
689 }
690
691 /* clear edge sensitive interrupts before handler(s) are
692 called so that we don't miss any interrupt occurred while
693 executing them */
694 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
695 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
696 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
697
698 /* if there is only edge sensitive GPIO pin interrupts
699 configured, we could unmask GPIO bank interrupt immediately */
700 if (!level_mask && !unmasked) {
701 unmasked = 1;
702 chained_irq_exit(chip, desc);
703 }
704
705 isr |= retrigger;
706 retrigger = 0;
707 if (!isr)
708 break;
709
710 gpio_irq = bank->virtual_irq_start;
711 for (; isr != 0; isr >>= 1, gpio_irq++) {
712 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
713
714 if (!(isr & 1))
715 continue;
716
717#ifdef CONFIG_ARCH_OMAP1
718 /*
719 * Some chips can't respond to both rising and falling
720 * at the same time. If this irq was requested with
721 * both flags, we need to flip the ICR data for the IRQ
722 * to respond to the IRQ for the opposite direction.
723 * This will be indicated in the bank toggle_mask.
724 */
725 if (bank->toggle_mask & (1 << gpio_index))
726 _toggle_gpio_edge_triggering(bank, gpio_index);
727#endif
728
729 generic_handle_irq(gpio_irq);
730 }
731 }
732 /* if bank has any level sensitive GPIO pin interrupt
733 configured, we must unmask the bank interrupt only after
734 handler(s) are executed in order to avoid spurious bank
735 interrupt */
736exit:
737 if (!unmasked)
738 chained_irq_exit(chip, desc);
739}
740
741static void gpio_irq_shutdown(struct irq_data *d)
742{
743 unsigned int gpio = d->irq - IH_GPIO_BASE;
744 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
745 unsigned long flags;
746
747 spin_lock_irqsave(&bank->lock, flags);
748 _reset_gpio(bank, gpio);
749 spin_unlock_irqrestore(&bank->lock, flags);
750}
751
752static void gpio_ack_irq(struct irq_data *d)
753{
754 unsigned int gpio = d->irq - IH_GPIO_BASE;
755 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
756
757 _clear_gpio_irqstatus(bank, gpio);
758}
759
760static void gpio_mask_irq(struct irq_data *d)
761{
762 unsigned int gpio = d->irq - IH_GPIO_BASE;
763 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
764 unsigned long flags;
765
766 spin_lock_irqsave(&bank->lock, flags);
767 _set_gpio_irqenable(bank, gpio, 0);
768 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
769 spin_unlock_irqrestore(&bank->lock, flags);
770}
771
772static void gpio_unmask_irq(struct irq_data *d)
773{
774 unsigned int gpio = d->irq - IH_GPIO_BASE;
775 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
776 unsigned int irq_mask = GPIO_BIT(bank, gpio);
777 u32 trigger = irqd_get_trigger_type(d);
778 unsigned long flags;
779
780 spin_lock_irqsave(&bank->lock, flags);
781 if (trigger)
782 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
783
784 /* For level-triggered GPIOs, the clearing must be done after
785 * the HW source is cleared, thus after the handler has run */
786 if (bank->level_mask & irq_mask) {
787 _set_gpio_irqenable(bank, gpio, 0);
788 _clear_gpio_irqstatus(bank, gpio);
789 }
790
791 _set_gpio_irqenable(bank, gpio, 1);
792 spin_unlock_irqrestore(&bank->lock, flags);
793}
794
795static struct irq_chip gpio_irq_chip = {
796 .name = "GPIO",
797 .irq_shutdown = gpio_irq_shutdown,
798 .irq_ack = gpio_ack_irq,
799 .irq_mask = gpio_mask_irq,
800 .irq_unmask = gpio_unmask_irq,
801 .irq_set_type = gpio_irq_type,
802 .irq_set_wake = gpio_wake_enable,
803};
804
805/*---------------------------------------------------------------------*/
806
807#ifdef CONFIG_ARCH_OMAP1
808
809#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
810
811#ifdef CONFIG_ARCH_OMAP16XX
812
813#include <linux/platform_device.h>
814
815static int omap_mpuio_suspend_noirq(struct device *dev)
816{
817 struct platform_device *pdev = to_platform_device(dev);
818 struct gpio_bank *bank = platform_get_drvdata(pdev);
819 void __iomem *mask_reg = bank->base +
820 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
821 unsigned long flags;
822
823 spin_lock_irqsave(&bank->lock, flags);
824 bank->saved_wakeup = __raw_readl(mask_reg);
825 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
826 spin_unlock_irqrestore(&bank->lock, flags);
827
828 return 0;
829}
830
831static int omap_mpuio_resume_noirq(struct device *dev)
832{
833 struct platform_device *pdev = to_platform_device(dev);
834 struct gpio_bank *bank = platform_get_drvdata(pdev);
835 void __iomem *mask_reg = bank->base +
836 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
837 unsigned long flags;
838
839 spin_lock_irqsave(&bank->lock, flags);
840 __raw_writel(bank->saved_wakeup, mask_reg);
841 spin_unlock_irqrestore(&bank->lock, flags);
842
843 return 0;
844}
845
846static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
847 .suspend_noirq = omap_mpuio_suspend_noirq,
848 .resume_noirq = omap_mpuio_resume_noirq,
849};
850
851/* use platform_driver for this. */
852static struct platform_driver omap_mpuio_driver = {
853 .driver = {
854 .name = "mpuio",
855 .pm = &omap_mpuio_dev_pm_ops,
856 },
857};
858
859static struct platform_device omap_mpuio_device = {
860 .name = "mpuio",
861 .id = -1,
862 .dev = {
863 .driver = &omap_mpuio_driver.driver,
864 }
865 /* could list the /proc/iomem resources */
866};
867
868static inline void mpuio_init(void)
869{
870 struct gpio_bank *bank = &gpio_bank[0];
871 platform_set_drvdata(&omap_mpuio_device, bank);
872
873 if (platform_driver_register(&omap_mpuio_driver) == 0)
874 (void) platform_device_register(&omap_mpuio_device);
875}
876
877#else
878static inline void mpuio_init(void) {}
879#endif /* 16xx */
880
881#else
882
883#define bank_is_mpuio(bank) 0
884static inline void mpuio_init(void) {}
885
886#endif
887
888/*---------------------------------------------------------------------*/
889
890/* REVISIT these are stupid implementations! replace by ones that
891 * don't switch on METHOD_* and which mostly avoid spinlocks
892 */
893
894static int gpio_input(struct gpio_chip *chip, unsigned offset)
895{
896 struct gpio_bank *bank;
897 unsigned long flags;
898
899 bank = container_of(chip, struct gpio_bank, chip);
900 spin_lock_irqsave(&bank->lock, flags);
901 _set_gpio_direction(bank, offset, 1);
902 spin_unlock_irqrestore(&bank->lock, flags);
903 return 0;
904}
905
906static int gpio_is_input(struct gpio_bank *bank, int mask)
907{
908 void __iomem *reg = bank->base + bank->regs->direction;
909
910 return __raw_readl(reg) & mask;
911}
912
913static int gpio_get(struct gpio_chip *chip, unsigned offset)
914{
915 struct gpio_bank *bank;
916 void __iomem *reg;
917 int gpio;
918 u32 mask;
919
920 gpio = chip->base + offset;
921 bank = container_of(chip, struct gpio_bank, chip);
922 reg = bank->base;
923 mask = GPIO_BIT(bank, gpio);
924
925 if (gpio_is_input(bank, mask))
926 return _get_gpio_datain(bank, gpio);
927 else
928 return _get_gpio_dataout(bank, gpio);
929}
930
931static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
932{
933 struct gpio_bank *bank;
934 unsigned long flags;
935
936 bank = container_of(chip, struct gpio_bank, chip);
937 spin_lock_irqsave(&bank->lock, flags);
938 bank->set_dataout(bank, offset, value);
939 _set_gpio_direction(bank, offset, 0);
940 spin_unlock_irqrestore(&bank->lock, flags);
941 return 0;
942}
943
944static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
945 unsigned debounce)
946{
947 struct gpio_bank *bank;
948 unsigned long flags;
949
950 bank = container_of(chip, struct gpio_bank, chip);
951
952 if (!bank->dbck) {
953 bank->dbck = clk_get(bank->dev, "dbclk");
954 if (IS_ERR(bank->dbck))
955 dev_err(bank->dev, "Could not get gpio dbck\n");
956 }
957
958 spin_lock_irqsave(&bank->lock, flags);
959 _set_gpio_debounce(bank, offset, debounce);
960 spin_unlock_irqrestore(&bank->lock, flags);
961
962 return 0;
963}
964
965static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
966{
967 struct gpio_bank *bank;
968 unsigned long flags;
969
970 bank = container_of(chip, struct gpio_bank, chip);
971 spin_lock_irqsave(&bank->lock, flags);
972 bank->set_dataout(bank, offset, value);
973 spin_unlock_irqrestore(&bank->lock, flags);
974}
975
976static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
977{
978 struct gpio_bank *bank;
979
980 bank = container_of(chip, struct gpio_bank, chip);
981 return bank->virtual_irq_start + offset;
982}
983
984/*---------------------------------------------------------------------*/
985
986static void __init omap_gpio_show_rev(struct gpio_bank *bank)
987{
988 static bool called;
989 u32 rev;
990
991 if (called || bank->regs->revision == USHRT_MAX)
992 return;
993
994 rev = __raw_readw(bank->base + bank->regs->revision);
995 pr_info("OMAP GPIO hardware version %d.%d\n",
996 (rev >> 4) & 0x0f, rev & 0x0f);
997
998 called = true;
999}
1000
1001/* This lock class tells lockdep that GPIO irqs are in a different
1002 * category than their parents, so it won't report false recursion.
1003 */
1004static struct lock_class_key gpio_lock_class;
1005
1006static inline int init_gpio_info(struct platform_device *pdev)
1007{
1008 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1009 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1010 GFP_KERNEL);
1011 if (!gpio_bank) {
1012 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1013 return -ENOMEM;
1014 }
1015 return 0;
1016}
1017
1018/* TODO: Cleanup cpu_is_* checks */
1019static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1020{
1021 if (cpu_class_is_omap2()) {
1022 if (cpu_is_omap44xx()) {
1023 __raw_writel(0xffffffff, bank->base +
1024 OMAP4_GPIO_IRQSTATUSCLR0);
1025 __raw_writel(0x00000000, bank->base +
1026 OMAP4_GPIO_DEBOUNCENABLE);
1027 /* Initialize interface clk ungated, module enabled */
1028 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1029 } else if (cpu_is_omap34xx()) {
1030 __raw_writel(0x00000000, bank->base +
1031 OMAP24XX_GPIO_IRQENABLE1);
1032 __raw_writel(0xffffffff, bank->base +
1033 OMAP24XX_GPIO_IRQSTATUS1);
1034 __raw_writel(0x00000000, bank->base +
1035 OMAP24XX_GPIO_DEBOUNCE_EN);
1036
1037 /* Initialize interface clk ungated, module enabled */
1038 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1039 } else if (cpu_is_omap24xx()) {
1040 static const u32 non_wakeup_gpios[] = {
1041 0xe203ffc0, 0x08700040
1042 };
1043 if (id < ARRAY_SIZE(non_wakeup_gpios))
1044 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1045 }
1046 } else if (cpu_class_is_omap1()) {
1047 if (bank_is_mpuio(bank))
1048 __raw_writew(0xffff, bank->base +
1049 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1050 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1051 __raw_writew(0xffff, bank->base
1052 + OMAP1510_GPIO_INT_MASK);
1053 __raw_writew(0x0000, bank->base
1054 + OMAP1510_GPIO_INT_STATUS);
1055 }
1056 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1057 __raw_writew(0x0000, bank->base
1058 + OMAP1610_GPIO_IRQENABLE1);
1059 __raw_writew(0xffff, bank->base
1060 + OMAP1610_GPIO_IRQSTATUS1);
1061 __raw_writew(0x0014, bank->base
1062 + OMAP1610_GPIO_SYSCONFIG);
1063
1064 /*
1065 * Enable system clock for GPIO module.
1066 * The CAM_CLK_CTRL *is* really the right place.
1067 */
1068 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1069 ULPD_CAM_CLK_CTRL);
1070 }
1071 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1072 __raw_writel(0xffffffff, bank->base
1073 + OMAP7XX_GPIO_INT_MASK);
1074 __raw_writel(0x00000000, bank->base
1075 + OMAP7XX_GPIO_INT_STATUS);
1076 }
1077 }
1078}
1079
1080static __init void
1081omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1082 unsigned int num)
1083{
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086
1087 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1088 handle_simple_irq);
1089 ct = gc->chip_types;
1090
1091 /* NOTE: No ack required, reading IRQ status clears it. */
1092 ct->chip.irq_mask = irq_gc_mask_set_bit;
1093 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1094 ct->chip.irq_set_type = gpio_irq_type;
1095 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1096 if (cpu_is_omap16xx())
1097 ct->chip.irq_set_wake = gpio_wake_enable,
1098
1099 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1100 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1101 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1102}
1103
1104static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1105{
1106 int j;
1107 static int gpio;
1108
1109 bank->mod_usage = 0;
1110 /*
1111 * REVISIT eventually switch from OMAP-specific gpio structs
1112 * over to the generic ones
1113 */
1114 bank->chip.request = omap_gpio_request;
1115 bank->chip.free = omap_gpio_free;
1116 bank->chip.direction_input = gpio_input;
1117 bank->chip.get = gpio_get;
1118 bank->chip.direction_output = gpio_output;
1119 bank->chip.set_debounce = gpio_debounce;
1120 bank->chip.set = gpio_set;
1121 bank->chip.to_irq = gpio_2irq;
1122 if (bank_is_mpuio(bank)) {
1123 bank->chip.label = "mpuio";
1124#ifdef CONFIG_ARCH_OMAP16XX
1125 bank->chip.dev = &omap_mpuio_device.dev;
1126#endif
1127 bank->chip.base = OMAP_MPUIO(0);
1128 } else {
1129 bank->chip.label = "gpio";
1130 bank->chip.base = gpio;
1131 gpio += bank->width;
1132 }
1133 bank->chip.ngpio = bank->width;
1134
1135 gpiochip_add(&bank->chip);
1136
1137 for (j = bank->virtual_irq_start;
1138 j < bank->virtual_irq_start + bank->width; j++) {
1139 irq_set_lockdep_class(j, &gpio_lock_class);
1140 irq_set_chip_data(j, bank);
1141 if (bank_is_mpuio(bank)) {
1142 omap_mpuio_alloc_gc(bank, j, bank->width);
1143 } else {
1144 irq_set_chip(j, &gpio_irq_chip);
1145 irq_set_handler(j, handle_simple_irq);
1146 set_irq_flags(j, IRQF_VALID);
1147 }
1148 }
1149 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1150 irq_set_handler_data(bank->irq, bank);
1151}
1152
1153static int __devinit omap_gpio_probe(struct platform_device *pdev)
1154{
1155 static int gpio_init_done;
1156 struct omap_gpio_platform_data *pdata;
1157 struct resource *res;
1158 int id;
1159 struct gpio_bank *bank;
1160
1161 if (!pdev->dev.platform_data)
1162 return -EINVAL;
1163
1164 pdata = pdev->dev.platform_data;
1165
1166 if (!gpio_init_done) {
1167 int ret;
1168
1169 ret = init_gpio_info(pdev);
1170 if (ret)
1171 return ret;
1172 }
1173
1174 id = pdev->id;
1175 bank = &gpio_bank[id];
1176
1177 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1178 if (unlikely(!res)) {
1179 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1180 return -ENODEV;
1181 }
1182
1183 bank->irq = res->start;
1184 bank->virtual_irq_start = pdata->virtual_irq_start;
1185 bank->method = pdata->bank_type;
1186 bank->dev = &pdev->dev;
1187 bank->dbck_flag = pdata->dbck_flag;
1188 bank->stride = pdata->bank_stride;
1189 bank->width = pdata->bank_width;
1190
1191 bank->regs = pdata->regs;
1192
1193 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1194 bank->set_dataout = _set_gpio_dataout_reg;
1195 else
1196 bank->set_dataout = _set_gpio_dataout_mask;
1197
1198 spin_lock_init(&bank->lock);
1199
1200 /* Static mapping, never released */
1201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1202 if (unlikely(!res)) {
1203 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1204 return -ENODEV;
1205 }
1206
1207 bank->base = ioremap(res->start, resource_size(res));
1208 if (!bank->base) {
1209 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1210 return -ENOMEM;
1211 }
1212
1213 pm_runtime_enable(bank->dev);
1214 pm_runtime_get_sync(bank->dev);
1215
1216 omap_gpio_mod_init(bank, id);
1217 omap_gpio_chip_init(bank);
1218 omap_gpio_show_rev(bank);
1219
1220 if (!gpio_init_done)
1221 gpio_init_done = 1;
1222
1223 return 0;
1224}
1225
1226#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1227static int omap_gpio_suspend(void)
1228{
1229 int i;
1230
1231 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1232 return 0;
1233
1234 for (i = 0; i < gpio_bank_count; i++) {
1235 struct gpio_bank *bank = &gpio_bank[i];
1236 void __iomem *wake_status;
1237 void __iomem *wake_clear;
1238 void __iomem *wake_set;
1239 unsigned long flags;
1240
1241 switch (bank->method) {
1242#ifdef CONFIG_ARCH_OMAP16XX
1243 case METHOD_GPIO_1610:
1244 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1245 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1246 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1247 break;
1248#endif
1249#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1250 case METHOD_GPIO_24XX:
1251 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1252 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1253 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1254 break;
1255#endif
1256#ifdef CONFIG_ARCH_OMAP4
1257 case METHOD_GPIO_44XX:
1258 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1259 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1260 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1261 break;
1262#endif
1263 default:
1264 continue;
1265 }
1266
1267 spin_lock_irqsave(&bank->lock, flags);
1268 bank->saved_wakeup = __raw_readl(wake_status);
1269 __raw_writel(0xffffffff, wake_clear);
1270 __raw_writel(bank->suspend_wakeup, wake_set);
1271 spin_unlock_irqrestore(&bank->lock, flags);
1272 }
1273
1274 return 0;
1275}
1276
1277static void omap_gpio_resume(void)
1278{
1279 int i;
1280
1281 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1282 return;
1283
1284 for (i = 0; i < gpio_bank_count; i++) {
1285 struct gpio_bank *bank = &gpio_bank[i];
1286 void __iomem *wake_clear;
1287 void __iomem *wake_set;
1288 unsigned long flags;
1289
1290 switch (bank->method) {
1291#ifdef CONFIG_ARCH_OMAP16XX
1292 case METHOD_GPIO_1610:
1293 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1294 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1295 break;
1296#endif
1297#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1298 case METHOD_GPIO_24XX:
1299 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1300 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1301 break;
1302#endif
1303#ifdef CONFIG_ARCH_OMAP4
1304 case METHOD_GPIO_44XX:
1305 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1306 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1307 break;
1308#endif
1309 default:
1310 continue;
1311 }
1312
1313 spin_lock_irqsave(&bank->lock, flags);
1314 __raw_writel(0xffffffff, wake_clear);
1315 __raw_writel(bank->saved_wakeup, wake_set);
1316 spin_unlock_irqrestore(&bank->lock, flags);
1317 }
1318}
1319
1320static struct syscore_ops omap_gpio_syscore_ops = {
1321 .suspend = omap_gpio_suspend,
1322 .resume = omap_gpio_resume,
1323};
1324
1325#endif
1326
1327#ifdef CONFIG_ARCH_OMAP2PLUS
1328
1329static int workaround_enabled;
1330
1331void omap2_gpio_prepare_for_idle(int off_mode)
1332{
1333 int i, c = 0;
1334 int min = 0;
1335
1336 if (cpu_is_omap34xx())
1337 min = 1;
1338
1339 for (i = min; i < gpio_bank_count; i++) {
1340 struct gpio_bank *bank = &gpio_bank[i];
1341 u32 l1 = 0, l2 = 0;
1342 int j;
1343
1344 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1345 clk_disable(bank->dbck);
1346
1347 if (!off_mode)
1348 continue;
1349
1350 /* If going to OFF, remove triggering for all
1351 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1352 * generated. See OMAP2420 Errata item 1.101. */
1353 if (!(bank->enabled_non_wakeup_gpios))
1354 continue;
1355
1356 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1357 bank->saved_datain = __raw_readl(bank->base +
1358 OMAP24XX_GPIO_DATAIN);
1359 l1 = __raw_readl(bank->base +
1360 OMAP24XX_GPIO_FALLINGDETECT);
1361 l2 = __raw_readl(bank->base +
1362 OMAP24XX_GPIO_RISINGDETECT);
1363 }
1364
1365 if (cpu_is_omap44xx()) {
1366 bank->saved_datain = __raw_readl(bank->base +
1367 OMAP4_GPIO_DATAIN);
1368 l1 = __raw_readl(bank->base +
1369 OMAP4_GPIO_FALLINGDETECT);
1370 l2 = __raw_readl(bank->base +
1371 OMAP4_GPIO_RISINGDETECT);
1372 }
1373
1374 bank->saved_fallingdetect = l1;
1375 bank->saved_risingdetect = l2;
1376 l1 &= ~bank->enabled_non_wakeup_gpios;
1377 l2 &= ~bank->enabled_non_wakeup_gpios;
1378
1379 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1380 __raw_writel(l1, bank->base +
1381 OMAP24XX_GPIO_FALLINGDETECT);
1382 __raw_writel(l2, bank->base +
1383 OMAP24XX_GPIO_RISINGDETECT);
1384 }
1385
1386 if (cpu_is_omap44xx()) {
1387 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1388 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1389 }
1390
1391 c++;
1392 }
1393 if (!c) {
1394 workaround_enabled = 0;
1395 return;
1396 }
1397 workaround_enabled = 1;
1398}
1399
1400void omap2_gpio_resume_after_idle(void)
1401{
1402 int i;
1403 int min = 0;
1404
1405 if (cpu_is_omap34xx())
1406 min = 1;
1407 for (i = min; i < gpio_bank_count; i++) {
1408 struct gpio_bank *bank = &gpio_bank[i];
1409 u32 l = 0, gen, gen0, gen1;
1410 int j;
1411
1412 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1413 clk_enable(bank->dbck);
1414
1415 if (!workaround_enabled)
1416 continue;
1417
1418 if (!(bank->enabled_non_wakeup_gpios))
1419 continue;
1420
1421 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1422 __raw_writel(bank->saved_fallingdetect,
1423 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1424 __raw_writel(bank->saved_risingdetect,
1425 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1426 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1427 }
1428
1429 if (cpu_is_omap44xx()) {
1430 __raw_writel(bank->saved_fallingdetect,
1431 bank->base + OMAP4_GPIO_FALLINGDETECT);
1432 __raw_writel(bank->saved_risingdetect,
1433 bank->base + OMAP4_GPIO_RISINGDETECT);
1434 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1435 }
1436
1437 /* Check if any of the non-wakeup interrupt GPIOs have changed
1438 * state. If so, generate an IRQ by software. This is
1439 * horribly racy, but it's the best we can do to work around
1440 * this silicon bug. */
1441 l ^= bank->saved_datain;
1442 l &= bank->enabled_non_wakeup_gpios;
1443
1444 /*
1445 * No need to generate IRQs for the rising edge for gpio IRQs
1446 * configured with falling edge only; and vice versa.
1447 */
1448 gen0 = l & bank->saved_fallingdetect;
1449 gen0 &= bank->saved_datain;
1450
1451 gen1 = l & bank->saved_risingdetect;
1452 gen1 &= ~(bank->saved_datain);
1453
1454 /* FIXME: Consider GPIO IRQs with level detections properly! */
1455 gen = l & (~(bank->saved_fallingdetect) &
1456 ~(bank->saved_risingdetect));
1457 /* Consider all GPIO IRQs needed to be updated */
1458 gen |= gen0 | gen1;
1459
1460 if (gen) {
1461 u32 old0, old1;
1462
1463 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1464 old0 = __raw_readl(bank->base +
1465 OMAP24XX_GPIO_LEVELDETECT0);
1466 old1 = __raw_readl(bank->base +
1467 OMAP24XX_GPIO_LEVELDETECT1);
1468 __raw_writel(old0 | gen, bank->base +
1469 OMAP24XX_GPIO_LEVELDETECT0);
1470 __raw_writel(old1 | gen, bank->base +
1471 OMAP24XX_GPIO_LEVELDETECT1);
1472 __raw_writel(old0, bank->base +
1473 OMAP24XX_GPIO_LEVELDETECT0);
1474 __raw_writel(old1, bank->base +
1475 OMAP24XX_GPIO_LEVELDETECT1);
1476 }
1477
1478 if (cpu_is_omap44xx()) {
1479 old0 = __raw_readl(bank->base +
1480 OMAP4_GPIO_LEVELDETECT0);
1481 old1 = __raw_readl(bank->base +
1482 OMAP4_GPIO_LEVELDETECT1);
1483 __raw_writel(old0 | l, bank->base +
1484 OMAP4_GPIO_LEVELDETECT0);
1485 __raw_writel(old1 | l, bank->base +
1486 OMAP4_GPIO_LEVELDETECT1);
1487 __raw_writel(old0, bank->base +
1488 OMAP4_GPIO_LEVELDETECT0);
1489 __raw_writel(old1, bank->base +
1490 OMAP4_GPIO_LEVELDETECT1);
1491 }
1492 }
1493 }
1494
1495}
1496
1497#endif
1498
1499#ifdef CONFIG_ARCH_OMAP3
1500/* save the registers of bank 2-6 */
1501void omap_gpio_save_context(void)
1502{
1503 int i;
1504
1505 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1506 for (i = 1; i < gpio_bank_count; i++) {
1507 struct gpio_bank *bank = &gpio_bank[i];
1508 gpio_context[i].irqenable1 =
1509 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1510 gpio_context[i].irqenable2 =
1511 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1512 gpio_context[i].wake_en =
1513 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1514 gpio_context[i].ctrl =
1515 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1516 gpio_context[i].oe =
1517 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1518 gpio_context[i].leveldetect0 =
1519 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1520 gpio_context[i].leveldetect1 =
1521 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1522 gpio_context[i].risingdetect =
1523 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1524 gpio_context[i].fallingdetect =
1525 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1526 gpio_context[i].dataout =
1527 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1528 }
1529}
1530
1531/* restore the required registers of bank 2-6 */
1532void omap_gpio_restore_context(void)
1533{
1534 int i;
1535
1536 for (i = 1; i < gpio_bank_count; i++) {
1537 struct gpio_bank *bank = &gpio_bank[i];
1538 __raw_writel(gpio_context[i].irqenable1,
1539 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1540 __raw_writel(gpio_context[i].irqenable2,
1541 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1542 __raw_writel(gpio_context[i].wake_en,
1543 bank->base + OMAP24XX_GPIO_WAKE_EN);
1544 __raw_writel(gpio_context[i].ctrl,
1545 bank->base + OMAP24XX_GPIO_CTRL);
1546 __raw_writel(gpio_context[i].oe,
1547 bank->base + OMAP24XX_GPIO_OE);
1548 __raw_writel(gpio_context[i].leveldetect0,
1549 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1550 __raw_writel(gpio_context[i].leveldetect1,
1551 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1552 __raw_writel(gpio_context[i].risingdetect,
1553 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1554 __raw_writel(gpio_context[i].fallingdetect,
1555 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1556 __raw_writel(gpio_context[i].dataout,
1557 bank->base + OMAP24XX_GPIO_DATAOUT);
1558 }
1559}
1560#endif
1561
1562static struct platform_driver omap_gpio_driver = {
1563 .probe = omap_gpio_probe,
1564 .driver = {
1565 .name = "omap_gpio",
1566 },
1567};
1568
1569/*
1570 * gpio driver register needs to be done before
1571 * machine_init functions access gpio APIs.
1572 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1573 */
1574static int __init omap_gpio_drv_reg(void)
1575{
1576 return platform_driver_register(&omap_gpio_driver);
1577}
1578postcore_initcall(omap_gpio_drv_reg);
1579
1580static int __init omap_gpio_sysinit(void)
1581{
1582 mpuio_init();
1583
1584#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1585 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1586 register_syscore_ops(&omap_gpio_syscore_ops);
1587#endif
1588
1589 return 0;
1590}
1591
1592arch_initcall(omap_gpio_sysinit);
1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
28#include <linux/irqchip/chained_irq.h>
29#include <linux/gpio.h>
30#include <linux/platform_data/gpio-omap.h>
31
32#define OFF_MODE 1
33
34static LIST_HEAD(omap_gpio_list);
35
36struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49};
50
51struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 u16 irq;
55 struct irq_domain *domain;
56 u32 non_wakeup_gpios;
57 u32 enabled_non_wakeup_gpios;
58 struct gpio_regs context;
59 u32 saved_datain;
60 u32 level_mask;
61 u32 toggle_mask;
62 spinlock_t lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 struct device *dev;
70 bool is_mpuio;
71 bool dbck_flag;
72 bool loses_context;
73 bool context_valid;
74 int stride;
75 u32 width;
76 int context_loss_count;
77 int power_mode;
78 bool workaround_enabled;
79
80 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
81 int (*get_context_loss_count)(struct device *dev);
82
83 struct omap_gpio_reg_offs *regs;
84};
85
86#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
87#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
88#define GPIO_MOD_CTRL_BIT BIT(0)
89
90#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
91#define LINE_USED(line, offset) (line & (1 << offset))
92
93static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
94{
95 return bank->chip.base + gpio_irq;
96}
97
98static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
99{
100 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
101
102 return irq_find_mapping(bank->domain, offset);
103}
104
105static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
106{
107 void __iomem *reg = bank->base;
108 u32 l;
109
110 reg += bank->regs->direction;
111 l = readl_relaxed(reg);
112 if (is_input)
113 l |= 1 << gpio;
114 else
115 l &= ~(1 << gpio);
116 writel_relaxed(l, reg);
117 bank->context.oe = l;
118}
119
120
121/* set data out value using dedicate set/clear register */
122static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
123{
124 void __iomem *reg = bank->base;
125 u32 l = GPIO_BIT(bank, gpio);
126
127 if (enable) {
128 reg += bank->regs->set_dataout;
129 bank->context.dataout |= l;
130 } else {
131 reg += bank->regs->clr_dataout;
132 bank->context.dataout &= ~l;
133 }
134
135 writel_relaxed(l, reg);
136}
137
138/* set data out value using mask register */
139static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
140{
141 void __iomem *reg = bank->base + bank->regs->dataout;
142 u32 gpio_bit = GPIO_BIT(bank, gpio);
143 u32 l;
144
145 l = readl_relaxed(reg);
146 if (enable)
147 l |= gpio_bit;
148 else
149 l &= ~gpio_bit;
150 writel_relaxed(l, reg);
151 bank->context.dataout = l;
152}
153
154static int _get_gpio_datain(struct gpio_bank *bank, int offset)
155{
156 void __iomem *reg = bank->base + bank->regs->datain;
157
158 return (readl_relaxed(reg) & (1 << offset)) != 0;
159}
160
161static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
162{
163 void __iomem *reg = bank->base + bank->regs->dataout;
164
165 return (readl_relaxed(reg) & (1 << offset)) != 0;
166}
167
168static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
169{
170 int l = readl_relaxed(base + reg);
171
172 if (set)
173 l |= mask;
174 else
175 l &= ~mask;
176
177 writel_relaxed(l, base + reg);
178}
179
180static inline void _gpio_dbck_enable(struct gpio_bank *bank)
181{
182 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
183 clk_enable(bank->dbck);
184 bank->dbck_enabled = true;
185
186 writel_relaxed(bank->dbck_enable_mask,
187 bank->base + bank->regs->debounce_en);
188 }
189}
190
191static inline void _gpio_dbck_disable(struct gpio_bank *bank)
192{
193 if (bank->dbck_enable_mask && bank->dbck_enabled) {
194 /*
195 * Disable debounce before cutting it's clock. If debounce is
196 * enabled but the clock is not, GPIO module seems to be unable
197 * to detect events and generate interrupts at least on OMAP3.
198 */
199 writel_relaxed(0, bank->base + bank->regs->debounce_en);
200
201 clk_disable(bank->dbck);
202 bank->dbck_enabled = false;
203 }
204}
205
206/**
207 * _set_gpio_debounce - low level gpio debounce time
208 * @bank: the gpio bank we're acting upon
209 * @gpio: the gpio number on this @gpio
210 * @debounce: debounce time to use
211 *
212 * OMAP's debounce time is in 31us steps so we need
213 * to convert and round up to the closest unit.
214 */
215static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
216 unsigned debounce)
217{
218 void __iomem *reg;
219 u32 val;
220 u32 l;
221
222 if (!bank->dbck_flag)
223 return;
224
225 if (debounce < 32)
226 debounce = 0x01;
227 else if (debounce > 7936)
228 debounce = 0xff;
229 else
230 debounce = (debounce / 0x1f) - 1;
231
232 l = GPIO_BIT(bank, gpio);
233
234 clk_enable(bank->dbck);
235 reg = bank->base + bank->regs->debounce;
236 writel_relaxed(debounce, reg);
237
238 reg = bank->base + bank->regs->debounce_en;
239 val = readl_relaxed(reg);
240
241 if (debounce)
242 val |= l;
243 else
244 val &= ~l;
245 bank->dbck_enable_mask = val;
246
247 writel_relaxed(val, reg);
248 clk_disable(bank->dbck);
249 /*
250 * Enable debounce clock per module.
251 * This call is mandatory because in omap_gpio_request() when
252 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
253 * runtime callbck fails to turn on dbck because dbck_enable_mask
254 * used within _gpio_dbck_enable() is still not initialized at
255 * that point. Therefore we have to enable dbck here.
256 */
257 _gpio_dbck_enable(bank);
258 if (bank->dbck_enable_mask) {
259 bank->context.debounce = debounce;
260 bank->context.debounce_en = val;
261 }
262}
263
264/**
265 * _clear_gpio_debounce - clear debounce settings for a gpio
266 * @bank: the gpio bank we're acting upon
267 * @gpio: the gpio number on this @gpio
268 *
269 * If a gpio is using debounce, then clear the debounce enable bit and if
270 * this is the only gpio in this bank using debounce, then clear the debounce
271 * time too. The debounce clock will also be disabled when calling this function
272 * if this is the only gpio in the bank using debounce.
273 */
274static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
275{
276 u32 gpio_bit = GPIO_BIT(bank, gpio);
277
278 if (!bank->dbck_flag)
279 return;
280
281 if (!(bank->dbck_enable_mask & gpio_bit))
282 return;
283
284 bank->dbck_enable_mask &= ~gpio_bit;
285 bank->context.debounce_en &= ~gpio_bit;
286 writel_relaxed(bank->context.debounce_en,
287 bank->base + bank->regs->debounce_en);
288
289 if (!bank->dbck_enable_mask) {
290 bank->context.debounce = 0;
291 writel_relaxed(bank->context.debounce, bank->base +
292 bank->regs->debounce);
293 clk_disable(bank->dbck);
294 bank->dbck_enabled = false;
295 }
296}
297
298static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
299 unsigned trigger)
300{
301 void __iomem *base = bank->base;
302 u32 gpio_bit = 1 << gpio;
303
304 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
305 trigger & IRQ_TYPE_LEVEL_LOW);
306 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
307 trigger & IRQ_TYPE_LEVEL_HIGH);
308 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
309 trigger & IRQ_TYPE_EDGE_RISING);
310 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
311 trigger & IRQ_TYPE_EDGE_FALLING);
312
313 bank->context.leveldetect0 =
314 readl_relaxed(bank->base + bank->regs->leveldetect0);
315 bank->context.leveldetect1 =
316 readl_relaxed(bank->base + bank->regs->leveldetect1);
317 bank->context.risingdetect =
318 readl_relaxed(bank->base + bank->regs->risingdetect);
319 bank->context.fallingdetect =
320 readl_relaxed(bank->base + bank->regs->fallingdetect);
321
322 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
323 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
324 bank->context.wake_en =
325 readl_relaxed(bank->base + bank->regs->wkup_en);
326 }
327
328 /* This part needs to be executed always for OMAP{34xx, 44xx} */
329 if (!bank->regs->irqctrl) {
330 /* On omap24xx proceed only when valid GPIO bit is set */
331 if (bank->non_wakeup_gpios) {
332 if (!(bank->non_wakeup_gpios & gpio_bit))
333 goto exit;
334 }
335
336 /*
337 * Log the edge gpio and manually trigger the IRQ
338 * after resume if the input level changes
339 * to avoid irq lost during PER RET/OFF mode
340 * Applies for omap2 non-wakeup gpio and all omap3 gpios
341 */
342 if (trigger & IRQ_TYPE_EDGE_BOTH)
343 bank->enabled_non_wakeup_gpios |= gpio_bit;
344 else
345 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
346 }
347
348exit:
349 bank->level_mask =
350 readl_relaxed(bank->base + bank->regs->leveldetect0) |
351 readl_relaxed(bank->base + bank->regs->leveldetect1);
352}
353
354#ifdef CONFIG_ARCH_OMAP1
355/*
356 * This only applies to chips that can't do both rising and falling edge
357 * detection at once. For all other chips, this function is a noop.
358 */
359static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
360{
361 void __iomem *reg = bank->base;
362 u32 l = 0;
363
364 if (!bank->regs->irqctrl)
365 return;
366
367 reg += bank->regs->irqctrl;
368
369 l = readl_relaxed(reg);
370 if ((l >> gpio) & 1)
371 l &= ~(1 << gpio);
372 else
373 l |= 1 << gpio;
374
375 writel_relaxed(l, reg);
376}
377#else
378static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
379#endif
380
381static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
382 unsigned trigger)
383{
384 void __iomem *reg = bank->base;
385 void __iomem *base = bank->base;
386 u32 l = 0;
387
388 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
389 set_gpio_trigger(bank, gpio, trigger);
390 } else if (bank->regs->irqctrl) {
391 reg += bank->regs->irqctrl;
392
393 l = readl_relaxed(reg);
394 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
395 bank->toggle_mask |= 1 << gpio;
396 if (trigger & IRQ_TYPE_EDGE_RISING)
397 l |= 1 << gpio;
398 else if (trigger & IRQ_TYPE_EDGE_FALLING)
399 l &= ~(1 << gpio);
400 else
401 return -EINVAL;
402
403 writel_relaxed(l, reg);
404 } else if (bank->regs->edgectrl1) {
405 if (gpio & 0x08)
406 reg += bank->regs->edgectrl2;
407 else
408 reg += bank->regs->edgectrl1;
409
410 gpio &= 0x07;
411 l = readl_relaxed(reg);
412 l &= ~(3 << (gpio << 1));
413 if (trigger & IRQ_TYPE_EDGE_RISING)
414 l |= 2 << (gpio << 1);
415 if (trigger & IRQ_TYPE_EDGE_FALLING)
416 l |= 1 << (gpio << 1);
417
418 /* Enable wake-up during idle for dynamic tick */
419 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
420 bank->context.wake_en =
421 readl_relaxed(bank->base + bank->regs->wkup_en);
422 writel_relaxed(l, reg);
423 }
424 return 0;
425}
426
427static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
428{
429 if (bank->regs->pinctrl) {
430 void __iomem *reg = bank->base + bank->regs->pinctrl;
431
432 /* Claim the pin for MPU */
433 writel_relaxed(readl_relaxed(reg) | (1 << offset), reg);
434 }
435
436 if (bank->regs->ctrl && !BANK_USED(bank)) {
437 void __iomem *reg = bank->base + bank->regs->ctrl;
438 u32 ctrl;
439
440 ctrl = readl_relaxed(reg);
441 /* Module is enabled, clocks are not gated */
442 ctrl &= ~GPIO_MOD_CTRL_BIT;
443 writel_relaxed(ctrl, reg);
444 bank->context.ctrl = ctrl;
445 }
446}
447
448static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
449{
450 void __iomem *base = bank->base;
451
452 if (bank->regs->wkup_en &&
453 !LINE_USED(bank->mod_usage, offset) &&
454 !LINE_USED(bank->irq_usage, offset)) {
455 /* Disable wake-up during idle for dynamic tick */
456 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
457 bank->context.wake_en =
458 readl_relaxed(bank->base + bank->regs->wkup_en);
459 }
460
461 if (bank->regs->ctrl && !BANK_USED(bank)) {
462 void __iomem *reg = bank->base + bank->regs->ctrl;
463 u32 ctrl;
464
465 ctrl = readl_relaxed(reg);
466 /* Module is disabled, clocks are gated */
467 ctrl |= GPIO_MOD_CTRL_BIT;
468 writel_relaxed(ctrl, reg);
469 bank->context.ctrl = ctrl;
470 }
471}
472
473static int gpio_is_input(struct gpio_bank *bank, int mask)
474{
475 void __iomem *reg = bank->base + bank->regs->direction;
476
477 return readl_relaxed(reg) & mask;
478}
479
480static int gpio_irq_type(struct irq_data *d, unsigned type)
481{
482 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
483 unsigned gpio = 0;
484 int retval;
485 unsigned long flags;
486 unsigned offset;
487
488 if (!BANK_USED(bank))
489 pm_runtime_get_sync(bank->dev);
490
491#ifdef CONFIG_ARCH_OMAP1
492 if (d->irq > IH_MPUIO_BASE)
493 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
494#endif
495
496 if (!gpio)
497 gpio = irq_to_gpio(bank, d->hwirq);
498
499 if (type & ~IRQ_TYPE_SENSE_MASK)
500 return -EINVAL;
501
502 if (!bank->regs->leveldetect0 &&
503 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
504 return -EINVAL;
505
506 spin_lock_irqsave(&bank->lock, flags);
507 offset = GPIO_INDEX(bank, gpio);
508 retval = _set_gpio_triggering(bank, offset, type);
509 if (!LINE_USED(bank->mod_usage, offset)) {
510 _enable_gpio_module(bank, offset);
511 _set_gpio_direction(bank, offset, 1);
512 } else if (!gpio_is_input(bank, 1 << offset)) {
513 spin_unlock_irqrestore(&bank->lock, flags);
514 return -EINVAL;
515 }
516
517 retval = gpio_lock_as_irq(&bank->chip, offset);
518 if (retval) {
519 dev_err(bank->dev, "unable to lock offset %d for IRQ\n",
520 offset);
521 spin_unlock_irqrestore(&bank->lock, flags);
522 return retval;
523 }
524
525 bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio);
526 spin_unlock_irqrestore(&bank->lock, flags);
527
528 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
529 __irq_set_handler_locked(d->irq, handle_level_irq);
530 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
531 __irq_set_handler_locked(d->irq, handle_edge_irq);
532
533 return retval;
534}
535
536static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
537{
538 void __iomem *reg = bank->base;
539
540 reg += bank->regs->irqstatus;
541 writel_relaxed(gpio_mask, reg);
542
543 /* Workaround for clearing DSP GPIO interrupts to allow retention */
544 if (bank->regs->irqstatus2) {
545 reg = bank->base + bank->regs->irqstatus2;
546 writel_relaxed(gpio_mask, reg);
547 }
548
549 /* Flush posted write for the irq status to avoid spurious interrupts */
550 readl_relaxed(reg);
551}
552
553static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
554{
555 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
556}
557
558static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
559{
560 void __iomem *reg = bank->base;
561 u32 l;
562 u32 mask = (1 << bank->width) - 1;
563
564 reg += bank->regs->irqenable;
565 l = readl_relaxed(reg);
566 if (bank->regs->irqenable_inv)
567 l = ~l;
568 l &= mask;
569 return l;
570}
571
572static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
573{
574 void __iomem *reg = bank->base;
575 u32 l;
576
577 if (bank->regs->set_irqenable) {
578 reg += bank->regs->set_irqenable;
579 l = gpio_mask;
580 bank->context.irqenable1 |= gpio_mask;
581 } else {
582 reg += bank->regs->irqenable;
583 l = readl_relaxed(reg);
584 if (bank->regs->irqenable_inv)
585 l &= ~gpio_mask;
586 else
587 l |= gpio_mask;
588 bank->context.irqenable1 = l;
589 }
590
591 writel_relaxed(l, reg);
592}
593
594static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
595{
596 void __iomem *reg = bank->base;
597 u32 l;
598
599 if (bank->regs->clr_irqenable) {
600 reg += bank->regs->clr_irqenable;
601 l = gpio_mask;
602 bank->context.irqenable1 &= ~gpio_mask;
603 } else {
604 reg += bank->regs->irqenable;
605 l = readl_relaxed(reg);
606 if (bank->regs->irqenable_inv)
607 l |= gpio_mask;
608 else
609 l &= ~gpio_mask;
610 bank->context.irqenable1 = l;
611 }
612
613 writel_relaxed(l, reg);
614}
615
616static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
617{
618 if (enable)
619 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
620 else
621 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
622}
623
624/*
625 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
626 * 1510 does not seem to have a wake-up register. If JTAG is connected
627 * to the target, system will wake up always on GPIO events. While
628 * system is running all registered GPIO interrupts need to have wake-up
629 * enabled. When system is suspended, only selected GPIO interrupts need
630 * to have wake-up enabled.
631 */
632static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
633{
634 u32 gpio_bit = GPIO_BIT(bank, gpio);
635 unsigned long flags;
636
637 if (bank->non_wakeup_gpios & gpio_bit) {
638 dev_err(bank->dev,
639 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
640 return -EINVAL;
641 }
642
643 spin_lock_irqsave(&bank->lock, flags);
644 if (enable)
645 bank->context.wake_en |= gpio_bit;
646 else
647 bank->context.wake_en &= ~gpio_bit;
648
649 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
650 spin_unlock_irqrestore(&bank->lock, flags);
651
652 return 0;
653}
654
655static void _reset_gpio(struct gpio_bank *bank, int gpio)
656{
657 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
658 _set_gpio_irqenable(bank, gpio, 0);
659 _clear_gpio_irqstatus(bank, gpio);
660 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
661 _clear_gpio_debounce(bank, gpio);
662}
663
664/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
665static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
666{
667 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
668 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
669
670 return _set_gpio_wakeup(bank, gpio, enable);
671}
672
673static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
674{
675 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
676 unsigned long flags;
677
678 /*
679 * If this is the first gpio_request for the bank,
680 * enable the bank module.
681 */
682 if (!BANK_USED(bank))
683 pm_runtime_get_sync(bank->dev);
684
685 spin_lock_irqsave(&bank->lock, flags);
686 /* Set trigger to none. You need to enable the desired trigger with
687 * request_irq() or set_irq_type(). Only do this if the IRQ line has
688 * not already been requested.
689 */
690 if (!LINE_USED(bank->irq_usage, offset)) {
691 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
692 _enable_gpio_module(bank, offset);
693 }
694 bank->mod_usage |= 1 << offset;
695 spin_unlock_irqrestore(&bank->lock, flags);
696
697 return 0;
698}
699
700static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
701{
702 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
703 unsigned long flags;
704
705 spin_lock_irqsave(&bank->lock, flags);
706 bank->mod_usage &= ~(1 << offset);
707 _disable_gpio_module(bank, offset);
708 _reset_gpio(bank, bank->chip.base + offset);
709 spin_unlock_irqrestore(&bank->lock, flags);
710
711 /*
712 * If this is the last gpio to be freed in the bank,
713 * disable the bank module.
714 */
715 if (!BANK_USED(bank))
716 pm_runtime_put(bank->dev);
717}
718
719/*
720 * We need to unmask the GPIO bank interrupt as soon as possible to
721 * avoid missing GPIO interrupts for other lines in the bank.
722 * Then we need to mask-read-clear-unmask the triggered GPIO lines
723 * in the bank to avoid missing nested interrupts for a GPIO line.
724 * If we wait to unmask individual GPIO lines in the bank after the
725 * line's interrupt handler has been run, we may miss some nested
726 * interrupts.
727 */
728static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
729{
730 void __iomem *isr_reg = NULL;
731 u32 isr;
732 unsigned int bit;
733 struct gpio_bank *bank;
734 int unmasked = 0;
735 struct irq_chip *chip = irq_desc_get_chip(desc);
736
737 chained_irq_enter(chip, desc);
738
739 bank = irq_get_handler_data(irq);
740 isr_reg = bank->base + bank->regs->irqstatus;
741 pm_runtime_get_sync(bank->dev);
742
743 if (WARN_ON(!isr_reg))
744 goto exit;
745
746 while (1) {
747 u32 isr_saved, level_mask = 0;
748 u32 enabled;
749
750 enabled = _get_gpio_irqbank_mask(bank);
751 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
752
753 if (bank->level_mask)
754 level_mask = bank->level_mask & enabled;
755
756 /* clear edge sensitive interrupts before handler(s) are
757 called so that we don't miss any interrupt occurred while
758 executing them */
759 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
760 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
761 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
762
763 /* if there is only edge sensitive GPIO pin interrupts
764 configured, we could unmask GPIO bank interrupt immediately */
765 if (!level_mask && !unmasked) {
766 unmasked = 1;
767 chained_irq_exit(chip, desc);
768 }
769
770 if (!isr)
771 break;
772
773 while (isr) {
774 bit = __ffs(isr);
775 isr &= ~(1 << bit);
776
777 /*
778 * Some chips can't respond to both rising and falling
779 * at the same time. If this irq was requested with
780 * both flags, we need to flip the ICR data for the IRQ
781 * to respond to the IRQ for the opposite direction.
782 * This will be indicated in the bank toggle_mask.
783 */
784 if (bank->toggle_mask & (1 << bit))
785 _toggle_gpio_edge_triggering(bank, bit);
786
787 generic_handle_irq(irq_find_mapping(bank->domain, bit));
788 }
789 }
790 /* if bank has any level sensitive GPIO pin interrupt
791 configured, we must unmask the bank interrupt only after
792 handler(s) are executed in order to avoid spurious bank
793 interrupt */
794exit:
795 if (!unmasked)
796 chained_irq_exit(chip, desc);
797 pm_runtime_put(bank->dev);
798}
799
800static void gpio_irq_shutdown(struct irq_data *d)
801{
802 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
803 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
804 unsigned long flags;
805 unsigned offset = GPIO_INDEX(bank, gpio);
806
807 spin_lock_irqsave(&bank->lock, flags);
808 gpio_unlock_as_irq(&bank->chip, offset);
809 bank->irq_usage &= ~(1 << offset);
810 _disable_gpio_module(bank, offset);
811 _reset_gpio(bank, gpio);
812 spin_unlock_irqrestore(&bank->lock, flags);
813
814 /*
815 * If this is the last IRQ to be freed in the bank,
816 * disable the bank module.
817 */
818 if (!BANK_USED(bank))
819 pm_runtime_put(bank->dev);
820}
821
822static void gpio_ack_irq(struct irq_data *d)
823{
824 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
825 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
826
827 _clear_gpio_irqstatus(bank, gpio);
828}
829
830static void gpio_mask_irq(struct irq_data *d)
831{
832 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
833 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
834 unsigned long flags;
835
836 spin_lock_irqsave(&bank->lock, flags);
837 _set_gpio_irqenable(bank, gpio, 0);
838 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
839 spin_unlock_irqrestore(&bank->lock, flags);
840}
841
842static void gpio_unmask_irq(struct irq_data *d)
843{
844 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
845 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
846 unsigned int irq_mask = GPIO_BIT(bank, gpio);
847 u32 trigger = irqd_get_trigger_type(d);
848 unsigned long flags;
849
850 spin_lock_irqsave(&bank->lock, flags);
851 if (trigger)
852 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
853
854 /* For level-triggered GPIOs, the clearing must be done after
855 * the HW source is cleared, thus after the handler has run */
856 if (bank->level_mask & irq_mask) {
857 _set_gpio_irqenable(bank, gpio, 0);
858 _clear_gpio_irqstatus(bank, gpio);
859 }
860
861 _set_gpio_irqenable(bank, gpio, 1);
862 spin_unlock_irqrestore(&bank->lock, flags);
863}
864
865static struct irq_chip gpio_irq_chip = {
866 .name = "GPIO",
867 .irq_shutdown = gpio_irq_shutdown,
868 .irq_ack = gpio_ack_irq,
869 .irq_mask = gpio_mask_irq,
870 .irq_unmask = gpio_unmask_irq,
871 .irq_set_type = gpio_irq_type,
872 .irq_set_wake = gpio_wake_enable,
873};
874
875/*---------------------------------------------------------------------*/
876
877static int omap_mpuio_suspend_noirq(struct device *dev)
878{
879 struct platform_device *pdev = to_platform_device(dev);
880 struct gpio_bank *bank = platform_get_drvdata(pdev);
881 void __iomem *mask_reg = bank->base +
882 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
883 unsigned long flags;
884
885 spin_lock_irqsave(&bank->lock, flags);
886 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
887 spin_unlock_irqrestore(&bank->lock, flags);
888
889 return 0;
890}
891
892static int omap_mpuio_resume_noirq(struct device *dev)
893{
894 struct platform_device *pdev = to_platform_device(dev);
895 struct gpio_bank *bank = platform_get_drvdata(pdev);
896 void __iomem *mask_reg = bank->base +
897 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
898 unsigned long flags;
899
900 spin_lock_irqsave(&bank->lock, flags);
901 writel_relaxed(bank->context.wake_en, mask_reg);
902 spin_unlock_irqrestore(&bank->lock, flags);
903
904 return 0;
905}
906
907static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
908 .suspend_noirq = omap_mpuio_suspend_noirq,
909 .resume_noirq = omap_mpuio_resume_noirq,
910};
911
912/* use platform_driver for this. */
913static struct platform_driver omap_mpuio_driver = {
914 .driver = {
915 .name = "mpuio",
916 .pm = &omap_mpuio_dev_pm_ops,
917 },
918};
919
920static struct platform_device omap_mpuio_device = {
921 .name = "mpuio",
922 .id = -1,
923 .dev = {
924 .driver = &omap_mpuio_driver.driver,
925 }
926 /* could list the /proc/iomem resources */
927};
928
929static inline void mpuio_init(struct gpio_bank *bank)
930{
931 platform_set_drvdata(&omap_mpuio_device, bank);
932
933 if (platform_driver_register(&omap_mpuio_driver) == 0)
934 (void) platform_device_register(&omap_mpuio_device);
935}
936
937/*---------------------------------------------------------------------*/
938
939static int gpio_input(struct gpio_chip *chip, unsigned offset)
940{
941 struct gpio_bank *bank;
942 unsigned long flags;
943
944 bank = container_of(chip, struct gpio_bank, chip);
945 spin_lock_irqsave(&bank->lock, flags);
946 _set_gpio_direction(bank, offset, 1);
947 spin_unlock_irqrestore(&bank->lock, flags);
948 return 0;
949}
950
951static int gpio_get(struct gpio_chip *chip, unsigned offset)
952{
953 struct gpio_bank *bank;
954 u32 mask;
955
956 bank = container_of(chip, struct gpio_bank, chip);
957 mask = (1 << offset);
958
959 if (gpio_is_input(bank, mask))
960 return _get_gpio_datain(bank, offset);
961 else
962 return _get_gpio_dataout(bank, offset);
963}
964
965static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
966{
967 struct gpio_bank *bank;
968 unsigned long flags;
969
970 bank = container_of(chip, struct gpio_bank, chip);
971 spin_lock_irqsave(&bank->lock, flags);
972 bank->set_dataout(bank, offset, value);
973 _set_gpio_direction(bank, offset, 0);
974 spin_unlock_irqrestore(&bank->lock, flags);
975 return 0;
976}
977
978static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
979 unsigned debounce)
980{
981 struct gpio_bank *bank;
982 unsigned long flags;
983
984 bank = container_of(chip, struct gpio_bank, chip);
985
986 spin_lock_irqsave(&bank->lock, flags);
987 _set_gpio_debounce(bank, offset, debounce);
988 spin_unlock_irqrestore(&bank->lock, flags);
989
990 return 0;
991}
992
993static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
994{
995 struct gpio_bank *bank;
996 unsigned long flags;
997
998 bank = container_of(chip, struct gpio_bank, chip);
999 spin_lock_irqsave(&bank->lock, flags);
1000 bank->set_dataout(bank, offset, value);
1001 spin_unlock_irqrestore(&bank->lock, flags);
1002}
1003
1004/*---------------------------------------------------------------------*/
1005
1006static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1007{
1008 static bool called;
1009 u32 rev;
1010
1011 if (called || bank->regs->revision == USHRT_MAX)
1012 return;
1013
1014 rev = readw_relaxed(bank->base + bank->regs->revision);
1015 pr_info("OMAP GPIO hardware version %d.%d\n",
1016 (rev >> 4) & 0x0f, rev & 0x0f);
1017
1018 called = true;
1019}
1020
1021/* This lock class tells lockdep that GPIO irqs are in a different
1022 * category than their parents, so it won't report false recursion.
1023 */
1024static struct lock_class_key gpio_lock_class;
1025
1026static void omap_gpio_mod_init(struct gpio_bank *bank)
1027{
1028 void __iomem *base = bank->base;
1029 u32 l = 0xffffffff;
1030
1031 if (bank->width == 16)
1032 l = 0xffff;
1033
1034 if (bank->is_mpuio) {
1035 writel_relaxed(l, bank->base + bank->regs->irqenable);
1036 return;
1037 }
1038
1039 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
1040 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
1041 if (bank->regs->debounce_en)
1042 writel_relaxed(0, base + bank->regs->debounce_en);
1043
1044 /* Save OE default value (0xffffffff) in the context */
1045 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1046 /* Initialize interface clk ungated, module enabled */
1047 if (bank->regs->ctrl)
1048 writel_relaxed(0, base + bank->regs->ctrl);
1049
1050 bank->dbck = clk_get(bank->dev, "dbclk");
1051 if (IS_ERR(bank->dbck))
1052 dev_err(bank->dev, "Could not get gpio dbck\n");
1053}
1054
1055static void
1056omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1057 unsigned int num)
1058{
1059 struct irq_chip_generic *gc;
1060 struct irq_chip_type *ct;
1061
1062 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1063 handle_simple_irq);
1064 if (!gc) {
1065 dev_err(bank->dev, "Memory alloc failed for gc\n");
1066 return;
1067 }
1068
1069 ct = gc->chip_types;
1070
1071 /* NOTE: No ack required, reading IRQ status clears it. */
1072 ct->chip.irq_mask = irq_gc_mask_set_bit;
1073 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1074 ct->chip.irq_set_type = gpio_irq_type;
1075
1076 if (bank->regs->wkup_en)
1077 ct->chip.irq_set_wake = gpio_wake_enable;
1078
1079 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1080 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1081 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1082}
1083
1084static void omap_gpio_chip_init(struct gpio_bank *bank)
1085{
1086 int j;
1087 static int gpio;
1088
1089 /*
1090 * REVISIT eventually switch from OMAP-specific gpio structs
1091 * over to the generic ones
1092 */
1093 bank->chip.request = omap_gpio_request;
1094 bank->chip.free = omap_gpio_free;
1095 bank->chip.direction_input = gpio_input;
1096 bank->chip.get = gpio_get;
1097 bank->chip.direction_output = gpio_output;
1098 bank->chip.set_debounce = gpio_debounce;
1099 bank->chip.set = gpio_set;
1100 bank->chip.to_irq = omap_gpio_to_irq;
1101 if (bank->is_mpuio) {
1102 bank->chip.label = "mpuio";
1103 if (bank->regs->wkup_en)
1104 bank->chip.dev = &omap_mpuio_device.dev;
1105 bank->chip.base = OMAP_MPUIO(0);
1106 } else {
1107 bank->chip.label = "gpio";
1108 bank->chip.base = gpio;
1109 gpio += bank->width;
1110 }
1111 bank->chip.ngpio = bank->width;
1112
1113 gpiochip_add(&bank->chip);
1114
1115 for (j = 0; j < bank->width; j++) {
1116 int irq = irq_create_mapping(bank->domain, j);
1117 irq_set_lockdep_class(irq, &gpio_lock_class);
1118 irq_set_chip_data(irq, bank);
1119 if (bank->is_mpuio) {
1120 omap_mpuio_alloc_gc(bank, irq, bank->width);
1121 } else {
1122 irq_set_chip_and_handler(irq, &gpio_irq_chip,
1123 handle_simple_irq);
1124 set_irq_flags(irq, IRQF_VALID);
1125 }
1126 }
1127 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1128 irq_set_handler_data(bank->irq, bank);
1129}
1130
1131static const struct of_device_id omap_gpio_match[];
1132
1133static int omap_gpio_probe(struct platform_device *pdev)
1134{
1135 struct device *dev = &pdev->dev;
1136 struct device_node *node = dev->of_node;
1137 const struct of_device_id *match;
1138 const struct omap_gpio_platform_data *pdata;
1139 struct resource *res;
1140 struct gpio_bank *bank;
1141#ifdef CONFIG_ARCH_OMAP1
1142 int irq_base;
1143#endif
1144
1145 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1146
1147 pdata = match ? match->data : dev_get_platdata(dev);
1148 if (!pdata)
1149 return -EINVAL;
1150
1151 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1152 if (!bank) {
1153 dev_err(dev, "Memory alloc failed\n");
1154 return -ENOMEM;
1155 }
1156
1157 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1158 if (unlikely(!res)) {
1159 dev_err(dev, "Invalid IRQ resource\n");
1160 return -ENODEV;
1161 }
1162
1163 bank->irq = res->start;
1164 bank->dev = dev;
1165 bank->dbck_flag = pdata->dbck_flag;
1166 bank->stride = pdata->bank_stride;
1167 bank->width = pdata->bank_width;
1168 bank->is_mpuio = pdata->is_mpuio;
1169 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1170 bank->regs = pdata->regs;
1171#ifdef CONFIG_OF_GPIO
1172 bank->chip.of_node = of_node_get(node);
1173#endif
1174 if (node) {
1175 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1176 bank->loses_context = true;
1177 } else {
1178 bank->loses_context = pdata->loses_context;
1179
1180 if (bank->loses_context)
1181 bank->get_context_loss_count =
1182 pdata->get_context_loss_count;
1183 }
1184
1185#ifdef CONFIG_ARCH_OMAP1
1186 /*
1187 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1188 * irq_alloc_descs() and irq_domain_add_legacy() and just use a
1189 * linear IRQ domain mapping for all OMAP platforms.
1190 */
1191 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1192 if (irq_base < 0) {
1193 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1194 return -ENODEV;
1195 }
1196
1197 bank->domain = irq_domain_add_legacy(node, bank->width, irq_base,
1198 0, &irq_domain_simple_ops, NULL);
1199#else
1200 bank->domain = irq_domain_add_linear(node, bank->width,
1201 &irq_domain_simple_ops, NULL);
1202#endif
1203 if (!bank->domain) {
1204 dev_err(dev, "Couldn't register an IRQ domain\n");
1205 return -ENODEV;
1206 }
1207
1208 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1209 bank->set_dataout = _set_gpio_dataout_reg;
1210 else
1211 bank->set_dataout = _set_gpio_dataout_mask;
1212
1213 spin_lock_init(&bank->lock);
1214
1215 /* Static mapping, never released */
1216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1217 bank->base = devm_ioremap_resource(dev, res);
1218 if (IS_ERR(bank->base)) {
1219 irq_domain_remove(bank->domain);
1220 return PTR_ERR(bank->base);
1221 }
1222
1223 platform_set_drvdata(pdev, bank);
1224
1225 pm_runtime_enable(bank->dev);
1226 pm_runtime_irq_safe(bank->dev);
1227 pm_runtime_get_sync(bank->dev);
1228
1229 if (bank->is_mpuio)
1230 mpuio_init(bank);
1231
1232 omap_gpio_mod_init(bank);
1233 omap_gpio_chip_init(bank);
1234 omap_gpio_show_rev(bank);
1235
1236 pm_runtime_put(bank->dev);
1237
1238 list_add_tail(&bank->node, &omap_gpio_list);
1239
1240 return 0;
1241}
1242
1243#ifdef CONFIG_ARCH_OMAP2PLUS
1244
1245#if defined(CONFIG_PM_RUNTIME)
1246static void omap_gpio_restore_context(struct gpio_bank *bank);
1247
1248static int omap_gpio_runtime_suspend(struct device *dev)
1249{
1250 struct platform_device *pdev = to_platform_device(dev);
1251 struct gpio_bank *bank = platform_get_drvdata(pdev);
1252 u32 l1 = 0, l2 = 0;
1253 unsigned long flags;
1254 u32 wake_low, wake_hi;
1255
1256 spin_lock_irqsave(&bank->lock, flags);
1257
1258 /*
1259 * Only edges can generate a wakeup event to the PRCM.
1260 *
1261 * Therefore, ensure any wake-up capable GPIOs have
1262 * edge-detection enabled before going idle to ensure a wakeup
1263 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1264 * NDA TRM 25.5.3.1)
1265 *
1266 * The normal values will be restored upon ->runtime_resume()
1267 * by writing back the values saved in bank->context.
1268 */
1269 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1270 if (wake_low)
1271 writel_relaxed(wake_low | bank->context.fallingdetect,
1272 bank->base + bank->regs->fallingdetect);
1273 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1274 if (wake_hi)
1275 writel_relaxed(wake_hi | bank->context.risingdetect,
1276 bank->base + bank->regs->risingdetect);
1277
1278 if (!bank->enabled_non_wakeup_gpios)
1279 goto update_gpio_context_count;
1280
1281 if (bank->power_mode != OFF_MODE) {
1282 bank->power_mode = 0;
1283 goto update_gpio_context_count;
1284 }
1285 /*
1286 * If going to OFF, remove triggering for all
1287 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1288 * generated. See OMAP2420 Errata item 1.101.
1289 */
1290 bank->saved_datain = readl_relaxed(bank->base +
1291 bank->regs->datain);
1292 l1 = bank->context.fallingdetect;
1293 l2 = bank->context.risingdetect;
1294
1295 l1 &= ~bank->enabled_non_wakeup_gpios;
1296 l2 &= ~bank->enabled_non_wakeup_gpios;
1297
1298 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1299 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1300
1301 bank->workaround_enabled = true;
1302
1303update_gpio_context_count:
1304 if (bank->get_context_loss_count)
1305 bank->context_loss_count =
1306 bank->get_context_loss_count(bank->dev);
1307
1308 _gpio_dbck_disable(bank);
1309 spin_unlock_irqrestore(&bank->lock, flags);
1310
1311 return 0;
1312}
1313
1314static void omap_gpio_init_context(struct gpio_bank *p);
1315
1316static int omap_gpio_runtime_resume(struct device *dev)
1317{
1318 struct platform_device *pdev = to_platform_device(dev);
1319 struct gpio_bank *bank = platform_get_drvdata(pdev);
1320 u32 l = 0, gen, gen0, gen1;
1321 unsigned long flags;
1322 int c;
1323
1324 spin_lock_irqsave(&bank->lock, flags);
1325
1326 /*
1327 * On the first resume during the probe, the context has not
1328 * been initialised and so initialise it now. Also initialise
1329 * the context loss count.
1330 */
1331 if (bank->loses_context && !bank->context_valid) {
1332 omap_gpio_init_context(bank);
1333
1334 if (bank->get_context_loss_count)
1335 bank->context_loss_count =
1336 bank->get_context_loss_count(bank->dev);
1337 }
1338
1339 _gpio_dbck_enable(bank);
1340
1341 /*
1342 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1343 * GPIOs were set to edge trigger also in order to be able to
1344 * generate a PRCM wakeup. Here we restore the
1345 * pre-runtime_suspend() values for edge triggering.
1346 */
1347 writel_relaxed(bank->context.fallingdetect,
1348 bank->base + bank->regs->fallingdetect);
1349 writel_relaxed(bank->context.risingdetect,
1350 bank->base + bank->regs->risingdetect);
1351
1352 if (bank->loses_context) {
1353 if (!bank->get_context_loss_count) {
1354 omap_gpio_restore_context(bank);
1355 } else {
1356 c = bank->get_context_loss_count(bank->dev);
1357 if (c != bank->context_loss_count) {
1358 omap_gpio_restore_context(bank);
1359 } else {
1360 spin_unlock_irqrestore(&bank->lock, flags);
1361 return 0;
1362 }
1363 }
1364 }
1365
1366 if (!bank->workaround_enabled) {
1367 spin_unlock_irqrestore(&bank->lock, flags);
1368 return 0;
1369 }
1370
1371 l = readl_relaxed(bank->base + bank->regs->datain);
1372
1373 /*
1374 * Check if any of the non-wakeup interrupt GPIOs have changed
1375 * state. If so, generate an IRQ by software. This is
1376 * horribly racy, but it's the best we can do to work around
1377 * this silicon bug.
1378 */
1379 l ^= bank->saved_datain;
1380 l &= bank->enabled_non_wakeup_gpios;
1381
1382 /*
1383 * No need to generate IRQs for the rising edge for gpio IRQs
1384 * configured with falling edge only; and vice versa.
1385 */
1386 gen0 = l & bank->context.fallingdetect;
1387 gen0 &= bank->saved_datain;
1388
1389 gen1 = l & bank->context.risingdetect;
1390 gen1 &= ~(bank->saved_datain);
1391
1392 /* FIXME: Consider GPIO IRQs with level detections properly! */
1393 gen = l & (~(bank->context.fallingdetect) &
1394 ~(bank->context.risingdetect));
1395 /* Consider all GPIO IRQs needed to be updated */
1396 gen |= gen0 | gen1;
1397
1398 if (gen) {
1399 u32 old0, old1;
1400
1401 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1402 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1403
1404 if (!bank->regs->irqstatus_raw0) {
1405 writel_relaxed(old0 | gen, bank->base +
1406 bank->regs->leveldetect0);
1407 writel_relaxed(old1 | gen, bank->base +
1408 bank->regs->leveldetect1);
1409 }
1410
1411 if (bank->regs->irqstatus_raw0) {
1412 writel_relaxed(old0 | l, bank->base +
1413 bank->regs->leveldetect0);
1414 writel_relaxed(old1 | l, bank->base +
1415 bank->regs->leveldetect1);
1416 }
1417 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1418 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1419 }
1420
1421 bank->workaround_enabled = false;
1422 spin_unlock_irqrestore(&bank->lock, flags);
1423
1424 return 0;
1425}
1426#endif /* CONFIG_PM_RUNTIME */
1427
1428void omap2_gpio_prepare_for_idle(int pwr_mode)
1429{
1430 struct gpio_bank *bank;
1431
1432 list_for_each_entry(bank, &omap_gpio_list, node) {
1433 if (!BANK_USED(bank) || !bank->loses_context)
1434 continue;
1435
1436 bank->power_mode = pwr_mode;
1437
1438 pm_runtime_put_sync_suspend(bank->dev);
1439 }
1440}
1441
1442void omap2_gpio_resume_after_idle(void)
1443{
1444 struct gpio_bank *bank;
1445
1446 list_for_each_entry(bank, &omap_gpio_list, node) {
1447 if (!BANK_USED(bank) || !bank->loses_context)
1448 continue;
1449
1450 pm_runtime_get_sync(bank->dev);
1451 }
1452}
1453
1454#if defined(CONFIG_PM_RUNTIME)
1455static void omap_gpio_init_context(struct gpio_bank *p)
1456{
1457 struct omap_gpio_reg_offs *regs = p->regs;
1458 void __iomem *base = p->base;
1459
1460 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1461 p->context.oe = readl_relaxed(base + regs->direction);
1462 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1463 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1464 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1465 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1466 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1467 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1468 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1469
1470 if (regs->set_dataout && p->regs->clr_dataout)
1471 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1472 else
1473 p->context.dataout = readl_relaxed(base + regs->dataout);
1474
1475 p->context_valid = true;
1476}
1477
1478static void omap_gpio_restore_context(struct gpio_bank *bank)
1479{
1480 writel_relaxed(bank->context.wake_en,
1481 bank->base + bank->regs->wkup_en);
1482 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1483 writel_relaxed(bank->context.leveldetect0,
1484 bank->base + bank->regs->leveldetect0);
1485 writel_relaxed(bank->context.leveldetect1,
1486 bank->base + bank->regs->leveldetect1);
1487 writel_relaxed(bank->context.risingdetect,
1488 bank->base + bank->regs->risingdetect);
1489 writel_relaxed(bank->context.fallingdetect,
1490 bank->base + bank->regs->fallingdetect);
1491 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1492 writel_relaxed(bank->context.dataout,
1493 bank->base + bank->regs->set_dataout);
1494 else
1495 writel_relaxed(bank->context.dataout,
1496 bank->base + bank->regs->dataout);
1497 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1498
1499 if (bank->dbck_enable_mask) {
1500 writel_relaxed(bank->context.debounce, bank->base +
1501 bank->regs->debounce);
1502 writel_relaxed(bank->context.debounce_en,
1503 bank->base + bank->regs->debounce_en);
1504 }
1505
1506 writel_relaxed(bank->context.irqenable1,
1507 bank->base + bank->regs->irqenable);
1508 writel_relaxed(bank->context.irqenable2,
1509 bank->base + bank->regs->irqenable2);
1510}
1511#endif /* CONFIG_PM_RUNTIME */
1512#else
1513#define omap_gpio_runtime_suspend NULL
1514#define omap_gpio_runtime_resume NULL
1515static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1516#endif
1517
1518static const struct dev_pm_ops gpio_pm_ops = {
1519 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1520 NULL)
1521};
1522
1523#if defined(CONFIG_OF)
1524static struct omap_gpio_reg_offs omap2_gpio_regs = {
1525 .revision = OMAP24XX_GPIO_REVISION,
1526 .direction = OMAP24XX_GPIO_OE,
1527 .datain = OMAP24XX_GPIO_DATAIN,
1528 .dataout = OMAP24XX_GPIO_DATAOUT,
1529 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1530 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1531 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1532 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1533 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1534 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1535 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1536 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1537 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1538 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1539 .ctrl = OMAP24XX_GPIO_CTRL,
1540 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1541 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1542 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1543 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1544 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1545};
1546
1547static struct omap_gpio_reg_offs omap4_gpio_regs = {
1548 .revision = OMAP4_GPIO_REVISION,
1549 .direction = OMAP4_GPIO_OE,
1550 .datain = OMAP4_GPIO_DATAIN,
1551 .dataout = OMAP4_GPIO_DATAOUT,
1552 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1553 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1554 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1555 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1556 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1557 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1558 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1559 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1560 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1561 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1562 .ctrl = OMAP4_GPIO_CTRL,
1563 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1564 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1565 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1566 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1567 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1568};
1569
1570static const struct omap_gpio_platform_data omap2_pdata = {
1571 .regs = &omap2_gpio_regs,
1572 .bank_width = 32,
1573 .dbck_flag = false,
1574};
1575
1576static const struct omap_gpio_platform_data omap3_pdata = {
1577 .regs = &omap2_gpio_regs,
1578 .bank_width = 32,
1579 .dbck_flag = true,
1580};
1581
1582static const struct omap_gpio_platform_data omap4_pdata = {
1583 .regs = &omap4_gpio_regs,
1584 .bank_width = 32,
1585 .dbck_flag = true,
1586};
1587
1588static const struct of_device_id omap_gpio_match[] = {
1589 {
1590 .compatible = "ti,omap4-gpio",
1591 .data = &omap4_pdata,
1592 },
1593 {
1594 .compatible = "ti,omap3-gpio",
1595 .data = &omap3_pdata,
1596 },
1597 {
1598 .compatible = "ti,omap2-gpio",
1599 .data = &omap2_pdata,
1600 },
1601 { },
1602};
1603MODULE_DEVICE_TABLE(of, omap_gpio_match);
1604#endif
1605
1606static struct platform_driver omap_gpio_driver = {
1607 .probe = omap_gpio_probe,
1608 .driver = {
1609 .name = "omap_gpio",
1610 .pm = &gpio_pm_ops,
1611 .of_match_table = of_match_ptr(omap_gpio_match),
1612 },
1613};
1614
1615/*
1616 * gpio driver register needs to be done before
1617 * machine_init functions access gpio APIs.
1618 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1619 */
1620static int __init omap_gpio_drv_reg(void)
1621{
1622 return platform_driver_register(&omap_gpio_driver);
1623}
1624postcore_initcall(omap_gpio_drv_reg);