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1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36/* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
38 */
39
40/**
41 * DOC: uevents generated by i915 on it's device node
42 *
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
49 *
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
56 *
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
60 */
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65/**
66 * struct i915_user_extension - Base class for defining a chain of extensions
67 *
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
73 *
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
79 *
80 * Example chaining:
81 *
82 * .. code-block:: C
83 *
84 * struct i915_user_extension ext3 {
85 * .next_extension = 0, // end
86 * .name = ...,
87 * };
88 * struct i915_user_extension ext2 {
89 * .next_extension = (uintptr_t)&ext3,
90 * .name = ...,
91 * };
92 * struct i915_user_extension ext1 {
93 * .next_extension = (uintptr_t)&ext2,
94 * .name = ...,
95 * };
96 *
97 * Typically the struct i915_user_extension would be embedded in some uAPI
98 * struct, and in this case we would feed it the head of the chain(i.e ext1),
99 * which would then apply all of the above extensions.
100 *
101 */
102struct i915_user_extension {
103 /**
104 * @next_extension:
105 *
106 * Pointer to the next struct i915_user_extension, or zero if the end.
107 */
108 __u64 next_extension;
109 /**
110 * @name: Name of the extension.
111 *
112 * Note that the name here is just some integer.
113 *
114 * Also note that the name space for this is not global for the whole
115 * driver, but rather its scope/meaning is limited to the specific piece
116 * of uAPI which has embedded the struct i915_user_extension.
117 */
118 __u32 name;
119 /**
120 * @flags: MBZ
121 *
122 * All undefined bits must be zero.
123 */
124 __u32 flags;
125 /**
126 * @rsvd: MBZ
127 *
128 * Reserved for future use; must be zero.
129 */
130 __u32 rsvd[4];
131};
132
133/*
134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
136 */
137enum i915_mocs_table_index {
138 /*
139 * Not cached anywhere, coherency between CPU and GPU accesses is
140 * guaranteed.
141 */
142 I915_MOCS_UNCACHED,
143 /*
144 * Cacheability and coherency controlled by the kernel automatically
145 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
146 * usage of the surface (used for display scanout or not).
147 */
148 I915_MOCS_PTE,
149 /*
150 * Cached in all GPU caches available on the platform.
151 * Coherency between CPU and GPU accesses to the surface is not
152 * guaranteed without extra synchronization.
153 */
154 I915_MOCS_CACHED,
155};
156
157/*
158 * Different engines serve different roles, and there may be more than one
159 * engine serving each role. enum drm_i915_gem_engine_class provides a
160 * classification of the role of the engine, which may be used when requesting
161 * operations to be performed on a certain subset of engines, or for providing
162 * information about that group.
163 */
164enum drm_i915_gem_engine_class {
165 I915_ENGINE_CLASS_RENDER = 0,
166 I915_ENGINE_CLASS_COPY = 1,
167 I915_ENGINE_CLASS_VIDEO = 2,
168 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
169
170 /* should be kept compact */
171
172 I915_ENGINE_CLASS_INVALID = -1
173};
174
175/*
176 * There may be more than one engine fulfilling any role within the system.
177 * Each engine of a class is given a unique instance number and therefore
178 * any engine can be specified by its class:instance tuplet. APIs that allow
179 * access to any engine in the system will use struct i915_engine_class_instance
180 * for this identification.
181 */
182struct i915_engine_class_instance {
183 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
184 __u16 engine_instance;
185#define I915_ENGINE_CLASS_INVALID_NONE -1
186#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
187};
188
189/**
190 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
191 *
192 */
193
194enum drm_i915_pmu_engine_sample {
195 I915_SAMPLE_BUSY = 0,
196 I915_SAMPLE_WAIT = 1,
197 I915_SAMPLE_SEMA = 2
198};
199
200#define I915_PMU_SAMPLE_BITS (4)
201#define I915_PMU_SAMPLE_MASK (0xf)
202#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
203#define I915_PMU_CLASS_SHIFT \
204 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
205
206#define __I915_PMU_ENGINE(class, instance, sample) \
207 ((class) << I915_PMU_CLASS_SHIFT | \
208 (instance) << I915_PMU_SAMPLE_BITS | \
209 (sample))
210
211#define I915_PMU_ENGINE_BUSY(class, instance) \
212 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
213
214#define I915_PMU_ENGINE_WAIT(class, instance) \
215 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
216
217#define I915_PMU_ENGINE_SEMA(class, instance) \
218 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
219
220#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
221
222#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
223#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
224#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
225#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
226#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
227
228#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
229
230/* Each region is a minimum of 16k, and there are at most 255 of them.
231 */
232#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
233 * of chars for next/prev indices */
234#define I915_LOG_MIN_TEX_REGION_SIZE 14
235
236typedef struct _drm_i915_init {
237 enum {
238 I915_INIT_DMA = 0x01,
239 I915_CLEANUP_DMA = 0x02,
240 I915_RESUME_DMA = 0x03
241 } func;
242 unsigned int mmio_offset;
243 int sarea_priv_offset;
244 unsigned int ring_start;
245 unsigned int ring_end;
246 unsigned int ring_size;
247 unsigned int front_offset;
248 unsigned int back_offset;
249 unsigned int depth_offset;
250 unsigned int w;
251 unsigned int h;
252 unsigned int pitch;
253 unsigned int pitch_bits;
254 unsigned int back_pitch;
255 unsigned int depth_pitch;
256 unsigned int cpp;
257 unsigned int chipset;
258} drm_i915_init_t;
259
260typedef struct _drm_i915_sarea {
261 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
262 int last_upload; /* last time texture was uploaded */
263 int last_enqueue; /* last time a buffer was enqueued */
264 int last_dispatch; /* age of the most recently dispatched buffer */
265 int ctxOwner; /* last context to upload state */
266 int texAge;
267 int pf_enabled; /* is pageflipping allowed? */
268 int pf_active;
269 int pf_current_page; /* which buffer is being displayed? */
270 int perf_boxes; /* performance boxes to be displayed */
271 int width, height; /* screen size in pixels */
272
273 drm_handle_t front_handle;
274 int front_offset;
275 int front_size;
276
277 drm_handle_t back_handle;
278 int back_offset;
279 int back_size;
280
281 drm_handle_t depth_handle;
282 int depth_offset;
283 int depth_size;
284
285 drm_handle_t tex_handle;
286 int tex_offset;
287 int tex_size;
288 int log_tex_granularity;
289 int pitch;
290 int rotation; /* 0, 90, 180 or 270 */
291 int rotated_offset;
292 int rotated_size;
293 int rotated_pitch;
294 int virtualX, virtualY;
295
296 unsigned int front_tiled;
297 unsigned int back_tiled;
298 unsigned int depth_tiled;
299 unsigned int rotated_tiled;
300 unsigned int rotated2_tiled;
301
302 int pipeA_x;
303 int pipeA_y;
304 int pipeA_w;
305 int pipeA_h;
306 int pipeB_x;
307 int pipeB_y;
308 int pipeB_w;
309 int pipeB_h;
310
311 /* fill out some space for old userspace triple buffer */
312 drm_handle_t unused_handle;
313 __u32 unused1, unused2, unused3;
314
315 /* buffer object handles for static buffers. May change
316 * over the lifetime of the client.
317 */
318 __u32 front_bo_handle;
319 __u32 back_bo_handle;
320 __u32 unused_bo_handle;
321 __u32 depth_bo_handle;
322
323} drm_i915_sarea_t;
324
325/* due to userspace building against these headers we need some compat here */
326#define planeA_x pipeA_x
327#define planeA_y pipeA_y
328#define planeA_w pipeA_w
329#define planeA_h pipeA_h
330#define planeB_x pipeB_x
331#define planeB_y pipeB_y
332#define planeB_w pipeB_w
333#define planeB_h pipeB_h
334
335/* Flags for perf_boxes
336 */
337#define I915_BOX_RING_EMPTY 0x1
338#define I915_BOX_FLIP 0x2
339#define I915_BOX_WAIT 0x4
340#define I915_BOX_TEXTURE_LOAD 0x8
341#define I915_BOX_LOST_CONTEXT 0x10
342
343/*
344 * i915 specific ioctls.
345 *
346 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
347 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
348 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
349 */
350#define DRM_I915_INIT 0x00
351#define DRM_I915_FLUSH 0x01
352#define DRM_I915_FLIP 0x02
353#define DRM_I915_BATCHBUFFER 0x03
354#define DRM_I915_IRQ_EMIT 0x04
355#define DRM_I915_IRQ_WAIT 0x05
356#define DRM_I915_GETPARAM 0x06
357#define DRM_I915_SETPARAM 0x07
358#define DRM_I915_ALLOC 0x08
359#define DRM_I915_FREE 0x09
360#define DRM_I915_INIT_HEAP 0x0a
361#define DRM_I915_CMDBUFFER 0x0b
362#define DRM_I915_DESTROY_HEAP 0x0c
363#define DRM_I915_SET_VBLANK_PIPE 0x0d
364#define DRM_I915_GET_VBLANK_PIPE 0x0e
365#define DRM_I915_VBLANK_SWAP 0x0f
366#define DRM_I915_HWS_ADDR 0x11
367#define DRM_I915_GEM_INIT 0x13
368#define DRM_I915_GEM_EXECBUFFER 0x14
369#define DRM_I915_GEM_PIN 0x15
370#define DRM_I915_GEM_UNPIN 0x16
371#define DRM_I915_GEM_BUSY 0x17
372#define DRM_I915_GEM_THROTTLE 0x18
373#define DRM_I915_GEM_ENTERVT 0x19
374#define DRM_I915_GEM_LEAVEVT 0x1a
375#define DRM_I915_GEM_CREATE 0x1b
376#define DRM_I915_GEM_PREAD 0x1c
377#define DRM_I915_GEM_PWRITE 0x1d
378#define DRM_I915_GEM_MMAP 0x1e
379#define DRM_I915_GEM_SET_DOMAIN 0x1f
380#define DRM_I915_GEM_SW_FINISH 0x20
381#define DRM_I915_GEM_SET_TILING 0x21
382#define DRM_I915_GEM_GET_TILING 0x22
383#define DRM_I915_GEM_GET_APERTURE 0x23
384#define DRM_I915_GEM_MMAP_GTT 0x24
385#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
386#define DRM_I915_GEM_MADVISE 0x26
387#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
388#define DRM_I915_OVERLAY_ATTRS 0x28
389#define DRM_I915_GEM_EXECBUFFER2 0x29
390#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
391#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
392#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
393#define DRM_I915_GEM_WAIT 0x2c
394#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
395#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
396#define DRM_I915_GEM_SET_CACHING 0x2f
397#define DRM_I915_GEM_GET_CACHING 0x30
398#define DRM_I915_REG_READ 0x31
399#define DRM_I915_GET_RESET_STATS 0x32
400#define DRM_I915_GEM_USERPTR 0x33
401#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
402#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
403#define DRM_I915_PERF_OPEN 0x36
404#define DRM_I915_PERF_ADD_CONFIG 0x37
405#define DRM_I915_PERF_REMOVE_CONFIG 0x38
406#define DRM_I915_QUERY 0x39
407#define DRM_I915_GEM_VM_CREATE 0x3a
408#define DRM_I915_GEM_VM_DESTROY 0x3b
409#define DRM_I915_GEM_CREATE_EXT 0x3c
410/* Must be kept compact -- no holes */
411
412#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
413#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
414#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
415#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
416#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
417#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
418#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
419#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
420#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
421#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
422#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
423#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
424#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
425#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
426#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
427#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
428#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
429#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
430#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
431#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
432#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
433#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
434#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
435#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
436#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
437#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
438#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
439#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
440#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
441#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
442#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
443#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
444#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
445#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
446#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
447#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
448#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
449#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
450#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
451#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
452#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
453#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
454#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
455#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
456#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
457#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
458#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
459#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
460#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
461#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
462#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
463#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
464#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
465#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
466#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
467#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
468#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
469#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
470#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
471#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
472#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
473#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
474
475/* Allow drivers to submit batchbuffers directly to hardware, relying
476 * on the security mechanisms provided by hardware.
477 */
478typedef struct drm_i915_batchbuffer {
479 int start; /* agp offset */
480 int used; /* nr bytes in use */
481 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
482 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
483 int num_cliprects; /* mulitpass with multiple cliprects? */
484 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
485} drm_i915_batchbuffer_t;
486
487/* As above, but pass a pointer to userspace buffer which can be
488 * validated by the kernel prior to sending to hardware.
489 */
490typedef struct _drm_i915_cmdbuffer {
491 char __user *buf; /* pointer to userspace command buffer */
492 int sz; /* nr bytes in buf */
493 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
494 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
495 int num_cliprects; /* mulitpass with multiple cliprects? */
496 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
497} drm_i915_cmdbuffer_t;
498
499/* Userspace can request & wait on irq's:
500 */
501typedef struct drm_i915_irq_emit {
502 int __user *irq_seq;
503} drm_i915_irq_emit_t;
504
505typedef struct drm_i915_irq_wait {
506 int irq_seq;
507} drm_i915_irq_wait_t;
508
509/*
510 * Different modes of per-process Graphics Translation Table,
511 * see I915_PARAM_HAS_ALIASING_PPGTT
512 */
513#define I915_GEM_PPGTT_NONE 0
514#define I915_GEM_PPGTT_ALIASING 1
515#define I915_GEM_PPGTT_FULL 2
516
517/* Ioctl to query kernel params:
518 */
519#define I915_PARAM_IRQ_ACTIVE 1
520#define I915_PARAM_ALLOW_BATCHBUFFER 2
521#define I915_PARAM_LAST_DISPATCH 3
522#define I915_PARAM_CHIPSET_ID 4
523#define I915_PARAM_HAS_GEM 5
524#define I915_PARAM_NUM_FENCES_AVAIL 6
525#define I915_PARAM_HAS_OVERLAY 7
526#define I915_PARAM_HAS_PAGEFLIPPING 8
527#define I915_PARAM_HAS_EXECBUF2 9
528#define I915_PARAM_HAS_BSD 10
529#define I915_PARAM_HAS_BLT 11
530#define I915_PARAM_HAS_RELAXED_FENCING 12
531#define I915_PARAM_HAS_COHERENT_RINGS 13
532#define I915_PARAM_HAS_EXEC_CONSTANTS 14
533#define I915_PARAM_HAS_RELAXED_DELTA 15
534#define I915_PARAM_HAS_GEN7_SOL_RESET 16
535#define I915_PARAM_HAS_LLC 17
536#define I915_PARAM_HAS_ALIASING_PPGTT 18
537#define I915_PARAM_HAS_WAIT_TIMEOUT 19
538#define I915_PARAM_HAS_SEMAPHORES 20
539#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
540#define I915_PARAM_HAS_VEBOX 22
541#define I915_PARAM_HAS_SECURE_BATCHES 23
542#define I915_PARAM_HAS_PINNED_BATCHES 24
543#define I915_PARAM_HAS_EXEC_NO_RELOC 25
544#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
545#define I915_PARAM_HAS_WT 27
546#define I915_PARAM_CMD_PARSER_VERSION 28
547#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
548#define I915_PARAM_MMAP_VERSION 30
549#define I915_PARAM_HAS_BSD2 31
550#define I915_PARAM_REVISION 32
551#define I915_PARAM_SUBSLICE_TOTAL 33
552#define I915_PARAM_EU_TOTAL 34
553#define I915_PARAM_HAS_GPU_RESET 35
554#define I915_PARAM_HAS_RESOURCE_STREAMER 36
555#define I915_PARAM_HAS_EXEC_SOFTPIN 37
556#define I915_PARAM_HAS_POOLED_EU 38
557#define I915_PARAM_MIN_EU_IN_POOL 39
558#define I915_PARAM_MMAP_GTT_VERSION 40
559
560/*
561 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
562 * priorities and the driver will attempt to execute batches in priority order.
563 * The param returns a capability bitmask, nonzero implies that the scheduler
564 * is enabled, with different features present according to the mask.
565 *
566 * The initial priority for each batch is supplied by the context and is
567 * controlled via I915_CONTEXT_PARAM_PRIORITY.
568 */
569#define I915_PARAM_HAS_SCHEDULER 41
570#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
571#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
572#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
573#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
574#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
575
576#define I915_PARAM_HUC_STATUS 42
577
578/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
579 * synchronisation with implicit fencing on individual objects.
580 * See EXEC_OBJECT_ASYNC.
581 */
582#define I915_PARAM_HAS_EXEC_ASYNC 43
583
584/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
585 * both being able to pass in a sync_file fd to wait upon before executing,
586 * and being able to return a new sync_file fd that is signaled when the
587 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
588 */
589#define I915_PARAM_HAS_EXEC_FENCE 44
590
591/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
592 * user specified bufffers for post-mortem debugging of GPU hangs. See
593 * EXEC_OBJECT_CAPTURE.
594 */
595#define I915_PARAM_HAS_EXEC_CAPTURE 45
596
597#define I915_PARAM_SLICE_MASK 46
598
599/* Assuming it's uniform for each slice, this queries the mask of subslices
600 * per-slice for this system.
601 */
602#define I915_PARAM_SUBSLICE_MASK 47
603
604/*
605 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
606 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
607 */
608#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
609
610/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
611 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
612 */
613#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
614
615/*
616 * Query whether every context (both per-file default and user created) is
617 * isolated (insofar as HW supports). If this parameter is not true, then
618 * freshly created contexts may inherit values from an existing context,
619 * rather than default HW values. If true, it also ensures (insofar as HW
620 * supports) that all state set by this context will not leak to any other
621 * context.
622 *
623 * As not every engine across every gen support contexts, the returned
624 * value reports the support of context isolation for individual engines by
625 * returning a bitmask of each engine class set to true if that class supports
626 * isolation.
627 */
628#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
629
630/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
631 * registers. This used to be fixed per platform but from CNL onwards, this
632 * might vary depending on the parts.
633 */
634#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
635
636/*
637 * Once upon a time we supposed that writes through the GGTT would be
638 * immediately in physical memory (once flushed out of the CPU path). However,
639 * on a few different processors and chipsets, this is not necessarily the case
640 * as the writes appear to be buffered internally. Thus a read of the backing
641 * storage (physical memory) via a different path (with different physical tags
642 * to the indirect write via the GGTT) will see stale values from before
643 * the GGTT write. Inside the kernel, we can for the most part keep track of
644 * the different read/write domains in use (e.g. set-domain), but the assumption
645 * of coherency is baked into the ABI, hence reporting its true state in this
646 * parameter.
647 *
648 * Reports true when writes via mmap_gtt are immediately visible following an
649 * lfence to flush the WCB.
650 *
651 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
652 * internal buffer and are _not_ immediately visible to third parties accessing
653 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
654 * communications channel when reporting false is strongly disadvised.
655 */
656#define I915_PARAM_MMAP_GTT_COHERENT 52
657
658/*
659 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
660 * execution through use of explicit fence support.
661 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
662 */
663#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
664
665/*
666 * Revision of the i915-perf uAPI. The value returned helps determine what
667 * i915-perf features are available. See drm_i915_perf_property_id.
668 */
669#define I915_PARAM_PERF_REVISION 54
670
671/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
672 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
673 * I915_EXEC_USE_EXTENSIONS.
674 */
675#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
676
677/* Must be kept compact -- no holes and well documented */
678
679typedef struct drm_i915_getparam {
680 __s32 param;
681 /*
682 * WARNING: Using pointers instead of fixed-size u64 means we need to write
683 * compat32 code. Don't repeat this mistake.
684 */
685 int __user *value;
686} drm_i915_getparam_t;
687
688/* Ioctl to set kernel params:
689 */
690#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
691#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
692#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
693#define I915_SETPARAM_NUM_USED_FENCES 4
694/* Must be kept compact -- no holes */
695
696typedef struct drm_i915_setparam {
697 int param;
698 int value;
699} drm_i915_setparam_t;
700
701/* A memory manager for regions of shared memory:
702 */
703#define I915_MEM_REGION_AGP 1
704
705typedef struct drm_i915_mem_alloc {
706 int region;
707 int alignment;
708 int size;
709 int __user *region_offset; /* offset from start of fb or agp */
710} drm_i915_mem_alloc_t;
711
712typedef struct drm_i915_mem_free {
713 int region;
714 int region_offset;
715} drm_i915_mem_free_t;
716
717typedef struct drm_i915_mem_init_heap {
718 int region;
719 int size;
720 int start;
721} drm_i915_mem_init_heap_t;
722
723/* Allow memory manager to be torn down and re-initialized (eg on
724 * rotate):
725 */
726typedef struct drm_i915_mem_destroy_heap {
727 int region;
728} drm_i915_mem_destroy_heap_t;
729
730/* Allow X server to configure which pipes to monitor for vblank signals
731 */
732#define DRM_I915_VBLANK_PIPE_A 1
733#define DRM_I915_VBLANK_PIPE_B 2
734
735typedef struct drm_i915_vblank_pipe {
736 int pipe;
737} drm_i915_vblank_pipe_t;
738
739/* Schedule buffer swap at given vertical blank:
740 */
741typedef struct drm_i915_vblank_swap {
742 drm_drawable_t drawable;
743 enum drm_vblank_seq_type seqtype;
744 unsigned int sequence;
745} drm_i915_vblank_swap_t;
746
747typedef struct drm_i915_hws_addr {
748 __u64 addr;
749} drm_i915_hws_addr_t;
750
751struct drm_i915_gem_init {
752 /**
753 * Beginning offset in the GTT to be managed by the DRM memory
754 * manager.
755 */
756 __u64 gtt_start;
757 /**
758 * Ending offset in the GTT to be managed by the DRM memory
759 * manager.
760 */
761 __u64 gtt_end;
762};
763
764struct drm_i915_gem_create {
765 /**
766 * Requested size for the object.
767 *
768 * The (page-aligned) allocated size for the object will be returned.
769 */
770 __u64 size;
771 /**
772 * Returned handle for the object.
773 *
774 * Object handles are nonzero.
775 */
776 __u32 handle;
777 __u32 pad;
778};
779
780struct drm_i915_gem_pread {
781 /** Handle for the object being read. */
782 __u32 handle;
783 __u32 pad;
784 /** Offset into the object to read from */
785 __u64 offset;
786 /** Length of data to read */
787 __u64 size;
788 /**
789 * Pointer to write the data into.
790 *
791 * This is a fixed-size type for 32/64 compatibility.
792 */
793 __u64 data_ptr;
794};
795
796struct drm_i915_gem_pwrite {
797 /** Handle for the object being written to. */
798 __u32 handle;
799 __u32 pad;
800 /** Offset into the object to write to */
801 __u64 offset;
802 /** Length of data to write */
803 __u64 size;
804 /**
805 * Pointer to read the data from.
806 *
807 * This is a fixed-size type for 32/64 compatibility.
808 */
809 __u64 data_ptr;
810};
811
812struct drm_i915_gem_mmap {
813 /** Handle for the object being mapped. */
814 __u32 handle;
815 __u32 pad;
816 /** Offset in the object to map. */
817 __u64 offset;
818 /**
819 * Length of data to map.
820 *
821 * The value will be page-aligned.
822 */
823 __u64 size;
824 /**
825 * Returned pointer the data was mapped at.
826 *
827 * This is a fixed-size type for 32/64 compatibility.
828 */
829 __u64 addr_ptr;
830
831 /**
832 * Flags for extended behaviour.
833 *
834 * Added in version 2.
835 */
836 __u64 flags;
837#define I915_MMAP_WC 0x1
838};
839
840struct drm_i915_gem_mmap_gtt {
841 /** Handle for the object being mapped. */
842 __u32 handle;
843 __u32 pad;
844 /**
845 * Fake offset to use for subsequent mmap call
846 *
847 * This is a fixed-size type for 32/64 compatibility.
848 */
849 __u64 offset;
850};
851
852struct drm_i915_gem_mmap_offset {
853 /** Handle for the object being mapped. */
854 __u32 handle;
855 __u32 pad;
856 /**
857 * Fake offset to use for subsequent mmap call
858 *
859 * This is a fixed-size type for 32/64 compatibility.
860 */
861 __u64 offset;
862
863 /**
864 * Flags for extended behaviour.
865 *
866 * It is mandatory that one of the MMAP_OFFSET types
867 * (GTT, WC, WB, UC, etc) should be included.
868 */
869 __u64 flags;
870#define I915_MMAP_OFFSET_GTT 0
871#define I915_MMAP_OFFSET_WC 1
872#define I915_MMAP_OFFSET_WB 2
873#define I915_MMAP_OFFSET_UC 3
874
875 /*
876 * Zero-terminated chain of extensions.
877 *
878 * No current extensions defined; mbz.
879 */
880 __u64 extensions;
881};
882
883struct drm_i915_gem_set_domain {
884 /** Handle for the object */
885 __u32 handle;
886
887 /** New read domains */
888 __u32 read_domains;
889
890 /** New write domain */
891 __u32 write_domain;
892};
893
894struct drm_i915_gem_sw_finish {
895 /** Handle for the object */
896 __u32 handle;
897};
898
899struct drm_i915_gem_relocation_entry {
900 /**
901 * Handle of the buffer being pointed to by this relocation entry.
902 *
903 * It's appealing to make this be an index into the mm_validate_entry
904 * list to refer to the buffer, but this allows the driver to create
905 * a relocation list for state buffers and not re-write it per
906 * exec using the buffer.
907 */
908 __u32 target_handle;
909
910 /**
911 * Value to be added to the offset of the target buffer to make up
912 * the relocation entry.
913 */
914 __u32 delta;
915
916 /** Offset in the buffer the relocation entry will be written into */
917 __u64 offset;
918
919 /**
920 * Offset value of the target buffer that the relocation entry was last
921 * written as.
922 *
923 * If the buffer has the same offset as last time, we can skip syncing
924 * and writing the relocation. This value is written back out by
925 * the execbuffer ioctl when the relocation is written.
926 */
927 __u64 presumed_offset;
928
929 /**
930 * Target memory domains read by this operation.
931 */
932 __u32 read_domains;
933
934 /**
935 * Target memory domains written by this operation.
936 *
937 * Note that only one domain may be written by the whole
938 * execbuffer operation, so that where there are conflicts,
939 * the application will get -EINVAL back.
940 */
941 __u32 write_domain;
942};
943
944/** @{
945 * Intel memory domains
946 *
947 * Most of these just align with the various caches in
948 * the system and are used to flush and invalidate as
949 * objects end up cached in different domains.
950 */
951/** CPU cache */
952#define I915_GEM_DOMAIN_CPU 0x00000001
953/** Render cache, used by 2D and 3D drawing */
954#define I915_GEM_DOMAIN_RENDER 0x00000002
955/** Sampler cache, used by texture engine */
956#define I915_GEM_DOMAIN_SAMPLER 0x00000004
957/** Command queue, used to load batch buffers */
958#define I915_GEM_DOMAIN_COMMAND 0x00000008
959/** Instruction cache, used by shader programs */
960#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
961/** Vertex address cache */
962#define I915_GEM_DOMAIN_VERTEX 0x00000020
963/** GTT domain - aperture and scanout */
964#define I915_GEM_DOMAIN_GTT 0x00000040
965/** WC domain - uncached access */
966#define I915_GEM_DOMAIN_WC 0x00000080
967/** @} */
968
969struct drm_i915_gem_exec_object {
970 /**
971 * User's handle for a buffer to be bound into the GTT for this
972 * operation.
973 */
974 __u32 handle;
975
976 /** Number of relocations to be performed on this buffer */
977 __u32 relocation_count;
978 /**
979 * Pointer to array of struct drm_i915_gem_relocation_entry containing
980 * the relocations to be performed in this buffer.
981 */
982 __u64 relocs_ptr;
983
984 /** Required alignment in graphics aperture */
985 __u64 alignment;
986
987 /**
988 * Returned value of the updated offset of the object, for future
989 * presumed_offset writes.
990 */
991 __u64 offset;
992};
993
994/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
995struct drm_i915_gem_execbuffer {
996 /**
997 * List of buffers to be validated with their relocations to be
998 * performend on them.
999 *
1000 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
1001 *
1002 * These buffers must be listed in an order such that all relocations
1003 * a buffer is performing refer to buffers that have already appeared
1004 * in the validate list.
1005 */
1006 __u64 buffers_ptr;
1007 __u32 buffer_count;
1008
1009 /** Offset in the batchbuffer to start execution from. */
1010 __u32 batch_start_offset;
1011 /** Bytes used in batchbuffer from batch_start_offset */
1012 __u32 batch_len;
1013 __u32 DR1;
1014 __u32 DR4;
1015 __u32 num_cliprects;
1016 /** This is a struct drm_clip_rect *cliprects */
1017 __u64 cliprects_ptr;
1018};
1019
1020struct drm_i915_gem_exec_object2 {
1021 /**
1022 * User's handle for a buffer to be bound into the GTT for this
1023 * operation.
1024 */
1025 __u32 handle;
1026
1027 /** Number of relocations to be performed on this buffer */
1028 __u32 relocation_count;
1029 /**
1030 * Pointer to array of struct drm_i915_gem_relocation_entry containing
1031 * the relocations to be performed in this buffer.
1032 */
1033 __u64 relocs_ptr;
1034
1035 /** Required alignment in graphics aperture */
1036 __u64 alignment;
1037
1038 /**
1039 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
1040 * the user with the GTT offset at which this object will be pinned.
1041 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
1042 * presumed_offset of the object.
1043 * During execbuffer2 the kernel populates it with the value of the
1044 * current GTT offset of the object, for future presumed_offset writes.
1045 */
1046 __u64 offset;
1047
1048#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
1049#define EXEC_OBJECT_NEEDS_GTT (1<<1)
1050#define EXEC_OBJECT_WRITE (1<<2)
1051#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
1052#define EXEC_OBJECT_PINNED (1<<4)
1053#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
1054/* The kernel implicitly tracks GPU activity on all GEM objects, and
1055 * synchronises operations with outstanding rendering. This includes
1056 * rendering on other devices if exported via dma-buf. However, sometimes
1057 * this tracking is too coarse and the user knows better. For example,
1058 * if the object is split into non-overlapping ranges shared between different
1059 * clients or engines (i.e. suballocating objects), the implicit tracking
1060 * by kernel assumes that each operation affects the whole object rather
1061 * than an individual range, causing needless synchronisation between clients.
1062 * The kernel will also forgo any CPU cache flushes prior to rendering from
1063 * the object as the client is expected to be also handling such domain
1064 * tracking.
1065 *
1066 * The kernel maintains the implicit tracking in order to manage resources
1067 * used by the GPU - this flag only disables the synchronisation prior to
1068 * rendering with this object in this execbuf.
1069 *
1070 * Opting out of implicit synhronisation requires the user to do its own
1071 * explicit tracking to avoid rendering corruption. See, for example,
1072 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
1073 */
1074#define EXEC_OBJECT_ASYNC (1<<6)
1075/* Request that the contents of this execobject be copied into the error
1076 * state upon a GPU hang involving this batch for post-mortem debugging.
1077 * These buffers are recorded in no particular order as "user" in
1078 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
1079 * if the kernel supports this flag.
1080 */
1081#define EXEC_OBJECT_CAPTURE (1<<7)
1082/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
1083#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1084 __u64 flags;
1085
1086 union {
1087 __u64 rsvd1;
1088 __u64 pad_to_size;
1089 };
1090 __u64 rsvd2;
1091};
1092
1093struct drm_i915_gem_exec_fence {
1094 /**
1095 * User's handle for a drm_syncobj to wait on or signal.
1096 */
1097 __u32 handle;
1098
1099#define I915_EXEC_FENCE_WAIT (1<<0)
1100#define I915_EXEC_FENCE_SIGNAL (1<<1)
1101#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1102 __u32 flags;
1103};
1104
1105/*
1106 * See drm_i915_gem_execbuffer_ext_timeline_fences.
1107 */
1108#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
1109
1110/*
1111 * This structure describes an array of drm_syncobj and associated points for
1112 * timeline variants of drm_syncobj. It is invalid to append this structure to
1113 * the execbuf if I915_EXEC_FENCE_ARRAY is set.
1114 */
1115struct drm_i915_gem_execbuffer_ext_timeline_fences {
1116 struct i915_user_extension base;
1117
1118 /**
1119 * Number of element in the handles_ptr & value_ptr arrays.
1120 */
1121 __u64 fence_count;
1122
1123 /**
1124 * Pointer to an array of struct drm_i915_gem_exec_fence of length
1125 * fence_count.
1126 */
1127 __u64 handles_ptr;
1128
1129 /**
1130 * Pointer to an array of u64 values of length fence_count. Values
1131 * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
1132 * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
1133 */
1134 __u64 values_ptr;
1135};
1136
1137struct drm_i915_gem_execbuffer2 {
1138 /**
1139 * List of gem_exec_object2 structs
1140 */
1141 __u64 buffers_ptr;
1142 __u32 buffer_count;
1143
1144 /** Offset in the batchbuffer to start execution from. */
1145 __u32 batch_start_offset;
1146 /** Bytes used in batchbuffer from batch_start_offset */
1147 __u32 batch_len;
1148 __u32 DR1;
1149 __u32 DR4;
1150 __u32 num_cliprects;
1151 /**
1152 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1153 * & I915_EXEC_USE_EXTENSIONS are not set.
1154 *
1155 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
1156 * of struct drm_i915_gem_exec_fence and num_cliprects is the length
1157 * of the array.
1158 *
1159 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
1160 * single struct i915_user_extension and num_cliprects is 0.
1161 */
1162 __u64 cliprects_ptr;
1163#define I915_EXEC_RING_MASK (0x3f)
1164#define I915_EXEC_DEFAULT (0<<0)
1165#define I915_EXEC_RENDER (1<<0)
1166#define I915_EXEC_BSD (2<<0)
1167#define I915_EXEC_BLT (3<<0)
1168#define I915_EXEC_VEBOX (4<<0)
1169
1170/* Used for switching the constants addressing mode on gen4+ RENDER ring.
1171 * Gen6+ only supports relative addressing to dynamic state (default) and
1172 * absolute addressing.
1173 *
1174 * These flags are ignored for the BSD and BLT rings.
1175 */
1176#define I915_EXEC_CONSTANTS_MASK (3<<6)
1177#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1178#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1179#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1180 __u64 flags;
1181 __u64 rsvd1; /* now used for context info */
1182 __u64 rsvd2;
1183};
1184
1185/** Resets the SO write offset registers for transform feedback on gen7. */
1186#define I915_EXEC_GEN7_SOL_RESET (1<<8)
1187
1188/** Request a privileged ("secure") batch buffer. Note only available for
1189 * DRM_ROOT_ONLY | DRM_MASTER processes.
1190 */
1191#define I915_EXEC_SECURE (1<<9)
1192
1193/** Inform the kernel that the batch is and will always be pinned. This
1194 * negates the requirement for a workaround to be performed to avoid
1195 * an incoherent CS (such as can be found on 830/845). If this flag is
1196 * not passed, the kernel will endeavour to make sure the batch is
1197 * coherent with the CS before execution. If this flag is passed,
1198 * userspace assumes the responsibility for ensuring the same.
1199 */
1200#define I915_EXEC_IS_PINNED (1<<10)
1201
1202/** Provide a hint to the kernel that the command stream and auxiliary
1203 * state buffers already holds the correct presumed addresses and so the
1204 * relocation process may be skipped if no buffers need to be moved in
1205 * preparation for the execbuffer.
1206 */
1207#define I915_EXEC_NO_RELOC (1<<11)
1208
1209/** Use the reloc.handle as an index into the exec object array rather
1210 * than as the per-file handle.
1211 */
1212#define I915_EXEC_HANDLE_LUT (1<<12)
1213
1214/** Used for switching BSD rings on the platforms with two BSD rings */
1215#define I915_EXEC_BSD_SHIFT (13)
1216#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1217/* default ping-pong mode */
1218#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1219#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1220#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1221
1222/** Tell the kernel that the batchbuffer is processed by
1223 * the resource streamer.
1224 */
1225#define I915_EXEC_RESOURCE_STREAMER (1<<15)
1226
1227/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1228 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1229 * the batch.
1230 *
1231 * Returns -EINVAL if the sync_file fd cannot be found.
1232 */
1233#define I915_EXEC_FENCE_IN (1<<16)
1234
1235/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1236 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1237 * to the caller, and it should be close() after use. (The fd is a regular
1238 * file descriptor and will be cleaned up on process termination. It holds
1239 * a reference to the request, but nothing else.)
1240 *
1241 * The sync_file fd can be combined with other sync_file and passed either
1242 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1243 * will only occur after this request completes), or to other devices.
1244 *
1245 * Using I915_EXEC_FENCE_OUT requires use of
1246 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1247 * back to userspace. Failure to do so will cause the out-fence to always
1248 * be reported as zero, and the real fence fd to be leaked.
1249 */
1250#define I915_EXEC_FENCE_OUT (1<<17)
1251
1252/*
1253 * Traditionally the execbuf ioctl has only considered the final element in
1254 * the execobject[] to be the executable batch. Often though, the client
1255 * will known the batch object prior to construction and being able to place
1256 * it into the execobject[] array first can simplify the relocation tracking.
1257 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1258 * execobject[] as the * batch instead (the default is to use the last
1259 * element).
1260 */
1261#define I915_EXEC_BATCH_FIRST (1<<18)
1262
1263/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1264 * define an array of i915_gem_exec_fence structures which specify a set of
1265 * dma fences to wait upon or signal.
1266 */
1267#define I915_EXEC_FENCE_ARRAY (1<<19)
1268
1269/*
1270 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1271 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1272 * the batch.
1273 *
1274 * Returns -EINVAL if the sync_file fd cannot be found.
1275 */
1276#define I915_EXEC_FENCE_SUBMIT (1 << 20)
1277
1278/*
1279 * Setting I915_EXEC_USE_EXTENSIONS implies that
1280 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
1281 * list of i915_user_extension. Each i915_user_extension node is the base of a
1282 * larger structure. The list of supported structures are listed in the
1283 * drm_i915_gem_execbuffer_ext enum.
1284 */
1285#define I915_EXEC_USE_EXTENSIONS (1 << 21)
1286
1287#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
1288
1289#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1290#define i915_execbuffer2_set_context_id(eb2, context) \
1291 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1292#define i915_execbuffer2_get_context_id(eb2) \
1293 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1294
1295struct drm_i915_gem_pin {
1296 /** Handle of the buffer to be pinned. */
1297 __u32 handle;
1298 __u32 pad;
1299
1300 /** alignment required within the aperture */
1301 __u64 alignment;
1302
1303 /** Returned GTT offset of the buffer. */
1304 __u64 offset;
1305};
1306
1307struct drm_i915_gem_unpin {
1308 /** Handle of the buffer to be unpinned. */
1309 __u32 handle;
1310 __u32 pad;
1311};
1312
1313struct drm_i915_gem_busy {
1314 /** Handle of the buffer to check for busy */
1315 __u32 handle;
1316
1317 /** Return busy status
1318 *
1319 * A return of 0 implies that the object is idle (after
1320 * having flushed any pending activity), and a non-zero return that
1321 * the object is still in-flight on the GPU. (The GPU has not yet
1322 * signaled completion for all pending requests that reference the
1323 * object.) An object is guaranteed to become idle eventually (so
1324 * long as no new GPU commands are executed upon it). Due to the
1325 * asynchronous nature of the hardware, an object reported
1326 * as busy may become idle before the ioctl is completed.
1327 *
1328 * Furthermore, if the object is busy, which engine is busy is only
1329 * provided as a guide and only indirectly by reporting its class
1330 * (there may be more than one engine in each class). There are race
1331 * conditions which prevent the report of which engines are busy from
1332 * being always accurate. However, the converse is not true. If the
1333 * object is idle, the result of the ioctl, that all engines are idle,
1334 * is accurate.
1335 *
1336 * The returned dword is split into two fields to indicate both
1337 * the engine classess on which the object is being read, and the
1338 * engine class on which it is currently being written (if any).
1339 *
1340 * The low word (bits 0:15) indicate if the object is being written
1341 * to by any engine (there can only be one, as the GEM implicit
1342 * synchronisation rules force writes to be serialised). Only the
1343 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1344 * 1 not 0 etc) for the last write is reported.
1345 *
1346 * The high word (bits 16:31) are a bitmask of which engines classes
1347 * are currently reading from the object. Multiple engines may be
1348 * reading from the object simultaneously.
1349 *
1350 * The value of each engine class is the same as specified in the
1351 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1352 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1353 * reported as active itself. Some hardware may have parallel
1354 * execution engines, e.g. multiple media engines, which are
1355 * mapped to the same class identifier and so are not separately
1356 * reported for busyness.
1357 *
1358 * Caveat emptor:
1359 * Only the boolean result of this query is reliable; that is whether
1360 * the object is idle or busy. The report of which engines are busy
1361 * should be only used as a heuristic.
1362 */
1363 __u32 busy;
1364};
1365
1366/**
1367 * I915_CACHING_NONE
1368 *
1369 * GPU access is not coherent with cpu caches. Default for machines without an
1370 * LLC.
1371 */
1372#define I915_CACHING_NONE 0
1373/**
1374 * I915_CACHING_CACHED
1375 *
1376 * GPU access is coherent with cpu caches and furthermore the data is cached in
1377 * last-level caches shared between cpu cores and the gpu GT. Default on
1378 * machines with HAS_LLC.
1379 */
1380#define I915_CACHING_CACHED 1
1381/**
1382 * I915_CACHING_DISPLAY
1383 *
1384 * Special GPU caching mode which is coherent with the scanout engines.
1385 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1386 * cache mode (like write-through or gfdt flushing) is available. The kernel
1387 * automatically sets this mode when using a buffer as a scanout target.
1388 * Userspace can manually set this mode to avoid a costly stall and clflush in
1389 * the hotpath of drawing the first frame.
1390 */
1391#define I915_CACHING_DISPLAY 2
1392
1393struct drm_i915_gem_caching {
1394 /**
1395 * Handle of the buffer to set/get the caching level of. */
1396 __u32 handle;
1397
1398 /**
1399 * Cacheing level to apply or return value
1400 *
1401 * bits0-15 are for generic caching control (i.e. the above defined
1402 * values). bits16-31 are reserved for platform-specific variations
1403 * (e.g. l3$ caching on gen7). */
1404 __u32 caching;
1405};
1406
1407#define I915_TILING_NONE 0
1408#define I915_TILING_X 1
1409#define I915_TILING_Y 2
1410#define I915_TILING_LAST I915_TILING_Y
1411
1412#define I915_BIT_6_SWIZZLE_NONE 0
1413#define I915_BIT_6_SWIZZLE_9 1
1414#define I915_BIT_6_SWIZZLE_9_10 2
1415#define I915_BIT_6_SWIZZLE_9_11 3
1416#define I915_BIT_6_SWIZZLE_9_10_11 4
1417/* Not seen by userland */
1418#define I915_BIT_6_SWIZZLE_UNKNOWN 5
1419/* Seen by userland. */
1420#define I915_BIT_6_SWIZZLE_9_17 6
1421#define I915_BIT_6_SWIZZLE_9_10_17 7
1422
1423struct drm_i915_gem_set_tiling {
1424 /** Handle of the buffer to have its tiling state updated */
1425 __u32 handle;
1426
1427 /**
1428 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1429 * I915_TILING_Y).
1430 *
1431 * This value is to be set on request, and will be updated by the
1432 * kernel on successful return with the actual chosen tiling layout.
1433 *
1434 * The tiling mode may be demoted to I915_TILING_NONE when the system
1435 * has bit 6 swizzling that can't be managed correctly by GEM.
1436 *
1437 * Buffer contents become undefined when changing tiling_mode.
1438 */
1439 __u32 tiling_mode;
1440
1441 /**
1442 * Stride in bytes for the object when in I915_TILING_X or
1443 * I915_TILING_Y.
1444 */
1445 __u32 stride;
1446
1447 /**
1448 * Returned address bit 6 swizzling required for CPU access through
1449 * mmap mapping.
1450 */
1451 __u32 swizzle_mode;
1452};
1453
1454struct drm_i915_gem_get_tiling {
1455 /** Handle of the buffer to get tiling state for. */
1456 __u32 handle;
1457
1458 /**
1459 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1460 * I915_TILING_Y).
1461 */
1462 __u32 tiling_mode;
1463
1464 /**
1465 * Returned address bit 6 swizzling required for CPU access through
1466 * mmap mapping.
1467 */
1468 __u32 swizzle_mode;
1469
1470 /**
1471 * Returned address bit 6 swizzling required for CPU access through
1472 * mmap mapping whilst bound.
1473 */
1474 __u32 phys_swizzle_mode;
1475};
1476
1477struct drm_i915_gem_get_aperture {
1478 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1479 __u64 aper_size;
1480
1481 /**
1482 * Available space in the aperture used by i915_gem_execbuffer, in
1483 * bytes
1484 */
1485 __u64 aper_available_size;
1486};
1487
1488struct drm_i915_get_pipe_from_crtc_id {
1489 /** ID of CRTC being requested **/
1490 __u32 crtc_id;
1491
1492 /** pipe of requested CRTC **/
1493 __u32 pipe;
1494};
1495
1496#define I915_MADV_WILLNEED 0
1497#define I915_MADV_DONTNEED 1
1498#define __I915_MADV_PURGED 2 /* internal state */
1499
1500struct drm_i915_gem_madvise {
1501 /** Handle of the buffer to change the backing store advice */
1502 __u32 handle;
1503
1504 /* Advice: either the buffer will be needed again in the near future,
1505 * or wont be and could be discarded under memory pressure.
1506 */
1507 __u32 madv;
1508
1509 /** Whether the backing store still exists. */
1510 __u32 retained;
1511};
1512
1513/* flags */
1514#define I915_OVERLAY_TYPE_MASK 0xff
1515#define I915_OVERLAY_YUV_PLANAR 0x01
1516#define I915_OVERLAY_YUV_PACKED 0x02
1517#define I915_OVERLAY_RGB 0x03
1518
1519#define I915_OVERLAY_DEPTH_MASK 0xff00
1520#define I915_OVERLAY_RGB24 0x1000
1521#define I915_OVERLAY_RGB16 0x2000
1522#define I915_OVERLAY_RGB15 0x3000
1523#define I915_OVERLAY_YUV422 0x0100
1524#define I915_OVERLAY_YUV411 0x0200
1525#define I915_OVERLAY_YUV420 0x0300
1526#define I915_OVERLAY_YUV410 0x0400
1527
1528#define I915_OVERLAY_SWAP_MASK 0xff0000
1529#define I915_OVERLAY_NO_SWAP 0x000000
1530#define I915_OVERLAY_UV_SWAP 0x010000
1531#define I915_OVERLAY_Y_SWAP 0x020000
1532#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1533
1534#define I915_OVERLAY_FLAGS_MASK 0xff000000
1535#define I915_OVERLAY_ENABLE 0x01000000
1536
1537struct drm_intel_overlay_put_image {
1538 /* various flags and src format description */
1539 __u32 flags;
1540 /* source picture description */
1541 __u32 bo_handle;
1542 /* stride values and offsets are in bytes, buffer relative */
1543 __u16 stride_Y; /* stride for packed formats */
1544 __u16 stride_UV;
1545 __u32 offset_Y; /* offset for packet formats */
1546 __u32 offset_U;
1547 __u32 offset_V;
1548 /* in pixels */
1549 __u16 src_width;
1550 __u16 src_height;
1551 /* to compensate the scaling factors for partially covered surfaces */
1552 __u16 src_scan_width;
1553 __u16 src_scan_height;
1554 /* output crtc description */
1555 __u32 crtc_id;
1556 __u16 dst_x;
1557 __u16 dst_y;
1558 __u16 dst_width;
1559 __u16 dst_height;
1560};
1561
1562/* flags */
1563#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1564#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1565#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1566struct drm_intel_overlay_attrs {
1567 __u32 flags;
1568 __u32 color_key;
1569 __s32 brightness;
1570 __u32 contrast;
1571 __u32 saturation;
1572 __u32 gamma0;
1573 __u32 gamma1;
1574 __u32 gamma2;
1575 __u32 gamma3;
1576 __u32 gamma4;
1577 __u32 gamma5;
1578};
1579
1580/*
1581 * Intel sprite handling
1582 *
1583 * Color keying works with a min/mask/max tuple. Both source and destination
1584 * color keying is allowed.
1585 *
1586 * Source keying:
1587 * Sprite pixels within the min & max values, masked against the color channels
1588 * specified in the mask field, will be transparent. All other pixels will
1589 * be displayed on top of the primary plane. For RGB surfaces, only the min
1590 * and mask fields will be used; ranged compares are not allowed.
1591 *
1592 * Destination keying:
1593 * Primary plane pixels that match the min value, masked against the color
1594 * channels specified in the mask field, will be replaced by corresponding
1595 * pixels from the sprite plane.
1596 *
1597 * Note that source & destination keying are exclusive; only one can be
1598 * active on a given plane.
1599 */
1600
1601#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1602 * flags==0 to disable colorkeying.
1603 */
1604#define I915_SET_COLORKEY_DESTINATION (1<<1)
1605#define I915_SET_COLORKEY_SOURCE (1<<2)
1606struct drm_intel_sprite_colorkey {
1607 __u32 plane_id;
1608 __u32 min_value;
1609 __u32 channel_mask;
1610 __u32 max_value;
1611 __u32 flags;
1612};
1613
1614struct drm_i915_gem_wait {
1615 /** Handle of BO we shall wait on */
1616 __u32 bo_handle;
1617 __u32 flags;
1618 /** Number of nanoseconds to wait, Returns time remaining. */
1619 __s64 timeout_ns;
1620};
1621
1622struct drm_i915_gem_context_create {
1623 __u32 ctx_id; /* output: id of new context*/
1624 __u32 pad;
1625};
1626
1627struct drm_i915_gem_context_create_ext {
1628 __u32 ctx_id; /* output: id of new context*/
1629 __u32 flags;
1630#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1631#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1632#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1633 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1634 __u64 extensions;
1635};
1636
1637struct drm_i915_gem_context_param {
1638 __u32 ctx_id;
1639 __u32 size;
1640 __u64 param;
1641#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1642#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1643#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1644#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1645#define I915_CONTEXT_PARAM_BANNABLE 0x5
1646#define I915_CONTEXT_PARAM_PRIORITY 0x6
1647#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1648#define I915_CONTEXT_DEFAULT_PRIORITY 0
1649#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1650 /*
1651 * When using the following param, value should be a pointer to
1652 * drm_i915_gem_context_param_sseu.
1653 */
1654#define I915_CONTEXT_PARAM_SSEU 0x7
1655
1656/*
1657 * Not all clients may want to attempt automatic recover of a context after
1658 * a hang (for example, some clients may only submit very small incremental
1659 * batches relying on known logical state of previous batches which will never
1660 * recover correctly and each attempt will hang), and so would prefer that
1661 * the context is forever banned instead.
1662 *
1663 * If set to false (0), after a reset, subsequent (and in flight) rendering
1664 * from this context is discarded, and the client will need to create a new
1665 * context to use instead.
1666 *
1667 * If set to true (1), the kernel will automatically attempt to recover the
1668 * context by skipping the hanging batch and executing the next batch starting
1669 * from the default context state (discarding the incomplete logical context
1670 * state lost due to the reset).
1671 *
1672 * On creation, all new contexts are marked as recoverable.
1673 */
1674#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1675
1676 /*
1677 * The id of the associated virtual memory address space (ppGTT) of
1678 * this context. Can be retrieved and passed to another context
1679 * (on the same fd) for both to use the same ppGTT and so share
1680 * address layouts, and avoid reloading the page tables on context
1681 * switches between themselves.
1682 *
1683 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1684 */
1685#define I915_CONTEXT_PARAM_VM 0x9
1686
1687/*
1688 * I915_CONTEXT_PARAM_ENGINES:
1689 *
1690 * Bind this context to operate on this subset of available engines. Henceforth,
1691 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1692 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1693 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1694 * Use
1695 * engine_class: I915_ENGINE_CLASS_INVALID,
1696 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1697 * to specify a gap in the array that can be filled in later, e.g. by a
1698 * virtual engine used for load balancing.
1699 *
1700 * Setting the number of engines bound to the context to 0, by passing a zero
1701 * sized argument, will revert back to default settings.
1702 *
1703 * See struct i915_context_param_engines.
1704 *
1705 * Extensions:
1706 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1707 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1708 */
1709#define I915_CONTEXT_PARAM_ENGINES 0xa
1710
1711/*
1712 * I915_CONTEXT_PARAM_PERSISTENCE:
1713 *
1714 * Allow the context and active rendering to survive the process until
1715 * completion. Persistence allows fire-and-forget clients to queue up a
1716 * bunch of work, hand the output over to a display server and then quit.
1717 * If the context is marked as not persistent, upon closing (either via
1718 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
1719 * or process termination), the context and any outstanding requests will be
1720 * cancelled (and exported fences for cancelled requests marked as -EIO).
1721 *
1722 * By default, new contexts allow persistence.
1723 */
1724#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1725
1726/*
1727 * I915_CONTEXT_PARAM_RINGSIZE:
1728 *
1729 * Sets the size of the CS ringbuffer to use for logical ring contexts. This
1730 * applies a limit of how many batches can be queued to HW before the caller
1731 * is blocked due to lack of space for more commands.
1732 *
1733 * Only reliably possible to be set prior to first use, i.e. during
1734 * construction. At any later point, the current execution must be flushed as
1735 * the ring can only be changed while the context is idle. Note, the ringsize
1736 * can be specified as a constructor property, see
1737 * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
1738 *
1739 * Only applies to the current set of engine and lost when those engines
1740 * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
1741 *
1742 * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
1743 * Default is 16 KiB.
1744 */
1745#define I915_CONTEXT_PARAM_RINGSIZE 0xc
1746/* Must be kept compact -- no holes and well documented */
1747
1748 __u64 value;
1749};
1750
1751/*
1752 * Context SSEU programming
1753 *
1754 * It may be necessary for either functional or performance reason to configure
1755 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1756 * Sub-slice/EU).
1757 *
1758 * This is done by configuring SSEU configuration using the below
1759 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1760 * userspace intends to use.
1761 *
1762 * Not all GPUs or engines support this functionality in which case an error
1763 * code -ENODEV will be returned.
1764 *
1765 * Also, flexibility of possible SSEU configuration permutations varies between
1766 * GPU generations and software imposed limitations. Requesting such a
1767 * combination will return an error code of -EINVAL.
1768 *
1769 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1770 * favour of a single global setting.
1771 */
1772struct drm_i915_gem_context_param_sseu {
1773 /*
1774 * Engine class & instance to be configured or queried.
1775 */
1776 struct i915_engine_class_instance engine;
1777
1778 /*
1779 * Unknown flags must be cleared to zero.
1780 */
1781 __u32 flags;
1782#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1783
1784 /*
1785 * Mask of slices to enable for the context. Valid values are a subset
1786 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1787 */
1788 __u64 slice_mask;
1789
1790 /*
1791 * Mask of subslices to enable for the context. Valid values are a
1792 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1793 */
1794 __u64 subslice_mask;
1795
1796 /*
1797 * Minimum/Maximum number of EUs to enable per subslice for the
1798 * context. min_eus_per_subslice must be inferior or equal to
1799 * max_eus_per_subslice.
1800 */
1801 __u16 min_eus_per_subslice;
1802 __u16 max_eus_per_subslice;
1803
1804 /*
1805 * Unused for now. Must be cleared to zero.
1806 */
1807 __u32 rsvd;
1808};
1809
1810/*
1811 * i915_context_engines_load_balance:
1812 *
1813 * Enable load balancing across this set of engines.
1814 *
1815 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1816 * used will proxy the execbuffer request onto one of the set of engines
1817 * in such a way as to distribute the load evenly across the set.
1818 *
1819 * The set of engines must be compatible (e.g. the same HW class) as they
1820 * will share the same logical GPU context and ring.
1821 *
1822 * To intermix rendering with the virtual engine and direct rendering onto
1823 * the backing engines (bypassing the load balancing proxy), the context must
1824 * be defined to use a single timeline for all engines.
1825 */
1826struct i915_context_engines_load_balance {
1827 struct i915_user_extension base;
1828
1829 __u16 engine_index;
1830 __u16 num_siblings;
1831 __u32 flags; /* all undefined flags must be zero */
1832
1833 __u64 mbz64; /* reserved for future use; must be zero */
1834
1835 struct i915_engine_class_instance engines[0];
1836} __attribute__((packed));
1837
1838#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1839 struct i915_user_extension base; \
1840 __u16 engine_index; \
1841 __u16 num_siblings; \
1842 __u32 flags; \
1843 __u64 mbz64; \
1844 struct i915_engine_class_instance engines[N__]; \
1845} __attribute__((packed)) name__
1846
1847/*
1848 * i915_context_engines_bond:
1849 *
1850 * Constructed bonded pairs for execution within a virtual engine.
1851 *
1852 * All engines are equal, but some are more equal than others. Given
1853 * the distribution of resources in the HW, it may be preferable to run
1854 * a request on a given subset of engines in parallel to a request on a
1855 * specific engine. We enable this selection of engines within a virtual
1856 * engine by specifying bonding pairs, for any given master engine we will
1857 * only execute on one of the corresponding siblings within the virtual engine.
1858 *
1859 * To execute a request in parallel on the master engine and a sibling requires
1860 * coordination with a I915_EXEC_FENCE_SUBMIT.
1861 */
1862struct i915_context_engines_bond {
1863 struct i915_user_extension base;
1864
1865 struct i915_engine_class_instance master;
1866
1867 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1868 __u16 num_bonds;
1869
1870 __u64 flags; /* all undefined flags must be zero */
1871 __u64 mbz64[4]; /* reserved for future use; must be zero */
1872
1873 struct i915_engine_class_instance engines[0];
1874} __attribute__((packed));
1875
1876#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1877 struct i915_user_extension base; \
1878 struct i915_engine_class_instance master; \
1879 __u16 virtual_index; \
1880 __u16 num_bonds; \
1881 __u64 flags; \
1882 __u64 mbz64[4]; \
1883 struct i915_engine_class_instance engines[N__]; \
1884} __attribute__((packed)) name__
1885
1886struct i915_context_param_engines {
1887 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1888#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1889#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1890 struct i915_engine_class_instance engines[0];
1891} __attribute__((packed));
1892
1893#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1894 __u64 extensions; \
1895 struct i915_engine_class_instance engines[N__]; \
1896} __attribute__((packed)) name__
1897
1898struct drm_i915_gem_context_create_ext_setparam {
1899#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1900 struct i915_user_extension base;
1901 struct drm_i915_gem_context_param param;
1902};
1903
1904struct drm_i915_gem_context_create_ext_clone {
1905#define I915_CONTEXT_CREATE_EXT_CLONE 1
1906 struct i915_user_extension base;
1907 __u32 clone_id;
1908 __u32 flags;
1909#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1910#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1911#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1912#define I915_CONTEXT_CLONE_SSEU (1u << 3)
1913#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1914#define I915_CONTEXT_CLONE_VM (1u << 5)
1915#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1916 __u64 rsvd;
1917};
1918
1919struct drm_i915_gem_context_destroy {
1920 __u32 ctx_id;
1921 __u32 pad;
1922};
1923
1924/*
1925 * DRM_I915_GEM_VM_CREATE -
1926 *
1927 * Create a new virtual memory address space (ppGTT) for use within a context
1928 * on the same file. Extensions can be provided to configure exactly how the
1929 * address space is setup upon creation.
1930 *
1931 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1932 * returned in the outparam @id.
1933 *
1934 * No flags are defined, with all bits reserved and must be zero.
1935 *
1936 * An extension chain maybe provided, starting with @extensions, and terminated
1937 * by the @next_extension being 0. Currently, no extensions are defined.
1938 *
1939 * DRM_I915_GEM_VM_DESTROY -
1940 *
1941 * Destroys a previously created VM id, specified in @id.
1942 *
1943 * No extensions or flags are allowed currently, and so must be zero.
1944 */
1945struct drm_i915_gem_vm_control {
1946 __u64 extensions;
1947 __u32 flags;
1948 __u32 vm_id;
1949};
1950
1951struct drm_i915_reg_read {
1952 /*
1953 * Register offset.
1954 * For 64bit wide registers where the upper 32bits don't immediately
1955 * follow the lower 32bits, the offset of the lower 32bits must
1956 * be specified
1957 */
1958 __u64 offset;
1959#define I915_REG_READ_8B_WA (1ul << 0)
1960
1961 __u64 val; /* Return value */
1962};
1963
1964/* Known registers:
1965 *
1966 * Render engine timestamp - 0x2358 + 64bit - gen7+
1967 * - Note this register returns an invalid value if using the default
1968 * single instruction 8byte read, in order to workaround that pass
1969 * flag I915_REG_READ_8B_WA in offset field.
1970 *
1971 */
1972
1973struct drm_i915_reset_stats {
1974 __u32 ctx_id;
1975 __u32 flags;
1976
1977 /* All resets since boot/module reload, for all contexts */
1978 __u32 reset_count;
1979
1980 /* Number of batches lost when active in GPU, for this context */
1981 __u32 batch_active;
1982
1983 /* Number of batches lost pending for execution, for this context */
1984 __u32 batch_pending;
1985
1986 __u32 pad;
1987};
1988
1989struct drm_i915_gem_userptr {
1990 __u64 user_ptr;
1991 __u64 user_size;
1992 __u32 flags;
1993#define I915_USERPTR_READ_ONLY 0x1
1994#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1995 /**
1996 * Returned handle for the object.
1997 *
1998 * Object handles are nonzero.
1999 */
2000 __u32 handle;
2001};
2002
2003enum drm_i915_oa_format {
2004 I915_OA_FORMAT_A13 = 1, /* HSW only */
2005 I915_OA_FORMAT_A29, /* HSW only */
2006 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
2007 I915_OA_FORMAT_B4_C8, /* HSW only */
2008 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
2009 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
2010 I915_OA_FORMAT_C4_B8, /* HSW+ */
2011
2012 /* Gen8+ */
2013 I915_OA_FORMAT_A12,
2014 I915_OA_FORMAT_A12_B8_C8,
2015 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
2016
2017 I915_OA_FORMAT_MAX /* non-ABI */
2018};
2019
2020enum drm_i915_perf_property_id {
2021 /**
2022 * Open the stream for a specific context handle (as used with
2023 * execbuffer2). A stream opened for a specific context this way
2024 * won't typically require root privileges.
2025 *
2026 * This property is available in perf revision 1.
2027 */
2028 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
2029
2030 /**
2031 * A value of 1 requests the inclusion of raw OA unit reports as
2032 * part of stream samples.
2033 *
2034 * This property is available in perf revision 1.
2035 */
2036 DRM_I915_PERF_PROP_SAMPLE_OA,
2037
2038 /**
2039 * The value specifies which set of OA unit metrics should be
2040 * configured, defining the contents of any OA unit reports.
2041 *
2042 * This property is available in perf revision 1.
2043 */
2044 DRM_I915_PERF_PROP_OA_METRICS_SET,
2045
2046 /**
2047 * The value specifies the size and layout of OA unit reports.
2048 *
2049 * This property is available in perf revision 1.
2050 */
2051 DRM_I915_PERF_PROP_OA_FORMAT,
2052
2053 /**
2054 * Specifying this property implicitly requests periodic OA unit
2055 * sampling and (at least on Haswell) the sampling frequency is derived
2056 * from this exponent as follows:
2057 *
2058 * 80ns * 2^(period_exponent + 1)
2059 *
2060 * This property is available in perf revision 1.
2061 */
2062 DRM_I915_PERF_PROP_OA_EXPONENT,
2063
2064 /**
2065 * Specifying this property is only valid when specify a context to
2066 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
2067 * will hold preemption of the particular context we want to gather
2068 * performance data about. The execbuf2 submissions must include a
2069 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
2070 *
2071 * This property is available in perf revision 3.
2072 */
2073 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
2074
2075 /**
2076 * Specifying this pins all contexts to the specified SSEU power
2077 * configuration for the duration of the recording.
2078 *
2079 * This parameter's value is a pointer to a struct
2080 * drm_i915_gem_context_param_sseu.
2081 *
2082 * This property is available in perf revision 4.
2083 */
2084 DRM_I915_PERF_PROP_GLOBAL_SSEU,
2085
2086 /**
2087 * This optional parameter specifies the timer interval in nanoseconds
2088 * at which the i915 driver will check the OA buffer for available data.
2089 * Minimum allowed value is 100 microseconds. A default value is used by
2090 * the driver if this parameter is not specified. Note that larger timer
2091 * values will reduce cpu consumption during OA perf captures. However,
2092 * excessively large values would potentially result in OA buffer
2093 * overwrites as captures reach end of the OA buffer.
2094 *
2095 * This property is available in perf revision 5.
2096 */
2097 DRM_I915_PERF_PROP_POLL_OA_PERIOD,
2098
2099 DRM_I915_PERF_PROP_MAX /* non-ABI */
2100};
2101
2102struct drm_i915_perf_open_param {
2103 __u32 flags;
2104#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
2105#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
2106#define I915_PERF_FLAG_DISABLED (1<<2)
2107
2108 /** The number of u64 (id, value) pairs */
2109 __u32 num_properties;
2110
2111 /**
2112 * Pointer to array of u64 (id, value) pairs configuring the stream
2113 * to open.
2114 */
2115 __u64 properties_ptr;
2116};
2117
2118/*
2119 * Enable data capture for a stream that was either opened in a disabled state
2120 * via I915_PERF_FLAG_DISABLED or was later disabled via
2121 * I915_PERF_IOCTL_DISABLE.
2122 *
2123 * It is intended to be cheaper to disable and enable a stream than it may be
2124 * to close and re-open a stream with the same configuration.
2125 *
2126 * It's undefined whether any pending data for the stream will be lost.
2127 *
2128 * This ioctl is available in perf revision 1.
2129 */
2130#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
2131
2132/*
2133 * Disable data capture for a stream.
2134 *
2135 * It is an error to try and read a stream that is disabled.
2136 *
2137 * This ioctl is available in perf revision 1.
2138 */
2139#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
2140
2141/*
2142 * Change metrics_set captured by a stream.
2143 *
2144 * If the stream is bound to a specific context, the configuration change
2145 * will performed inline with that context such that it takes effect before
2146 * the next execbuf submission.
2147 *
2148 * Returns the previously bound metrics set id, or a negative error code.
2149 *
2150 * This ioctl is available in perf revision 2.
2151 */
2152#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
2153
2154/*
2155 * Common to all i915 perf records
2156 */
2157struct drm_i915_perf_record_header {
2158 __u32 type;
2159 __u16 pad;
2160 __u16 size;
2161};
2162
2163enum drm_i915_perf_record_type {
2164
2165 /**
2166 * Samples are the work horse record type whose contents are extensible
2167 * and defined when opening an i915 perf stream based on the given
2168 * properties.
2169 *
2170 * Boolean properties following the naming convention
2171 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
2172 * every sample.
2173 *
2174 * The order of these sample properties given by userspace has no
2175 * affect on the ordering of data within a sample. The order is
2176 * documented here.
2177 *
2178 * struct {
2179 * struct drm_i915_perf_record_header header;
2180 *
2181 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
2182 * };
2183 */
2184 DRM_I915_PERF_RECORD_SAMPLE = 1,
2185
2186 /*
2187 * Indicates that one or more OA reports were not written by the
2188 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
2189 * command collides with periodic sampling - which would be more likely
2190 * at higher sampling frequencies.
2191 */
2192 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
2193
2194 /**
2195 * An error occurred that resulted in all pending OA reports being lost.
2196 */
2197 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
2198
2199 DRM_I915_PERF_RECORD_MAX /* non-ABI */
2200};
2201
2202/*
2203 * Structure to upload perf dynamic configuration into the kernel.
2204 */
2205struct drm_i915_perf_oa_config {
2206 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
2207 char uuid[36];
2208
2209 __u32 n_mux_regs;
2210 __u32 n_boolean_regs;
2211 __u32 n_flex_regs;
2212
2213 /*
2214 * These fields are pointers to tuples of u32 values (register address,
2215 * value). For example the expected length of the buffer pointed by
2216 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
2217 */
2218 __u64 mux_regs_ptr;
2219 __u64 boolean_regs_ptr;
2220 __u64 flex_regs_ptr;
2221};
2222
2223/**
2224 * struct drm_i915_query_item - An individual query for the kernel to process.
2225 *
2226 * The behaviour is determined by the @query_id. Note that exactly what
2227 * @data_ptr is also depends on the specific @query_id.
2228 */
2229struct drm_i915_query_item {
2230 /** @query_id: The id for this query */
2231 __u64 query_id;
2232#define DRM_I915_QUERY_TOPOLOGY_INFO 1
2233#define DRM_I915_QUERY_ENGINE_INFO 2
2234#define DRM_I915_QUERY_PERF_CONFIG 3
2235#define DRM_I915_QUERY_MEMORY_REGIONS 4
2236/* Must be kept compact -- no holes and well documented */
2237
2238 /**
2239 * @length:
2240 *
2241 * When set to zero by userspace, this is filled with the size of the
2242 * data to be written at the @data_ptr pointer. The kernel sets this
2243 * value to a negative value to signal an error on a particular query
2244 * item.
2245 */
2246 __s32 length;
2247
2248 /**
2249 * @flags:
2250 *
2251 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2252 *
2253 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2254 * following:
2255 *
2256 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2257 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2258 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2259 */
2260 __u32 flags;
2261#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2262#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2263#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2264
2265 /**
2266 * @data_ptr:
2267 *
2268 * Data will be written at the location pointed by @data_ptr when the
2269 * value of @length matches the length of the data to be written by the
2270 * kernel.
2271 */
2272 __u64 data_ptr;
2273};
2274
2275/**
2276 * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
2277 * kernel to fill out.
2278 *
2279 * Note that this is generally a two step process for each struct
2280 * drm_i915_query_item in the array:
2281 *
2282 * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
2283 * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
2284 * kernel will then fill in the size, in bytes, which tells userspace how
2285 * memory it needs to allocate for the blob(say for an array of properties).
2286 *
2287 * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
2288 * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
2289 * the &drm_i915_query_item.length should still be the same as what the
2290 * kernel previously set. At this point the kernel can fill in the blob.
2291 *
2292 * Note that for some query items it can make sense for userspace to just pass
2293 * in a buffer/blob equal to or larger than the required size. In this case only
2294 * a single ioctl call is needed. For some smaller query items this can work
2295 * quite well.
2296 *
2297 */
2298struct drm_i915_query {
2299 /** @num_items: The number of elements in the @items_ptr array */
2300 __u32 num_items;
2301
2302 /**
2303 * @flags: Unused for now. Must be cleared to zero.
2304 */
2305 __u32 flags;
2306
2307 /**
2308 * @items_ptr:
2309 *
2310 * Pointer to an array of struct drm_i915_query_item. The number of
2311 * array elements is @num_items.
2312 */
2313 __u64 items_ptr;
2314};
2315
2316/*
2317 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2318 *
2319 * data: contains the 3 pieces of information :
2320 *
2321 * - the slice mask with one bit per slice telling whether a slice is
2322 * available. The availability of slice X can be queried with the following
2323 * formula :
2324 *
2325 * (data[X / 8] >> (X % 8)) & 1
2326 *
2327 * - the subslice mask for each slice with one bit per subslice telling
2328 * whether a subslice is available. Gen12 has dual-subslices, which are
2329 * similar to two gen11 subslices. For gen12, this array represents dual-
2330 * subslices. The availability of subslice Y in slice X can be queried
2331 * with the following formula :
2332 *
2333 * (data[subslice_offset +
2334 * X * subslice_stride +
2335 * Y / 8] >> (Y % 8)) & 1
2336 *
2337 * - the EU mask for each subslice in each slice with one bit per EU telling
2338 * whether an EU is available. The availability of EU Z in subslice Y in
2339 * slice X can be queried with the following formula :
2340 *
2341 * (data[eu_offset +
2342 * (X * max_subslices + Y) * eu_stride +
2343 * Z / 8] >> (Z % 8)) & 1
2344 */
2345struct drm_i915_query_topology_info {
2346 /*
2347 * Unused for now. Must be cleared to zero.
2348 */
2349 __u16 flags;
2350
2351 __u16 max_slices;
2352 __u16 max_subslices;
2353 __u16 max_eus_per_subslice;
2354
2355 /*
2356 * Offset in data[] at which the subslice masks are stored.
2357 */
2358 __u16 subslice_offset;
2359
2360 /*
2361 * Stride at which each of the subslice masks for each slice are
2362 * stored.
2363 */
2364 __u16 subslice_stride;
2365
2366 /*
2367 * Offset in data[] at which the EU masks are stored.
2368 */
2369 __u16 eu_offset;
2370
2371 /*
2372 * Stride at which each of the EU masks for each subslice are stored.
2373 */
2374 __u16 eu_stride;
2375
2376 __u8 data[];
2377};
2378
2379/**
2380 * struct drm_i915_engine_info
2381 *
2382 * Describes one engine and it's capabilities as known to the driver.
2383 */
2384struct drm_i915_engine_info {
2385 /** @engine: Engine class and instance. */
2386 struct i915_engine_class_instance engine;
2387
2388 /** @rsvd0: Reserved field. */
2389 __u32 rsvd0;
2390
2391 /** @flags: Engine flags. */
2392 __u64 flags;
2393
2394 /** @capabilities: Capabilities of this engine. */
2395 __u64 capabilities;
2396#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2397#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2398
2399 /** @rsvd1: Reserved fields. */
2400 __u64 rsvd1[4];
2401};
2402
2403/**
2404 * struct drm_i915_query_engine_info
2405 *
2406 * Engine info query enumerates all engines known to the driver by filling in
2407 * an array of struct drm_i915_engine_info structures.
2408 */
2409struct drm_i915_query_engine_info {
2410 /** @num_engines: Number of struct drm_i915_engine_info structs following. */
2411 __u32 num_engines;
2412
2413 /** @rsvd: MBZ */
2414 __u32 rsvd[3];
2415
2416 /** @engines: Marker for drm_i915_engine_info structures. */
2417 struct drm_i915_engine_info engines[];
2418};
2419
2420/*
2421 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2422 */
2423struct drm_i915_query_perf_config {
2424 union {
2425 /*
2426 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2427 * this fields to the number of configurations available.
2428 */
2429 __u64 n_configs;
2430
2431 /*
2432 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2433 * i915 will use the value in this field as configuration
2434 * identifier to decide what data to write into config_ptr.
2435 */
2436 __u64 config;
2437
2438 /*
2439 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2440 * i915 will use the value in this field as configuration
2441 * identifier to decide what data to write into config_ptr.
2442 *
2443 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2444 */
2445 char uuid[36];
2446 };
2447
2448 /*
2449 * Unused for now. Must be cleared to zero.
2450 */
2451 __u32 flags;
2452
2453 /*
2454 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2455 * write an array of __u64 of configuration identifiers.
2456 *
2457 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2458 * write a struct drm_i915_perf_oa_config. If the following fields of
2459 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2460 * the associated pointers the values of submitted when the
2461 * configuration was created :
2462 *
2463 * - n_mux_regs
2464 * - n_boolean_regs
2465 * - n_flex_regs
2466 */
2467 __u8 data[];
2468};
2469
2470/**
2471 * enum drm_i915_gem_memory_class - Supported memory classes
2472 */
2473enum drm_i915_gem_memory_class {
2474 /** @I915_MEMORY_CLASS_SYSTEM: System memory */
2475 I915_MEMORY_CLASS_SYSTEM = 0,
2476 /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
2477 I915_MEMORY_CLASS_DEVICE,
2478};
2479
2480/**
2481 * struct drm_i915_gem_memory_class_instance - Identify particular memory region
2482 */
2483struct drm_i915_gem_memory_class_instance {
2484 /** @memory_class: See enum drm_i915_gem_memory_class */
2485 __u16 memory_class;
2486
2487 /** @memory_instance: Which instance */
2488 __u16 memory_instance;
2489};
2490
2491/**
2492 * struct drm_i915_memory_region_info - Describes one region as known to the
2493 * driver.
2494 *
2495 * Note that we reserve some stuff here for potential future work. As an example
2496 * we might want expose the capabilities for a given region, which could include
2497 * things like if the region is CPU mappable/accessible, what are the supported
2498 * mapping types etc.
2499 *
2500 * Note that to extend struct drm_i915_memory_region_info and struct
2501 * drm_i915_query_memory_regions in the future the plan is to do the following:
2502 *
2503 * .. code-block:: C
2504 *
2505 * struct drm_i915_memory_region_info {
2506 * struct drm_i915_gem_memory_class_instance region;
2507 * union {
2508 * __u32 rsvd0;
2509 * __u32 new_thing1;
2510 * };
2511 * ...
2512 * union {
2513 * __u64 rsvd1[8];
2514 * struct {
2515 * __u64 new_thing2;
2516 * __u64 new_thing3;
2517 * ...
2518 * };
2519 * };
2520 * };
2521 *
2522 * With this things should remain source compatible between versions for
2523 * userspace, even as we add new fields.
2524 *
2525 * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
2526 * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
2527 * at &drm_i915_query_item.query_id.
2528 */
2529struct drm_i915_memory_region_info {
2530 /** @region: The class:instance pair encoding */
2531 struct drm_i915_gem_memory_class_instance region;
2532
2533 /** @rsvd0: MBZ */
2534 __u32 rsvd0;
2535
2536 /** @probed_size: Memory probed by the driver (-1 = unknown) */
2537 __u64 probed_size;
2538
2539 /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
2540 __u64 unallocated_size;
2541
2542 /** @rsvd1: MBZ */
2543 __u64 rsvd1[8];
2544};
2545
2546/**
2547 * struct drm_i915_query_memory_regions
2548 *
2549 * The region info query enumerates all regions known to the driver by filling
2550 * in an array of struct drm_i915_memory_region_info structures.
2551 *
2552 * Example for getting the list of supported regions:
2553 *
2554 * .. code-block:: C
2555 *
2556 * struct drm_i915_query_memory_regions *info;
2557 * struct drm_i915_query_item item = {
2558 * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
2559 * };
2560 * struct drm_i915_query query = {
2561 * .num_items = 1,
2562 * .items_ptr = (uintptr_t)&item,
2563 * };
2564 * int err, i;
2565 *
2566 * // First query the size of the blob we need, this needs to be large
2567 * // enough to hold our array of regions. The kernel will fill out the
2568 * // item.length for us, which is the number of bytes we need.
2569 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
2570 * if (err) ...
2571 *
2572 * info = calloc(1, item.length);
2573 * // Now that we allocated the required number of bytes, we call the ioctl
2574 * // again, this time with the data_ptr pointing to our newly allocated
2575 * // blob, which the kernel can then populate with the all the region info.
2576 * item.data_ptr = (uintptr_t)&info,
2577 *
2578 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
2579 * if (err) ...
2580 *
2581 * // We can now access each region in the array
2582 * for (i = 0; i < info->num_regions; i++) {
2583 * struct drm_i915_memory_region_info mr = info->regions[i];
2584 * u16 class = mr.region.class;
2585 * u16 instance = mr.region.instance;
2586 *
2587 * ....
2588 * }
2589 *
2590 * free(info);
2591 */
2592struct drm_i915_query_memory_regions {
2593 /** @num_regions: Number of supported regions */
2594 __u32 num_regions;
2595
2596 /** @rsvd: MBZ */
2597 __u32 rsvd[3];
2598
2599 /** @regions: Info about each supported region */
2600 struct drm_i915_memory_region_info regions[];
2601};
2602
2603/**
2604 * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
2605 * extension support using struct i915_user_extension.
2606 *
2607 * Note that in the future we want to have our buffer flags here, at least for
2608 * the stuff that is immutable. Previously we would have two ioctls, one to
2609 * create the object with gem_create, and another to apply various parameters,
2610 * however this creates some ambiguity for the params which are considered
2611 * immutable. Also in general we're phasing out the various SET/GET ioctls.
2612 */
2613struct drm_i915_gem_create_ext {
2614 /**
2615 * @size: Requested size for the object.
2616 *
2617 * The (page-aligned) allocated size for the object will be returned.
2618 *
2619 * Note that for some devices we have might have further minimum
2620 * page-size restrictions(larger than 4K), like for device local-memory.
2621 * However in general the final size here should always reflect any
2622 * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
2623 * extension to place the object in device local-memory.
2624 */
2625 __u64 size;
2626 /**
2627 * @handle: Returned handle for the object.
2628 *
2629 * Object handles are nonzero.
2630 */
2631 __u32 handle;
2632 /** @flags: MBZ */
2633 __u32 flags;
2634 /**
2635 * @extensions: The chain of extensions to apply to this object.
2636 *
2637 * This will be useful in the future when we need to support several
2638 * different extensions, and we need to apply more than one when
2639 * creating the object. See struct i915_user_extension.
2640 *
2641 * If we don't supply any extensions then we get the same old gem_create
2642 * behaviour.
2643 *
2644 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
2645 * struct drm_i915_gem_create_ext_memory_regions.
2646 */
2647#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
2648 __u64 extensions;
2649};
2650
2651/**
2652 * struct drm_i915_gem_create_ext_memory_regions - The
2653 * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
2654 *
2655 * Set the object with the desired set of placements/regions in priority
2656 * order. Each entry must be unique and supported by the device.
2657 *
2658 * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
2659 * an equivalent layout of class:instance pair encodings. See struct
2660 * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
2661 * query the supported regions for a device.
2662 *
2663 * As an example, on discrete devices, if we wish to set the placement as
2664 * device local-memory we can do something like:
2665 *
2666 * .. code-block:: C
2667 *
2668 * struct drm_i915_gem_memory_class_instance region_lmem = {
2669 * .memory_class = I915_MEMORY_CLASS_DEVICE,
2670 * .memory_instance = 0,
2671 * };
2672 * struct drm_i915_gem_create_ext_memory_regions regions = {
2673 * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
2674 * .regions = (uintptr_t)®ion_lmem,
2675 * .num_regions = 1,
2676 * };
2677 * struct drm_i915_gem_create_ext create_ext = {
2678 * .size = 16 * PAGE_SIZE,
2679 * .extensions = (uintptr_t)®ions,
2680 * };
2681 *
2682 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
2683 * if (err) ...
2684 *
2685 * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
2686 * along with the final object size in &drm_i915_gem_create_ext.size, which
2687 * should account for any rounding up, if required.
2688 */
2689struct drm_i915_gem_create_ext_memory_regions {
2690 /** @base: Extension link. See struct i915_user_extension. */
2691 struct i915_user_extension base;
2692
2693 /** @pad: MBZ */
2694 __u32 pad;
2695 /** @num_regions: Number of elements in the @regions array. */
2696 __u32 num_regions;
2697 /**
2698 * @regions: The regions/placements array.
2699 *
2700 * An array of struct drm_i915_gem_memory_class_instance.
2701 */
2702 __u64 regions;
2703};
2704
2705#if defined(__cplusplus)
2706}
2707#endif
2708
2709#endif /* _UAPI_I915_DRM_H_ */