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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the NXP ISP1760 chip
4 *
5 * However, the code might contain some bugs. What doesn't work for sure is:
6 * - ISO
7 * - OTG
8 e The interrupt line is configured as active low, level.
9 *
10 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
11 *
12 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
13 *
14 * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org>
15 *
16 */
17#include <linux/gpio/consumer.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22#include <linux/usb.h>
23#include <linux/usb/hcd.h>
24#include <linux/debugfs.h>
25#include <linux/uaccess.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28#include <linux/mm.h>
29#include <linux/timer.h>
30#include <asm/unaligned.h>
31#include <asm/cacheflush.h>
32
33#include "isp1760-core.h"
34#include "isp1760-hcd.h"
35#include "isp1760-regs.h"
36
37static struct kmem_cache *qtd_cachep;
38static struct kmem_cache *qh_cachep;
39static struct kmem_cache *urb_listitem_cachep;
40
41typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
42 struct isp1760_qtd *qtd);
43
44static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
45{
46 return *(struct isp1760_hcd **)hcd->hcd_priv;
47}
48
49#define dw_to_le32(x) (cpu_to_le32((__force u32)x))
50#define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x)))
51
52/* urb state*/
53#define DELETE_URB (0x0008)
54#define NO_TRANSFER_ACTIVE (0xffffffff)
55
56/* Philips Proprietary Transfer Descriptor (PTD) */
57typedef __u32 __bitwise __dw;
58struct ptd {
59 __dw dw0;
60 __dw dw1;
61 __dw dw2;
62 __dw dw3;
63 __dw dw4;
64 __dw dw5;
65 __dw dw6;
66 __dw dw7;
67};
68
69struct ptd_le32 {
70 __le32 dw0;
71 __le32 dw1;
72 __le32 dw2;
73 __le32 dw3;
74 __le32 dw4;
75 __le32 dw5;
76 __le32 dw6;
77 __le32 dw7;
78};
79
80#define PTD_OFFSET 0x0400
81#define ISO_PTD_OFFSET 0x0400
82#define INT_PTD_OFFSET 0x0800
83#define ATL_PTD_OFFSET 0x0c00
84#define PAYLOAD_OFFSET 0x1000
85
86#define ISP_BANK_0 0x00
87#define ISP_BANK_1 0x01
88#define ISP_BANK_2 0x02
89#define ISP_BANK_3 0x03
90
91#define TO_DW(x) ((__force __dw)x)
92#define TO_U32(x) ((__force u32)x)
93
94 /* ATL */
95 /* DW0 */
96#define DW0_VALID_BIT TO_DW(1)
97#define FROM_DW0_VALID(x) (TO_U32(x) & 0x01)
98#define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3))
99#define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18))
100#define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29))
101#define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31))
102/* DW1 */
103#define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3))
104#define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10))
105#define DW1_TRANS_BULK TO_DW(((u32)2 << 12))
106#define DW1_TRANS_INT TO_DW(((u32)3 << 12))
107#define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14))
108#define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16))
109#define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18))
110#define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25))
111/* DW2 */
112#define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8))
113#define TO_DW2_RL(x) TO_DW(((x) << 25))
114#define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf)
115/* DW3 */
116#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff)
117#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff)
118#define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19))
119#define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf)
120#define TO_DW3_CERR(x) TO_DW(((x) << 23))
121#define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3)
122#define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25))
123#define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1)
124#define TO_DW3_PING(x) TO_DW(((x) << 26))
125#define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1)
126#define DW3_ERROR_BIT TO_DW((1 << 28))
127#define DW3_BABBLE_BIT TO_DW((1 << 29))
128#define DW3_HALT_BIT TO_DW((1 << 30))
129#define DW3_ACTIVE_BIT TO_DW((1 << 31))
130#define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01)
131
132#define INT_UNDERRUN (1 << 2)
133#define INT_BABBLE (1 << 1)
134#define INT_EXACT (1 << 0)
135
136#define SETUP_PID (2)
137#define IN_PID (1)
138#define OUT_PID (0)
139
140/* Errata 1 */
141#define RL_COUNTER (0)
142#define NAK_COUNTER (0)
143#define ERR_COUNTER (3)
144
145struct isp1760_qtd {
146 u8 packet_type;
147 void *data_buffer;
148 u32 payload_addr;
149
150 /* the rest is HCD-private */
151 struct list_head qtd_list;
152 struct urb *urb;
153 size_t length;
154 size_t actual_length;
155
156 /* QTD_ENQUEUED: waiting for transfer (inactive) */
157 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
158 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
159 interrupt handler may touch this qtd! */
160 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
161 /* QTD_RETIRE: transfer error/abort qtd */
162#define QTD_ENQUEUED 0
163#define QTD_PAYLOAD_ALLOC 1
164#define QTD_XFER_STARTED 2
165#define QTD_XFER_COMPLETE 3
166#define QTD_RETIRE 4
167 u32 status;
168};
169
170/* Queue head, one for each active endpoint */
171struct isp1760_qh {
172 struct list_head qh_list;
173 struct list_head qtd_list;
174 u32 toggle;
175 u32 ping;
176 int slot;
177 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
178};
179
180struct urb_listitem {
181 struct list_head urb_list;
182 struct urb *urb;
183};
184
185static const u32 isp176x_hc_portsc1_fields[] = {
186 [PORT_OWNER] = BIT(13),
187 [PORT_POWER] = BIT(12),
188 [PORT_LSTATUS] = BIT(10),
189 [PORT_RESET] = BIT(8),
190 [PORT_SUSPEND] = BIT(7),
191 [PORT_RESUME] = BIT(6),
192 [PORT_PE] = BIT(2),
193 [PORT_CSC] = BIT(1),
194 [PORT_CONNECT] = BIT(0),
195};
196
197/*
198 * Access functions for isp176x registers regmap fields
199 */
200static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field)
201{
202 struct isp1760_hcd *priv = hcd_to_priv(hcd);
203
204 return isp1760_field_read(priv->fields, field);
205}
206
207/*
208 * We need, in isp176x, to write directly the values to the portsc1
209 * register so it will make the other values to trigger.
210 */
211static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field,
212 u32 val)
213{
214 u32 bit = isp176x_hc_portsc1_fields[field];
215 u16 portsc1_reg = priv->is_isp1763 ? ISP1763_HC_PORTSC1 :
216 ISP176x_HC_PORTSC1;
217 u32 port_status = readl(priv->base + portsc1_reg);
218
219 if (val)
220 writel(port_status | bit, priv->base + portsc1_reg);
221 else
222 writel(port_status & ~bit, priv->base + portsc1_reg);
223}
224
225static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val)
226{
227 struct isp1760_hcd *priv = hcd_to_priv(hcd);
228
229 if (unlikely((field >= PORT_OWNER && field <= PORT_CONNECT)))
230 return isp1760_hcd_portsc1_set_clear(priv, field, val);
231
232 isp1760_field_write(priv->fields, field, val);
233}
234
235static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field)
236{
237 isp1760_hcd_write(hcd, field, 0xFFFFFFFF);
238}
239
240static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field)
241{
242 isp1760_hcd_write(hcd, field, 0);
243}
244
245static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field,
246 u32 timeout_us)
247{
248 struct isp1760_hcd *priv = hcd_to_priv(hcd);
249 u32 val;
250
251 isp1760_hcd_set(hcd, field);
252
253 return regmap_field_read_poll_timeout(priv->fields[field], val,
254 val, 0, timeout_us);
255}
256
257static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field,
258 u32 timeout_us)
259{
260 struct isp1760_hcd *priv = hcd_to_priv(hcd);
261 u32 val;
262
263 isp1760_hcd_set(hcd, field);
264
265 return regmap_field_read_poll_timeout(priv->fields[field], val,
266 !val, 0, timeout_us);
267}
268
269static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field,
270 u32 timeout_us)
271{
272 struct isp1760_hcd *priv = hcd_to_priv(hcd);
273 u32 val;
274
275 isp1760_hcd_clear(hcd, field);
276
277 return regmap_field_read_poll_timeout(priv->fields[field], val,
278 !val, 0, timeout_us);
279}
280
281static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field)
282{
283 return !!isp1760_hcd_read(hcd, field);
284}
285
286static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd)
287{
288 struct isp1760_hcd *priv = hcd_to_priv(hcd);
289
290 if (priv->is_isp1763)
291 return true;
292
293 return isp1760_hcd_is_set(hcd, HCS_PPC);
294}
295
296static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd)
297{
298 struct isp1760_hcd *priv = hcd_to_priv(hcd);
299
300 if (priv->is_isp1763)
301 return 1;
302
303 return isp1760_hcd_read(hcd, HCS_N_PORTS);
304}
305
306/*
307 * Access functions for isp176x memory (offset >= 0x0400).
308 *
309 * bank_reads8() reads memory locations prefetched by an earlier write to
310 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
311 * bank optimizations, you should use the more generic mem_read() below.
312 *
313 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
314 * below.
315 *
316 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
317 * doesn't quite work because some people have to enforce 32-bit access
318 */
319static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
320 __u32 *dst, u32 bytes)
321{
322 __u32 __iomem *src;
323 u32 val;
324 __u8 *src_byteptr;
325 __u8 *dst_byteptr;
326
327 src = src_base + (bank_addr | src_offset);
328
329 if (src_offset < PAYLOAD_OFFSET) {
330 while (bytes >= 4) {
331 *dst = readl_relaxed(src);
332 bytes -= 4;
333 src++;
334 dst++;
335 }
336 } else {
337 while (bytes >= 4) {
338 *dst = __raw_readl(src);
339 bytes -= 4;
340 src++;
341 dst++;
342 }
343 }
344
345 if (!bytes)
346 return;
347
348 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
349 * allocated.
350 */
351 if (src_offset < PAYLOAD_OFFSET)
352 val = readl_relaxed(src);
353 else
354 val = __raw_readl(src);
355
356 dst_byteptr = (void *) dst;
357 src_byteptr = (void *) &val;
358 while (bytes > 0) {
359 *dst_byteptr = *src_byteptr;
360 dst_byteptr++;
361 src_byteptr++;
362 bytes--;
363 }
364}
365
366static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst,
367 u32 bytes)
368{
369 struct isp1760_hcd *priv = hcd_to_priv(hcd);
370
371 isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset);
372 ndelay(100);
373
374 bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes);
375}
376
377/*
378 * ISP1763 does not have the banks direct host controller memory access,
379 * needs to use the HC_DATA register. Add data read/write according to this,
380 * and also adjust 16bit access.
381 */
382static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr,
383 u16 *dstptr, u32 bytes)
384{
385 struct isp1760_hcd *priv = hcd_to_priv(hcd);
386
387 /* Write the starting device address to the hcd memory register */
388 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr);
389 ndelay(100); /* Delay between consecutive access */
390
391 /* As long there are at least 16-bit to read ... */
392 while (bytes >= 2) {
393 *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA);
394 bytes -= 2;
395 dstptr++;
396 }
397
398 /* If there are no more bytes to read, return */
399 if (bytes <= 0)
400 return;
401
402 *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF);
403}
404
405static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst,
406 u32 bytes)
407{
408 struct isp1760_hcd *priv = hcd_to_priv(hcd);
409
410 if (!priv->is_isp1763)
411 return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes);
412
413 isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes);
414}
415
416static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset,
417 __u32 const *src, u32 bytes)
418{
419 __u32 __iomem *dst;
420
421 dst = dst_base + dst_offset;
422
423 if (dst_offset < PAYLOAD_OFFSET) {
424 while (bytes >= 4) {
425 writel_relaxed(*src, dst);
426 bytes -= 4;
427 src++;
428 dst++;
429 }
430 } else {
431 while (bytes >= 4) {
432 __raw_writel(*src, dst);
433 bytes -= 4;
434 src++;
435 dst++;
436 }
437 }
438
439 if (!bytes)
440 return;
441 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
442 * extra bytes should not be read by the HW.
443 */
444
445 if (dst_offset < PAYLOAD_OFFSET)
446 writel_relaxed(*src, dst);
447 else
448 __raw_writel(*src, dst);
449}
450
451static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src,
452 u32 bytes)
453{
454 struct isp1760_hcd *priv = hcd_to_priv(hcd);
455
456 /* Write the starting device address to the hcd memory register */
457 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr);
458 ndelay(100); /* Delay between consecutive access */
459
460 while (bytes >= 2) {
461 /* Get and write the data; then adjust the data ptr and len */
462 __raw_writew(*src, priv->base + ISP1763_HC_DATA);
463 bytes -= 2;
464 src++;
465 }
466
467 /* If there are no more bytes to process, return */
468 if (bytes <= 0)
469 return;
470
471 /*
472 * The only way to get here is if there is a single byte left,
473 * get it and write it to the data reg;
474 */
475 writew(*((u8 *)src), priv->base + ISP1763_HC_DATA);
476}
477
478static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src,
479 u32 bytes)
480{
481 struct isp1760_hcd *priv = hcd_to_priv(hcd);
482
483 if (!priv->is_isp1763)
484 return isp1760_mem_write(priv->base, dst_offset, src, bytes);
485
486 isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes);
487}
488
489/*
490 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
491 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
492 */
493static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
494 struct ptd *ptd)
495{
496 u16 src_offset = ptd_offset + slot * sizeof(*ptd);
497 struct isp1760_hcd *priv = hcd_to_priv(hcd);
498
499 isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset);
500 ndelay(90);
501
502 bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd,
503 sizeof(*ptd));
504}
505
506static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
507 struct ptd *ptd)
508{
509 u16 src_offset = ptd_offset + slot * sizeof(*ptd);
510 struct ptd_le32 le32_ptd;
511
512 isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd));
513 /* Normalize the data obtained */
514 ptd->dw0 = le32_to_dw(le32_ptd.dw0);
515 ptd->dw1 = le32_to_dw(le32_ptd.dw1);
516 ptd->dw2 = le32_to_dw(le32_ptd.dw2);
517 ptd->dw3 = le32_to_dw(le32_ptd.dw3);
518 ptd->dw4 = le32_to_dw(le32_ptd.dw4);
519 ptd->dw5 = le32_to_dw(le32_ptd.dw5);
520 ptd->dw6 = le32_to_dw(le32_ptd.dw6);
521 ptd->dw7 = le32_to_dw(le32_ptd.dw7);
522}
523
524static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
525 struct ptd *ptd)
526{
527 struct isp1760_hcd *priv = hcd_to_priv(hcd);
528
529 if (!priv->is_isp1763)
530 return isp1760_ptd_read(hcd, ptd_offset, slot, ptd);
531
532 isp1763_ptd_read(hcd, ptd_offset, slot, ptd);
533}
534
535static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
536 struct ptd *cpu_ptd)
537{
538 u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd);
539 struct ptd_le32 ptd;
540
541 ptd.dw0 = dw_to_le32(cpu_ptd->dw0);
542 ptd.dw1 = dw_to_le32(cpu_ptd->dw1);
543 ptd.dw2 = dw_to_le32(cpu_ptd->dw2);
544 ptd.dw3 = dw_to_le32(cpu_ptd->dw3);
545 ptd.dw4 = dw_to_le32(cpu_ptd->dw4);
546 ptd.dw5 = dw_to_le32(cpu_ptd->dw5);
547 ptd.dw6 = dw_to_le32(cpu_ptd->dw6);
548 ptd.dw7 = dw_to_le32(cpu_ptd->dw7);
549
550 isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0,
551 8 * sizeof(ptd.dw0));
552}
553
554static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
555 struct ptd *ptd)
556{
557 u32 dst_offset = ptd_offset + slot * sizeof(*ptd);
558
559 /*
560 * Make sure dw0 gets written last (after other dw's and after payload)
561 * since it contains the enable bit
562 */
563 isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0),
564 (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1));
565 wmb();
566 isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0,
567 sizeof(ptd->dw0));
568}
569
570static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
571 struct ptd *ptd)
572{
573 struct isp1760_hcd *priv = hcd_to_priv(hcd);
574
575 if (!priv->is_isp1763)
576 return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd);
577
578 isp1763_ptd_write(hcd, ptd_offset, slot, ptd);
579}
580
581/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
582static void init_memory(struct isp1760_hcd *priv)
583{
584 const struct isp1760_memory_layout *mem = priv->memory_layout;
585 int i, j, curr;
586 u32 payload_addr;
587
588 payload_addr = PAYLOAD_OFFSET;
589
590 for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) {
591 for (j = 0; j < mem->blocks[i]; j++) {
592 priv->memory_pool[curr + j].start = payload_addr;
593 priv->memory_pool[curr + j].size = mem->blocks_size[i];
594 priv->memory_pool[curr + j].free = 1;
595 payload_addr += priv->memory_pool[curr + j].size;
596 }
597 }
598
599 WARN_ON(payload_addr - priv->memory_pool[0].start >
600 mem->payload_area_size);
601}
602
603static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
604{
605 struct isp1760_hcd *priv = hcd_to_priv(hcd);
606 const struct isp1760_memory_layout *mem = priv->memory_layout;
607 int i;
608
609 WARN_ON(qtd->payload_addr);
610
611 if (!qtd->length)
612 return;
613
614 for (i = 0; i < mem->payload_blocks; i++) {
615 if (priv->memory_pool[i].size >= qtd->length &&
616 priv->memory_pool[i].free) {
617 priv->memory_pool[i].free = 0;
618 qtd->payload_addr = priv->memory_pool[i].start;
619 return;
620 }
621 }
622}
623
624static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
625{
626 struct isp1760_hcd *priv = hcd_to_priv(hcd);
627 const struct isp1760_memory_layout *mem = priv->memory_layout;
628 int i;
629
630 if (!qtd->payload_addr)
631 return;
632
633 for (i = 0; i < mem->payload_blocks; i++) {
634 if (priv->memory_pool[i].start == qtd->payload_addr) {
635 WARN_ON(priv->memory_pool[i].free);
636 priv->memory_pool[i].free = 1;
637 qtd->payload_addr = 0;
638 return;
639 }
640 }
641
642 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
643 __func__, qtd->payload_addr);
644 WARN_ON(1);
645 qtd->payload_addr = 0;
646}
647
648/* reset a non-running (STS_HALT == 1) controller */
649static int ehci_reset(struct usb_hcd *hcd)
650{
651 struct isp1760_hcd *priv = hcd_to_priv(hcd);
652
653 hcd->state = HC_STATE_HALT;
654 priv->next_statechange = jiffies;
655
656 return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000);
657}
658
659static struct isp1760_qh *qh_alloc(gfp_t flags)
660{
661 struct isp1760_qh *qh;
662
663 qh = kmem_cache_zalloc(qh_cachep, flags);
664 if (!qh)
665 return NULL;
666
667 INIT_LIST_HEAD(&qh->qh_list);
668 INIT_LIST_HEAD(&qh->qtd_list);
669 qh->slot = -1;
670
671 return qh;
672}
673
674static void qh_free(struct isp1760_qh *qh)
675{
676 WARN_ON(!list_empty(&qh->qtd_list));
677 WARN_ON(qh->slot > -1);
678 kmem_cache_free(qh_cachep, qh);
679}
680
681/* one-time init, only for memory state */
682static int priv_init(struct usb_hcd *hcd)
683{
684 struct isp1760_hcd *priv = hcd_to_priv(hcd);
685 u32 isoc_cache;
686 u32 isoc_thres;
687 int i;
688
689 spin_lock_init(&priv->lock);
690
691 for (i = 0; i < QH_END; i++)
692 INIT_LIST_HEAD(&priv->qh_list[i]);
693
694 /*
695 * hw default: 1K periodic list heads, one per frame.
696 * periodic_size can shrink by USBCMD update if hcc_params allows.
697 */
698 priv->periodic_size = DEFAULT_I_TDPS;
699
700 if (priv->is_isp1763) {
701 priv->i_thresh = 2;
702 return 0;
703 }
704
705 /* controllers may cache some of the periodic schedule ... */
706 isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE);
707 isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES);
708
709 /* full frame cache */
710 if (isoc_cache)
711 priv->i_thresh = 8;
712 else /* N microframes cached */
713 priv->i_thresh = 2 + isoc_thres;
714
715 return 0;
716}
717
718static int isp1760_hc_setup(struct usb_hcd *hcd)
719{
720 struct isp1760_hcd *priv = hcd_to_priv(hcd);
721 u32 atx_reset;
722 int result;
723 u32 scratch;
724 u32 pattern;
725
726 if (priv->is_isp1763)
727 pattern = 0xcafe;
728 else
729 pattern = 0xdeadcafe;
730
731 isp1760_hcd_write(hcd, HC_SCRATCH, pattern);
732
733 /* Change bus pattern */
734 scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
735 dev_err(hcd->self.controller, "Scratch test 0x%08x\n", scratch);
736 scratch = isp1760_hcd_read(hcd, HC_SCRATCH);
737 if (scratch != pattern) {
738 dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", scratch);
739 return -ENODEV;
740 }
741
742 /*
743 * The RESET_HC bit in the SW_RESET register is supposed to reset the
744 * host controller without touching the CPU interface registers, but at
745 * least on the ISP1761 it seems to behave as the RESET_ALL bit and
746 * reset the whole device. We thus can't use it here, so let's reset
747 * the host controller through the EHCI USB Command register. The device
748 * has been reset in core code anyway, so this shouldn't matter.
749 */
750 isp1760_hcd_clear(hcd, ISO_BUF_FILL);
751 isp1760_hcd_clear(hcd, INT_BUF_FILL);
752 isp1760_hcd_clear(hcd, ATL_BUF_FILL);
753
754 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
755 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
756 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
757
758 result = ehci_reset(hcd);
759 if (result)
760 return result;
761
762 /* Step 11 passed */
763
764 /* ATL reset */
765 if (priv->is_isp1763)
766 atx_reset = SW_RESET_RESET_ATX;
767 else
768 atx_reset = ALL_ATX_RESET;
769
770 isp1760_hcd_set(hcd, atx_reset);
771 mdelay(10);
772 isp1760_hcd_clear(hcd, atx_reset);
773
774 if (priv->is_isp1763) {
775 isp1760_hcd_set(hcd, HW_OTG_DISABLE);
776 isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR);
777 isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR);
778 mdelay(10);
779
780 isp1760_hcd_set(hcd, HW_INTF_LOCK);
781 }
782
783 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE);
784 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE);
785
786 return priv_init(hcd);
787}
788
789static u32 base_to_chip(u32 base)
790{
791 return ((base - 0x400) >> 3);
792}
793
794static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
795{
796 struct urb *urb;
797
798 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
799 return 1;
800
801 urb = qtd->urb;
802 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
803 return (qtd->urb != urb);
804}
805
806/* magic numbers that can affect system performance */
807#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
808#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
809#define EHCI_TUNE_RL_TT 0
810#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
811#define EHCI_TUNE_MULT_TT 1
812#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
813
814static void create_ptd_atl(struct isp1760_qh *qh,
815 struct isp1760_qtd *qtd, struct ptd *ptd)
816{
817 u32 maxpacket;
818 u32 multi;
819 u32 rl = RL_COUNTER;
820 u32 nak = NAK_COUNTER;
821
822 memset(ptd, 0, sizeof(*ptd));
823
824 /* according to 3.6.2, max packet len can not be > 0x400 */
825 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
826 usb_pipeout(qtd->urb->pipe));
827 multi = 1 + ((maxpacket >> 11) & 0x3);
828 maxpacket &= 0x7ff;
829
830 /* DW0 */
831 ptd->dw0 = DW0_VALID_BIT;
832 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
833 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
834 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
835
836 /* DW1 */
837 ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1));
838 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
839 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
840
841 if (usb_pipebulk(qtd->urb->pipe))
842 ptd->dw1 |= DW1_TRANS_BULK;
843 else if (usb_pipeint(qtd->urb->pipe))
844 ptd->dw1 |= DW1_TRANS_INT;
845
846 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
847 /* split transaction */
848
849 ptd->dw1 |= DW1_TRANS_SPLIT;
850 if (qtd->urb->dev->speed == USB_SPEED_LOW)
851 ptd->dw1 |= DW1_SE_USB_LOSPEED;
852
853 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
854 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
855
856 /* SE bit for Split INT transfers */
857 if (usb_pipeint(qtd->urb->pipe) &&
858 (qtd->urb->dev->speed == USB_SPEED_LOW))
859 ptd->dw1 |= DW1_SE_USB_LOSPEED;
860
861 rl = 0;
862 nak = 0;
863 } else {
864 ptd->dw0 |= TO_DW0_MULTI(multi);
865 if (usb_pipecontrol(qtd->urb->pipe) ||
866 usb_pipebulk(qtd->urb->pipe))
867 ptd->dw3 |= TO_DW3_PING(qh->ping);
868 }
869 /* DW2 */
870 ptd->dw2 = 0;
871 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
872 ptd->dw2 |= TO_DW2_RL(rl);
873
874 /* DW3 */
875 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
876 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
877 if (usb_pipecontrol(qtd->urb->pipe)) {
878 if (qtd->data_buffer == qtd->urb->setup_packet)
879 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
880 else if (last_qtd_of_urb(qtd, qh))
881 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
882 }
883
884 ptd->dw3 |= DW3_ACTIVE_BIT;
885 /* Cerr */
886 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
887}
888
889static void transform_add_int(struct isp1760_qh *qh,
890 struct isp1760_qtd *qtd, struct ptd *ptd)
891{
892 u32 usof;
893 u32 period;
894
895 /*
896 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
897 * the algorithm from the original Philips driver code, which was
898 * pretty much used in this driver before as well, is quite horrendous
899 * and, i believe, incorrect. The code below follows the datasheet and
900 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
901 * more reliable this way (fingers crossed...).
902 */
903
904 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
905 /* urb->interval is in units of microframes (1/8 ms) */
906 period = qtd->urb->interval >> 3;
907
908 if (qtd->urb->interval > 4)
909 usof = 0x01; /* One bit set =>
910 interval 1 ms * uFrame-match */
911 else if (qtd->urb->interval > 2)
912 usof = 0x22; /* Two bits set => interval 1/2 ms */
913 else if (qtd->urb->interval > 1)
914 usof = 0x55; /* Four bits set => interval 1/4 ms */
915 else
916 usof = 0xff; /* All bits set => interval 1/8 ms */
917 } else {
918 /* urb->interval is in units of frames (1 ms) */
919 period = qtd->urb->interval;
920 usof = 0x0f; /* Execute Start Split on any of the
921 four first uFrames */
922
923 /*
924 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
925 * complete split needs to be sent. Valid only for IN." Also,
926 * "All bits can be set to one for every transfer." (p 82,
927 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
928 * that number come from? 0xff seems to work fine...
929 */
930 /* ptd->dw5 = 0x1c; */
931 ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */
932 }
933
934 period = period >> 1;/* Ensure equal or shorter period than requested */
935 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
936
937 ptd->dw2 |= TO_DW(period);
938 ptd->dw4 = TO_DW(usof);
939}
940
941static void create_ptd_int(struct isp1760_qh *qh,
942 struct isp1760_qtd *qtd, struct ptd *ptd)
943{
944 create_ptd_atl(qh, qtd, ptd);
945 transform_add_int(qh, qtd, ptd);
946}
947
948static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
949__releases(priv->lock)
950__acquires(priv->lock)
951{
952 struct isp1760_hcd *priv = hcd_to_priv(hcd);
953
954 if (!urb->unlinked) {
955 if (urb->status == -EINPROGRESS)
956 urb->status = 0;
957 }
958
959 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
960 void *ptr;
961 for (ptr = urb->transfer_buffer;
962 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
963 ptr += PAGE_SIZE)
964 flush_dcache_page(virt_to_page(ptr));
965 }
966
967 /* complete() can reenter this HCD */
968 usb_hcd_unlink_urb_from_ep(hcd, urb);
969 spin_unlock(&priv->lock);
970 usb_hcd_giveback_urb(hcd, urb, urb->status);
971 spin_lock(&priv->lock);
972}
973
974static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
975 u8 packet_type)
976{
977 struct isp1760_qtd *qtd;
978
979 qtd = kmem_cache_zalloc(qtd_cachep, flags);
980 if (!qtd)
981 return NULL;
982
983 INIT_LIST_HEAD(&qtd->qtd_list);
984 qtd->urb = urb;
985 qtd->packet_type = packet_type;
986 qtd->status = QTD_ENQUEUED;
987 qtd->actual_length = 0;
988
989 return qtd;
990}
991
992static void qtd_free(struct isp1760_qtd *qtd)
993{
994 WARN_ON(qtd->payload_addr);
995 kmem_cache_free(qtd_cachep, qtd);
996}
997
998static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
999 struct isp1760_slotinfo *slots,
1000 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
1001 struct ptd *ptd)
1002{
1003 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1004 const struct isp1760_memory_layout *mem = priv->memory_layout;
1005 int skip_map;
1006
1007 WARN_ON((slot < 0) || (slot > mem->slot_num - 1));
1008 WARN_ON(qtd->length && !qtd->payload_addr);
1009 WARN_ON(slots[slot].qtd);
1010 WARN_ON(slots[slot].qh);
1011 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
1012
1013 if (priv->is_isp1763)
1014 ndelay(100);
1015
1016 /* Make sure done map has not triggered from some unlinked transfer */
1017 if (ptd_offset == ATL_PTD_OFFSET) {
1018 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1019 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP,
1020 skip_map | (1 << slot));
1021 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP);
1022 priv->atl_done_map &= ~(1 << slot);
1023 } else {
1024 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1025 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP,
1026 skip_map | (1 << slot));
1027 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP);
1028 priv->int_done_map &= ~(1 << slot);
1029 }
1030
1031 skip_map &= ~(1 << slot);
1032 qh->slot = slot;
1033 qtd->status = QTD_XFER_STARTED;
1034 slots[slot].timestamp = jiffies;
1035 slots[slot].qtd = qtd;
1036 slots[slot].qh = qh;
1037 ptd_write(hcd, ptd_offset, slot, ptd);
1038
1039 if (ptd_offset == ATL_PTD_OFFSET)
1040 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map);
1041 else
1042 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map);
1043}
1044
1045static int is_short_bulk(struct isp1760_qtd *qtd)
1046{
1047 return (usb_pipebulk(qtd->urb->pipe) &&
1048 (qtd->actual_length < qtd->length));
1049}
1050
1051static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
1052 struct list_head *urb_list)
1053{
1054 struct isp1760_qtd *qtd, *qtd_next;
1055 struct urb_listitem *urb_listitem;
1056 int last_qtd;
1057
1058 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
1059 if (qtd->status < QTD_XFER_COMPLETE)
1060 break;
1061
1062 last_qtd = last_qtd_of_urb(qtd, qh);
1063
1064 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
1065 qtd_next->status = QTD_RETIRE;
1066
1067 if (qtd->status == QTD_XFER_COMPLETE) {
1068 if (qtd->actual_length) {
1069 switch (qtd->packet_type) {
1070 case IN_PID:
1071 mem_read(hcd, qtd->payload_addr,
1072 qtd->data_buffer,
1073 qtd->actual_length);
1074 fallthrough;
1075 case OUT_PID:
1076 qtd->urb->actual_length +=
1077 qtd->actual_length;
1078 fallthrough;
1079 case SETUP_PID:
1080 break;
1081 }
1082 }
1083
1084 if (is_short_bulk(qtd)) {
1085 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
1086 qtd->urb->status = -EREMOTEIO;
1087 if (!last_qtd)
1088 qtd_next->status = QTD_RETIRE;
1089 }
1090 }
1091
1092 if (qtd->payload_addr)
1093 free_mem(hcd, qtd);
1094
1095 if (last_qtd) {
1096 if ((qtd->status == QTD_RETIRE) &&
1097 (qtd->urb->status == -EINPROGRESS))
1098 qtd->urb->status = -EPIPE;
1099 /* Defer calling of urb_done() since it releases lock */
1100 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
1101 GFP_ATOMIC);
1102 if (unlikely(!urb_listitem))
1103 break; /* Try again on next call */
1104 urb_listitem->urb = qtd->urb;
1105 list_add_tail(&urb_listitem->urb_list, urb_list);
1106 }
1107
1108 list_del(&qtd->qtd_list);
1109 qtd_free(qtd);
1110 }
1111}
1112
1113#define ENQUEUE_DEPTH 2
1114static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
1115{
1116 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1117 const struct isp1760_memory_layout *mem = priv->memory_layout;
1118 int slot_num = mem->slot_num;
1119 int ptd_offset;
1120 struct isp1760_slotinfo *slots;
1121 int curr_slot, free_slot;
1122 int n;
1123 struct ptd ptd;
1124 struct isp1760_qtd *qtd;
1125
1126 if (unlikely(list_empty(&qh->qtd_list))) {
1127 WARN_ON(1);
1128 return;
1129 }
1130
1131 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
1132 if (qh->tt_buffer_dirty)
1133 return;
1134
1135 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
1136 qtd_list)->urb->pipe)) {
1137 ptd_offset = INT_PTD_OFFSET;
1138 slots = priv->int_slots;
1139 } else {
1140 ptd_offset = ATL_PTD_OFFSET;
1141 slots = priv->atl_slots;
1142 }
1143
1144 free_slot = -1;
1145 for (curr_slot = 0; curr_slot < slot_num; curr_slot++) {
1146 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
1147 free_slot = curr_slot;
1148 if (slots[curr_slot].qh == qh)
1149 break;
1150 }
1151
1152 n = 0;
1153 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1154 if (qtd->status == QTD_ENQUEUED) {
1155 WARN_ON(qtd->payload_addr);
1156 alloc_mem(hcd, qtd);
1157 if ((qtd->length) && (!qtd->payload_addr))
1158 break;
1159
1160 if (qtd->length && (qtd->packet_type == SETUP_PID ||
1161 qtd->packet_type == OUT_PID)) {
1162 mem_write(hcd, qtd->payload_addr,
1163 qtd->data_buffer, qtd->length);
1164 }
1165
1166 qtd->status = QTD_PAYLOAD_ALLOC;
1167 }
1168
1169 if (qtd->status == QTD_PAYLOAD_ALLOC) {
1170/*
1171 if ((curr_slot > 31) && (free_slot == -1))
1172 dev_dbg(hcd->self.controller, "%s: No slot "
1173 "available for transfer\n", __func__);
1174*/
1175 /* Start xfer for this endpoint if not already done */
1176 if ((curr_slot > slot_num - 1) && (free_slot > -1)) {
1177 if (usb_pipeint(qtd->urb->pipe))
1178 create_ptd_int(qh, qtd, &ptd);
1179 else
1180 create_ptd_atl(qh, qtd, &ptd);
1181
1182 start_bus_transfer(hcd, ptd_offset, free_slot,
1183 slots, qtd, qh, &ptd);
1184 curr_slot = free_slot;
1185 }
1186
1187 n++;
1188 if (n >= ENQUEUE_DEPTH)
1189 break;
1190 }
1191 }
1192}
1193
1194static void schedule_ptds(struct usb_hcd *hcd)
1195{
1196 struct isp1760_hcd *priv;
1197 struct isp1760_qh *qh, *qh_next;
1198 struct list_head *ep_queue;
1199 LIST_HEAD(urb_list);
1200 struct urb_listitem *urb_listitem, *urb_listitem_next;
1201 int i;
1202
1203 if (!hcd) {
1204 WARN_ON(1);
1205 return;
1206 }
1207
1208 priv = hcd_to_priv(hcd);
1209
1210 /*
1211 * check finished/retired xfers, transfer payloads, call urb_done()
1212 */
1213 for (i = 0; i < QH_END; i++) {
1214 ep_queue = &priv->qh_list[i];
1215 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
1216 collect_qtds(hcd, qh, &urb_list);
1217 if (list_empty(&qh->qtd_list))
1218 list_del(&qh->qh_list);
1219 }
1220 }
1221
1222 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
1223 urb_list) {
1224 isp1760_urb_done(hcd, urb_listitem->urb);
1225 kmem_cache_free(urb_listitem_cachep, urb_listitem);
1226 }
1227
1228 /*
1229 * Schedule packets for transfer.
1230 *
1231 * According to USB2.0 specification:
1232 *
1233 * 1st prio: interrupt xfers, up to 80 % of bandwidth
1234 * 2nd prio: control xfers
1235 * 3rd prio: bulk xfers
1236 *
1237 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
1238 * is very unclear on how to prioritize traffic):
1239 *
1240 * 1) Enqueue any queued control transfers, as long as payload chip mem
1241 * and PTD ATL slots are available.
1242 * 2) Enqueue any queued INT transfers, as long as payload chip mem
1243 * and PTD INT slots are available.
1244 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1245 * and PTD ATL slots are available.
1246 *
1247 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1248 * conservation of chip mem and performance.
1249 *
1250 * I'm sure this scheme could be improved upon!
1251 */
1252 for (i = 0; i < QH_END; i++) {
1253 ep_queue = &priv->qh_list[i];
1254 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1255 enqueue_qtds(hcd, qh);
1256 }
1257}
1258
1259#define PTD_STATE_QTD_DONE 1
1260#define PTD_STATE_QTD_RELOAD 2
1261#define PTD_STATE_URB_RETIRE 3
1262
1263static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1264 struct urb *urb)
1265{
1266 u32 dw4;
1267 int i;
1268
1269 dw4 = TO_U32(ptd->dw4);
1270 dw4 >>= 8;
1271
1272 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1273 need to handle these errors? Is it done in hardware? */
1274
1275 if (ptd->dw3 & DW3_HALT_BIT) {
1276
1277 urb->status = -EPROTO; /* Default unknown error */
1278
1279 for (i = 0; i < 8; i++) {
1280 switch (dw4 & 0x7) {
1281 case INT_UNDERRUN:
1282 dev_dbg(hcd->self.controller, "%s: underrun "
1283 "during uFrame %d\n",
1284 __func__, i);
1285 urb->status = -ECOMM; /* Could not write data */
1286 break;
1287 case INT_EXACT:
1288 dev_dbg(hcd->self.controller, "%s: transaction "
1289 "error during uFrame %d\n",
1290 __func__, i);
1291 urb->status = -EPROTO; /* timeout, bad CRC, PID
1292 error etc. */
1293 break;
1294 case INT_BABBLE:
1295 dev_dbg(hcd->self.controller, "%s: babble "
1296 "error during uFrame %d\n",
1297 __func__, i);
1298 urb->status = -EOVERFLOW;
1299 break;
1300 }
1301 dw4 >>= 3;
1302 }
1303
1304 return PTD_STATE_URB_RETIRE;
1305 }
1306
1307 return PTD_STATE_QTD_DONE;
1308}
1309
1310static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1311 struct urb *urb)
1312{
1313 WARN_ON(!ptd);
1314 if (ptd->dw3 & DW3_HALT_BIT) {
1315 if (ptd->dw3 & DW3_BABBLE_BIT)
1316 urb->status = -EOVERFLOW;
1317 else if (FROM_DW3_CERR(ptd->dw3))
1318 urb->status = -EPIPE; /* Stall */
1319 else
1320 urb->status = -EPROTO; /* Unknown */
1321/*
1322 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1323 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1324 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1325 __func__,
1326 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1327 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1328*/
1329 return PTD_STATE_URB_RETIRE;
1330 }
1331
1332 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1333 /* Transfer Error, *but* active and no HALT -> reload */
1334 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1335 return PTD_STATE_QTD_RELOAD;
1336 }
1337
1338 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1339 /*
1340 * NAKs are handled in HW by the chip. Usually if the
1341 * device is not able to send data fast enough.
1342 * This happens mostly on slower hardware.
1343 */
1344 return PTD_STATE_QTD_RELOAD;
1345 }
1346
1347 return PTD_STATE_QTD_DONE;
1348}
1349
1350static void handle_done_ptds(struct usb_hcd *hcd)
1351{
1352 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1353 struct ptd ptd;
1354 struct isp1760_qh *qh;
1355 int slot;
1356 int state;
1357 struct isp1760_slotinfo *slots;
1358 u32 ptd_offset;
1359 struct isp1760_qtd *qtd;
1360 int modified;
1361 int skip_map;
1362
1363 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1364 priv->int_done_map &= ~skip_map;
1365 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1366 priv->atl_done_map &= ~skip_map;
1367
1368 modified = priv->int_done_map || priv->atl_done_map;
1369
1370 while (priv->int_done_map || priv->atl_done_map) {
1371 if (priv->int_done_map) {
1372 /* INT ptd */
1373 slot = __ffs(priv->int_done_map);
1374 priv->int_done_map &= ~(1 << slot);
1375 slots = priv->int_slots;
1376 /* This should not trigger, and could be removed if
1377 noone have any problems with it triggering: */
1378 if (!slots[slot].qh) {
1379 WARN_ON(1);
1380 continue;
1381 }
1382 ptd_offset = INT_PTD_OFFSET;
1383 ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd);
1384 state = check_int_transfer(hcd, &ptd,
1385 slots[slot].qtd->urb);
1386 } else {
1387 /* ATL ptd */
1388 slot = __ffs(priv->atl_done_map);
1389 priv->atl_done_map &= ~(1 << slot);
1390 slots = priv->atl_slots;
1391 /* This should not trigger, and could be removed if
1392 noone have any problems with it triggering: */
1393 if (!slots[slot].qh) {
1394 WARN_ON(1);
1395 continue;
1396 }
1397 ptd_offset = ATL_PTD_OFFSET;
1398 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd);
1399 state = check_atl_transfer(hcd, &ptd,
1400 slots[slot].qtd->urb);
1401 }
1402
1403 qtd = slots[slot].qtd;
1404 slots[slot].qtd = NULL;
1405 qh = slots[slot].qh;
1406 slots[slot].qh = NULL;
1407 qh->slot = -1;
1408
1409 WARN_ON(qtd->status != QTD_XFER_STARTED);
1410
1411 switch (state) {
1412 case PTD_STATE_QTD_DONE:
1413 if ((usb_pipeint(qtd->urb->pipe)) &&
1414 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1415 qtd->actual_length =
1416 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1417 else
1418 qtd->actual_length =
1419 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1420
1421 qtd->status = QTD_XFER_COMPLETE;
1422 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1423 is_short_bulk(qtd))
1424 qtd = NULL;
1425 else
1426 qtd = list_entry(qtd->qtd_list.next,
1427 typeof(*qtd), qtd_list);
1428
1429 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1430 qh->ping = FROM_DW3_PING(ptd.dw3);
1431 break;
1432
1433 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1434 qtd->status = QTD_PAYLOAD_ALLOC;
1435 ptd.dw0 |= DW0_VALID_BIT;
1436 /* RL counter = ERR counter */
1437 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1438 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1439 ptd.dw3 &= ~TO_DW3_CERR(3);
1440 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1441 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1442 qh->ping = FROM_DW3_PING(ptd.dw3);
1443 break;
1444
1445 case PTD_STATE_URB_RETIRE:
1446 qtd->status = QTD_RETIRE;
1447 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1448 (qtd->urb->status != -EPIPE) &&
1449 (qtd->urb->status != -EREMOTEIO)) {
1450 qh->tt_buffer_dirty = 1;
1451 if (usb_hub_clear_tt_buffer(qtd->urb))
1452 /* Clear failed; let's hope things work
1453 anyway */
1454 qh->tt_buffer_dirty = 0;
1455 }
1456 qtd = NULL;
1457 qh->toggle = 0;
1458 qh->ping = 0;
1459 break;
1460
1461 default:
1462 WARN_ON(1);
1463 continue;
1464 }
1465
1466 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1467 if (slots == priv->int_slots) {
1468 if (state == PTD_STATE_QTD_RELOAD)
1469 dev_err(hcd->self.controller,
1470 "%s: PTD_STATE_QTD_RELOAD on "
1471 "interrupt packet\n", __func__);
1472 if (state != PTD_STATE_QTD_RELOAD)
1473 create_ptd_int(qh, qtd, &ptd);
1474 } else {
1475 if (state != PTD_STATE_QTD_RELOAD)
1476 create_ptd_atl(qh, qtd, &ptd);
1477 }
1478
1479 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1480 qh, &ptd);
1481 }
1482 }
1483
1484 if (modified)
1485 schedule_ptds(hcd);
1486}
1487
1488static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1489{
1490 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1491 irqreturn_t irqret = IRQ_NONE;
1492 u32 int_reg;
1493 u32 imask;
1494
1495 spin_lock(&priv->lock);
1496
1497 if (!(hcd->state & HC_STATE_RUNNING))
1498 goto leave;
1499
1500 imask = isp1760_hcd_read(hcd, HC_INTERRUPT);
1501 if (unlikely(!imask))
1502 goto leave;
1503
1504 int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT :
1505 ISP176x_HC_INTERRUPT;
1506 isp1760_reg_write(priv->regs, int_reg, imask);
1507
1508 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP);
1509 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP);
1510
1511 handle_done_ptds(hcd);
1512
1513 irqret = IRQ_HANDLED;
1514
1515leave:
1516 spin_unlock(&priv->lock);
1517
1518 return irqret;
1519}
1520
1521/*
1522 * Workaround for problem described in chip errata 2:
1523 *
1524 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1525 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1526 * ATL done interrupts (the "instead of" might be important since it seems
1527 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1528 * to set the PTD's done bit in addition to not generating an interrupt!).
1529 *
1530 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1531 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1532 *
1533 * If we use SOF interrupts only, we get latency between ptd completion and the
1534 * actual handling. This is very noticeable in testusb runs which takes several
1535 * minutes longer without ATL interrupts.
1536 *
1537 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1538 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1539 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1540 * completed and its done map bit is set.
1541 *
1542 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1543 * not to cause too much lag when this HW bug occurs, while still hopefully
1544 * ensuring that the check does not falsely trigger.
1545 */
1546#define SLOT_TIMEOUT 300
1547#define SLOT_CHECK_PERIOD 200
1548static struct timer_list errata2_timer;
1549static struct usb_hcd *errata2_timer_hcd;
1550
1551static void errata2_function(struct timer_list *unused)
1552{
1553 struct usb_hcd *hcd = errata2_timer_hcd;
1554 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1555 const struct isp1760_memory_layout *mem = priv->memory_layout;
1556 int slot;
1557 struct ptd ptd;
1558 unsigned long spinflags;
1559
1560 spin_lock_irqsave(&priv->lock, spinflags);
1561
1562 for (slot = 0; slot < mem->slot_num; slot++)
1563 if (priv->atl_slots[slot].qh && time_after(jiffies,
1564 priv->atl_slots[slot].timestamp +
1565 msecs_to_jiffies(SLOT_TIMEOUT))) {
1566 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd);
1567 if (!FROM_DW0_VALID(ptd.dw0) &&
1568 !FROM_DW3_ACTIVE(ptd.dw3))
1569 priv->atl_done_map |= 1 << slot;
1570 }
1571
1572 if (priv->atl_done_map)
1573 handle_done_ptds(hcd);
1574
1575 spin_unlock_irqrestore(&priv->lock, spinflags);
1576
1577 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1578 add_timer(&errata2_timer);
1579}
1580
1581static int isp1763_run(struct usb_hcd *hcd)
1582{
1583 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1584 int retval;
1585 u32 chipid_h;
1586 u32 chipid_l;
1587 u32 chip_rev;
1588 u32 ptd_atl_int;
1589 u32 ptd_iso;
1590
1591 hcd->uses_new_polling = 1;
1592 hcd->state = HC_STATE_RUNNING;
1593
1594 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
1595 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW);
1596 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV);
1597 dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n",
1598 chipid_h, chipid_l, chip_rev);
1599
1600 isp1760_hcd_clear(hcd, ISO_BUF_FILL);
1601 isp1760_hcd_clear(hcd, INT_BUF_FILL);
1602 isp1760_hcd_clear(hcd, ATL_BUF_FILL);
1603
1604 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
1605 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
1606 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
1607 ndelay(100);
1608 isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP);
1609 isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP);
1610 isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP);
1611
1612 isp1760_hcd_set(hcd, HW_OTG_DISABLE);
1613 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7));
1614 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15));
1615 mdelay(10);
1616
1617 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE);
1618 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE);
1619
1620 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN);
1621
1622 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND);
1623 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND);
1624 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND);
1625
1626 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR);
1627 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR);
1628 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR);
1629
1630 ptd_atl_int = 0x8000;
1631 ptd_iso = 0x0001;
1632
1633 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int);
1634 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int);
1635 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso);
1636
1637 isp1760_hcd_set(hcd, ATL_BUF_FILL);
1638 isp1760_hcd_set(hcd, INT_BUF_FILL);
1639
1640 isp1760_hcd_clear(hcd, CMD_LRESET);
1641 isp1760_hcd_clear(hcd, CMD_RESET);
1642
1643 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000);
1644 if (retval)
1645 return retval;
1646
1647 down_write(&ehci_cf_port_reset_rwsem);
1648 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000);
1649 up_write(&ehci_cf_port_reset_rwsem);
1650 if (retval)
1651 return retval;
1652
1653 return 0;
1654}
1655
1656static int isp1760_run(struct usb_hcd *hcd)
1657{
1658 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1659 int retval;
1660 u32 chipid_h;
1661 u32 chipid_l;
1662 u32 chip_rev;
1663 u32 ptd_atl_int;
1664 u32 ptd_iso;
1665
1666 /*
1667 * ISP1763 have some differences in the setup and order to enable
1668 * the ports, disable otg, setup buffers, and ATL, INT, ISO status.
1669 * So, just handle it a separate sequence.
1670 */
1671 if (priv->is_isp1763)
1672 return isp1763_run(hcd);
1673
1674 hcd->uses_new_polling = 1;
1675
1676 hcd->state = HC_STATE_RUNNING;
1677
1678 /* Set PTD interrupt AND & OR maps */
1679 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND);
1680 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND);
1681 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND);
1682
1683 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR);
1684 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR);
1685 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR);
1686
1687 /* step 23 passed */
1688
1689 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN);
1690
1691 isp1760_hcd_clear(hcd, CMD_LRESET);
1692 isp1760_hcd_clear(hcd, CMD_RESET);
1693
1694 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000);
1695 if (retval)
1696 return retval;
1697
1698 /*
1699 * XXX
1700 * Spec says to write FLAG_CF as last config action, priv code grabs
1701 * the semaphore while doing so.
1702 */
1703 down_write(&ehci_cf_port_reset_rwsem);
1704
1705 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000);
1706 up_write(&ehci_cf_port_reset_rwsem);
1707 if (retval)
1708 return retval;
1709
1710 errata2_timer_hcd = hcd;
1711 timer_setup(&errata2_timer, errata2_function, 0);
1712 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1713 add_timer(&errata2_timer);
1714
1715 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
1716 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW);
1717 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV);
1718 dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n",
1719 chipid_h, chipid_l, chip_rev);
1720
1721 /* PTD Register Init Part 2, Step 28 */
1722
1723 /* Setup registers controlling PTD checking */
1724 ptd_atl_int = 0x80000000;
1725 ptd_iso = 0x00000001;
1726
1727 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int);
1728 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int);
1729 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso);
1730
1731 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
1732 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
1733 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
1734
1735 isp1760_hcd_set(hcd, ATL_BUF_FILL);
1736 isp1760_hcd_set(hcd, INT_BUF_FILL);
1737
1738 /* GRR this is run-once init(), being done every time the HC starts.
1739 * So long as they're part of class devices, we can't do it init()
1740 * since the class device isn't created that early.
1741 */
1742 return 0;
1743}
1744
1745static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1746{
1747 qtd->data_buffer = databuffer;
1748
1749 qtd->length = len;
1750
1751 return qtd->length;
1752}
1753
1754static void qtd_list_free(struct list_head *qtd_list)
1755{
1756 struct isp1760_qtd *qtd, *qtd_next;
1757
1758 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1759 list_del(&qtd->qtd_list);
1760 qtd_free(qtd);
1761 }
1762}
1763
1764/*
1765 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1766 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1767 */
1768#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1769static void packetize_urb(struct usb_hcd *hcd,
1770 struct urb *urb, struct list_head *head, gfp_t flags)
1771{
1772 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1773 const struct isp1760_memory_layout *mem = priv->memory_layout;
1774 struct isp1760_qtd *qtd;
1775 void *buf;
1776 int len, maxpacketsize;
1777 u8 packet_type;
1778
1779 /*
1780 * URBs map to sequences of QTDs: one logical transaction
1781 */
1782
1783 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1784 /* XXX This looks like usb storage / SCSI bug */
1785 dev_err(hcd->self.controller,
1786 "buf is null, dma is %08lx len is %d\n",
1787 (long unsigned)urb->transfer_dma,
1788 urb->transfer_buffer_length);
1789 WARN_ON(1);
1790 }
1791
1792 if (usb_pipein(urb->pipe))
1793 packet_type = IN_PID;
1794 else
1795 packet_type = OUT_PID;
1796
1797 if (usb_pipecontrol(urb->pipe)) {
1798 qtd = qtd_alloc(flags, urb, SETUP_PID);
1799 if (!qtd)
1800 goto cleanup;
1801 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1802 list_add_tail(&qtd->qtd_list, head);
1803
1804 /* for zero length DATA stages, STATUS is always IN */
1805 if (urb->transfer_buffer_length == 0)
1806 packet_type = IN_PID;
1807 }
1808
1809 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1810 usb_pipeout(urb->pipe)));
1811
1812 /*
1813 * buffer gets wrapped in one or more qtds;
1814 * last one may be "short" (including zero len)
1815 * and may serve as a control status ack
1816 */
1817 buf = urb->transfer_buffer;
1818 len = urb->transfer_buffer_length;
1819
1820 for (;;) {
1821 int this_qtd_len;
1822
1823 qtd = qtd_alloc(flags, urb, packet_type);
1824 if (!qtd)
1825 goto cleanup;
1826
1827 if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1])
1828 this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1];
1829 else
1830 this_qtd_len = len;
1831
1832 this_qtd_len = qtd_fill(qtd, buf, this_qtd_len);
1833 list_add_tail(&qtd->qtd_list, head);
1834
1835 len -= this_qtd_len;
1836 buf += this_qtd_len;
1837
1838 if (len <= 0)
1839 break;
1840 }
1841
1842 /*
1843 * control requests may need a terminating data "status" ack;
1844 * bulk ones may need a terminating short packet (zero length).
1845 */
1846 if (urb->transfer_buffer_length != 0) {
1847 int one_more = 0;
1848
1849 if (usb_pipecontrol(urb->pipe)) {
1850 one_more = 1;
1851 if (packet_type == IN_PID)
1852 packet_type = OUT_PID;
1853 else
1854 packet_type = IN_PID;
1855 } else if (usb_pipebulk(urb->pipe)
1856 && (urb->transfer_flags & URB_ZERO_PACKET)
1857 && !(urb->transfer_buffer_length %
1858 maxpacketsize)) {
1859 one_more = 1;
1860 }
1861 if (one_more) {
1862 qtd = qtd_alloc(flags, urb, packet_type);
1863 if (!qtd)
1864 goto cleanup;
1865
1866 /* never any data in such packets */
1867 qtd_fill(qtd, NULL, 0);
1868 list_add_tail(&qtd->qtd_list, head);
1869 }
1870 }
1871
1872 return;
1873
1874cleanup:
1875 qtd_list_free(head);
1876}
1877
1878static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1879 gfp_t mem_flags)
1880{
1881 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1882 struct list_head *ep_queue;
1883 struct isp1760_qh *qh, *qhit;
1884 unsigned long spinflags;
1885 LIST_HEAD(new_qtds);
1886 int retval;
1887 int qh_in_queue;
1888
1889 switch (usb_pipetype(urb->pipe)) {
1890 case PIPE_CONTROL:
1891 ep_queue = &priv->qh_list[QH_CONTROL];
1892 break;
1893 case PIPE_BULK:
1894 ep_queue = &priv->qh_list[QH_BULK];
1895 break;
1896 case PIPE_INTERRUPT:
1897 if (urb->interval < 0)
1898 return -EINVAL;
1899 /* FIXME: Check bandwidth */
1900 ep_queue = &priv->qh_list[QH_INTERRUPT];
1901 break;
1902 case PIPE_ISOCHRONOUS:
1903 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1904 "not yet supported\n",
1905 __func__);
1906 return -EPIPE;
1907 default:
1908 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1909 __func__);
1910 return -EPIPE;
1911 }
1912
1913 if (usb_pipein(urb->pipe))
1914 urb->actual_length = 0;
1915
1916 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1917 if (list_empty(&new_qtds))
1918 return -ENOMEM;
1919
1920 retval = 0;
1921 spin_lock_irqsave(&priv->lock, spinflags);
1922
1923 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1924 retval = -ESHUTDOWN;
1925 qtd_list_free(&new_qtds);
1926 goto out;
1927 }
1928 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1929 if (retval) {
1930 qtd_list_free(&new_qtds);
1931 goto out;
1932 }
1933
1934 qh = urb->ep->hcpriv;
1935 if (qh) {
1936 qh_in_queue = 0;
1937 list_for_each_entry(qhit, ep_queue, qh_list) {
1938 if (qhit == qh) {
1939 qh_in_queue = 1;
1940 break;
1941 }
1942 }
1943 if (!qh_in_queue)
1944 list_add_tail(&qh->qh_list, ep_queue);
1945 } else {
1946 qh = qh_alloc(GFP_ATOMIC);
1947 if (!qh) {
1948 retval = -ENOMEM;
1949 usb_hcd_unlink_urb_from_ep(hcd, urb);
1950 qtd_list_free(&new_qtds);
1951 goto out;
1952 }
1953 list_add_tail(&qh->qh_list, ep_queue);
1954 urb->ep->hcpriv = qh;
1955 }
1956
1957 list_splice_tail(&new_qtds, &qh->qtd_list);
1958 schedule_ptds(hcd);
1959
1960out:
1961 spin_unlock_irqrestore(&priv->lock, spinflags);
1962 return retval;
1963}
1964
1965static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1966 struct isp1760_qh *qh)
1967{
1968 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1969 int skip_map;
1970
1971 WARN_ON(qh->slot == -1);
1972
1973 /* We need to forcefully reclaim the slot since some transfers never
1974 return, e.g. interrupt transfers and NAKed bulk transfers. */
1975 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1976 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1977 skip_map |= (1 << qh->slot);
1978 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map);
1979 ndelay(100);
1980 priv->atl_slots[qh->slot].qh = NULL;
1981 priv->atl_slots[qh->slot].qtd = NULL;
1982 } else {
1983 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1984 skip_map |= (1 << qh->slot);
1985 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map);
1986 priv->int_slots[qh->slot].qh = NULL;
1987 priv->int_slots[qh->slot].qtd = NULL;
1988 }
1989
1990 qh->slot = -1;
1991}
1992
1993/*
1994 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1995 * any active transfer belonging to the urb in the process.
1996 */
1997static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1998 struct isp1760_qtd *qtd)
1999{
2000 struct urb *urb;
2001 int urb_was_running;
2002
2003 urb = qtd->urb;
2004 urb_was_running = 0;
2005 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
2006 if (qtd->urb != urb)
2007 break;
2008
2009 if (qtd->status >= QTD_XFER_STARTED)
2010 urb_was_running = 1;
2011 if (last_qtd_of_urb(qtd, qh) &&
2012 (qtd->status >= QTD_XFER_COMPLETE))
2013 urb_was_running = 0;
2014
2015 if (qtd->status == QTD_XFER_STARTED)
2016 kill_transfer(hcd, urb, qh);
2017 qtd->status = QTD_RETIRE;
2018 }
2019
2020 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
2021 qh->tt_buffer_dirty = 1;
2022 if (usb_hub_clear_tt_buffer(urb))
2023 /* Clear failed; let's hope things work anyway */
2024 qh->tt_buffer_dirty = 0;
2025 }
2026}
2027
2028static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2029 int status)
2030{
2031 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2032 unsigned long spinflags;
2033 struct isp1760_qh *qh;
2034 struct isp1760_qtd *qtd;
2035 int retval = 0;
2036
2037 spin_lock_irqsave(&priv->lock, spinflags);
2038 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
2039 if (retval)
2040 goto out;
2041
2042 qh = urb->ep->hcpriv;
2043 if (!qh) {
2044 retval = -EINVAL;
2045 goto out;
2046 }
2047
2048 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
2049 if (qtd->urb == urb) {
2050 dequeue_urb_from_qtd(hcd, qh, qtd);
2051 list_move(&qtd->qtd_list, &qh->qtd_list);
2052 break;
2053 }
2054
2055 urb->status = status;
2056 schedule_ptds(hcd);
2057
2058out:
2059 spin_unlock_irqrestore(&priv->lock, spinflags);
2060 return retval;
2061}
2062
2063static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2064 struct usb_host_endpoint *ep)
2065{
2066 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2067 unsigned long spinflags;
2068 struct isp1760_qh *qh, *qh_iter;
2069 int i;
2070
2071 spin_lock_irqsave(&priv->lock, spinflags);
2072
2073 qh = ep->hcpriv;
2074 if (!qh)
2075 goto out;
2076
2077 WARN_ON(!list_empty(&qh->qtd_list));
2078
2079 for (i = 0; i < QH_END; i++)
2080 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
2081 if (qh_iter == qh) {
2082 list_del(&qh_iter->qh_list);
2083 i = QH_END;
2084 break;
2085 }
2086 qh_free(qh);
2087 ep->hcpriv = NULL;
2088
2089 schedule_ptds(hcd);
2090
2091out:
2092 spin_unlock_irqrestore(&priv->lock, spinflags);
2093}
2094
2095static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
2096{
2097 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2098 u32 status = 0;
2099 int retval = 1;
2100 unsigned long flags;
2101
2102 /* if !PM, root hub timers won't get shut down ... */
2103 if (!HC_IS_RUNNING(hcd->state))
2104 return 0;
2105
2106 /* init status to no-changes */
2107 buf[0] = 0;
2108
2109 spin_lock_irqsave(&priv->lock, flags);
2110
2111 if (isp1760_hcd_is_set(hcd, PORT_OWNER) &&
2112 isp1760_hcd_is_set(hcd, PORT_CSC)) {
2113 isp1760_hcd_clear(hcd, PORT_CSC);
2114 goto done;
2115 }
2116
2117 /*
2118 * Return status information even for ports with OWNER set.
2119 * Otherwise hub_wq wouldn't see the disconnect event when a
2120 * high-speed device is switched over to the companion
2121 * controller by the user.
2122 */
2123 if (isp1760_hcd_is_set(hcd, PORT_CSC) ||
2124 (isp1760_hcd_is_set(hcd, PORT_RESUME) &&
2125 time_after_eq(jiffies, priv->reset_done))) {
2126 buf [0] |= 1 << (0 + 1);
2127 status = STS_PCD;
2128 }
2129 /* FIXME autosuspend idle root hubs */
2130done:
2131 spin_unlock_irqrestore(&priv->lock, flags);
2132 return status ? retval : 0;
2133}
2134
2135static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
2136 struct usb_hub_descriptor *desc)
2137{
2138 int ports;
2139 u16 temp;
2140
2141 ports = isp1760_hcd_n_ports(priv->hcd);
2142
2143 desc->bDescriptorType = USB_DT_HUB;
2144 /* priv 1.0, 2.3.9 says 20ms max */
2145 desc->bPwrOn2PwrGood = 10;
2146 desc->bHubContrCurrent = 0;
2147
2148 desc->bNbrPorts = ports;
2149 temp = 1 + (ports / 8);
2150 desc->bDescLength = 7 + 2 * temp;
2151
2152 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
2153 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
2154 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
2155
2156 /* per-port overcurrent reporting */
2157 temp = HUB_CHAR_INDV_PORT_OCPM;
2158 if (isp1760_hcd_ppc_is_set(priv->hcd))
2159 /* per-port power control */
2160 temp |= HUB_CHAR_INDV_PORT_LPSM;
2161 else
2162 /* no power switching */
2163 temp |= HUB_CHAR_NO_LPSM;
2164 desc->wHubCharacteristics = cpu_to_le16(temp);
2165}
2166
2167#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
2168
2169static void check_reset_complete(struct usb_hcd *hcd, int index)
2170{
2171 if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT)))
2172 return;
2173
2174 /* if reset finished and it's still not enabled -- handoff */
2175 if (!isp1760_hcd_is_set(hcd, PORT_PE)) {
2176 dev_info(hcd->self.controller,
2177 "port %d full speed --> companion\n", index + 1);
2178
2179 isp1760_hcd_set(hcd, PORT_OWNER);
2180
2181 isp1760_hcd_clear(hcd, PORT_CSC);
2182 } else {
2183 dev_info(hcd->self.controller, "port %d high speed\n",
2184 index + 1);
2185 }
2186
2187 return;
2188}
2189
2190static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2191 u16 wValue, u16 wIndex, char *buf, u16 wLength)
2192{
2193 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2194 u32 status;
2195 unsigned long flags;
2196 int retval = 0;
2197 int ports;
2198
2199 ports = isp1760_hcd_n_ports(hcd);
2200
2201 /*
2202 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
2203 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
2204 * (track current state ourselves) ... blink for diagnostics,
2205 * power, "this is the one", etc. EHCI spec supports this.
2206 */
2207
2208 spin_lock_irqsave(&priv->lock, flags);
2209 switch (typeReq) {
2210 case ClearHubFeature:
2211 switch (wValue) {
2212 case C_HUB_LOCAL_POWER:
2213 case C_HUB_OVER_CURRENT:
2214 /* no hub-wide feature/status flags */
2215 break;
2216 default:
2217 goto error;
2218 }
2219 break;
2220 case ClearPortFeature:
2221 if (!wIndex || wIndex > ports)
2222 goto error;
2223 wIndex--;
2224
2225 /*
2226 * Even if OWNER is set, so the port is owned by the
2227 * companion controller, hub_wq needs to be able to clear
2228 * the port-change status bits (especially
2229 * USB_PORT_STAT_C_CONNECTION).
2230 */
2231
2232 switch (wValue) {
2233 case USB_PORT_FEAT_ENABLE:
2234 isp1760_hcd_clear(hcd, PORT_PE);
2235 break;
2236 case USB_PORT_FEAT_C_ENABLE:
2237 /* XXX error? */
2238 break;
2239 case USB_PORT_FEAT_SUSPEND:
2240 if (isp1760_hcd_is_set(hcd, PORT_RESET))
2241 goto error;
2242
2243 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) {
2244 if (!isp1760_hcd_is_set(hcd, PORT_PE))
2245 goto error;
2246 /* resume signaling for 20 msec */
2247 isp1760_hcd_clear(hcd, PORT_CSC);
2248 isp1760_hcd_set(hcd, PORT_RESUME);
2249
2250 priv->reset_done = jiffies +
2251 msecs_to_jiffies(USB_RESUME_TIMEOUT);
2252 }
2253 break;
2254 case USB_PORT_FEAT_C_SUSPEND:
2255 /* we auto-clear this feature */
2256 break;
2257 case USB_PORT_FEAT_POWER:
2258 if (isp1760_hcd_ppc_is_set(hcd))
2259 isp1760_hcd_clear(hcd, PORT_POWER);
2260 break;
2261 case USB_PORT_FEAT_C_CONNECTION:
2262 isp1760_hcd_set(hcd, PORT_CSC);
2263 break;
2264 case USB_PORT_FEAT_C_OVER_CURRENT:
2265 /* XXX error ?*/
2266 break;
2267 case USB_PORT_FEAT_C_RESET:
2268 /* GetPortStatus clears reset */
2269 break;
2270 default:
2271 goto error;
2272 }
2273 isp1760_hcd_read(hcd, CMD_RUN);
2274 break;
2275 case GetHubDescriptor:
2276 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
2277 buf);
2278 break;
2279 case GetHubStatus:
2280 /* no hub-wide feature/status flags */
2281 memset(buf, 0, 4);
2282 break;
2283 case GetPortStatus:
2284 if (!wIndex || wIndex > ports)
2285 goto error;
2286 wIndex--;
2287 status = 0;
2288
2289 /* wPortChange bits */
2290 if (isp1760_hcd_is_set(hcd, PORT_CSC))
2291 status |= USB_PORT_STAT_C_CONNECTION << 16;
2292
2293 /* whoever resumes must GetPortStatus to complete it!! */
2294 if (isp1760_hcd_is_set(hcd, PORT_RESUME)) {
2295 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
2296
2297 /* Remote Wakeup received? */
2298 if (!priv->reset_done) {
2299 /* resume signaling for 20 msec */
2300 priv->reset_done = jiffies
2301 + msecs_to_jiffies(20);
2302 /* check the port again */
2303 mod_timer(&hcd->rh_timer, priv->reset_done);
2304 }
2305
2306 /* resume completed? */
2307 else if (time_after_eq(jiffies,
2308 priv->reset_done)) {
2309 status |= USB_PORT_STAT_C_SUSPEND << 16;
2310 priv->reset_done = 0;
2311
2312 /* stop resume signaling */
2313 isp1760_hcd_clear(hcd, PORT_CSC);
2314
2315 retval = isp1760_hcd_clear_and_wait(hcd,
2316 PORT_RESUME, 2000);
2317 if (retval != 0) {
2318 dev_err(hcd->self.controller,
2319 "port %d resume error %d\n",
2320 wIndex + 1, retval);
2321 goto error;
2322 }
2323 }
2324 }
2325
2326 /* whoever resets must GetPortStatus to complete it!! */
2327 if (isp1760_hcd_is_set(hcd, PORT_RESET) &&
2328 time_after_eq(jiffies, priv->reset_done)) {
2329 status |= USB_PORT_STAT_C_RESET << 16;
2330 priv->reset_done = 0;
2331
2332 /* force reset to complete */
2333 /* REVISIT: some hardware needs 550+ usec to clear
2334 * this bit; seems too long to spin routinely...
2335 */
2336 retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET,
2337 750);
2338 if (retval != 0) {
2339 dev_err(hcd->self.controller, "port %d reset error %d\n",
2340 wIndex + 1, retval);
2341 goto error;
2342 }
2343
2344 /* see what we found out */
2345 check_reset_complete(hcd, wIndex);
2346 }
2347 /*
2348 * Even if OWNER is set, there's no harm letting hub_wq
2349 * see the wPortStatus values (they should all be 0 except
2350 * for PORT_POWER anyway).
2351 */
2352
2353 if (isp1760_hcd_is_set(hcd, PORT_OWNER))
2354 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2355
2356 if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) {
2357 status |= USB_PORT_STAT_CONNECTION;
2358 /* status may be from integrated TT */
2359 status |= USB_PORT_STAT_HIGH_SPEED;
2360 }
2361 if (isp1760_hcd_is_set(hcd, PORT_PE))
2362 status |= USB_PORT_STAT_ENABLE;
2363 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) &&
2364 isp1760_hcd_is_set(hcd, PORT_RESUME))
2365 status |= USB_PORT_STAT_SUSPEND;
2366 if (isp1760_hcd_is_set(hcd, PORT_RESET))
2367 status |= USB_PORT_STAT_RESET;
2368 if (isp1760_hcd_is_set(hcd, PORT_POWER))
2369 status |= USB_PORT_STAT_POWER;
2370
2371 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2372 break;
2373 case SetHubFeature:
2374 switch (wValue) {
2375 case C_HUB_LOCAL_POWER:
2376 case C_HUB_OVER_CURRENT:
2377 /* no hub-wide feature/status flags */
2378 break;
2379 default:
2380 goto error;
2381 }
2382 break;
2383 case SetPortFeature:
2384 wIndex &= 0xff;
2385 if (!wIndex || wIndex > ports)
2386 goto error;
2387 wIndex--;
2388
2389 if (isp1760_hcd_is_set(hcd, PORT_OWNER))
2390 break;
2391
2392 switch (wValue) {
2393 case USB_PORT_FEAT_ENABLE:
2394 isp1760_hcd_set(hcd, PORT_PE);
2395 break;
2396
2397 case USB_PORT_FEAT_SUSPEND:
2398 if (!isp1760_hcd_is_set(hcd, PORT_PE) ||
2399 isp1760_hcd_is_set(hcd, PORT_RESET))
2400 goto error;
2401
2402 isp1760_hcd_set(hcd, PORT_SUSPEND);
2403 break;
2404 case USB_PORT_FEAT_POWER:
2405 if (isp1760_hcd_ppc_is_set(hcd))
2406 isp1760_hcd_set(hcd, PORT_POWER);
2407 break;
2408 case USB_PORT_FEAT_RESET:
2409 if (isp1760_hcd_is_set(hcd, PORT_RESUME))
2410 goto error;
2411 /* line status bits may report this as low speed,
2412 * which can be fine if this root hub has a
2413 * transaction translator built in.
2414 */
2415 if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) &&
2416 !isp1760_hcd_is_set(hcd, PORT_PE)) &&
2417 (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) {
2418 isp1760_hcd_set(hcd, PORT_OWNER);
2419 } else {
2420 isp1760_hcd_set(hcd, PORT_RESET);
2421 isp1760_hcd_clear(hcd, PORT_PE);
2422
2423 /*
2424 * caller must wait, then call GetPortStatus
2425 * usb 2.0 spec says 50 ms resets on root
2426 */
2427 priv->reset_done = jiffies +
2428 msecs_to_jiffies(50);
2429 }
2430 break;
2431 default:
2432 goto error;
2433 }
2434 break;
2435
2436 default:
2437error:
2438 /* "stall" on error */
2439 retval = -EPIPE;
2440 }
2441 spin_unlock_irqrestore(&priv->lock, flags);
2442 return retval;
2443}
2444
2445static int isp1760_get_frame(struct usb_hcd *hcd)
2446{
2447 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2448 u32 fr;
2449
2450 fr = isp1760_hcd_read(hcd, HC_FRINDEX);
2451 return (fr >> 3) % priv->periodic_size;
2452}
2453
2454static void isp1760_stop(struct usb_hcd *hcd)
2455{
2456 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2457
2458 del_timer(&errata2_timer);
2459
2460 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2461 NULL, 0);
2462 msleep(20);
2463
2464 spin_lock_irq(&priv->lock);
2465 ehci_reset(hcd);
2466 /* Disable IRQ */
2467 isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN);
2468 spin_unlock_irq(&priv->lock);
2469
2470 isp1760_hcd_clear(hcd, FLAG_CF);
2471}
2472
2473static void isp1760_shutdown(struct usb_hcd *hcd)
2474{
2475 isp1760_stop(hcd);
2476
2477 isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN);
2478
2479 isp1760_hcd_clear(hcd, CMD_RUN);
2480}
2481
2482static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2483 struct usb_host_endpoint *ep)
2484{
2485 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2486 struct isp1760_qh *qh = ep->hcpriv;
2487 unsigned long spinflags;
2488
2489 if (!qh)
2490 return;
2491
2492 spin_lock_irqsave(&priv->lock, spinflags);
2493 qh->tt_buffer_dirty = 0;
2494 schedule_ptds(hcd);
2495 spin_unlock_irqrestore(&priv->lock, spinflags);
2496}
2497
2498
2499static const struct hc_driver isp1760_hc_driver = {
2500 .description = "isp1760-hcd",
2501 .product_desc = "NXP ISP1760 USB Host Controller",
2502 .hcd_priv_size = sizeof(struct isp1760_hcd *),
2503 .irq = isp1760_irq,
2504 .flags = HCD_MEMORY | HCD_USB2,
2505 .reset = isp1760_hc_setup,
2506 .start = isp1760_run,
2507 .stop = isp1760_stop,
2508 .shutdown = isp1760_shutdown,
2509 .urb_enqueue = isp1760_urb_enqueue,
2510 .urb_dequeue = isp1760_urb_dequeue,
2511 .endpoint_disable = isp1760_endpoint_disable,
2512 .get_frame_number = isp1760_get_frame,
2513 .hub_status_data = isp1760_hub_status_data,
2514 .hub_control = isp1760_hub_control,
2515 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2516};
2517
2518int __init isp1760_init_kmem_once(void)
2519{
2520 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2521 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2522 SLAB_MEM_SPREAD, NULL);
2523
2524 if (!urb_listitem_cachep)
2525 return -ENOMEM;
2526
2527 qtd_cachep = kmem_cache_create("isp1760_qtd",
2528 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2529 SLAB_MEM_SPREAD, NULL);
2530
2531 if (!qtd_cachep)
2532 return -ENOMEM;
2533
2534 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2535 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2536
2537 if (!qh_cachep) {
2538 kmem_cache_destroy(qtd_cachep);
2539 return -ENOMEM;
2540 }
2541
2542 return 0;
2543}
2544
2545void isp1760_deinit_kmem_cache(void)
2546{
2547 kmem_cache_destroy(qtd_cachep);
2548 kmem_cache_destroy(qh_cachep);
2549 kmem_cache_destroy(urb_listitem_cachep);
2550}
2551
2552int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem,
2553 int irq, unsigned long irqflags,
2554 struct device *dev)
2555{
2556 const struct isp1760_memory_layout *mem_layout = priv->memory_layout;
2557 struct usb_hcd *hcd;
2558 int ret;
2559
2560 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2561 if (!hcd)
2562 return -ENOMEM;
2563
2564 *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2565
2566 priv->hcd = hcd;
2567
2568 priv->atl_slots = kcalloc(mem_layout->slot_num,
2569 sizeof(struct isp1760_slotinfo), GFP_KERNEL);
2570 if (!priv->atl_slots) {
2571 ret = -ENOMEM;
2572 goto put_hcd;
2573 }
2574
2575 priv->int_slots = kcalloc(mem_layout->slot_num,
2576 sizeof(struct isp1760_slotinfo), GFP_KERNEL);
2577 if (!priv->int_slots) {
2578 ret = -ENOMEM;
2579 goto free_atl_slots;
2580 }
2581
2582 init_memory(priv);
2583
2584 hcd->irq = irq;
2585 hcd->rsrc_start = mem->start;
2586 hcd->rsrc_len = resource_size(mem);
2587
2588 /* This driver doesn't support wakeup requests */
2589 hcd->cant_recv_wakeups = 1;
2590
2591 ret = usb_add_hcd(hcd, irq, irqflags);
2592 if (ret)
2593 goto free_int_slots;
2594
2595 device_wakeup_enable(hcd->self.controller);
2596
2597 return 0;
2598
2599free_int_slots:
2600 kfree(priv->int_slots);
2601free_atl_slots:
2602 kfree(priv->atl_slots);
2603put_hcd:
2604 usb_put_hcd(hcd);
2605 return ret;
2606}
2607
2608void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2609{
2610 if (!priv->hcd)
2611 return;
2612
2613 usb_remove_hcd(priv->hcd);
2614 usb_put_hcd(priv->hcd);
2615 kfree(priv->atl_slots);
2616 kfree(priv->int_slots);
2617}