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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the NXP ISP1760 chip
4 *
5 * However, the code might contain some bugs. What doesn't work for sure is:
6 * - ISO
7 * - OTG
8 e The interrupt line is configured as active low, level.
9 *
10 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
11 *
12 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
13 *
14 */
15#include <linux/gpio/consumer.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/list.h>
20#include <linux/usb.h>
21#include <linux/usb/hcd.h>
22#include <linux/debugfs.h>
23#include <linux/uaccess.h>
24#include <linux/io.h>
25#include <linux/mm.h>
26#include <linux/timer.h>
27#include <asm/unaligned.h>
28#include <asm/cacheflush.h>
29
30#include "isp1760-core.h"
31#include "isp1760-hcd.h"
32#include "isp1760-regs.h"
33
34static struct kmem_cache *qtd_cachep;
35static struct kmem_cache *qh_cachep;
36static struct kmem_cache *urb_listitem_cachep;
37
38typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
39 struct isp1760_qtd *qtd);
40
41static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
42{
43 return *(struct isp1760_hcd **)hcd->hcd_priv;
44}
45
46/* urb state*/
47#define DELETE_URB (0x0008)
48#define NO_TRANSFER_ACTIVE (0xffffffff)
49
50/* Philips Proprietary Transfer Descriptor (PTD) */
51typedef __u32 __bitwise __dw;
52struct ptd {
53 __dw dw0;
54 __dw dw1;
55 __dw dw2;
56 __dw dw3;
57 __dw dw4;
58 __dw dw5;
59 __dw dw6;
60 __dw dw7;
61};
62#define PTD_OFFSET 0x0400
63#define ISO_PTD_OFFSET 0x0400
64#define INT_PTD_OFFSET 0x0800
65#define ATL_PTD_OFFSET 0x0c00
66#define PAYLOAD_OFFSET 0x1000
67
68
69/* ATL */
70/* DW0 */
71#define DW0_VALID_BIT 1
72#define FROM_DW0_VALID(x) ((x) & 0x01)
73#define TO_DW0_LENGTH(x) (((u32) x) << 3)
74#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
75#define TO_DW0_MULTI(x) (((u32) x) << 29)
76#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
77/* DW1 */
78#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
79#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
80#define DW1_TRANS_BULK ((u32) 2 << 12)
81#define DW1_TRANS_INT ((u32) 3 << 12)
82#define DW1_TRANS_SPLIT ((u32) 1 << 14)
83#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
84#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
85#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
86/* DW2 */
87#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
88#define TO_DW2_RL(x) ((x) << 25)
89#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
90/* DW3 */
91#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
92#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
93#define TO_DW3_NAKCOUNT(x) ((x) << 19)
94#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
95#define TO_DW3_CERR(x) ((x) << 23)
96#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
97#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
98#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
99#define TO_DW3_PING(x) ((x) << 26)
100#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
101#define DW3_ERROR_BIT (1 << 28)
102#define DW3_BABBLE_BIT (1 << 29)
103#define DW3_HALT_BIT (1 << 30)
104#define DW3_ACTIVE_BIT (1 << 31)
105#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
106
107#define INT_UNDERRUN (1 << 2)
108#define INT_BABBLE (1 << 1)
109#define INT_EXACT (1 << 0)
110
111#define SETUP_PID (2)
112#define IN_PID (1)
113#define OUT_PID (0)
114
115/* Errata 1 */
116#define RL_COUNTER (0)
117#define NAK_COUNTER (0)
118#define ERR_COUNTER (2)
119
120struct isp1760_qtd {
121 u8 packet_type;
122 void *data_buffer;
123 u32 payload_addr;
124
125 /* the rest is HCD-private */
126 struct list_head qtd_list;
127 struct urb *urb;
128 size_t length;
129 size_t actual_length;
130
131 /* QTD_ENQUEUED: waiting for transfer (inactive) */
132 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
133 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
134 interrupt handler may touch this qtd! */
135 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
136 /* QTD_RETIRE: transfer error/abort qtd */
137#define QTD_ENQUEUED 0
138#define QTD_PAYLOAD_ALLOC 1
139#define QTD_XFER_STARTED 2
140#define QTD_XFER_COMPLETE 3
141#define QTD_RETIRE 4
142 u32 status;
143};
144
145/* Queue head, one for each active endpoint */
146struct isp1760_qh {
147 struct list_head qh_list;
148 struct list_head qtd_list;
149 u32 toggle;
150 u32 ping;
151 int slot;
152 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
153};
154
155struct urb_listitem {
156 struct list_head urb_list;
157 struct urb *urb;
158};
159
160/*
161 * Access functions for isp176x registers (addresses 0..0x03FF).
162 */
163static u32 reg_read32(void __iomem *base, u32 reg)
164{
165 return isp1760_read32(base, reg);
166}
167
168static void reg_write32(void __iomem *base, u32 reg, u32 val)
169{
170 isp1760_write32(base, reg, val);
171}
172
173/*
174 * Access functions for isp176x memory (offset >= 0x0400).
175 *
176 * bank_reads8() reads memory locations prefetched by an earlier write to
177 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
178 * bank optimizations, you should use the more generic mem_reads8() below.
179 *
180 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
181 * below.
182 *
183 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
184 * doesn't quite work because some people have to enforce 32-bit access
185 */
186static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
187 __u32 *dst, u32 bytes)
188{
189 __u32 __iomem *src;
190 u32 val;
191 __u8 *src_byteptr;
192 __u8 *dst_byteptr;
193
194 src = src_base + (bank_addr | src_offset);
195
196 if (src_offset < PAYLOAD_OFFSET) {
197 while (bytes >= 4) {
198 *dst = le32_to_cpu(__raw_readl(src));
199 bytes -= 4;
200 src++;
201 dst++;
202 }
203 } else {
204 while (bytes >= 4) {
205 *dst = __raw_readl(src);
206 bytes -= 4;
207 src++;
208 dst++;
209 }
210 }
211
212 if (!bytes)
213 return;
214
215 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
216 * allocated.
217 */
218 if (src_offset < PAYLOAD_OFFSET)
219 val = le32_to_cpu(__raw_readl(src));
220 else
221 val = __raw_readl(src);
222
223 dst_byteptr = (void *) dst;
224 src_byteptr = (void *) &val;
225 while (bytes > 0) {
226 *dst_byteptr = *src_byteptr;
227 dst_byteptr++;
228 src_byteptr++;
229 bytes--;
230 }
231}
232
233static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
234 u32 bytes)
235{
236 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
237 ndelay(90);
238 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
239}
240
241static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
242 __u32 const *src, u32 bytes)
243{
244 __u32 __iomem *dst;
245
246 dst = dst_base + dst_offset;
247
248 if (dst_offset < PAYLOAD_OFFSET) {
249 while (bytes >= 4) {
250 __raw_writel(cpu_to_le32(*src), dst);
251 bytes -= 4;
252 src++;
253 dst++;
254 }
255 } else {
256 while (bytes >= 4) {
257 __raw_writel(*src, dst);
258 bytes -= 4;
259 src++;
260 dst++;
261 }
262 }
263
264 if (!bytes)
265 return;
266 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
267 * extra bytes should not be read by the HW.
268 */
269
270 if (dst_offset < PAYLOAD_OFFSET)
271 __raw_writel(cpu_to_le32(*src), dst);
272 else
273 __raw_writel(*src, dst);
274}
275
276/*
277 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
278 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
279 */
280static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
281 struct ptd *ptd)
282{
283 reg_write32(base, HC_MEMORY_REG,
284 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
285 ndelay(90);
286 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
287 (void *) ptd, sizeof(*ptd));
288}
289
290static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
291 struct ptd *ptd)
292{
293 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
294 &ptd->dw1, 7*sizeof(ptd->dw1));
295 /* Make sure dw0 gets written last (after other dw's and after payload)
296 since it contains the enable bit */
297 wmb();
298 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
299 sizeof(ptd->dw0));
300}
301
302
303/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
304static void init_memory(struct isp1760_hcd *priv)
305{
306 int i, curr;
307 u32 payload_addr;
308
309 payload_addr = PAYLOAD_OFFSET;
310 for (i = 0; i < BLOCK_1_NUM; i++) {
311 priv->memory_pool[i].start = payload_addr;
312 priv->memory_pool[i].size = BLOCK_1_SIZE;
313 priv->memory_pool[i].free = 1;
314 payload_addr += priv->memory_pool[i].size;
315 }
316
317 curr = i;
318 for (i = 0; i < BLOCK_2_NUM; i++) {
319 priv->memory_pool[curr + i].start = payload_addr;
320 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
321 priv->memory_pool[curr + i].free = 1;
322 payload_addr += priv->memory_pool[curr + i].size;
323 }
324
325 curr = i;
326 for (i = 0; i < BLOCK_3_NUM; i++) {
327 priv->memory_pool[curr + i].start = payload_addr;
328 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
329 priv->memory_pool[curr + i].free = 1;
330 payload_addr += priv->memory_pool[curr + i].size;
331 }
332
333 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
334}
335
336static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
337{
338 struct isp1760_hcd *priv = hcd_to_priv(hcd);
339 int i;
340
341 WARN_ON(qtd->payload_addr);
342
343 if (!qtd->length)
344 return;
345
346 for (i = 0; i < BLOCKS; i++) {
347 if (priv->memory_pool[i].size >= qtd->length &&
348 priv->memory_pool[i].free) {
349 priv->memory_pool[i].free = 0;
350 qtd->payload_addr = priv->memory_pool[i].start;
351 return;
352 }
353 }
354}
355
356static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
357{
358 struct isp1760_hcd *priv = hcd_to_priv(hcd);
359 int i;
360
361 if (!qtd->payload_addr)
362 return;
363
364 for (i = 0; i < BLOCKS; i++) {
365 if (priv->memory_pool[i].start == qtd->payload_addr) {
366 WARN_ON(priv->memory_pool[i].free);
367 priv->memory_pool[i].free = 1;
368 qtd->payload_addr = 0;
369 return;
370 }
371 }
372
373 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
374 __func__, qtd->payload_addr);
375 WARN_ON(1);
376 qtd->payload_addr = 0;
377}
378
379static int handshake(struct usb_hcd *hcd, u32 reg,
380 u32 mask, u32 done, int usec)
381{
382 u32 result;
383
384 do {
385 result = reg_read32(hcd->regs, reg);
386 if (result == ~0)
387 return -ENODEV;
388 result &= mask;
389 if (result == done)
390 return 0;
391 udelay(1);
392 usec--;
393 } while (usec > 0);
394 return -ETIMEDOUT;
395}
396
397/* reset a non-running (STS_HALT == 1) controller */
398static int ehci_reset(struct usb_hcd *hcd)
399{
400 struct isp1760_hcd *priv = hcd_to_priv(hcd);
401
402 u32 command = reg_read32(hcd->regs, HC_USBCMD);
403
404 command |= CMD_RESET;
405 reg_write32(hcd->regs, HC_USBCMD, command);
406 hcd->state = HC_STATE_HALT;
407 priv->next_statechange = jiffies;
408
409 return handshake(hcd, HC_USBCMD, CMD_RESET, 0, 250 * 1000);
410}
411
412static struct isp1760_qh *qh_alloc(gfp_t flags)
413{
414 struct isp1760_qh *qh;
415
416 qh = kmem_cache_zalloc(qh_cachep, flags);
417 if (!qh)
418 return NULL;
419
420 INIT_LIST_HEAD(&qh->qh_list);
421 INIT_LIST_HEAD(&qh->qtd_list);
422 qh->slot = -1;
423
424 return qh;
425}
426
427static void qh_free(struct isp1760_qh *qh)
428{
429 WARN_ON(!list_empty(&qh->qtd_list));
430 WARN_ON(qh->slot > -1);
431 kmem_cache_free(qh_cachep, qh);
432}
433
434/* one-time init, only for memory state */
435static int priv_init(struct usb_hcd *hcd)
436{
437 struct isp1760_hcd *priv = hcd_to_priv(hcd);
438 u32 hcc_params;
439 int i;
440
441 spin_lock_init(&priv->lock);
442
443 for (i = 0; i < QH_END; i++)
444 INIT_LIST_HEAD(&priv->qh_list[i]);
445
446 /*
447 * hw default: 1K periodic list heads, one per frame.
448 * periodic_size can shrink by USBCMD update if hcc_params allows.
449 */
450 priv->periodic_size = DEFAULT_I_TDPS;
451
452 /* controllers may cache some of the periodic schedule ... */
453 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
454 /* full frame cache */
455 if (HCC_ISOC_CACHE(hcc_params))
456 priv->i_thresh = 8;
457 else /* N microframes cached */
458 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
459
460 return 0;
461}
462
463static int isp1760_hc_setup(struct usb_hcd *hcd)
464{
465 struct isp1760_hcd *priv = hcd_to_priv(hcd);
466 int result;
467 u32 scratch, hwmode;
468
469 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
470 /* Change bus pattern */
471 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
472 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
473 if (scratch != 0xdeadbabe) {
474 dev_err(hcd->self.controller, "Scratch test failed.\n");
475 return -ENODEV;
476 }
477
478 /*
479 * The RESET_HC bit in the SW_RESET register is supposed to reset the
480 * host controller without touching the CPU interface registers, but at
481 * least on the ISP1761 it seems to behave as the RESET_ALL bit and
482 * reset the whole device. We thus can't use it here, so let's reset
483 * the host controller through the EHCI USB Command register. The device
484 * has been reset in core code anyway, so this shouldn't matter.
485 */
486 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
487 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
488 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
489 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
490
491 result = ehci_reset(hcd);
492 if (result)
493 return result;
494
495 /* Step 11 passed */
496
497 /* ATL reset */
498 hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET;
499 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
500 mdelay(10);
501 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
502
503 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
504
505 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
506
507 return priv_init(hcd);
508}
509
510static u32 base_to_chip(u32 base)
511{
512 return ((base - 0x400) >> 3);
513}
514
515static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
516{
517 struct urb *urb;
518
519 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
520 return 1;
521
522 urb = qtd->urb;
523 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
524 return (qtd->urb != urb);
525}
526
527/* magic numbers that can affect system performance */
528#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
529#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
530#define EHCI_TUNE_RL_TT 0
531#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
532#define EHCI_TUNE_MULT_TT 1
533#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
534
535static void create_ptd_atl(struct isp1760_qh *qh,
536 struct isp1760_qtd *qtd, struct ptd *ptd)
537{
538 u32 maxpacket;
539 u32 multi;
540 u32 rl = RL_COUNTER;
541 u32 nak = NAK_COUNTER;
542
543 memset(ptd, 0, sizeof(*ptd));
544
545 /* according to 3.6.2, max packet len can not be > 0x400 */
546 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
547 usb_pipeout(qtd->urb->pipe));
548 multi = 1 + ((maxpacket >> 11) & 0x3);
549 maxpacket &= 0x7ff;
550
551 /* DW0 */
552 ptd->dw0 = DW0_VALID_BIT;
553 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
554 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
555 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
556
557 /* DW1 */
558 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
559 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
560 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
561
562 if (usb_pipebulk(qtd->urb->pipe))
563 ptd->dw1 |= DW1_TRANS_BULK;
564 else if (usb_pipeint(qtd->urb->pipe))
565 ptd->dw1 |= DW1_TRANS_INT;
566
567 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
568 /* split transaction */
569
570 ptd->dw1 |= DW1_TRANS_SPLIT;
571 if (qtd->urb->dev->speed == USB_SPEED_LOW)
572 ptd->dw1 |= DW1_SE_USB_LOSPEED;
573
574 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
575 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
576
577 /* SE bit for Split INT transfers */
578 if (usb_pipeint(qtd->urb->pipe) &&
579 (qtd->urb->dev->speed == USB_SPEED_LOW))
580 ptd->dw1 |= 2 << 16;
581
582 rl = 0;
583 nak = 0;
584 } else {
585 ptd->dw0 |= TO_DW0_MULTI(multi);
586 if (usb_pipecontrol(qtd->urb->pipe) ||
587 usb_pipebulk(qtd->urb->pipe))
588 ptd->dw3 |= TO_DW3_PING(qh->ping);
589 }
590 /* DW2 */
591 ptd->dw2 = 0;
592 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
593 ptd->dw2 |= TO_DW2_RL(rl);
594
595 /* DW3 */
596 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
597 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
598 if (usb_pipecontrol(qtd->urb->pipe)) {
599 if (qtd->data_buffer == qtd->urb->setup_packet)
600 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
601 else if (last_qtd_of_urb(qtd, qh))
602 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
603 }
604
605 ptd->dw3 |= DW3_ACTIVE_BIT;
606 /* Cerr */
607 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
608}
609
610static void transform_add_int(struct isp1760_qh *qh,
611 struct isp1760_qtd *qtd, struct ptd *ptd)
612{
613 u32 usof;
614 u32 period;
615
616 /*
617 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
618 * the algorithm from the original Philips driver code, which was
619 * pretty much used in this driver before as well, is quite horrendous
620 * and, i believe, incorrect. The code below follows the datasheet and
621 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
622 * more reliable this way (fingers crossed...).
623 */
624
625 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
626 /* urb->interval is in units of microframes (1/8 ms) */
627 period = qtd->urb->interval >> 3;
628
629 if (qtd->urb->interval > 4)
630 usof = 0x01; /* One bit set =>
631 interval 1 ms * uFrame-match */
632 else if (qtd->urb->interval > 2)
633 usof = 0x22; /* Two bits set => interval 1/2 ms */
634 else if (qtd->urb->interval > 1)
635 usof = 0x55; /* Four bits set => interval 1/4 ms */
636 else
637 usof = 0xff; /* All bits set => interval 1/8 ms */
638 } else {
639 /* urb->interval is in units of frames (1 ms) */
640 period = qtd->urb->interval;
641 usof = 0x0f; /* Execute Start Split on any of the
642 four first uFrames */
643
644 /*
645 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
646 * complete split needs to be sent. Valid only for IN." Also,
647 * "All bits can be set to one for every transfer." (p 82,
648 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
649 * that number come from? 0xff seems to work fine...
650 */
651 /* ptd->dw5 = 0x1c; */
652 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
653 }
654
655 period = period >> 1;/* Ensure equal or shorter period than requested */
656 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
657
658 ptd->dw2 |= period;
659 ptd->dw4 = usof;
660}
661
662static void create_ptd_int(struct isp1760_qh *qh,
663 struct isp1760_qtd *qtd, struct ptd *ptd)
664{
665 create_ptd_atl(qh, qtd, ptd);
666 transform_add_int(qh, qtd, ptd);
667}
668
669static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
670__releases(priv->lock)
671__acquires(priv->lock)
672{
673 struct isp1760_hcd *priv = hcd_to_priv(hcd);
674
675 if (!urb->unlinked) {
676 if (urb->status == -EINPROGRESS)
677 urb->status = 0;
678 }
679
680 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
681 void *ptr;
682 for (ptr = urb->transfer_buffer;
683 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
684 ptr += PAGE_SIZE)
685 flush_dcache_page(virt_to_page(ptr));
686 }
687
688 /* complete() can reenter this HCD */
689 usb_hcd_unlink_urb_from_ep(hcd, urb);
690 spin_unlock(&priv->lock);
691 usb_hcd_giveback_urb(hcd, urb, urb->status);
692 spin_lock(&priv->lock);
693}
694
695static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
696 u8 packet_type)
697{
698 struct isp1760_qtd *qtd;
699
700 qtd = kmem_cache_zalloc(qtd_cachep, flags);
701 if (!qtd)
702 return NULL;
703
704 INIT_LIST_HEAD(&qtd->qtd_list);
705 qtd->urb = urb;
706 qtd->packet_type = packet_type;
707 qtd->status = QTD_ENQUEUED;
708 qtd->actual_length = 0;
709
710 return qtd;
711}
712
713static void qtd_free(struct isp1760_qtd *qtd)
714{
715 WARN_ON(qtd->payload_addr);
716 kmem_cache_free(qtd_cachep, qtd);
717}
718
719static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
720 struct isp1760_slotinfo *slots,
721 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
722 struct ptd *ptd)
723{
724 struct isp1760_hcd *priv = hcd_to_priv(hcd);
725 int skip_map;
726
727 WARN_ON((slot < 0) || (slot > 31));
728 WARN_ON(qtd->length && !qtd->payload_addr);
729 WARN_ON(slots[slot].qtd);
730 WARN_ON(slots[slot].qh);
731 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
732
733 /* Make sure done map has not triggered from some unlinked transfer */
734 if (ptd_offset == ATL_PTD_OFFSET) {
735 priv->atl_done_map |= reg_read32(hcd->regs,
736 HC_ATL_PTD_DONEMAP_REG);
737 priv->atl_done_map &= ~(1 << slot);
738 } else {
739 priv->int_done_map |= reg_read32(hcd->regs,
740 HC_INT_PTD_DONEMAP_REG);
741 priv->int_done_map &= ~(1 << slot);
742 }
743
744 qh->slot = slot;
745 qtd->status = QTD_XFER_STARTED;
746 slots[slot].timestamp = jiffies;
747 slots[slot].qtd = qtd;
748 slots[slot].qh = qh;
749 ptd_write(hcd->regs, ptd_offset, slot, ptd);
750
751 if (ptd_offset == ATL_PTD_OFFSET) {
752 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
753 skip_map &= ~(1 << qh->slot);
754 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
755 } else {
756 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
757 skip_map &= ~(1 << qh->slot);
758 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
759 }
760}
761
762static int is_short_bulk(struct isp1760_qtd *qtd)
763{
764 return (usb_pipebulk(qtd->urb->pipe) &&
765 (qtd->actual_length < qtd->length));
766}
767
768static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
769 struct list_head *urb_list)
770{
771 int last_qtd;
772 struct isp1760_qtd *qtd, *qtd_next;
773 struct urb_listitem *urb_listitem;
774
775 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
776 if (qtd->status < QTD_XFER_COMPLETE)
777 break;
778
779 last_qtd = last_qtd_of_urb(qtd, qh);
780
781 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
782 qtd_next->status = QTD_RETIRE;
783
784 if (qtd->status == QTD_XFER_COMPLETE) {
785 if (qtd->actual_length) {
786 switch (qtd->packet_type) {
787 case IN_PID:
788 mem_reads8(hcd->regs, qtd->payload_addr,
789 qtd->data_buffer,
790 qtd->actual_length);
791 fallthrough;
792 case OUT_PID:
793 qtd->urb->actual_length +=
794 qtd->actual_length;
795 fallthrough;
796 case SETUP_PID:
797 break;
798 }
799 }
800
801 if (is_short_bulk(qtd)) {
802 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
803 qtd->urb->status = -EREMOTEIO;
804 if (!last_qtd)
805 qtd_next->status = QTD_RETIRE;
806 }
807 }
808
809 if (qtd->payload_addr)
810 free_mem(hcd, qtd);
811
812 if (last_qtd) {
813 if ((qtd->status == QTD_RETIRE) &&
814 (qtd->urb->status == -EINPROGRESS))
815 qtd->urb->status = -EPIPE;
816 /* Defer calling of urb_done() since it releases lock */
817 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
818 GFP_ATOMIC);
819 if (unlikely(!urb_listitem))
820 break; /* Try again on next call */
821 urb_listitem->urb = qtd->urb;
822 list_add_tail(&urb_listitem->urb_list, urb_list);
823 }
824
825 list_del(&qtd->qtd_list);
826 qtd_free(qtd);
827 }
828}
829
830#define ENQUEUE_DEPTH 2
831static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
832{
833 struct isp1760_hcd *priv = hcd_to_priv(hcd);
834 int ptd_offset;
835 struct isp1760_slotinfo *slots;
836 int curr_slot, free_slot;
837 int n;
838 struct ptd ptd;
839 struct isp1760_qtd *qtd;
840
841 if (unlikely(list_empty(&qh->qtd_list))) {
842 WARN_ON(1);
843 return;
844 }
845
846 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
847 if (qh->tt_buffer_dirty)
848 return;
849
850 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
851 qtd_list)->urb->pipe)) {
852 ptd_offset = INT_PTD_OFFSET;
853 slots = priv->int_slots;
854 } else {
855 ptd_offset = ATL_PTD_OFFSET;
856 slots = priv->atl_slots;
857 }
858
859 free_slot = -1;
860 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
861 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
862 free_slot = curr_slot;
863 if (slots[curr_slot].qh == qh)
864 break;
865 }
866
867 n = 0;
868 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
869 if (qtd->status == QTD_ENQUEUED) {
870 WARN_ON(qtd->payload_addr);
871 alloc_mem(hcd, qtd);
872 if ((qtd->length) && (!qtd->payload_addr))
873 break;
874
875 if ((qtd->length) &&
876 ((qtd->packet_type == SETUP_PID) ||
877 (qtd->packet_type == OUT_PID))) {
878 mem_writes8(hcd->regs, qtd->payload_addr,
879 qtd->data_buffer, qtd->length);
880 }
881
882 qtd->status = QTD_PAYLOAD_ALLOC;
883 }
884
885 if (qtd->status == QTD_PAYLOAD_ALLOC) {
886/*
887 if ((curr_slot > 31) && (free_slot == -1))
888 dev_dbg(hcd->self.controller, "%s: No slot "
889 "available for transfer\n", __func__);
890*/
891 /* Start xfer for this endpoint if not already done */
892 if ((curr_slot > 31) && (free_slot > -1)) {
893 if (usb_pipeint(qtd->urb->pipe))
894 create_ptd_int(qh, qtd, &ptd);
895 else
896 create_ptd_atl(qh, qtd, &ptd);
897
898 start_bus_transfer(hcd, ptd_offset, free_slot,
899 slots, qtd, qh, &ptd);
900 curr_slot = free_slot;
901 }
902
903 n++;
904 if (n >= ENQUEUE_DEPTH)
905 break;
906 }
907 }
908}
909
910static void schedule_ptds(struct usb_hcd *hcd)
911{
912 struct isp1760_hcd *priv;
913 struct isp1760_qh *qh, *qh_next;
914 struct list_head *ep_queue;
915 LIST_HEAD(urb_list);
916 struct urb_listitem *urb_listitem, *urb_listitem_next;
917 int i;
918
919 if (!hcd) {
920 WARN_ON(1);
921 return;
922 }
923
924 priv = hcd_to_priv(hcd);
925
926 /*
927 * check finished/retired xfers, transfer payloads, call urb_done()
928 */
929 for (i = 0; i < QH_END; i++) {
930 ep_queue = &priv->qh_list[i];
931 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
932 collect_qtds(hcd, qh, &urb_list);
933 if (list_empty(&qh->qtd_list))
934 list_del(&qh->qh_list);
935 }
936 }
937
938 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
939 urb_list) {
940 isp1760_urb_done(hcd, urb_listitem->urb);
941 kmem_cache_free(urb_listitem_cachep, urb_listitem);
942 }
943
944 /*
945 * Schedule packets for transfer.
946 *
947 * According to USB2.0 specification:
948 *
949 * 1st prio: interrupt xfers, up to 80 % of bandwidth
950 * 2nd prio: control xfers
951 * 3rd prio: bulk xfers
952 *
953 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
954 * is very unclear on how to prioritize traffic):
955 *
956 * 1) Enqueue any queued control transfers, as long as payload chip mem
957 * and PTD ATL slots are available.
958 * 2) Enqueue any queued INT transfers, as long as payload chip mem
959 * and PTD INT slots are available.
960 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
961 * and PTD ATL slots are available.
962 *
963 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
964 * conservation of chip mem and performance.
965 *
966 * I'm sure this scheme could be improved upon!
967 */
968 for (i = 0; i < QH_END; i++) {
969 ep_queue = &priv->qh_list[i];
970 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
971 enqueue_qtds(hcd, qh);
972 }
973}
974
975#define PTD_STATE_QTD_DONE 1
976#define PTD_STATE_QTD_RELOAD 2
977#define PTD_STATE_URB_RETIRE 3
978
979static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
980 struct urb *urb)
981{
982 __dw dw4;
983 int i;
984
985 dw4 = ptd->dw4;
986 dw4 >>= 8;
987
988 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
989 need to handle these errors? Is it done in hardware? */
990
991 if (ptd->dw3 & DW3_HALT_BIT) {
992
993 urb->status = -EPROTO; /* Default unknown error */
994
995 for (i = 0; i < 8; i++) {
996 switch (dw4 & 0x7) {
997 case INT_UNDERRUN:
998 dev_dbg(hcd->self.controller, "%s: underrun "
999 "during uFrame %d\n",
1000 __func__, i);
1001 urb->status = -ECOMM; /* Could not write data */
1002 break;
1003 case INT_EXACT:
1004 dev_dbg(hcd->self.controller, "%s: transaction "
1005 "error during uFrame %d\n",
1006 __func__, i);
1007 urb->status = -EPROTO; /* timeout, bad CRC, PID
1008 error etc. */
1009 break;
1010 case INT_BABBLE:
1011 dev_dbg(hcd->self.controller, "%s: babble "
1012 "error during uFrame %d\n",
1013 __func__, i);
1014 urb->status = -EOVERFLOW;
1015 break;
1016 }
1017 dw4 >>= 3;
1018 }
1019
1020 return PTD_STATE_URB_RETIRE;
1021 }
1022
1023 return PTD_STATE_QTD_DONE;
1024}
1025
1026static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1027 struct urb *urb)
1028{
1029 WARN_ON(!ptd);
1030 if (ptd->dw3 & DW3_HALT_BIT) {
1031 if (ptd->dw3 & DW3_BABBLE_BIT)
1032 urb->status = -EOVERFLOW;
1033 else if (FROM_DW3_CERR(ptd->dw3))
1034 urb->status = -EPIPE; /* Stall */
1035 else
1036 urb->status = -EPROTO; /* Unknown */
1037/*
1038 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1039 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1040 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1041 __func__,
1042 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1043 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1044*/
1045 return PTD_STATE_URB_RETIRE;
1046 }
1047
1048 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1049 /* Transfer Error, *but* active and no HALT -> reload */
1050 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1051 return PTD_STATE_QTD_RELOAD;
1052 }
1053
1054 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1055 /*
1056 * NAKs are handled in HW by the chip. Usually if the
1057 * device is not able to send data fast enough.
1058 * This happens mostly on slower hardware.
1059 */
1060 return PTD_STATE_QTD_RELOAD;
1061 }
1062
1063 return PTD_STATE_QTD_DONE;
1064}
1065
1066static void handle_done_ptds(struct usb_hcd *hcd)
1067{
1068 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1069 struct ptd ptd;
1070 struct isp1760_qh *qh;
1071 int slot;
1072 int state;
1073 struct isp1760_slotinfo *slots;
1074 u32 ptd_offset;
1075 struct isp1760_qtd *qtd;
1076 int modified;
1077 int skip_map;
1078
1079 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1080 priv->int_done_map &= ~skip_map;
1081 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1082 priv->atl_done_map &= ~skip_map;
1083
1084 modified = priv->int_done_map || priv->atl_done_map;
1085
1086 while (priv->int_done_map || priv->atl_done_map) {
1087 if (priv->int_done_map) {
1088 /* INT ptd */
1089 slot = __ffs(priv->int_done_map);
1090 priv->int_done_map &= ~(1 << slot);
1091 slots = priv->int_slots;
1092 /* This should not trigger, and could be removed if
1093 noone have any problems with it triggering: */
1094 if (!slots[slot].qh) {
1095 WARN_ON(1);
1096 continue;
1097 }
1098 ptd_offset = INT_PTD_OFFSET;
1099 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1100 state = check_int_transfer(hcd, &ptd,
1101 slots[slot].qtd->urb);
1102 } else {
1103 /* ATL ptd */
1104 slot = __ffs(priv->atl_done_map);
1105 priv->atl_done_map &= ~(1 << slot);
1106 slots = priv->atl_slots;
1107 /* This should not trigger, and could be removed if
1108 noone have any problems with it triggering: */
1109 if (!slots[slot].qh) {
1110 WARN_ON(1);
1111 continue;
1112 }
1113 ptd_offset = ATL_PTD_OFFSET;
1114 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1115 state = check_atl_transfer(hcd, &ptd,
1116 slots[slot].qtd->urb);
1117 }
1118
1119 qtd = slots[slot].qtd;
1120 slots[slot].qtd = NULL;
1121 qh = slots[slot].qh;
1122 slots[slot].qh = NULL;
1123 qh->slot = -1;
1124
1125 WARN_ON(qtd->status != QTD_XFER_STARTED);
1126
1127 switch (state) {
1128 case PTD_STATE_QTD_DONE:
1129 if ((usb_pipeint(qtd->urb->pipe)) &&
1130 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1131 qtd->actual_length =
1132 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1133 else
1134 qtd->actual_length =
1135 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1136
1137 qtd->status = QTD_XFER_COMPLETE;
1138 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1139 is_short_bulk(qtd))
1140 qtd = NULL;
1141 else
1142 qtd = list_entry(qtd->qtd_list.next,
1143 typeof(*qtd), qtd_list);
1144
1145 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1146 qh->ping = FROM_DW3_PING(ptd.dw3);
1147 break;
1148
1149 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1150 qtd->status = QTD_PAYLOAD_ALLOC;
1151 ptd.dw0 |= DW0_VALID_BIT;
1152 /* RL counter = ERR counter */
1153 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1154 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1155 ptd.dw3 &= ~TO_DW3_CERR(3);
1156 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1157 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1158 qh->ping = FROM_DW3_PING(ptd.dw3);
1159 break;
1160
1161 case PTD_STATE_URB_RETIRE:
1162 qtd->status = QTD_RETIRE;
1163 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1164 (qtd->urb->status != -EPIPE) &&
1165 (qtd->urb->status != -EREMOTEIO)) {
1166 qh->tt_buffer_dirty = 1;
1167 if (usb_hub_clear_tt_buffer(qtd->urb))
1168 /* Clear failed; let's hope things work
1169 anyway */
1170 qh->tt_buffer_dirty = 0;
1171 }
1172 qtd = NULL;
1173 qh->toggle = 0;
1174 qh->ping = 0;
1175 break;
1176
1177 default:
1178 WARN_ON(1);
1179 continue;
1180 }
1181
1182 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1183 if (slots == priv->int_slots) {
1184 if (state == PTD_STATE_QTD_RELOAD)
1185 dev_err(hcd->self.controller,
1186 "%s: PTD_STATE_QTD_RELOAD on "
1187 "interrupt packet\n", __func__);
1188 if (state != PTD_STATE_QTD_RELOAD)
1189 create_ptd_int(qh, qtd, &ptd);
1190 } else {
1191 if (state != PTD_STATE_QTD_RELOAD)
1192 create_ptd_atl(qh, qtd, &ptd);
1193 }
1194
1195 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1196 qh, &ptd);
1197 }
1198 }
1199
1200 if (modified)
1201 schedule_ptds(hcd);
1202}
1203
1204static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1205{
1206 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1207 u32 imask;
1208 irqreturn_t irqret = IRQ_NONE;
1209
1210 spin_lock(&priv->lock);
1211
1212 if (!(hcd->state & HC_STATE_RUNNING))
1213 goto leave;
1214
1215 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1216 if (unlikely(!imask))
1217 goto leave;
1218 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1219
1220 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1221 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1222
1223 handle_done_ptds(hcd);
1224
1225 irqret = IRQ_HANDLED;
1226leave:
1227 spin_unlock(&priv->lock);
1228
1229 return irqret;
1230}
1231
1232/*
1233 * Workaround for problem described in chip errata 2:
1234 *
1235 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1236 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1237 * ATL done interrupts (the "instead of" might be important since it seems
1238 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1239 * to set the PTD's done bit in addition to not generating an interrupt!).
1240 *
1241 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1242 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1243 *
1244 * If we use SOF interrupts only, we get latency between ptd completion and the
1245 * actual handling. This is very noticeable in testusb runs which takes several
1246 * minutes longer without ATL interrupts.
1247 *
1248 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1249 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1250 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1251 * completed and its done map bit is set.
1252 *
1253 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1254 * not to cause too much lag when this HW bug occurs, while still hopefully
1255 * ensuring that the check does not falsely trigger.
1256 */
1257#define SLOT_TIMEOUT 300
1258#define SLOT_CHECK_PERIOD 200
1259static struct timer_list errata2_timer;
1260static struct usb_hcd *errata2_timer_hcd;
1261
1262static void errata2_function(struct timer_list *unused)
1263{
1264 struct usb_hcd *hcd = errata2_timer_hcd;
1265 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1266 int slot;
1267 struct ptd ptd;
1268 unsigned long spinflags;
1269
1270 spin_lock_irqsave(&priv->lock, spinflags);
1271
1272 for (slot = 0; slot < 32; slot++)
1273 if (priv->atl_slots[slot].qh && time_after(jiffies,
1274 priv->atl_slots[slot].timestamp +
1275 msecs_to_jiffies(SLOT_TIMEOUT))) {
1276 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1277 if (!FROM_DW0_VALID(ptd.dw0) &&
1278 !FROM_DW3_ACTIVE(ptd.dw3))
1279 priv->atl_done_map |= 1 << slot;
1280 }
1281
1282 if (priv->atl_done_map)
1283 handle_done_ptds(hcd);
1284
1285 spin_unlock_irqrestore(&priv->lock, spinflags);
1286
1287 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1288 add_timer(&errata2_timer);
1289}
1290
1291static int isp1760_run(struct usb_hcd *hcd)
1292{
1293 int retval;
1294 u32 temp;
1295 u32 command;
1296 u32 chipid;
1297
1298 hcd->uses_new_polling = 1;
1299
1300 hcd->state = HC_STATE_RUNNING;
1301
1302 /* Set PTD interrupt AND & OR maps */
1303 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1304 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1305 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1306 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1307 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1308 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1309 /* step 23 passed */
1310
1311 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1312 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1313
1314 command = reg_read32(hcd->regs, HC_USBCMD);
1315 command &= ~(CMD_LRESET|CMD_RESET);
1316 command |= CMD_RUN;
1317 reg_write32(hcd->regs, HC_USBCMD, command);
1318
1319 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1320 if (retval)
1321 return retval;
1322
1323 /*
1324 * XXX
1325 * Spec says to write FLAG_CF as last config action, priv code grabs
1326 * the semaphore while doing so.
1327 */
1328 down_write(&ehci_cf_port_reset_rwsem);
1329 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1330
1331 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1332 up_write(&ehci_cf_port_reset_rwsem);
1333 if (retval)
1334 return retval;
1335
1336 errata2_timer_hcd = hcd;
1337 timer_setup(&errata2_timer, errata2_function, 0);
1338 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1339 add_timer(&errata2_timer);
1340
1341 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1342 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1343 chipid & 0xffff, chipid >> 16);
1344
1345 /* PTD Register Init Part 2, Step 28 */
1346
1347 /* Setup registers controlling PTD checking */
1348 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1349 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1350 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1351 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1352 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1353 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1354 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1355 ATL_BUF_FILL | INT_BUF_FILL);
1356
1357 /* GRR this is run-once init(), being done every time the HC starts.
1358 * So long as they're part of class devices, we can't do it init()
1359 * since the class device isn't created that early.
1360 */
1361 return 0;
1362}
1363
1364static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1365{
1366 qtd->data_buffer = databuffer;
1367
1368 if (len > MAX_PAYLOAD_SIZE)
1369 len = MAX_PAYLOAD_SIZE;
1370 qtd->length = len;
1371
1372 return qtd->length;
1373}
1374
1375static void qtd_list_free(struct list_head *qtd_list)
1376{
1377 struct isp1760_qtd *qtd, *qtd_next;
1378
1379 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1380 list_del(&qtd->qtd_list);
1381 qtd_free(qtd);
1382 }
1383}
1384
1385/*
1386 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1387 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1388 */
1389#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1390static void packetize_urb(struct usb_hcd *hcd,
1391 struct urb *urb, struct list_head *head, gfp_t flags)
1392{
1393 struct isp1760_qtd *qtd;
1394 void *buf;
1395 int len, maxpacketsize;
1396 u8 packet_type;
1397
1398 /*
1399 * URBs map to sequences of QTDs: one logical transaction
1400 */
1401
1402 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1403 /* XXX This looks like usb storage / SCSI bug */
1404 dev_err(hcd->self.controller,
1405 "buf is null, dma is %08lx len is %d\n",
1406 (long unsigned)urb->transfer_dma,
1407 urb->transfer_buffer_length);
1408 WARN_ON(1);
1409 }
1410
1411 if (usb_pipein(urb->pipe))
1412 packet_type = IN_PID;
1413 else
1414 packet_type = OUT_PID;
1415
1416 if (usb_pipecontrol(urb->pipe)) {
1417 qtd = qtd_alloc(flags, urb, SETUP_PID);
1418 if (!qtd)
1419 goto cleanup;
1420 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1421 list_add_tail(&qtd->qtd_list, head);
1422
1423 /* for zero length DATA stages, STATUS is always IN */
1424 if (urb->transfer_buffer_length == 0)
1425 packet_type = IN_PID;
1426 }
1427
1428 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1429 usb_pipeout(urb->pipe)));
1430
1431 /*
1432 * buffer gets wrapped in one or more qtds;
1433 * last one may be "short" (including zero len)
1434 * and may serve as a control status ack
1435 */
1436 buf = urb->transfer_buffer;
1437 len = urb->transfer_buffer_length;
1438
1439 for (;;) {
1440 int this_qtd_len;
1441
1442 qtd = qtd_alloc(flags, urb, packet_type);
1443 if (!qtd)
1444 goto cleanup;
1445 this_qtd_len = qtd_fill(qtd, buf, len);
1446 list_add_tail(&qtd->qtd_list, head);
1447
1448 len -= this_qtd_len;
1449 buf += this_qtd_len;
1450
1451 if (len <= 0)
1452 break;
1453 }
1454
1455 /*
1456 * control requests may need a terminating data "status" ack;
1457 * bulk ones may need a terminating short packet (zero length).
1458 */
1459 if (urb->transfer_buffer_length != 0) {
1460 int one_more = 0;
1461
1462 if (usb_pipecontrol(urb->pipe)) {
1463 one_more = 1;
1464 if (packet_type == IN_PID)
1465 packet_type = OUT_PID;
1466 else
1467 packet_type = IN_PID;
1468 } else if (usb_pipebulk(urb->pipe)
1469 && (urb->transfer_flags & URB_ZERO_PACKET)
1470 && !(urb->transfer_buffer_length %
1471 maxpacketsize)) {
1472 one_more = 1;
1473 }
1474 if (one_more) {
1475 qtd = qtd_alloc(flags, urb, packet_type);
1476 if (!qtd)
1477 goto cleanup;
1478
1479 /* never any data in such packets */
1480 qtd_fill(qtd, NULL, 0);
1481 list_add_tail(&qtd->qtd_list, head);
1482 }
1483 }
1484
1485 return;
1486
1487cleanup:
1488 qtd_list_free(head);
1489}
1490
1491static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1492 gfp_t mem_flags)
1493{
1494 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1495 struct list_head *ep_queue;
1496 struct isp1760_qh *qh, *qhit;
1497 unsigned long spinflags;
1498 LIST_HEAD(new_qtds);
1499 int retval;
1500 int qh_in_queue;
1501
1502 switch (usb_pipetype(urb->pipe)) {
1503 case PIPE_CONTROL:
1504 ep_queue = &priv->qh_list[QH_CONTROL];
1505 break;
1506 case PIPE_BULK:
1507 ep_queue = &priv->qh_list[QH_BULK];
1508 break;
1509 case PIPE_INTERRUPT:
1510 if (urb->interval < 0)
1511 return -EINVAL;
1512 /* FIXME: Check bandwidth */
1513 ep_queue = &priv->qh_list[QH_INTERRUPT];
1514 break;
1515 case PIPE_ISOCHRONOUS:
1516 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1517 "not yet supported\n",
1518 __func__);
1519 return -EPIPE;
1520 default:
1521 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1522 __func__);
1523 return -EPIPE;
1524 }
1525
1526 if (usb_pipein(urb->pipe))
1527 urb->actual_length = 0;
1528
1529 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1530 if (list_empty(&new_qtds))
1531 return -ENOMEM;
1532
1533 retval = 0;
1534 spin_lock_irqsave(&priv->lock, spinflags);
1535
1536 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1537 retval = -ESHUTDOWN;
1538 qtd_list_free(&new_qtds);
1539 goto out;
1540 }
1541 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1542 if (retval) {
1543 qtd_list_free(&new_qtds);
1544 goto out;
1545 }
1546
1547 qh = urb->ep->hcpriv;
1548 if (qh) {
1549 qh_in_queue = 0;
1550 list_for_each_entry(qhit, ep_queue, qh_list) {
1551 if (qhit == qh) {
1552 qh_in_queue = 1;
1553 break;
1554 }
1555 }
1556 if (!qh_in_queue)
1557 list_add_tail(&qh->qh_list, ep_queue);
1558 } else {
1559 qh = qh_alloc(GFP_ATOMIC);
1560 if (!qh) {
1561 retval = -ENOMEM;
1562 usb_hcd_unlink_urb_from_ep(hcd, urb);
1563 qtd_list_free(&new_qtds);
1564 goto out;
1565 }
1566 list_add_tail(&qh->qh_list, ep_queue);
1567 urb->ep->hcpriv = qh;
1568 }
1569
1570 list_splice_tail(&new_qtds, &qh->qtd_list);
1571 schedule_ptds(hcd);
1572
1573out:
1574 spin_unlock_irqrestore(&priv->lock, spinflags);
1575 return retval;
1576}
1577
1578static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1579 struct isp1760_qh *qh)
1580{
1581 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1582 int skip_map;
1583
1584 WARN_ON(qh->slot == -1);
1585
1586 /* We need to forcefully reclaim the slot since some transfers never
1587 return, e.g. interrupt transfers and NAKed bulk transfers. */
1588 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1589 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1590 skip_map |= (1 << qh->slot);
1591 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1592 priv->atl_slots[qh->slot].qh = NULL;
1593 priv->atl_slots[qh->slot].qtd = NULL;
1594 } else {
1595 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1596 skip_map |= (1 << qh->slot);
1597 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1598 priv->int_slots[qh->slot].qh = NULL;
1599 priv->int_slots[qh->slot].qtd = NULL;
1600 }
1601
1602 qh->slot = -1;
1603}
1604
1605/*
1606 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1607 * any active transfer belonging to the urb in the process.
1608 */
1609static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1610 struct isp1760_qtd *qtd)
1611{
1612 struct urb *urb;
1613 int urb_was_running;
1614
1615 urb = qtd->urb;
1616 urb_was_running = 0;
1617 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1618 if (qtd->urb != urb)
1619 break;
1620
1621 if (qtd->status >= QTD_XFER_STARTED)
1622 urb_was_running = 1;
1623 if (last_qtd_of_urb(qtd, qh) &&
1624 (qtd->status >= QTD_XFER_COMPLETE))
1625 urb_was_running = 0;
1626
1627 if (qtd->status == QTD_XFER_STARTED)
1628 kill_transfer(hcd, urb, qh);
1629 qtd->status = QTD_RETIRE;
1630 }
1631
1632 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1633 qh->tt_buffer_dirty = 1;
1634 if (usb_hub_clear_tt_buffer(urb))
1635 /* Clear failed; let's hope things work anyway */
1636 qh->tt_buffer_dirty = 0;
1637 }
1638}
1639
1640static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1641 int status)
1642{
1643 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1644 unsigned long spinflags;
1645 struct isp1760_qh *qh;
1646 struct isp1760_qtd *qtd;
1647 int retval = 0;
1648
1649 spin_lock_irqsave(&priv->lock, spinflags);
1650 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1651 if (retval)
1652 goto out;
1653
1654 qh = urb->ep->hcpriv;
1655 if (!qh) {
1656 retval = -EINVAL;
1657 goto out;
1658 }
1659
1660 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1661 if (qtd->urb == urb) {
1662 dequeue_urb_from_qtd(hcd, qh, qtd);
1663 list_move(&qtd->qtd_list, &qh->qtd_list);
1664 break;
1665 }
1666
1667 urb->status = status;
1668 schedule_ptds(hcd);
1669
1670out:
1671 spin_unlock_irqrestore(&priv->lock, spinflags);
1672 return retval;
1673}
1674
1675static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1676 struct usb_host_endpoint *ep)
1677{
1678 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1679 unsigned long spinflags;
1680 struct isp1760_qh *qh, *qh_iter;
1681 int i;
1682
1683 spin_lock_irqsave(&priv->lock, spinflags);
1684
1685 qh = ep->hcpriv;
1686 if (!qh)
1687 goto out;
1688
1689 WARN_ON(!list_empty(&qh->qtd_list));
1690
1691 for (i = 0; i < QH_END; i++)
1692 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1693 if (qh_iter == qh) {
1694 list_del(&qh_iter->qh_list);
1695 i = QH_END;
1696 break;
1697 }
1698 qh_free(qh);
1699 ep->hcpriv = NULL;
1700
1701 schedule_ptds(hcd);
1702
1703out:
1704 spin_unlock_irqrestore(&priv->lock, spinflags);
1705}
1706
1707static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1708{
1709 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1710 u32 temp, status = 0;
1711 u32 mask;
1712 int retval = 1;
1713 unsigned long flags;
1714
1715 /* if !PM, root hub timers won't get shut down ... */
1716 if (!HC_IS_RUNNING(hcd->state))
1717 return 0;
1718
1719 /* init status to no-changes */
1720 buf[0] = 0;
1721 mask = PORT_CSC;
1722
1723 spin_lock_irqsave(&priv->lock, flags);
1724 temp = reg_read32(hcd->regs, HC_PORTSC1);
1725
1726 if (temp & PORT_OWNER) {
1727 if (temp & PORT_CSC) {
1728 temp &= ~PORT_CSC;
1729 reg_write32(hcd->regs, HC_PORTSC1, temp);
1730 goto done;
1731 }
1732 }
1733
1734 /*
1735 * Return status information even for ports with OWNER set.
1736 * Otherwise hub_wq wouldn't see the disconnect event when a
1737 * high-speed device is switched over to the companion
1738 * controller by the user.
1739 */
1740
1741 if ((temp & mask) != 0
1742 || ((temp & PORT_RESUME) != 0
1743 && time_after_eq(jiffies,
1744 priv->reset_done))) {
1745 buf [0] |= 1 << (0 + 1);
1746 status = STS_PCD;
1747 }
1748 /* FIXME autosuspend idle root hubs */
1749done:
1750 spin_unlock_irqrestore(&priv->lock, flags);
1751 return status ? retval : 0;
1752}
1753
1754static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1755 struct usb_hub_descriptor *desc)
1756{
1757 int ports = HCS_N_PORTS(priv->hcs_params);
1758 u16 temp;
1759
1760 desc->bDescriptorType = USB_DT_HUB;
1761 /* priv 1.0, 2.3.9 says 20ms max */
1762 desc->bPwrOn2PwrGood = 10;
1763 desc->bHubContrCurrent = 0;
1764
1765 desc->bNbrPorts = ports;
1766 temp = 1 + (ports / 8);
1767 desc->bDescLength = 7 + 2 * temp;
1768
1769 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1770 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1771 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1772
1773 /* per-port overcurrent reporting */
1774 temp = HUB_CHAR_INDV_PORT_OCPM;
1775 if (HCS_PPC(priv->hcs_params))
1776 /* per-port power control */
1777 temp |= HUB_CHAR_INDV_PORT_LPSM;
1778 else
1779 /* no power switching */
1780 temp |= HUB_CHAR_NO_LPSM;
1781 desc->wHubCharacteristics = cpu_to_le16(temp);
1782}
1783
1784#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1785
1786static int check_reset_complete(struct usb_hcd *hcd, int index,
1787 int port_status)
1788{
1789 if (!(port_status & PORT_CONNECT))
1790 return port_status;
1791
1792 /* if reset finished and it's still not enabled -- handoff */
1793 if (!(port_status & PORT_PE)) {
1794
1795 dev_info(hcd->self.controller,
1796 "port %d full speed --> companion\n",
1797 index + 1);
1798
1799 port_status |= PORT_OWNER;
1800 port_status &= ~PORT_RWC_BITS;
1801 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1802
1803 } else
1804 dev_info(hcd->self.controller, "port %d high speed\n",
1805 index + 1);
1806
1807 return port_status;
1808}
1809
1810static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1811 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1812{
1813 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1814 int ports = HCS_N_PORTS(priv->hcs_params);
1815 u32 temp, status;
1816 unsigned long flags;
1817 int retval = 0;
1818
1819 /*
1820 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1821 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1822 * (track current state ourselves) ... blink for diagnostics,
1823 * power, "this is the one", etc. EHCI spec supports this.
1824 */
1825
1826 spin_lock_irqsave(&priv->lock, flags);
1827 switch (typeReq) {
1828 case ClearHubFeature:
1829 switch (wValue) {
1830 case C_HUB_LOCAL_POWER:
1831 case C_HUB_OVER_CURRENT:
1832 /* no hub-wide feature/status flags */
1833 break;
1834 default:
1835 goto error;
1836 }
1837 break;
1838 case ClearPortFeature:
1839 if (!wIndex || wIndex > ports)
1840 goto error;
1841 wIndex--;
1842 temp = reg_read32(hcd->regs, HC_PORTSC1);
1843
1844 /*
1845 * Even if OWNER is set, so the port is owned by the
1846 * companion controller, hub_wq needs to be able to clear
1847 * the port-change status bits (especially
1848 * USB_PORT_STAT_C_CONNECTION).
1849 */
1850
1851 switch (wValue) {
1852 case USB_PORT_FEAT_ENABLE:
1853 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1854 break;
1855 case USB_PORT_FEAT_C_ENABLE:
1856 /* XXX error? */
1857 break;
1858 case USB_PORT_FEAT_SUSPEND:
1859 if (temp & PORT_RESET)
1860 goto error;
1861
1862 if (temp & PORT_SUSPEND) {
1863 if ((temp & PORT_PE) == 0)
1864 goto error;
1865 /* resume signaling for 20 msec */
1866 temp &= ~(PORT_RWC_BITS);
1867 reg_write32(hcd->regs, HC_PORTSC1,
1868 temp | PORT_RESUME);
1869 priv->reset_done = jiffies +
1870 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1871 }
1872 break;
1873 case USB_PORT_FEAT_C_SUSPEND:
1874 /* we auto-clear this feature */
1875 break;
1876 case USB_PORT_FEAT_POWER:
1877 if (HCS_PPC(priv->hcs_params))
1878 reg_write32(hcd->regs, HC_PORTSC1,
1879 temp & ~PORT_POWER);
1880 break;
1881 case USB_PORT_FEAT_C_CONNECTION:
1882 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1883 break;
1884 case USB_PORT_FEAT_C_OVER_CURRENT:
1885 /* XXX error ?*/
1886 break;
1887 case USB_PORT_FEAT_C_RESET:
1888 /* GetPortStatus clears reset */
1889 break;
1890 default:
1891 goto error;
1892 }
1893 reg_read32(hcd->regs, HC_USBCMD);
1894 break;
1895 case GetHubDescriptor:
1896 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1897 buf);
1898 break;
1899 case GetHubStatus:
1900 /* no hub-wide feature/status flags */
1901 memset(buf, 0, 4);
1902 break;
1903 case GetPortStatus:
1904 if (!wIndex || wIndex > ports)
1905 goto error;
1906 wIndex--;
1907 status = 0;
1908 temp = reg_read32(hcd->regs, HC_PORTSC1);
1909
1910 /* wPortChange bits */
1911 if (temp & PORT_CSC)
1912 status |= USB_PORT_STAT_C_CONNECTION << 16;
1913
1914
1915 /* whoever resumes must GetPortStatus to complete it!! */
1916 if (temp & PORT_RESUME) {
1917 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1918
1919 /* Remote Wakeup received? */
1920 if (!priv->reset_done) {
1921 /* resume signaling for 20 msec */
1922 priv->reset_done = jiffies
1923 + msecs_to_jiffies(20);
1924 /* check the port again */
1925 mod_timer(&hcd->rh_timer, priv->reset_done);
1926 }
1927
1928 /* resume completed? */
1929 else if (time_after_eq(jiffies,
1930 priv->reset_done)) {
1931 status |= USB_PORT_STAT_C_SUSPEND << 16;
1932 priv->reset_done = 0;
1933
1934 /* stop resume signaling */
1935 temp = reg_read32(hcd->regs, HC_PORTSC1);
1936 reg_write32(hcd->regs, HC_PORTSC1,
1937 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1938 retval = handshake(hcd, HC_PORTSC1,
1939 PORT_RESUME, 0, 2000 /* 2msec */);
1940 if (retval != 0) {
1941 dev_err(hcd->self.controller,
1942 "port %d resume error %d\n",
1943 wIndex + 1, retval);
1944 goto error;
1945 }
1946 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1947 }
1948 }
1949
1950 /* whoever resets must GetPortStatus to complete it!! */
1951 if ((temp & PORT_RESET)
1952 && time_after_eq(jiffies,
1953 priv->reset_done)) {
1954 status |= USB_PORT_STAT_C_RESET << 16;
1955 priv->reset_done = 0;
1956
1957 /* force reset to complete */
1958 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1959 /* REVISIT: some hardware needs 550+ usec to clear
1960 * this bit; seems too long to spin routinely...
1961 */
1962 retval = handshake(hcd, HC_PORTSC1,
1963 PORT_RESET, 0, 750);
1964 if (retval != 0) {
1965 dev_err(hcd->self.controller, "port %d reset error %d\n",
1966 wIndex + 1, retval);
1967 goto error;
1968 }
1969
1970 /* see what we found out */
1971 temp = check_reset_complete(hcd, wIndex,
1972 reg_read32(hcd->regs, HC_PORTSC1));
1973 }
1974 /*
1975 * Even if OWNER is set, there's no harm letting hub_wq
1976 * see the wPortStatus values (they should all be 0 except
1977 * for PORT_POWER anyway).
1978 */
1979
1980 if (temp & PORT_OWNER)
1981 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1982
1983 if (temp & PORT_CONNECT) {
1984 status |= USB_PORT_STAT_CONNECTION;
1985 /* status may be from integrated TT */
1986 status |= USB_PORT_STAT_HIGH_SPEED;
1987 }
1988 if (temp & PORT_PE)
1989 status |= USB_PORT_STAT_ENABLE;
1990 if (temp & (PORT_SUSPEND|PORT_RESUME))
1991 status |= USB_PORT_STAT_SUSPEND;
1992 if (temp & PORT_RESET)
1993 status |= USB_PORT_STAT_RESET;
1994 if (temp & PORT_POWER)
1995 status |= USB_PORT_STAT_POWER;
1996
1997 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1998 break;
1999 case SetHubFeature:
2000 switch (wValue) {
2001 case C_HUB_LOCAL_POWER:
2002 case C_HUB_OVER_CURRENT:
2003 /* no hub-wide feature/status flags */
2004 break;
2005 default:
2006 goto error;
2007 }
2008 break;
2009 case SetPortFeature:
2010 wIndex &= 0xff;
2011 if (!wIndex || wIndex > ports)
2012 goto error;
2013 wIndex--;
2014 temp = reg_read32(hcd->regs, HC_PORTSC1);
2015 if (temp & PORT_OWNER)
2016 break;
2017
2018/* temp &= ~PORT_RWC_BITS; */
2019 switch (wValue) {
2020 case USB_PORT_FEAT_ENABLE:
2021 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2022 break;
2023
2024 case USB_PORT_FEAT_SUSPEND:
2025 if ((temp & PORT_PE) == 0
2026 || (temp & PORT_RESET) != 0)
2027 goto error;
2028
2029 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2030 break;
2031 case USB_PORT_FEAT_POWER:
2032 if (HCS_PPC(priv->hcs_params))
2033 reg_write32(hcd->regs, HC_PORTSC1,
2034 temp | PORT_POWER);
2035 break;
2036 case USB_PORT_FEAT_RESET:
2037 if (temp & PORT_RESUME)
2038 goto error;
2039 /* line status bits may report this as low speed,
2040 * which can be fine if this root hub has a
2041 * transaction translator built in.
2042 */
2043 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2044 && PORT_USB11(temp)) {
2045 temp |= PORT_OWNER;
2046 } else {
2047 temp |= PORT_RESET;
2048 temp &= ~PORT_PE;
2049
2050 /*
2051 * caller must wait, then call GetPortStatus
2052 * usb 2.0 spec says 50 ms resets on root
2053 */
2054 priv->reset_done = jiffies +
2055 msecs_to_jiffies(50);
2056 }
2057 reg_write32(hcd->regs, HC_PORTSC1, temp);
2058 break;
2059 default:
2060 goto error;
2061 }
2062 reg_read32(hcd->regs, HC_USBCMD);
2063 break;
2064
2065 default:
2066error:
2067 /* "stall" on error */
2068 retval = -EPIPE;
2069 }
2070 spin_unlock_irqrestore(&priv->lock, flags);
2071 return retval;
2072}
2073
2074static int isp1760_get_frame(struct usb_hcd *hcd)
2075{
2076 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2077 u32 fr;
2078
2079 fr = reg_read32(hcd->regs, HC_FRINDEX);
2080 return (fr >> 3) % priv->periodic_size;
2081}
2082
2083static void isp1760_stop(struct usb_hcd *hcd)
2084{
2085 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2086 u32 temp;
2087
2088 del_timer(&errata2_timer);
2089
2090 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2091 NULL, 0);
2092 msleep(20);
2093
2094 spin_lock_irq(&priv->lock);
2095 ehci_reset(hcd);
2096 /* Disable IRQ */
2097 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2098 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2099 spin_unlock_irq(&priv->lock);
2100
2101 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2102}
2103
2104static void isp1760_shutdown(struct usb_hcd *hcd)
2105{
2106 u32 command, temp;
2107
2108 isp1760_stop(hcd);
2109 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2110 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2111
2112 command = reg_read32(hcd->regs, HC_USBCMD);
2113 command &= ~CMD_RUN;
2114 reg_write32(hcd->regs, HC_USBCMD, command);
2115}
2116
2117static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2118 struct usb_host_endpoint *ep)
2119{
2120 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2121 struct isp1760_qh *qh = ep->hcpriv;
2122 unsigned long spinflags;
2123
2124 if (!qh)
2125 return;
2126
2127 spin_lock_irqsave(&priv->lock, spinflags);
2128 qh->tt_buffer_dirty = 0;
2129 schedule_ptds(hcd);
2130 spin_unlock_irqrestore(&priv->lock, spinflags);
2131}
2132
2133
2134static const struct hc_driver isp1760_hc_driver = {
2135 .description = "isp1760-hcd",
2136 .product_desc = "NXP ISP1760 USB Host Controller",
2137 .hcd_priv_size = sizeof(struct isp1760_hcd *),
2138 .irq = isp1760_irq,
2139 .flags = HCD_MEMORY | HCD_USB2,
2140 .reset = isp1760_hc_setup,
2141 .start = isp1760_run,
2142 .stop = isp1760_stop,
2143 .shutdown = isp1760_shutdown,
2144 .urb_enqueue = isp1760_urb_enqueue,
2145 .urb_dequeue = isp1760_urb_dequeue,
2146 .endpoint_disable = isp1760_endpoint_disable,
2147 .get_frame_number = isp1760_get_frame,
2148 .hub_status_data = isp1760_hub_status_data,
2149 .hub_control = isp1760_hub_control,
2150 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2151};
2152
2153int __init isp1760_init_kmem_once(void)
2154{
2155 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2156 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2157 SLAB_MEM_SPREAD, NULL);
2158
2159 if (!urb_listitem_cachep)
2160 return -ENOMEM;
2161
2162 qtd_cachep = kmem_cache_create("isp1760_qtd",
2163 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2164 SLAB_MEM_SPREAD, NULL);
2165
2166 if (!qtd_cachep)
2167 return -ENOMEM;
2168
2169 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2170 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2171
2172 if (!qh_cachep) {
2173 kmem_cache_destroy(qtd_cachep);
2174 return -ENOMEM;
2175 }
2176
2177 return 0;
2178}
2179
2180void isp1760_deinit_kmem_cache(void)
2181{
2182 kmem_cache_destroy(qtd_cachep);
2183 kmem_cache_destroy(qh_cachep);
2184 kmem_cache_destroy(urb_listitem_cachep);
2185}
2186
2187int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
2188 struct resource *mem, int irq, unsigned long irqflags,
2189 struct device *dev)
2190{
2191 struct usb_hcd *hcd;
2192 int ret;
2193
2194 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2195 if (!hcd)
2196 return -ENOMEM;
2197
2198 *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2199
2200 priv->hcd = hcd;
2201
2202 init_memory(priv);
2203
2204 hcd->irq = irq;
2205 hcd->regs = regs;
2206 hcd->rsrc_start = mem->start;
2207 hcd->rsrc_len = resource_size(mem);
2208
2209 /* This driver doesn't support wakeup requests */
2210 hcd->cant_recv_wakeups = 1;
2211
2212 ret = usb_add_hcd(hcd, irq, irqflags);
2213 if (ret)
2214 goto error;
2215
2216 device_wakeup_enable(hcd->self.controller);
2217
2218 return 0;
2219
2220error:
2221 usb_put_hcd(hcd);
2222 return ret;
2223}
2224
2225void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2226{
2227 if (!priv->hcd)
2228 return;
2229
2230 usb_remove_hcd(priv->hcd);
2231 usb_put_hcd(priv->hcd);
2232}