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1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/slab.h>
25
26#include "xhci.h"
27
28/* Device for a quirk */
29#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
30#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
31
32#define PCI_VENDOR_ID_ETRON 0x1b6f
33#define PCI_DEVICE_ID_ASROCK_P67 0x7023
34
35static const char hcd_name[] = "xhci_hcd";
36
37/* called after powerup, by probe or system-pm "wakeup" */
38static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
39{
40 /*
41 * TODO: Implement finding debug ports later.
42 * TODO: see if there are any quirks that need to be added to handle
43 * new extended capabilities.
44 */
45
46 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
47 if (!pci_set_mwi(pdev))
48 xhci_dbg(xhci, "MWI active\n");
49
50 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
51 return 0;
52}
53
54/* called during probe() after chip reset completes */
55static int xhci_pci_setup(struct usb_hcd *hcd)
56{
57 struct xhci_hcd *xhci;
58 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
59 int retval;
60 u32 temp;
61
62 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
63
64 if (usb_hcd_is_primary_hcd(hcd)) {
65 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
66 if (!xhci)
67 return -ENOMEM;
68 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
69 xhci->main_hcd = hcd;
70 /* Mark the first roothub as being USB 2.0.
71 * The xHCI driver will register the USB 3.0 roothub.
72 */
73 hcd->speed = HCD_USB2;
74 hcd->self.root_hub->speed = USB_SPEED_HIGH;
75 /*
76 * USB 2.0 roothub under xHCI has an integrated TT,
77 * (rate matching hub) as opposed to having an OHCI/UHCI
78 * companion controller.
79 */
80 hcd->has_tt = 1;
81 } else {
82 /* xHCI private pointer was set in xhci_pci_probe for the second
83 * registered roothub.
84 */
85 xhci = hcd_to_xhci(hcd);
86 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
87 if (HCC_64BIT_ADDR(temp)) {
88 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
89 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
90 } else {
91 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
92 }
93 return 0;
94 }
95
96 xhci->cap_regs = hcd->regs;
97 xhci->op_regs = hcd->regs +
98 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
99 xhci->run_regs = hcd->regs +
100 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
101 /* Cache read-only capability registers */
102 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
103 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
104 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
105 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
106 xhci->hci_version = HC_VERSION(xhci->hcc_params);
107 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
108 xhci_print_registers(xhci);
109
110 /* Look for vendor-specific quirks */
111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
112 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
113 if (pdev->revision == 0x0) {
114 xhci->quirks |= XHCI_RESET_EP_QUIRK;
115 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
116 " endpoint cmd after reset endpoint\n");
117 }
118 /* Fresco Logic confirms: all revisions of this chip do not
119 * support MSI, even though some of them claim to in their PCI
120 * capabilities.
121 */
122 xhci->quirks |= XHCI_BROKEN_MSI;
123 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
124 "has broken MSI implementation\n",
125 pdev->revision);
126 }
127
128 if (pdev->vendor == PCI_VENDOR_ID_NEC)
129 xhci->quirks |= XHCI_NEC_HOST;
130
131 /* AMD PLL quirk */
132 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
133 xhci->quirks |= XHCI_AMD_PLL_FIX;
134 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
135 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
136 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
137 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
138 xhci->limit_active_eps = 64;
139 }
140 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
141 pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
142 xhci->quirks |= XHCI_RESET_ON_RESUME;
143 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
144 }
145
146 /* Make sure the HC is halted. */
147 retval = xhci_halt(xhci);
148 if (retval)
149 goto error;
150
151 xhci_dbg(xhci, "Resetting HCD\n");
152 /* Reset the internal HC memory state and registers. */
153 retval = xhci_reset(xhci);
154 if (retval)
155 goto error;
156 xhci_dbg(xhci, "Reset complete\n");
157
158 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
159 if (HCC_64BIT_ADDR(temp)) {
160 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
161 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
162 } else {
163 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
164 }
165
166 xhci_dbg(xhci, "Calling HCD init\n");
167 /* Initialize HCD and host controller data structures. */
168 retval = xhci_init(hcd);
169 if (retval)
170 goto error;
171 xhci_dbg(xhci, "Called HCD init\n");
172
173 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
174 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
175
176 /* Find any debug ports */
177 retval = xhci_pci_reinit(xhci, pdev);
178 if (!retval)
179 return retval;
180
181error:
182 kfree(xhci);
183 return retval;
184}
185
186/*
187 * We need to register our own PCI probe function (instead of the USB core's
188 * function) in order to create a second roothub under xHCI.
189 */
190static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
191{
192 int retval;
193 struct xhci_hcd *xhci;
194 struct hc_driver *driver;
195 struct usb_hcd *hcd;
196
197 driver = (struct hc_driver *)id->driver_data;
198 /* Register the USB 2.0 roothub.
199 * FIXME: USB core must know to register the USB 2.0 roothub first.
200 * This is sort of silly, because we could just set the HCD driver flags
201 * to say USB 2.0, but I'm not sure what the implications would be in
202 * the other parts of the HCD code.
203 */
204 retval = usb_hcd_pci_probe(dev, id);
205
206 if (retval)
207 return retval;
208
209 /* USB 2.0 roothub is stored in the PCI device now. */
210 hcd = dev_get_drvdata(&dev->dev);
211 xhci = hcd_to_xhci(hcd);
212 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
213 pci_name(dev), hcd);
214 if (!xhci->shared_hcd) {
215 retval = -ENOMEM;
216 goto dealloc_usb2_hcd;
217 }
218
219 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
220 * is called by usb_add_hcd().
221 */
222 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
223
224 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
225 IRQF_DISABLED | IRQF_SHARED);
226 if (retval)
227 goto put_usb3_hcd;
228 /* Roothub already marked as USB 3.0 speed */
229 return 0;
230
231put_usb3_hcd:
232 usb_put_hcd(xhci->shared_hcd);
233dealloc_usb2_hcd:
234 usb_hcd_pci_remove(dev);
235 return retval;
236}
237
238static void xhci_pci_remove(struct pci_dev *dev)
239{
240 struct xhci_hcd *xhci;
241
242 xhci = hcd_to_xhci(pci_get_drvdata(dev));
243 if (xhci->shared_hcd) {
244 usb_remove_hcd(xhci->shared_hcd);
245 usb_put_hcd(xhci->shared_hcd);
246 }
247 usb_hcd_pci_remove(dev);
248 kfree(xhci);
249}
250
251#ifdef CONFIG_PM
252static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
253{
254 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
255 int retval = 0;
256
257 if (hcd->state != HC_STATE_SUSPENDED ||
258 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
259 return -EINVAL;
260
261 retval = xhci_suspend(xhci);
262
263 return retval;
264}
265
266static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
267{
268 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
269 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
270 int retval = 0;
271
272 /* The BIOS on systems with the Intel Panther Point chipset may or may
273 * not support xHCI natively. That means that during system resume, it
274 * may switch the ports back to EHCI so that users can use their
275 * keyboard to select a kernel from GRUB after resume from hibernate.
276 *
277 * The BIOS is supposed to remember whether the OS had xHCI ports
278 * enabled before resume, and switch the ports back to xHCI when the
279 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
280 * writers.
281 *
282 * Unconditionally switch the ports back to xHCI after a system resume.
283 * We can't tell whether the EHCI or xHCI controller will be resumed
284 * first, so we have to do the port switchover in both drivers. Writing
285 * a '1' to the port switchover registers should have no effect if the
286 * port was already switched over.
287 */
288 if (usb_is_intel_switchable_xhci(pdev))
289 usb_enable_xhci_ports(pdev);
290
291 retval = xhci_resume(xhci, hibernated);
292 return retval;
293}
294#endif /* CONFIG_PM */
295
296static const struct hc_driver xhci_pci_hc_driver = {
297 .description = hcd_name,
298 .product_desc = "xHCI Host Controller",
299 .hcd_priv_size = sizeof(struct xhci_hcd *),
300
301 /*
302 * generic hardware linkage
303 */
304 .irq = xhci_irq,
305 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
306
307 /*
308 * basic lifecycle operations
309 */
310 .reset = xhci_pci_setup,
311 .start = xhci_run,
312#ifdef CONFIG_PM
313 .pci_suspend = xhci_pci_suspend,
314 .pci_resume = xhci_pci_resume,
315#endif
316 .stop = xhci_stop,
317 .shutdown = xhci_shutdown,
318
319 /*
320 * managing i/o requests and associated device resources
321 */
322 .urb_enqueue = xhci_urb_enqueue,
323 .urb_dequeue = xhci_urb_dequeue,
324 .alloc_dev = xhci_alloc_dev,
325 .free_dev = xhci_free_dev,
326 .alloc_streams = xhci_alloc_streams,
327 .free_streams = xhci_free_streams,
328 .add_endpoint = xhci_add_endpoint,
329 .drop_endpoint = xhci_drop_endpoint,
330 .endpoint_reset = xhci_endpoint_reset,
331 .check_bandwidth = xhci_check_bandwidth,
332 .reset_bandwidth = xhci_reset_bandwidth,
333 .address_device = xhci_address_device,
334 .update_hub_device = xhci_update_hub_device,
335 .reset_device = xhci_discover_or_reset_device,
336
337 /*
338 * scheduling support
339 */
340 .get_frame_number = xhci_get_frame,
341
342 /* Root hub support */
343 .hub_control = xhci_hub_control,
344 .hub_status_data = xhci_hub_status_data,
345 .bus_suspend = xhci_bus_suspend,
346 .bus_resume = xhci_bus_resume,
347};
348
349/*-------------------------------------------------------------------------*/
350
351/* PCI driver selection metadata; PCI hotplugging uses this */
352static const struct pci_device_id pci_ids[] = { {
353 /* handle any USB 3.0 xHCI controller */
354 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
355 .driver_data = (unsigned long) &xhci_pci_hc_driver,
356 },
357 { /* end: all zeroes */ }
358};
359MODULE_DEVICE_TABLE(pci, pci_ids);
360
361/* pci driver glue; this is a "new style" PCI driver module */
362static struct pci_driver xhci_pci_driver = {
363 .name = (char *) hcd_name,
364 .id_table = pci_ids,
365
366 .probe = xhci_pci_probe,
367 .remove = xhci_pci_remove,
368 /* suspend and resume implemented later */
369
370 .shutdown = usb_hcd_pci_shutdown,
371#ifdef CONFIG_PM_SLEEP
372 .driver = {
373 .pm = &usb_hcd_pci_pm_ops
374 },
375#endif
376};
377
378int xhci_register_pci(void)
379{
380 return pci_register_driver(&xhci_pci_driver);
381}
382
383void xhci_unregister_pci(void)
384{
385 pci_unregister_driver(&xhci_pci_driver);
386}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/acpi.h>
15#include <linux/reset.h>
16
17#include "xhci.h"
18#include "xhci-trace.h"
19#include "xhci-pci.h"
20
21#define SSIC_PORT_NUM 2
22#define SSIC_PORT_CFG2 0x880c
23#define SSIC_PORT_CFG2_OFFSET 0x30
24#define PROG_DONE (1 << 30)
25#define SSIC_PORT_UNUSED (1 << 31)
26#define SPARSE_DISABLE_BIT 17
27#define SPARSE_CNTL_ENABLE 0xC12C
28
29/* Device for a quirk */
30#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
35
36#define PCI_VENDOR_ID_ETRON 0x1b6f
37#define PCI_DEVICE_ID_EJ168 0x7023
38
39#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
40#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
41#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
42#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
43#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
44#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
45#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
46#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
47#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
48#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
49#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
50#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
51#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
52#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
53#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
54#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
55#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
56#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
57#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
58#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
59#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
60#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
61#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
62
63#define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
64#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
65#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
66#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
67#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
68#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
69#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
70#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
71#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
72#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
73
74static const char hcd_name[] = "xhci_hcd";
75
76static struct hc_driver __read_mostly xhci_pci_hc_driver;
77
78static int xhci_pci_setup(struct usb_hcd *hcd);
79
80static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
81 .reset = xhci_pci_setup,
82};
83
84/* called after powerup, by probe or system-pm "wakeup" */
85static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
86{
87 /*
88 * TODO: Implement finding debug ports later.
89 * TODO: see if there are any quirks that need to be added to handle
90 * new extended capabilities.
91 */
92
93 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
94 if (!pci_set_mwi(pdev))
95 xhci_dbg(xhci, "MWI active\n");
96
97 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
98 return 0;
99}
100
101static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
102{
103 struct pci_dev *pdev = to_pci_dev(dev);
104 struct xhci_driver_data *driver_data;
105 const struct pci_device_id *id;
106
107 id = pci_match_id(pdev->driver->id_table, pdev);
108
109 if (id && id->driver_data) {
110 driver_data = (struct xhci_driver_data *)id->driver_data;
111 xhci->quirks |= driver_data->quirks;
112 }
113
114 /* Look for vendor-specific quirks */
115 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
116 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
117 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 ||
118 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
119 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
120 pdev->revision == 0x0) {
121 xhci->quirks |= XHCI_RESET_EP_QUIRK;
122 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
123 "QUIRK: Fresco Logic xHC needs configure"
124 " endpoint cmd after reset endpoint");
125 }
126 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
127 pdev->revision == 0x4) {
128 xhci->quirks |= XHCI_SLOW_SUSPEND;
129 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
130 "QUIRK: Fresco Logic xHC revision %u"
131 "must be suspended extra slowly",
132 pdev->revision);
133 }
134 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
135 xhci->quirks |= XHCI_BROKEN_STREAMS;
136 /* Fresco Logic confirms: all revisions of this chip do not
137 * support MSI, even though some of them claim to in their PCI
138 * capabilities.
139 */
140 xhci->quirks |= XHCI_BROKEN_MSI;
141 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
142 "QUIRK: Fresco Logic revision %u "
143 "has broken MSI implementation",
144 pdev->revision);
145 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
146 }
147
148 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
149 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
150 xhci->quirks |= XHCI_BROKEN_STREAMS;
151
152 if (pdev->vendor == PCI_VENDOR_ID_NEC)
153 xhci->quirks |= XHCI_NEC_HOST;
154
155 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
156 xhci->quirks |= XHCI_AMD_0x96_HOST;
157
158 /* AMD PLL quirk */
159 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
160 xhci->quirks |= XHCI_AMD_PLL_FIX;
161
162 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
163 (pdev->device == 0x145c ||
164 pdev->device == 0x15e0 ||
165 pdev->device == 0x15e1 ||
166 pdev->device == 0x43bb))
167 xhci->quirks |= XHCI_SUSPEND_DELAY;
168
169 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
170 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
171 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
172
173 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
174 xhci->quirks |= XHCI_DISABLE_SPARSE;
175 xhci->quirks |= XHCI_RESET_ON_RESUME;
176 }
177
178 if (pdev->vendor == PCI_VENDOR_ID_AMD)
179 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
180
181 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
182 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
183 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
184 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
185 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
186 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
187
188 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
189 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
190 xhci->quirks |= XHCI_BROKEN_D3COLD;
191
192 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
193 xhci->quirks |= XHCI_LPM_SUPPORT;
194 xhci->quirks |= XHCI_INTEL_HOST;
195 xhci->quirks |= XHCI_AVOID_BEI;
196 }
197 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
198 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
199 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
200 xhci->limit_active_eps = 64;
201 xhci->quirks |= XHCI_SW_BW_CHECKING;
202 /*
203 * PPT desktop boards DH77EB and DH77DF will power back on after
204 * a few seconds of being shutdown. The fix for this is to
205 * switch the ports from xHCI to EHCI on shutdown. We can't use
206 * DMI information to find those particular boards (since each
207 * vendor will change the board name), so we have to key off all
208 * PPT chipsets.
209 */
210 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
211 }
212 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
213 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
214 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
215 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
216 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
217 }
218 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
219 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
220 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
221 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
222 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
223 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
224 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
225 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
226 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
227 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
228 }
229 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
230 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
231 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
232 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
233 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
234 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
235 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
236 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
237 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
238 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
239 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
240 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
241 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
242 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
243 xhci->quirks |= XHCI_MISSING_CAS;
244
245 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
246 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
247 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
248 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
249 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
250 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
251 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
252 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
253 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
254 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
255 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
256 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
257 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
258 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
259
260 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
261 pdev->device == PCI_DEVICE_ID_EJ168) {
262 xhci->quirks |= XHCI_RESET_ON_RESUME;
263 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
264 xhci->quirks |= XHCI_BROKEN_STREAMS;
265 }
266 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
267 pdev->device == 0x0014) {
268 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
269 xhci->quirks |= XHCI_ZERO_64B_REGS;
270 }
271 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
272 pdev->device == 0x0015) {
273 xhci->quirks |= XHCI_RESET_ON_RESUME;
274 xhci->quirks |= XHCI_ZERO_64B_REGS;
275 }
276 if (pdev->vendor == PCI_VENDOR_ID_VIA)
277 xhci->quirks |= XHCI_RESET_ON_RESUME;
278
279 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
280 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
281 pdev->device == 0x3432)
282 xhci->quirks |= XHCI_BROKEN_STREAMS;
283
284 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
285 xhci->quirks |= XHCI_LPM_SUPPORT;
286 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
287 }
288
289 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
290 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
291 xhci->quirks |= XHCI_BROKEN_STREAMS;
292 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
293 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
294 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
295 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
296 }
297 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
298 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
299 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
300 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
301 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
302
303 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
304 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
305 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
306
307 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
308 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
309
310 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
311 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
312 pdev->device == 0x9026)
313 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
314
315 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
316 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
317 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
318 xhci->quirks |= XHCI_NO_SOFT_RETRY;
319
320 if (xhci->quirks & XHCI_RESET_ON_RESUME)
321 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
322 "QUIRK: Resetting on resume");
323}
324
325#ifdef CONFIG_ACPI
326static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
327{
328 static const guid_t intel_dsm_guid =
329 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
330 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
331 union acpi_object *obj;
332
333 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
334 NULL);
335 ACPI_FREE(obj);
336}
337#else
338static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
339#endif /* CONFIG_ACPI */
340
341/* called during probe() after chip reset completes */
342static int xhci_pci_setup(struct usb_hcd *hcd)
343{
344 struct xhci_hcd *xhci;
345 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
346 int retval;
347
348 xhci = hcd_to_xhci(hcd);
349 if (!xhci->sbrn)
350 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
351
352 /* imod_interval is the interrupt moderation value in nanoseconds. */
353 xhci->imod_interval = 40000;
354
355 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
356 if (retval)
357 return retval;
358
359 if (!usb_hcd_is_primary_hcd(hcd))
360 return 0;
361
362 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
363 xhci_pme_acpi_rtd3_enable(pdev);
364
365 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
366
367 /* Find any debug ports */
368 return xhci_pci_reinit(xhci, pdev);
369}
370
371/*
372 * We need to register our own PCI probe function (instead of the USB core's
373 * function) in order to create a second roothub under xHCI.
374 */
375static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
376{
377 int retval;
378 struct xhci_hcd *xhci;
379 struct usb_hcd *hcd;
380 struct xhci_driver_data *driver_data;
381 struct reset_control *reset;
382
383 driver_data = (struct xhci_driver_data *)id->driver_data;
384 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
385 retval = renesas_xhci_check_request_fw(dev, id);
386 if (retval)
387 return retval;
388 }
389
390 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
391 if (IS_ERR(reset))
392 return PTR_ERR(reset);
393 reset_control_reset(reset);
394
395 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
396 pm_runtime_get_noresume(&dev->dev);
397
398 /* Register the USB 2.0 roothub.
399 * FIXME: USB core must know to register the USB 2.0 roothub first.
400 * This is sort of silly, because we could just set the HCD driver flags
401 * to say USB 2.0, but I'm not sure what the implications would be in
402 * the other parts of the HCD code.
403 */
404 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
405
406 if (retval)
407 goto put_runtime_pm;
408
409 /* USB 2.0 roothub is stored in the PCI device now. */
410 hcd = dev_get_drvdata(&dev->dev);
411 xhci = hcd_to_xhci(hcd);
412 xhci->reset = reset;
413 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
414 pci_name(dev), hcd);
415 if (!xhci->shared_hcd) {
416 retval = -ENOMEM;
417 goto dealloc_usb2_hcd;
418 }
419
420 retval = xhci_ext_cap_init(xhci);
421 if (retval)
422 goto put_usb3_hcd;
423
424 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
425 IRQF_SHARED);
426 if (retval)
427 goto put_usb3_hcd;
428 /* Roothub already marked as USB 3.0 speed */
429
430 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
431 HCC_MAX_PSA(xhci->hcc_params) >= 4)
432 xhci->shared_hcd->can_do_streams = 1;
433
434 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
435 pm_runtime_put_noidle(&dev->dev);
436
437 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
438 pm_runtime_allow(&dev->dev);
439
440 return 0;
441
442put_usb3_hcd:
443 usb_put_hcd(xhci->shared_hcd);
444dealloc_usb2_hcd:
445 usb_hcd_pci_remove(dev);
446put_runtime_pm:
447 pm_runtime_put_noidle(&dev->dev);
448 return retval;
449}
450
451static void xhci_pci_remove(struct pci_dev *dev)
452{
453 struct xhci_hcd *xhci;
454
455 xhci = hcd_to_xhci(pci_get_drvdata(dev));
456 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
457 renesas_xhci_pci_exit(dev);
458
459 xhci->xhc_state |= XHCI_STATE_REMOVING;
460
461 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
462 pm_runtime_forbid(&dev->dev);
463
464 if (xhci->shared_hcd) {
465 usb_remove_hcd(xhci->shared_hcd);
466 usb_put_hcd(xhci->shared_hcd);
467 xhci->shared_hcd = NULL;
468 }
469
470 /* Workaround for spurious wakeups at shutdown with HSW */
471 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
472 pci_set_power_state(dev, PCI_D3hot);
473
474 usb_hcd_pci_remove(dev);
475}
476
477#ifdef CONFIG_PM
478/*
479 * In some Intel xHCI controllers, in order to get D3 working,
480 * through a vendor specific SSIC CONFIG register at offset 0x883c,
481 * SSIC PORT need to be marked as "unused" before putting xHCI
482 * into D3. After D3 exit, the SSIC port need to be marked as "used".
483 * Without this change, xHCI might not enter D3 state.
484 */
485static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
486{
487 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
488 u32 val;
489 void __iomem *reg;
490 int i;
491
492 for (i = 0; i < SSIC_PORT_NUM; i++) {
493 reg = (void __iomem *) xhci->cap_regs +
494 SSIC_PORT_CFG2 +
495 i * SSIC_PORT_CFG2_OFFSET;
496
497 /* Notify SSIC that SSIC profile programming is not done. */
498 val = readl(reg) & ~PROG_DONE;
499 writel(val, reg);
500
501 /* Mark SSIC port as unused(suspend) or used(resume) */
502 val = readl(reg);
503 if (suspend)
504 val |= SSIC_PORT_UNUSED;
505 else
506 val &= ~SSIC_PORT_UNUSED;
507 writel(val, reg);
508
509 /* Notify SSIC that SSIC profile programming is done */
510 val = readl(reg) | PROG_DONE;
511 writel(val, reg);
512 readl(reg);
513 }
514}
515
516/*
517 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
518 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
519 */
520static void xhci_pme_quirk(struct usb_hcd *hcd)
521{
522 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
523 void __iomem *reg;
524 u32 val;
525
526 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
527 val = readl(reg);
528 writel(val | BIT(28), reg);
529 readl(reg);
530}
531
532static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
533{
534 u32 reg;
535
536 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
537 reg &= ~BIT(SPARSE_DISABLE_BIT);
538 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
539}
540
541static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
542{
543 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
544 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
545 int ret;
546
547 /*
548 * Systems with the TI redriver that loses port status change events
549 * need to have the registers polled during D3, so avoid D3cold.
550 */
551 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
552 pci_d3cold_disable(pdev);
553
554 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
555 xhci_pme_quirk(hcd);
556
557 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
558 xhci_ssic_port_unused_quirk(hcd, true);
559
560 if (xhci->quirks & XHCI_DISABLE_SPARSE)
561 xhci_sparse_control_quirk(hcd);
562
563 ret = xhci_suspend(xhci, do_wakeup);
564 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
565 xhci_ssic_port_unused_quirk(hcd, false);
566
567 return ret;
568}
569
570static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
571{
572 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
573 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
574 int retval = 0;
575
576 reset_control_reset(xhci->reset);
577
578 /* The BIOS on systems with the Intel Panther Point chipset may or may
579 * not support xHCI natively. That means that during system resume, it
580 * may switch the ports back to EHCI so that users can use their
581 * keyboard to select a kernel from GRUB after resume from hibernate.
582 *
583 * The BIOS is supposed to remember whether the OS had xHCI ports
584 * enabled before resume, and switch the ports back to xHCI when the
585 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
586 * writers.
587 *
588 * Unconditionally switch the ports back to xHCI after a system resume.
589 * It should not matter whether the EHCI or xHCI controller is
590 * resumed first. It's enough to do the switchover in xHCI because
591 * USB core won't notice anything as the hub driver doesn't start
592 * running again until after all the devices (including both EHCI and
593 * xHCI host controllers) have been resumed.
594 */
595
596 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
597 usb_enable_intel_xhci_ports(pdev);
598
599 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
600 xhci_ssic_port_unused_quirk(hcd, false);
601
602 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
603 xhci_pme_quirk(hcd);
604
605 retval = xhci_resume(xhci, hibernated);
606 return retval;
607}
608
609static void xhci_pci_shutdown(struct usb_hcd *hcd)
610{
611 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
612 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
613
614 xhci_shutdown(hcd);
615
616 /* Yet another workaround for spurious wakeups at shutdown with HSW */
617 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
618 pci_set_power_state(pdev, PCI_D3hot);
619}
620#endif /* CONFIG_PM */
621
622/*-------------------------------------------------------------------------*/
623
624static const struct xhci_driver_data reneses_data = {
625 .quirks = XHCI_RENESAS_FW_QUIRK,
626 .firmware = "renesas_usb_fw.mem",
627};
628
629/* PCI driver selection metadata; PCI hotplugging uses this */
630static const struct pci_device_id pci_ids[] = {
631 { PCI_DEVICE(0x1912, 0x0014),
632 .driver_data = (unsigned long)&reneses_data,
633 },
634 { PCI_DEVICE(0x1912, 0x0015),
635 .driver_data = (unsigned long)&reneses_data,
636 },
637 /* handle any USB 3.0 xHCI controller */
638 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
639 },
640 { /* end: all zeroes */ }
641};
642MODULE_DEVICE_TABLE(pci, pci_ids);
643
644/*
645 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
646 * load firmware, so don't encumber the xhci-pci driver with it.
647 */
648#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
649MODULE_FIRMWARE("renesas_usb_fw.mem");
650#endif
651
652/* pci driver glue; this is a "new style" PCI driver module */
653static struct pci_driver xhci_pci_driver = {
654 .name = hcd_name,
655 .id_table = pci_ids,
656
657 .probe = xhci_pci_probe,
658 .remove = xhci_pci_remove,
659 /* suspend and resume implemented later */
660
661 .shutdown = usb_hcd_pci_shutdown,
662#ifdef CONFIG_PM
663 .driver = {
664 .pm = &usb_hcd_pci_pm_ops
665 },
666#endif
667};
668
669static int __init xhci_pci_init(void)
670{
671 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
672#ifdef CONFIG_PM
673 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
674 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
675 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
676#endif
677 return pci_register_driver(&xhci_pci_driver);
678}
679module_init(xhci_pci_init);
680
681static void __exit xhci_pci_exit(void)
682{
683 pci_unregister_driver(&xhci_pci_driver);
684}
685module_exit(xhci_pci_exit);
686
687MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
688MODULE_LICENSE("GPL");