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1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/slab.h>
25
26#include "xhci.h"
27
28/* Device for a quirk */
29#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
30#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
31
32#define PCI_VENDOR_ID_ETRON 0x1b6f
33#define PCI_DEVICE_ID_ASROCK_P67 0x7023
34
35static const char hcd_name[] = "xhci_hcd";
36
37/* called after powerup, by probe or system-pm "wakeup" */
38static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
39{
40 /*
41 * TODO: Implement finding debug ports later.
42 * TODO: see if there are any quirks that need to be added to handle
43 * new extended capabilities.
44 */
45
46 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
47 if (!pci_set_mwi(pdev))
48 xhci_dbg(xhci, "MWI active\n");
49
50 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
51 return 0;
52}
53
54/* called during probe() after chip reset completes */
55static int xhci_pci_setup(struct usb_hcd *hcd)
56{
57 struct xhci_hcd *xhci;
58 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
59 int retval;
60 u32 temp;
61
62 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
63
64 if (usb_hcd_is_primary_hcd(hcd)) {
65 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
66 if (!xhci)
67 return -ENOMEM;
68 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
69 xhci->main_hcd = hcd;
70 /* Mark the first roothub as being USB 2.0.
71 * The xHCI driver will register the USB 3.0 roothub.
72 */
73 hcd->speed = HCD_USB2;
74 hcd->self.root_hub->speed = USB_SPEED_HIGH;
75 /*
76 * USB 2.0 roothub under xHCI has an integrated TT,
77 * (rate matching hub) as opposed to having an OHCI/UHCI
78 * companion controller.
79 */
80 hcd->has_tt = 1;
81 } else {
82 /* xHCI private pointer was set in xhci_pci_probe for the second
83 * registered roothub.
84 */
85 xhci = hcd_to_xhci(hcd);
86 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
87 if (HCC_64BIT_ADDR(temp)) {
88 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
89 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
90 } else {
91 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
92 }
93 return 0;
94 }
95
96 xhci->cap_regs = hcd->regs;
97 xhci->op_regs = hcd->regs +
98 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
99 xhci->run_regs = hcd->regs +
100 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
101 /* Cache read-only capability registers */
102 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
103 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
104 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
105 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
106 xhci->hci_version = HC_VERSION(xhci->hcc_params);
107 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
108 xhci_print_registers(xhci);
109
110 /* Look for vendor-specific quirks */
111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
112 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
113 if (pdev->revision == 0x0) {
114 xhci->quirks |= XHCI_RESET_EP_QUIRK;
115 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
116 " endpoint cmd after reset endpoint\n");
117 }
118 /* Fresco Logic confirms: all revisions of this chip do not
119 * support MSI, even though some of them claim to in their PCI
120 * capabilities.
121 */
122 xhci->quirks |= XHCI_BROKEN_MSI;
123 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
124 "has broken MSI implementation\n",
125 pdev->revision);
126 }
127
128 if (pdev->vendor == PCI_VENDOR_ID_NEC)
129 xhci->quirks |= XHCI_NEC_HOST;
130
131 /* AMD PLL quirk */
132 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
133 xhci->quirks |= XHCI_AMD_PLL_FIX;
134 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
135 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
136 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
137 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
138 xhci->limit_active_eps = 64;
139 }
140 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
141 pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
142 xhci->quirks |= XHCI_RESET_ON_RESUME;
143 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
144 }
145
146 /* Make sure the HC is halted. */
147 retval = xhci_halt(xhci);
148 if (retval)
149 goto error;
150
151 xhci_dbg(xhci, "Resetting HCD\n");
152 /* Reset the internal HC memory state and registers. */
153 retval = xhci_reset(xhci);
154 if (retval)
155 goto error;
156 xhci_dbg(xhci, "Reset complete\n");
157
158 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
159 if (HCC_64BIT_ADDR(temp)) {
160 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
161 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
162 } else {
163 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
164 }
165
166 xhci_dbg(xhci, "Calling HCD init\n");
167 /* Initialize HCD and host controller data structures. */
168 retval = xhci_init(hcd);
169 if (retval)
170 goto error;
171 xhci_dbg(xhci, "Called HCD init\n");
172
173 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
174 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
175
176 /* Find any debug ports */
177 retval = xhci_pci_reinit(xhci, pdev);
178 if (!retval)
179 return retval;
180
181error:
182 kfree(xhci);
183 return retval;
184}
185
186/*
187 * We need to register our own PCI probe function (instead of the USB core's
188 * function) in order to create a second roothub under xHCI.
189 */
190static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
191{
192 int retval;
193 struct xhci_hcd *xhci;
194 struct hc_driver *driver;
195 struct usb_hcd *hcd;
196
197 driver = (struct hc_driver *)id->driver_data;
198 /* Register the USB 2.0 roothub.
199 * FIXME: USB core must know to register the USB 2.0 roothub first.
200 * This is sort of silly, because we could just set the HCD driver flags
201 * to say USB 2.0, but I'm not sure what the implications would be in
202 * the other parts of the HCD code.
203 */
204 retval = usb_hcd_pci_probe(dev, id);
205
206 if (retval)
207 return retval;
208
209 /* USB 2.0 roothub is stored in the PCI device now. */
210 hcd = dev_get_drvdata(&dev->dev);
211 xhci = hcd_to_xhci(hcd);
212 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
213 pci_name(dev), hcd);
214 if (!xhci->shared_hcd) {
215 retval = -ENOMEM;
216 goto dealloc_usb2_hcd;
217 }
218
219 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
220 * is called by usb_add_hcd().
221 */
222 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
223
224 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
225 IRQF_DISABLED | IRQF_SHARED);
226 if (retval)
227 goto put_usb3_hcd;
228 /* Roothub already marked as USB 3.0 speed */
229 return 0;
230
231put_usb3_hcd:
232 usb_put_hcd(xhci->shared_hcd);
233dealloc_usb2_hcd:
234 usb_hcd_pci_remove(dev);
235 return retval;
236}
237
238static void xhci_pci_remove(struct pci_dev *dev)
239{
240 struct xhci_hcd *xhci;
241
242 xhci = hcd_to_xhci(pci_get_drvdata(dev));
243 if (xhci->shared_hcd) {
244 usb_remove_hcd(xhci->shared_hcd);
245 usb_put_hcd(xhci->shared_hcd);
246 }
247 usb_hcd_pci_remove(dev);
248 kfree(xhci);
249}
250
251#ifdef CONFIG_PM
252static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
253{
254 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
255 int retval = 0;
256
257 if (hcd->state != HC_STATE_SUSPENDED ||
258 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
259 return -EINVAL;
260
261 retval = xhci_suspend(xhci);
262
263 return retval;
264}
265
266static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
267{
268 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
269 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
270 int retval = 0;
271
272 /* The BIOS on systems with the Intel Panther Point chipset may or may
273 * not support xHCI natively. That means that during system resume, it
274 * may switch the ports back to EHCI so that users can use their
275 * keyboard to select a kernel from GRUB after resume from hibernate.
276 *
277 * The BIOS is supposed to remember whether the OS had xHCI ports
278 * enabled before resume, and switch the ports back to xHCI when the
279 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
280 * writers.
281 *
282 * Unconditionally switch the ports back to xHCI after a system resume.
283 * We can't tell whether the EHCI or xHCI controller will be resumed
284 * first, so we have to do the port switchover in both drivers. Writing
285 * a '1' to the port switchover registers should have no effect if the
286 * port was already switched over.
287 */
288 if (usb_is_intel_switchable_xhci(pdev))
289 usb_enable_xhci_ports(pdev);
290
291 retval = xhci_resume(xhci, hibernated);
292 return retval;
293}
294#endif /* CONFIG_PM */
295
296static const struct hc_driver xhci_pci_hc_driver = {
297 .description = hcd_name,
298 .product_desc = "xHCI Host Controller",
299 .hcd_priv_size = sizeof(struct xhci_hcd *),
300
301 /*
302 * generic hardware linkage
303 */
304 .irq = xhci_irq,
305 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
306
307 /*
308 * basic lifecycle operations
309 */
310 .reset = xhci_pci_setup,
311 .start = xhci_run,
312#ifdef CONFIG_PM
313 .pci_suspend = xhci_pci_suspend,
314 .pci_resume = xhci_pci_resume,
315#endif
316 .stop = xhci_stop,
317 .shutdown = xhci_shutdown,
318
319 /*
320 * managing i/o requests and associated device resources
321 */
322 .urb_enqueue = xhci_urb_enqueue,
323 .urb_dequeue = xhci_urb_dequeue,
324 .alloc_dev = xhci_alloc_dev,
325 .free_dev = xhci_free_dev,
326 .alloc_streams = xhci_alloc_streams,
327 .free_streams = xhci_free_streams,
328 .add_endpoint = xhci_add_endpoint,
329 .drop_endpoint = xhci_drop_endpoint,
330 .endpoint_reset = xhci_endpoint_reset,
331 .check_bandwidth = xhci_check_bandwidth,
332 .reset_bandwidth = xhci_reset_bandwidth,
333 .address_device = xhci_address_device,
334 .update_hub_device = xhci_update_hub_device,
335 .reset_device = xhci_discover_or_reset_device,
336
337 /*
338 * scheduling support
339 */
340 .get_frame_number = xhci_get_frame,
341
342 /* Root hub support */
343 .hub_control = xhci_hub_control,
344 .hub_status_data = xhci_hub_status_data,
345 .bus_suspend = xhci_bus_suspend,
346 .bus_resume = xhci_bus_resume,
347};
348
349/*-------------------------------------------------------------------------*/
350
351/* PCI driver selection metadata; PCI hotplugging uses this */
352static const struct pci_device_id pci_ids[] = { {
353 /* handle any USB 3.0 xHCI controller */
354 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
355 .driver_data = (unsigned long) &xhci_pci_hc_driver,
356 },
357 { /* end: all zeroes */ }
358};
359MODULE_DEVICE_TABLE(pci, pci_ids);
360
361/* pci driver glue; this is a "new style" PCI driver module */
362static struct pci_driver xhci_pci_driver = {
363 .name = (char *) hcd_name,
364 .id_table = pci_ids,
365
366 .probe = xhci_pci_probe,
367 .remove = xhci_pci_remove,
368 /* suspend and resume implemented later */
369
370 .shutdown = usb_hcd_pci_shutdown,
371#ifdef CONFIG_PM_SLEEP
372 .driver = {
373 .pm = &usb_hcd_pci_pm_ops
374 },
375#endif
376};
377
378int xhci_register_pci(void)
379{
380 return pci_register_driver(&xhci_pci_driver);
381}
382
383void xhci_unregister_pci(void)
384{
385 pci_unregister_driver(&xhci_pci_driver);
386}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/acpi.h>
15
16#include "xhci.h"
17#include "xhci-trace.h"
18#include "xhci-pci.h"
19
20#define SSIC_PORT_NUM 2
21#define SSIC_PORT_CFG2 0x880c
22#define SSIC_PORT_CFG2_OFFSET 0x30
23#define PROG_DONE (1 << 30)
24#define SSIC_PORT_UNUSED (1 << 31)
25
26/* Device for a quirk */
27#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
28#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
29#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
30#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
31
32#define PCI_VENDOR_ID_ETRON 0x1b6f
33#define PCI_DEVICE_ID_EJ168 0x7023
34
35#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
36#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
37#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
38#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
39#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
40#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
41#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
42#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
43#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
44#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
45#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
46#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
47#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
48#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
49#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
50#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
51#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
52#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
53#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
54#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
55
56#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
57#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
58#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
59#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
60#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
61#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
62#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
63#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
64
65static const char hcd_name[] = "xhci_hcd";
66
67static struct hc_driver __read_mostly xhci_pci_hc_driver;
68
69static int xhci_pci_setup(struct usb_hcd *hcd);
70
71static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
72 .reset = xhci_pci_setup,
73};
74
75/* called after powerup, by probe or system-pm "wakeup" */
76static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
77{
78 /*
79 * TODO: Implement finding debug ports later.
80 * TODO: see if there are any quirks that need to be added to handle
81 * new extended capabilities.
82 */
83
84 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
85 if (!pci_set_mwi(pdev))
86 xhci_dbg(xhci, "MWI active\n");
87
88 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
89 return 0;
90}
91
92static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
93{
94 struct pci_dev *pdev = to_pci_dev(dev);
95 struct xhci_driver_data *driver_data;
96 const struct pci_device_id *id;
97
98 id = pci_match_id(pdev->driver->id_table, pdev);
99
100 if (id && id->driver_data) {
101 driver_data = (struct xhci_driver_data *)id->driver_data;
102 xhci->quirks |= driver_data->quirks;
103 }
104
105 /* Look for vendor-specific quirks */
106 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
107 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
108 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
109 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
110 pdev->revision == 0x0) {
111 xhci->quirks |= XHCI_RESET_EP_QUIRK;
112 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
113 "QUIRK: Fresco Logic xHC needs configure"
114 " endpoint cmd after reset endpoint");
115 }
116 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
117 pdev->revision == 0x4) {
118 xhci->quirks |= XHCI_SLOW_SUSPEND;
119 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
120 "QUIRK: Fresco Logic xHC revision %u"
121 "must be suspended extra slowly",
122 pdev->revision);
123 }
124 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
125 xhci->quirks |= XHCI_BROKEN_STREAMS;
126 /* Fresco Logic confirms: all revisions of this chip do not
127 * support MSI, even though some of them claim to in their PCI
128 * capabilities.
129 */
130 xhci->quirks |= XHCI_BROKEN_MSI;
131 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
132 "QUIRK: Fresco Logic revision %u "
133 "has broken MSI implementation",
134 pdev->revision);
135 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
136 }
137
138 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
139 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
140 xhci->quirks |= XHCI_BROKEN_STREAMS;
141
142 if (pdev->vendor == PCI_VENDOR_ID_NEC)
143 xhci->quirks |= XHCI_NEC_HOST;
144
145 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
146 xhci->quirks |= XHCI_AMD_0x96_HOST;
147
148 /* AMD PLL quirk */
149 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
150 xhci->quirks |= XHCI_AMD_PLL_FIX;
151
152 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
153 (pdev->device == 0x145c ||
154 pdev->device == 0x15e0 ||
155 pdev->device == 0x15e1 ||
156 pdev->device == 0x43bb))
157 xhci->quirks |= XHCI_SUSPEND_DELAY;
158
159 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
160 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
161 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
162
163 if (pdev->vendor == PCI_VENDOR_ID_AMD)
164 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
165
166 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
167 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
168 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
169 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
170 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
171 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
172
173 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
174 xhci->quirks |= XHCI_LPM_SUPPORT;
175 xhci->quirks |= XHCI_INTEL_HOST;
176 xhci->quirks |= XHCI_AVOID_BEI;
177 }
178 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
179 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
180 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
181 xhci->limit_active_eps = 64;
182 xhci->quirks |= XHCI_SW_BW_CHECKING;
183 /*
184 * PPT desktop boards DH77EB and DH77DF will power back on after
185 * a few seconds of being shutdown. The fix for this is to
186 * switch the ports from xHCI to EHCI on shutdown. We can't use
187 * DMI information to find those particular boards (since each
188 * vendor will change the board name), so we have to key off all
189 * PPT chipsets.
190 */
191 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
192 }
193 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
194 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
195 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
196 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
197 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
198 }
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
200 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
201 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
202 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
203 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
204 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
205 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
206 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
207 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
208 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
209 }
210 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
211 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
212 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
213 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
214 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
215 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
216 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
217 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
218 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
219 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
220 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
221 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
222 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
223 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
224 xhci->quirks |= XHCI_MISSING_CAS;
225
226 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
227 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
228 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
229 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
230 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
231 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
232 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
233 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
234 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
235 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI))
236 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
237
238 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
239 pdev->device == PCI_DEVICE_ID_EJ168) {
240 xhci->quirks |= XHCI_RESET_ON_RESUME;
241 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
242 xhci->quirks |= XHCI_BROKEN_STREAMS;
243 }
244 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
245 pdev->device == 0x0014) {
246 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
247 xhci->quirks |= XHCI_ZERO_64B_REGS;
248 }
249 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
250 pdev->device == 0x0015) {
251 xhci->quirks |= XHCI_RESET_ON_RESUME;
252 xhci->quirks |= XHCI_ZERO_64B_REGS;
253 }
254 if (pdev->vendor == PCI_VENDOR_ID_VIA)
255 xhci->quirks |= XHCI_RESET_ON_RESUME;
256
257 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
258 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
259 pdev->device == 0x3432)
260 xhci->quirks |= XHCI_BROKEN_STREAMS;
261
262 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
263 xhci->quirks |= XHCI_LPM_SUPPORT;
264
265 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
266 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
267 xhci->quirks |= XHCI_BROKEN_STREAMS;
268 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
269 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
270 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
271 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
272 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
273 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI))
274 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
275
276 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
277 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
278 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
279
280 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
281 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
282
283 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
284 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
285 pdev->device == 0x9026)
286 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
287
288 if (xhci->quirks & XHCI_RESET_ON_RESUME)
289 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
290 "QUIRK: Resetting on resume");
291}
292
293#ifdef CONFIG_ACPI
294static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
295{
296 static const guid_t intel_dsm_guid =
297 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
298 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
299 union acpi_object *obj;
300
301 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
302 NULL);
303 ACPI_FREE(obj);
304}
305#else
306static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
307#endif /* CONFIG_ACPI */
308
309/* called during probe() after chip reset completes */
310static int xhci_pci_setup(struct usb_hcd *hcd)
311{
312 struct xhci_hcd *xhci;
313 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
314 int retval;
315
316 xhci = hcd_to_xhci(hcd);
317 if (!xhci->sbrn)
318 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
319
320 /* imod_interval is the interrupt moderation value in nanoseconds. */
321 xhci->imod_interval = 40000;
322
323 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
324 if (retval)
325 return retval;
326
327 if (!usb_hcd_is_primary_hcd(hcd))
328 return 0;
329
330 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
331 xhci_pme_acpi_rtd3_enable(pdev);
332
333 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
334
335 /* Find any debug ports */
336 return xhci_pci_reinit(xhci, pdev);
337}
338
339/*
340 * We need to register our own PCI probe function (instead of the USB core's
341 * function) in order to create a second roothub under xHCI.
342 */
343static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
344{
345 int retval;
346 struct xhci_hcd *xhci;
347 struct usb_hcd *hcd;
348 struct xhci_driver_data *driver_data;
349
350 driver_data = (struct xhci_driver_data *)id->driver_data;
351 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
352 retval = renesas_xhci_check_request_fw(dev, id);
353 if (retval)
354 return retval;
355 }
356
357 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
358 pm_runtime_get_noresume(&dev->dev);
359
360 /* Register the USB 2.0 roothub.
361 * FIXME: USB core must know to register the USB 2.0 roothub first.
362 * This is sort of silly, because we could just set the HCD driver flags
363 * to say USB 2.0, but I'm not sure what the implications would be in
364 * the other parts of the HCD code.
365 */
366 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
367
368 if (retval)
369 goto put_runtime_pm;
370
371 /* USB 2.0 roothub is stored in the PCI device now. */
372 hcd = dev_get_drvdata(&dev->dev);
373 xhci = hcd_to_xhci(hcd);
374 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
375 pci_name(dev), hcd);
376 if (!xhci->shared_hcd) {
377 retval = -ENOMEM;
378 goto dealloc_usb2_hcd;
379 }
380
381 retval = xhci_ext_cap_init(xhci);
382 if (retval)
383 goto put_usb3_hcd;
384
385 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
386 IRQF_SHARED);
387 if (retval)
388 goto put_usb3_hcd;
389 /* Roothub already marked as USB 3.0 speed */
390
391 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
392 HCC_MAX_PSA(xhci->hcc_params) >= 4)
393 xhci->shared_hcd->can_do_streams = 1;
394
395 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
396 pm_runtime_put_noidle(&dev->dev);
397
398 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
399 pm_runtime_allow(&dev->dev);
400
401 return 0;
402
403put_usb3_hcd:
404 usb_put_hcd(xhci->shared_hcd);
405dealloc_usb2_hcd:
406 usb_hcd_pci_remove(dev);
407put_runtime_pm:
408 pm_runtime_put_noidle(&dev->dev);
409 return retval;
410}
411
412static void xhci_pci_remove(struct pci_dev *dev)
413{
414 struct xhci_hcd *xhci;
415
416 xhci = hcd_to_xhci(pci_get_drvdata(dev));
417 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
418 renesas_xhci_pci_exit(dev);
419
420 xhci->xhc_state |= XHCI_STATE_REMOVING;
421
422 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
423 pm_runtime_forbid(&dev->dev);
424
425 if (xhci->shared_hcd) {
426 usb_remove_hcd(xhci->shared_hcd);
427 usb_put_hcd(xhci->shared_hcd);
428 xhci->shared_hcd = NULL;
429 }
430
431 /* Workaround for spurious wakeups at shutdown with HSW */
432 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
433 pci_set_power_state(dev, PCI_D3hot);
434
435 usb_hcd_pci_remove(dev);
436}
437
438#ifdef CONFIG_PM
439/*
440 * In some Intel xHCI controllers, in order to get D3 working,
441 * through a vendor specific SSIC CONFIG register at offset 0x883c,
442 * SSIC PORT need to be marked as "unused" before putting xHCI
443 * into D3. After D3 exit, the SSIC port need to be marked as "used".
444 * Without this change, xHCI might not enter D3 state.
445 */
446static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
447{
448 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
449 u32 val;
450 void __iomem *reg;
451 int i;
452
453 for (i = 0; i < SSIC_PORT_NUM; i++) {
454 reg = (void __iomem *) xhci->cap_regs +
455 SSIC_PORT_CFG2 +
456 i * SSIC_PORT_CFG2_OFFSET;
457
458 /* Notify SSIC that SSIC profile programming is not done. */
459 val = readl(reg) & ~PROG_DONE;
460 writel(val, reg);
461
462 /* Mark SSIC port as unused(suspend) or used(resume) */
463 val = readl(reg);
464 if (suspend)
465 val |= SSIC_PORT_UNUSED;
466 else
467 val &= ~SSIC_PORT_UNUSED;
468 writel(val, reg);
469
470 /* Notify SSIC that SSIC profile programming is done */
471 val = readl(reg) | PROG_DONE;
472 writel(val, reg);
473 readl(reg);
474 }
475}
476
477/*
478 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
479 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
480 */
481static void xhci_pme_quirk(struct usb_hcd *hcd)
482{
483 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
484 void __iomem *reg;
485 u32 val;
486
487 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
488 val = readl(reg);
489 writel(val | BIT(28), reg);
490 readl(reg);
491}
492
493static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
494{
495 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
496 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
497 int ret;
498
499 /*
500 * Systems with the TI redriver that loses port status change events
501 * need to have the registers polled during D3, so avoid D3cold.
502 */
503 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
504 pci_d3cold_disable(pdev);
505
506 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
507 xhci_pme_quirk(hcd);
508
509 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
510 xhci_ssic_port_unused_quirk(hcd, true);
511
512 ret = xhci_suspend(xhci, do_wakeup);
513 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
514 xhci_ssic_port_unused_quirk(hcd, false);
515
516 return ret;
517}
518
519static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
520{
521 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
522 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
523 int retval = 0;
524
525 /* The BIOS on systems with the Intel Panther Point chipset may or may
526 * not support xHCI natively. That means that during system resume, it
527 * may switch the ports back to EHCI so that users can use their
528 * keyboard to select a kernel from GRUB after resume from hibernate.
529 *
530 * The BIOS is supposed to remember whether the OS had xHCI ports
531 * enabled before resume, and switch the ports back to xHCI when the
532 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
533 * writers.
534 *
535 * Unconditionally switch the ports back to xHCI after a system resume.
536 * It should not matter whether the EHCI or xHCI controller is
537 * resumed first. It's enough to do the switchover in xHCI because
538 * USB core won't notice anything as the hub driver doesn't start
539 * running again until after all the devices (including both EHCI and
540 * xHCI host controllers) have been resumed.
541 */
542
543 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
544 usb_enable_intel_xhci_ports(pdev);
545
546 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
547 xhci_ssic_port_unused_quirk(hcd, false);
548
549 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
550 xhci_pme_quirk(hcd);
551
552 retval = xhci_resume(xhci, hibernated);
553 return retval;
554}
555
556static void xhci_pci_shutdown(struct usb_hcd *hcd)
557{
558 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
559 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
560
561 xhci_shutdown(hcd);
562
563 /* Yet another workaround for spurious wakeups at shutdown with HSW */
564 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
565 pci_set_power_state(pdev, PCI_D3hot);
566}
567#endif /* CONFIG_PM */
568
569/*-------------------------------------------------------------------------*/
570
571static const struct xhci_driver_data reneses_data = {
572 .quirks = XHCI_RENESAS_FW_QUIRK,
573 .firmware = "renesas_usb_fw.mem",
574};
575
576/* PCI driver selection metadata; PCI hotplugging uses this */
577static const struct pci_device_id pci_ids[] = {
578 { PCI_DEVICE(0x1912, 0x0014),
579 .driver_data = (unsigned long)&reneses_data,
580 },
581 { PCI_DEVICE(0x1912, 0x0015),
582 .driver_data = (unsigned long)&reneses_data,
583 },
584 /* handle any USB 3.0 xHCI controller */
585 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
586 },
587 { /* end: all zeroes */ }
588};
589MODULE_DEVICE_TABLE(pci, pci_ids);
590MODULE_FIRMWARE("renesas_usb_fw.mem");
591
592/* pci driver glue; this is a "new style" PCI driver module */
593static struct pci_driver xhci_pci_driver = {
594 .name = hcd_name,
595 .id_table = pci_ids,
596
597 .probe = xhci_pci_probe,
598 .remove = xhci_pci_remove,
599 /* suspend and resume implemented later */
600
601 .shutdown = usb_hcd_pci_shutdown,
602#ifdef CONFIG_PM
603 .driver = {
604 .pm = &usb_hcd_pci_pm_ops
605 },
606#endif
607};
608
609static int __init xhci_pci_init(void)
610{
611 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
612#ifdef CONFIG_PM
613 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
614 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
615 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
616#endif
617 return pci_register_driver(&xhci_pci_driver);
618}
619module_init(xhci_pci_init);
620
621static void __exit xhci_pci_exit(void)
622{
623 pci_unregister_driver(&xhci_pci_driver);
624}
625module_exit(xhci_pci_exit);
626
627MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
628MODULE_LICENSE("GPL");